MC68340PV16VE

µ MOTOROLA MC68340 Integrated Processor with DMA User’s Manual ©MOTOROLA INC., 1992 Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. PREFACE The complete documentation package for the MC68340 consists of the MC68340UM/AD, MC68340 Integrated Processor with DMA User’s Manual, M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68340P/D, MC68340 Integrated Processor with DMA Product Brief. The MC68340 Integrated with DMA Processor User’s Manual describes the programming, capabilities, registers, and operation of the MC68340; the MC68000 Family Programmer’s Reference Manual provides instruction details for the MC68340; and the MC68340 Integrated Processor with DMA Product Brief provides a brief description of the MC68340 capabilities. This user’s manual is organized as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Device Overview Signal Descriptions Bus Operation System Integration Module CPU32 DMA Controller Module Serial Module Section 8 Section 9 Section 10 Section 11 Section 12 Timer Modules IEEE 1149.1 Test Access Port Applications Electrical Characteristics Ordering Information and Mechanical Data 68K FAX-IT FAX 512-891-8593 The Motorola High-End Technical Publication Department provides a FAX number for you to submit any questions and comments about this document. We welcome your suggestions for improving our documentation or any questions concerning our products. Please provide the part number and revision number (located in upper right-hand corner on the cover), and the title of the document when submitting. When referring to items in the manual please reference by the page number, paragraph number, figure number, table number, and line number if needed. Reference the line number from the top of the page. When we receive a FAX between the hours of 7:30 AM and 5:00 PM EST, Monday through Friday, we will respond within two hours. If the FAX is received after 5:00 PM or on the weekend, we will respond within two hours on the first working day following receipt of the FAX. When sending a FAX, please provide your name, company, FAX number, and voice number including area code (so we can talk to a real person if needed). 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS Paragraph Number Title Page Number Section 1 Device Overview 1.1 1.1.1 1.1.2 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.1.7 1.3.2 1.3.3 1.3.4 1.4 1.5 1.6 1.7 M68300 Family..................................................................................................1-2 Organization ..................................................................................................1-3 Advantages....................................................................................................1-3 Central Processor Unit..................................................................................... 1-3 CPU32 ............................................................................................................1-4 Background Debug Mode...........................................................................1-4 On-Chip Peripherals ........................................................................................1-5 System Integration Module.........................................................................1-5 External Bus Interface..............................................................................1-5 System Configuration and Protection...................................................1-6 Clock Synthesizer.....................................................................................1-6 Chip Select and Wait State Generation ...............................................1-6 Interrupt Handling.....................................................................................1-6 Discrete I/O Pins........................................................................................ 1-6 IEEE 1149.1 Test Access Port................................................................1-7 Direct Memory Access Module...................................................................1-7 Serial Module................................................................................................1-7 Timer Modules...............................................................................................1-8 Power Consumption Management................................................................1-8 Physical ..............................................................................................................1-9 Compact Disc-Interactive ................................................................................1-9 More Information...............................................................................................1-10 Section 2 Signal Descriptions 2.1 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 MOTOROLA Signal Index.......................................................................................................2-2 Address Bus.......................................................................................................2-4 Address Bus (A23–A0) ................................................................................2-4 Address Bus (A31–A24)..............................................................................2-4 Data Bus (D15–D0)..........................................................................................2-4 Function Codes (FC3–FC0)............................................................................2-5 Chip Selects (CS3–CS0) ................................................................................2-5 Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3) ...................................2-6 MC68340 USER'S MANUAL iii 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.12 2.12.1 2.12.2 2.12.3 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 2.13.6 2.13.7 2.13.8 2.14 2.14.1 2.14.2 2.14.3 iv Title Page Number Bus Control Signals .........................................................................................2-6 Data and Size Acknowledge (DSACK1, DSACK0)................................2-6 Address Strobe (AS)....................................................................................2-6 Data Strobe (DS)...........................................................................................2-7 Transfer Size (SIZ1, SIZ0) ..........................................................................2-7 Read/Write (R/W)...........................................................................................2-7 Bus Arbitration Signals....................................................................................2-7 Bus Request (BR)..........................................................................................2-7 Bus Grant (BG)...............................................................................................2-7 Bus Grant Acknowledge (BGACK).............................................................2-7 Read-Modify-Write Cycle (RMC).................................................................2-8 Exception Control Signals ..............................................................................2-8 Reset (RESET)...............................................................................................2-8 Halt (HALT)....................................................................................................2-8 Bus Error (BERR)...........................................................................................2-8 Clock Signals ....................................................................................................2-8 System Clock (CLKOUT)............................................................................2-8 Crystal Oscillator (EXTAL, XTAL)...............................................................2-9 External Filter Capacitor (XFC) ..................................................................2-9 Clock Mode Select (MODCK).....................................................................2-9 Instrumentation and Emulation Signals .......................................................2-9 Instruction Fetch (IFETCH)..........................................................................2-9 Instruction Pipe (IPIPE)...............................................................................2-9 Breakpoint (BKPT)........................................................................................2-10 Freeze (FREEZE)..........................................................................................2-10 DMA Module Signals.......................................................................................2-10 DMA Request (DREQ2, DREQ1).................................................................2-10 DMA Acknowledge (DACK2, DACK1)......................................................2-10 DMA Done (DONE2, DONE1)......................................................................2-10 Serial Module Signals.....................................................................................2-11 Serial Crystal Oscillator (X2, X1) ...............................................................2-11 Serial External Clock Input (SCLK)...........................................................2-11 Receive Data (RxDA, RxDB).......................................................................2-11 Transmit Data (TxDA, TxDB).......................................................................2-11 Clear to Send (CTSA, CTSB).....................................................................2-11 Request to Send (RTSA, RTSB)................................................................2-11 Transmitter Ready (T≈RDYA).....................................................................2-11 Receiver Ready (R≈RDYA) .........................................................................2-12 Timer Signals ....................................................................................................2-12 Timer Gate (TGATE2, TGATE1)................................................................2-12 Timer Input (TIN2, TIN1) ..............................................................................2-12 Timer Output (TOUT2, TOUT1)...................................................................2-12 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 2.15 2.15.1 2.15.2 2.15.3 2.15.4 2.16 2.17 2.18 Title Page Number Test Signals.......................................................................................................2-13 Test Clock (TCK)...........................................................................................2-13 Test Mode Select (TMS)..............................................................................2-13 Test Data In (TDI)..........................................................................................2-13 Test Data Out (TDO).....................................................................................2-13 Synthesizer Power (VCCSYN)..........................................................................2-13 System Power and Ground (VCC and GND)................................................2-13 Signal Summary...............................................................................................2-13 Section 3 Bus Operation 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.7.1 3.1.7.2 3.1.7.3 3.2 3.2.1 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4 3.2.3.5 3.2.3.6 3.2.3.7 3.2.4 3.2.5 3.2.6 3.3 3.3.1 3.3.2 3.3.3 MOTOROLA Bus Transfer Signals........................................................................................3-1 Bus Control Signals .....................................................................................3-2 Function Code Signals................................................................................3-3 Address Bus (A31–A0) ................................................................................3-4 Address Strobe (AS)....................................................................................3-4 Data Bus (D15–D0)......................................................................................3-4 Data Strobe (DS)...........................................................................................3-4 Bus Cycle Termination Signals..................................................................3-4 Data Transfer and Size Acknowledge Signals (DSACK1 and DSACK0).....................................................................3-4 Bus Error (BERR).......................................................................................3-5 Autovector (AVEC)....................................................................................3-5 Data Transfer Mechanism...............................................................................3-5 Dynamic Bus Sizing.....................................................................................3-5 Misaligned Operands...................................................................................3-7 Operand Transfer Cases.............................................................................3-7 Byte Operand to 8-Bit Port, Odd or Even (A0 = X) ..............................3-7 Byte Operand to 16-Bit Port, Even (A0 = 0)..........................................3-8 Byte Operand to 16-Bit Port, Odd (A0 = 1) ...........................................3-9 Word Operand to 8-Bit Port, Aligned.....................................................3-9 Word Operand to 16-Bit Port, Aligned...................................................3-10 Long-word Operand to 8-Bit Port, Aligned...........................................3-10 Long-Word Operand to 16-Bit Port, Aligned........................................3-12 Bus Operation................................................................................................3-14 Synchronous Operation with DSACK≈.....................................................3-14 Fast Termination Cycles..............................................................................3-15 Data Transfer Cycles........................................................................................3-16 Read Cycle.....................................................................................................3-16 Write Cycle.....................................................................................................3-18 Read-Modify-Write Cycle.............................................................................3-19 MC68340 USER'S MANUAL v 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.4.1 3.4.4.2 3.4.4.3 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 Title Page Number CPU Space Cycles........................................................................................... 3-21 Breakpoint Acknowledge Cycle.................................................................3-22 LPSTOP Broadcast Cycle...........................................................................3-23 Module Base Address Register Access....................................................3-27 Interrupt Acknowledge Bus Cycles............................................................3-27 Interrupt Acknowledge Cycle—Terminated Normally........................3-27 Autovector Interrupt Acknowledge Cycle .............................................3-29 Spurious Interrupt Cycle..........................................................................3-30 Bus Exception Control Cycles........................................................................3-32 Bus Errors.......................................................................................................3-34 Retry Operation .............................................................................................3-36 Halt Operation ...............................................................................................3-38 Double Bus Fault ..........................................................................................3-39 Bus Arbitration...................................................................................................3-40 Bus Request...................................................................................................3-43 Bus Grant........................................................................................................3-43 Bus Grant Acknowledge..............................................................................3-43 Bus Arbitration Control.................................................................................3-44 Show Cycles..................................................................................................3-44 Reset Operation ................................................................................................3-46 Section 4 System Integration Module 4.1 4.2 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.2.6 4.2.2.6.1 4.2.2.6.2 4.2.2.7 4.2.3 4.2.3.1 4.2.3.2 4.2.3.3 4.2.4 4.2.4.1 vi Module Overview..............................................................................................4-1 Module Operation.............................................................................................4-2 Module Base Address Register Operation...............................................4-2 System Configuration and Protection Operation....................................4-3 System Configuration ..............................................................................4-5 Internal Bus Monitor .................................................................................4-6 Double Bus Fault Monitor........................................................................4-6 Spurious Interrupt Monitor ......................................................................4-6 Software Watchdog..................................................................................4-6 Periodic Interrupt Timer ...........................................................................4-7 Periodic Timer Period Calculation.....................................................4-8 Using the Periodic Timer as a Real-Time Clock .............................4-9 Simultaneous Interrupts by Sources in the SIM40.............................4-9 Clock Synthesizer Operation......................................................................4-9 Phase Comparator and Filter .................................................................4-11 Frequency Divider ....................................................................................4-12 Clock Control.............................................................................................4-13 Chip Select Operation .................................................................................4-13 Programmable Features..........................................................................4-14 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 4.2.4.2 4.2.5 4.2.5.1 4.2.5.2 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.3 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 4.3.5 4.3.5.1 4.3.5.2 4.3.5.3 4.3.5.4 4.3.5.5 4.3.5.6 4.3.5.7 4.4 4.4.1 4.4.2 4.4.3 Title Page Number Global Chip Select Operation ................................................................4-14 External Bus Interface Operation...............................................................4-15 Port A...........................................................................................................4-15 Port B...........................................................................................................4-16 Low-Power Stop ...........................................................................................4-17 Freeze.............................................................................................................4-17 Programming Model.........................................................................................4-18 Module Base Address Register (MBAR)...................................................4-20 System Configuration and Protection Registers.....................................4-21 Module Configuration Register (MCR)..................................................4-21 Autovector Register (AVR).......................................................................4-23 Reset Status Register (RSR)...................................................................4-23 Software Interrupt Vector Register (SWIV)...........................................4-24 System Protection Control Register (SYPCR).....................................4-24 Periodic Interrupt Control Register (PICR) ...........................................4-26 Periodic Interrupt Timer Register (PITR)...............................................4-27 Software Service Register (SWSR) ......................................................4-28 Clock Synthesizer Control Register (SYNCR) ........................................4-28 Chip Select Registers ..................................................................................4-29 Base Address Registers ..........................................................................4-30 Address Mask Registers..........................................................................4-31 Chip Select Registers Programming Example....................................4-33 External Bus Interface Control....................................................................4-33 Port A Pin Assignment Register 1 (PPARA1).......................................4-33 Port A Pin Assignment Register 2 (PPARA2).......................................4-34 Port A Data Direction Register (DDRA).................................................4-34 Port A Data Register (PORTA)................................................................4-34 Port B Pin Assignment Register (PPARB) ............................................4-35 Port B Data Direction Register (DDRB).................................................4-35 Port B Data Register (PORTB, PORTB1) ..............................................4-35 MC68340 Initialization Sequence.................................................................4-36 Startup ............................................................................................................4-36 SIM40 Module Configuration .....................................................................4-36 SIM40 Example Configuration Code........................................................4-38 Section 5 CPU32 5.1 5.1.1 5.1.2 5.1.3 MOTOROLA Overview.............................................................................................................5-1 Features..........................................................................................................5-2 Virtual Memory ..............................................................................................5-2 Loop Mode Instruction Execution ..............................................................5-3 MC68340 USER'S MANUAL vii 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 5.1.4 5.1.5 5.1.6 5.1.7 5.1.7.1 5.1.7.2 5.1.8 5.1.9 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.1.1 5.3.1.1.1 5.3.1.1.2 5.3.1.2 5.3.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6 5.3.3.7 5.3.3.8 5.3.3.9 5.3.3.10 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 viii Title Page Number Vector Base Register....................................................................................5-4 Exception Handling......................................................................................5-4 Addressing Modes........................................................................................5-5 Instruction Set................................................................................................5-5 Table Lookup and Interpolate Instructions...........................................5-7 Low-Power STOP Instruction .................................................................5-7 Processing States.........................................................................................5-7 Privilege States.............................................................................................5-7 Architecture Summary .....................................................................................5-8 Programming Model.....................................................................................5-8 Registers.........................................................................................................5-10 Instruction Set....................................................................................................5-11 M68000 Family Compatibility.....................................................................5-11 New Instructions........................................................................................5-11 Low-Power Stop (LPSTOP)................................................................5-11 Table Lookup and Interpolation (TBL)..............................................5-12 Unimplemented Instructions...................................................................5-12 Instruction Format and Notation.................................................................5-12 Instruction Summary ....................................................................................5-15 Condition Code Register.........................................................................5-20 Data Movement Instructions ...................................................................5-21 Integer Arithmetic Operations.................................................................5-22 Logic Instructions......................................................................................5-24 Shift and Rotate Instructions...................................................................5-24 Bit Manipulation Instructions...................................................................5-25 Binary-Coded Decimal (BCD) Instructions ..........................................5-26 Program Control Instructions..................................................................5-26 System Control Instructions....................................................................5-27 Condition Tests .........................................................................................5-29 Using the TBL Instructions ..........................................................................5-29 Table Example 1: Standard Usage.......................................................5-30 Table Example 2: Compressed Table ..................................................5-31 Table Example 3: 8-Bit Independent Variable ....................................5-32 Table Example 4: Maintaining Precision..............................................5-34 Table Example 5: Surface Interpolations.............................................5-36 Nested Subroutine Calls.............................................................................5-36 Pipeline Synchronization with the NOP Instruction................................5-36 Processing States.............................................................................................5-36 State Transitions...........................................................................................5-37 Privilege Levels.............................................................................................5-37 Supervisor Privilege Level......................................................................5-37 User Privilege Level.................................................................................5-39 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 5.4.2.3 5.5 5.5.1 5.5.1.1 5.5.1.2 5.5.1.3 5.5.1.4 5.5.2 5.5.2.1 5.5.2.2 5.5.2.3 5.5.2.4 5.5.2.5 5.5.2.6 5.5.2.7 5.5.2.8 5.5.2.9 5.5.2.10 5.5.2.11 5.5.2.12 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.1.2 5.5.3.1.3 5.5.3.1.4 5.5.3.2 5.5.3.2.1 5.5.3.2.2 5.5.3.2.3 5.5.3.2.4 5.5.3.2.5 5.5.3.2.6 5.5.3.2.7 5.5.4 5.5.4.1 5.5.4.2 5.5.4.3 5.6 5.6.1 5.6.1.1 5.6.1.2 MOTOROLA Title Page Number Changing Privilege Level........................................................................5-39 Exception Processing ......................................................................................5-39 Exception Vectors.........................................................................................5-40 Types of Exceptions .................................................................................5-41 Exception Processing Sequence ..........................................................5-41 Exception Stack Frame............................................................................5-42 Multiple Exceptions ..................................................................................5-42 Processing of Specific Exceptions ............................................................5-44 Reset ...........................................................................................................5-44 Bus Error.....................................................................................................5-46 Address Error.............................................................................................5-46 Instruction Traps........................................................................................5-47 Software Breakpoints...............................................................................5-47 Hardware Breakpoints.............................................................................5-48 Format Error...............................................................................................5-48 Illegal or Unimplemented Instructions ..................................................5-48 Privilege Violations...................................................................................5-49 Tracing........................................................................................................5-50 Interrupts.....................................................................................................5-51 Return from Exception..............................................................................5-52 Fault Recovery...............................................................................................5-53 Types of Faults ..........................................................................................5-55 Type I—Released Write Faults...........................................................5-55 Type II—Prefetch, Operand, RMW, and MOVEP Faults.................5-56 Type III—Faults During MOVEM Operand Transfer .......................5-57 Type IV—Faults During Exception Processing ...............................5-57 Correcting a Fault .....................................................................................5-57 Type I—Completing Released Writes via Software .......................5-57 Type I—Completing Released Writes via RTE................................5-57 Type II—Correcting Faults via RTE....................................................5-58 Type III—Correcting Faults via Software..........................................5-58 Type III—Correcting Faults by Conversion and Restart.................5-58 Type III—Correcting Faults via RTE...................................................5-59 Type IV—Correcting Faults via Software .........................................5-59 CPU32 Stack Frames ..................................................................................5-60 Four-Word Stack Frame ..........................................................................5-60 Six-Word Stack Frame.............................................................................5-60 Bus Error Stack Frame.............................................................................5-60 Development Support......................................................................................5-63 CPU32 Integrated Development Support................................................5-63 Background Debug Mode (BDM) Overview ........................................5-64 Deterministic Opcode Tracking Overview............................................5-64 MC68340 USER'S MANUAL ix 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 5.6.1.3 5.6.2 5.6.2.1 5.6.2.2 5.6.2.2.1 5.6.2.2.2 5.6.2.2.3 5.6.2.3 5.6.2.4 5.6.2.5 5.6.2.5.1 5.6.2.5.2 5.6.2.5.3 5.6.2.6 5.6.2.7 5.6.2.7.1 5.6.2.7.2 5.6.2.8 5.6.2.8.1 5.6.2.8.2 5.6.2.8.3 5.6.2.8.4 5.6.2.8.5 5.6.2.8.6 5.6.2.8.7 5.6.2.8.8 5.6.2.8.9 5.6.2.8.10 5.6.2.8.11 5.6.2.8.12 5.6.2.8.13 5.6.2.8.14 5.6.2.8.15 5.6.2.8.16 5.6.3 5.6.3.1 5.6.3.2 5.6.3.3 5.7 5.7.1 5.7.1.1 5.7.1.2 x Title Page Number On-Chip Hardware Breakpoint Overview.............................................5-64 Background Debug Mode...........................................................................5-65 Enabling BDM ...........................................................................................5-65 BDM Sources ............................................................................................5-66 External BKPT Signal..........................................................................5-66 BGND Instruction ..................................................................................5-66 Double Bus Fault. .................................................................................5-66 Entering BDM ............................................................................................5-66 Command Execution................................................................................5-67 BDM Registers...........................................................................................5-67 Fault Address Register (FAR) .............................................................5-67 Return Program Counter (RPC) .........................................................5-67 Current Instruction Program Counter (PCC)....................................5-67 Returning from BDM.................................................................................5-68 Serial Interface..........................................................................................5-68 CPU Serial Logic..................................................................................5-69 Development System Serial Logic....................................................5-71 Command Set ...........................................................................................5-73 Command Format.................................................................................5-73 Command Sequence Diagram..........................................................5-74 Command Set Summary.....................................................................5-75 Read A/D Register (RAREG/RDREG)................................................5-76 Write A/D Register (WAREG/WDREG) ..............................................5-77 Read System Register (RSREG)........................................................5-77 Write System Register (WSREG).......................................................5-78 Read Memory Location (READ).........................................................5-79 Write Memory Location (WRITE)........................................................5-79 Dump Memory Block (DUMP). ...........................................................5-80 Fill Memory Block (FILL)......................................................................5-82 Resume Execution (GO)......................................................................5-83 Call User Code (CALL)........................................................................5-83 Reset Peripherals (RST)......................................................................5-85 No Operation (NOP).............................................................................5-85 Future Commands................................................................................5-86 Deterministic Opcode Tracking..................................................................5-86 Instruction Fetch (IFETCH)......................................................................5-86 Instruction Pipe (IPIPE)...........................................................................5-87 Opcode Tracking during Loop Mode ....................................................5-88 Instruction Execution Timing...........................................................................5-88 Resource Scheduling ..................................................................................5-88 Microsequencer ........................................................................................5-89 Instruction Pipeline...................................................................................5-89 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 5.7.1.3 5.7.1.3.1 5.7.1.3.2 5.7.1.3.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.1.7 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.7.3.3 5.7.3.4 5.7.3.5 5.7.3.6 5.7.3.7 5.7.3.8 5.7.3.9 5.7.3.10 5.7.3.11 5.7.3.12 5.7.3.13 5.7.3.14 Title Page Number Bus Controller Resources .......................................................................5-89 Prefetch Controller................................................................................5-90 Write Pending Buffer. ...........................................................................5-90 Microbus Controller..............................................................................5-91 Instruction Execution Overlap.................................................................5-91 Effects of Wait States................................................................................5-92 Instruction Execution Time Calculation ................................................5-92 Effects of Negative Tails ..........................................................................5-93 Instruction Stream Timing Examples ........................................................5-94 Timing Example 1—Execution Overlap................................................5-94 Timing Example 2—Branch Instructions ..............................................5-95 Timing Example 3—Negative Tails.......................................................5-96 Instruction Timing Tables ............................................................................5-97 Fetch Effective Address ...........................................................................5-99 Calculate Effective Address....................................................................5-100 MOVE Instruction ......................................................................................5-101 Special-Purpose MOVE Instruction.......................................................5-101 Arithmetic/Logic Instructions...................................................................5-102 Immediate Arithmetic/Logic Instructions...............................................5-105 Binary-Coded Decimal and Extended Instructions ............................5-106 Single Operand Instructions...................................................................5-107 Shift/Rotate Instructions...........................................................................5-108 Bit Manipulation Instructions...................................................................5-109 Conditional Branch Instructions.............................................................5-110 Control Instructions...................................................................................5-111 Exception-Related Instructions and Operations..................................5-111 Save and Restore Operations................................................................5-111 Section 6 DMA Controller Module 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.3.2.1 MOTOROLA DMA Module Overview....................................................................................6-2 DMA Module Signal Definitions.....................................................................6-4 DMA Request (DREQ≈)................................................................................6-4 DMA Acknowledge (DACK≈)......................................................................6-4 DMA Done (DONE≈).....................................................................................6-4 Transfer Request Generation .........................................................................6-4 Internal Request Generation.......................................................................6-4 Internal Request, Maximum Rate...........................................................6-5 Internal Request, Limited Rate ...............................................................6-5 External Request Generation .....................................................................6-5 External Burst Mode.................................................................................6-5 MC68340 USER'S MANUAL xi 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 6.3.2.2 6.4 6.4.1 6.4.1.1 6.4.1.2 6.4.2 6.4.2.1 6.4.2.2 6.5 6.6 6.6.1 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.3.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8 6.8 6.9 6.9.1 6.9.1.1 6.9.1.2 6.9.2 Title Page Number External Cycle Steal Mode .....................................................................6-5 Data Transfer Modes........................................................................................6-6 Single-Address Mode..................................................................................6-6 Single-Address Read...............................................................................6-7 Single-Address Write...............................................................................6-9 Dual-Address Mode .....................................................................................6-12 Dual-Address Read..................................................................................6-12 Dual-Address Write ..................................................................................6-14 Bus Arbitration...................................................................................................6-18 DMA Channel Operation.................................................................................6-18 Channel Initialization and Startup.............................................................6-18 Data Transfers...............................................................................................6-19 Internal Request Transfers......................................................................6-19 External Request Transfers.....................................................................6-19 Channel Termination ...................................................................................6-20 Channel Termination ...............................................................................6-20 Interrupt Operation....................................................................................6-20 Fast Termination Option ..........................................................................6-20 Register Description.........................................................................................6-22 Module Configuration Register (MCR)......................................................6-23 Interrupt Register (INTR)..............................................................................6-26 Channel Control Register (CCR) ...............................................................6-26 Channel Status Register (CSR).................................................................6-30 Function Code Register (FCR) ...................................................................6-32 Source Address Register (SAR) ................................................................6-33 Destination Address Register (DAR).........................................................6-33 Byte Transfer Counter Register (BTC) ......................................................6-34 Data Packing .....................................................................................................6-35 DMA Channel Initialization Sequence .........................................................6-36 DMA Channel Configuration ......................................................................6-36 DMA Channel Operation in Single-Address Mode............................6-37 DMA Channel Operation in Dual-Address Mode ...............................6-37 DMA Channel Example Configuration Code ..........................................6-38 Section 7 Serial Module 7.1 7.1.1 7.1.2 7.1.3 7.1.4 xii Module Overview..............................................................................................7-2 Serial Communication Channels A and B...............................................7-3 Baud Rate Generator Logic ........................................................................7-3 Internal Channel Control Logic..................................................................7-3 Interrupt Control Logic .................................................................................7-3 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.8.1 7.2.8.2 7.2.9 7.2.9.1 7.2.9.2 7.2.10 7.2.11 7.2.12 7.2.12.1 7.2.12.2 7.2.13 7.2.13.1 7.2.13.2 7.2.13.3 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.3 7.3.3.1 7.3.3.2 7.3.3.3 7.3.4 7.3.5 7.3.5.1 7.3.5.2 7.3.5.3 7.4 7.4.1 7.4.1.1 MOTOROLA Title Page Number Comparison of Serial Module to MC68681.............................................7-4 Serial Module Signal Definitions................................................................... 7-4 Crystal Input or External Clock (X1) ..........................................................7-5 Crystal Output (X2) .......................................................................................7-5 External Input (SCLK)..................................................................................7-6 Channel A Transmitter Serial Data Output (TxDA).................................7-6 Channel A Receiver Serial Data Input (RxDA)........................................7-6 Channel B Transmitter Serial Data Output (TxDB).................................7-6 Channel B Receiver Serial Data Input (RxDB)........................................7-6 Channel A Request-To-Send (RTSA) ......................................................7-6 RTSA...........................................................................................................7-6 OP0..............................................................................................................7-6 Channel B Request-To-Send (RTSB).......................................................7-6 RTSB ...........................................................................................................7-7 OP1..............................................................................................................7-7 Channel A Clear-To-Send (CTSA) ...........................................................7-7 Channel B Clear-To-Send (CTSB)............................................................7-7 Channel A Transmitter Ready (T≈RDYA).................................................7-7 T≈RDYA......................................................................................................7-7 OP6..............................................................................................................7-7 Channel A Receiver Ready (R≈RDYA).....................................................7-7 R≈RDYA......................................................................................................7-7 FFULLA.......................................................................................................7-7 OP4..............................................................................................................7-7 Operation............................................................................................................7-8 Baud Rate Generator ...................................................................................7-8 Transmitter and Receiver Operating Modes............................................7-8 Transmitter .................................................................................................7-10 Receiver......................................................................................................7-11 FIFO Stack..................................................................................................7-12 Looping Modes .............................................................................................7-14 Automatic Echo Mode..............................................................................7-14 Local Loopback Mode .............................................................................7-14 Remote Loopback Mode .........................................................................7-14 Multidrop Mode .............................................................................................7-15 Bus Operation................................................................................................7-17 Read Cycles...............................................................................................7-17 Write Cycles...............................................................................................7-17 Interrupt Acknowledge Cycles................................................................7-17 Register Description and Programming .......................................................7-17 Register Description.....................................................................................7-17 Module Configuration Register (MCR)..................................................7-19 MC68340 USER'S MANUAL xiii 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Continued) Paragraph Number 7.4.1.2 7.4.1.3 7.4.1.4 7.4.1.5 7.4.1.6 7.4.1.7 7.4.1.8 7.4.1.9 7.4.1.10 7.4.1.11 7.4.1.12 7.4.1.13 7.4.1.14 7.4.1.15 7.4.1.16 7.4.1.17 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.5 7.5.1 7.5.2 Title Page Number Interrupt Level Register (ILR)..................................................................7-21 Interrupt Vector Register (IVR)................................................................7-21 Mode Register 1 (MR1)............................................................................7-22 Status Register (SR).................................................................................7-24 Clock-Select Register (CSR)..................................................................7-26 Command Register (CR) .........................................................................7-27 Receiver Buffer (RB).................................................................................7-30 Transmitter Buffer (TB).............................................................................7-30 Input Port Change Register (IPCR)........................................................7-31 Auxiliary Control Register (ACR)............................................................7-32 Interrupt Status Register (ISR)................................................................7-32 Interrupt Enable Register (IER)...............................................................7-34 Input Port (IP).............................................................................................7-35 Output Port Control Register (OPCR)....................................................7-35 Output Port Data Register (OP) ..............................................................7-37 Mode Register 2 (MR2)............................................................................7-37 Programming.................................................................................................7-40 Serial Module Initialization .....................................................................7-40 I/O Driver Example....................................................................................7-40 Interrupt Handling.....................................................................................7-40 Serial Module Initialization Sequence .........................................................7-46 Serial Module Configuration ......................................................................7-46 Serial Module Example Configuration Code ..........................................7-47 Section 8 Timer Modules 8.1 8.1.1 8.1.1.1 8.1.1.2 8.1.1.3 8.1.1.4 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 xiv Module Overview..............................................................................................8-1 Timer and Counter Functions.....................................................................8-2 Prescaler and Counter.............................................................................8-2 Timeout Detection.....................................................................................8-2 Comparator................................................................................................8-2 Clock Selection Logic..............................................................................8-3 Internal Control Logic...................................................................................8-3 Interrupt Control Logic .................................................................................8-4 Timer Modules Signal Definitions .................................................................8-4 Timer Input (TIN1, TIN2) ..............................................................................8-5 Timer Gate (TGATE1, TGATE2)................................................................8-6 Timer Output (TOUT1, TOUT2)...................................................................8-6 Operating Modes ..............................................................................................8-6 Input Capture/Output Compare..................................................................8-6 Square-Wave Generator.............................................................................8-8 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 TABLE OF CONTENTS (Continued) Paragraph Number 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.9.1 8.3.9.2 8.3.9.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.5 8.5.1 8.5.2 Title Page Number Variable Duty-Cycle Square-Wave Generator........................................8-9 Variable-Width Single-Shot Pulse Generator.........................................8-10 Pulse-Width Measurement..........................................................................8-12 Period Measurement....................................................................................8-13 Event Count ...................................................................................................8-14 Timer Bypass.................................................................................................8-16 Bus Operation................................................................................................8-17 Read Cycles...............................................................................................8-17 Write Cycles...............................................................................................8-17 Interrupt Acknowledge Cycles................................................................8-17 Register Description.........................................................................................8-17 Module Configuration Register (MCR)......................................................8-18 Interrupt Register (IR) ...................................................................................8-20 Control Register (CR)...................................................................................8-20 Status Register (SR).....................................................................................8-23 Counter Register (CNTR) ............................................................................8-25 Preload 1 Register (PREL1)........................................................................ 8-25 Preload 2 Register (PREL2)........................................................................ 8-26 Compare Register (COM)............................................................................8-26 Timer Module Initialization Sequence..........................................................8-27 Timer Module Configuration.......................................................................8-27 Timer Module Example Configuration Code...........................................8-28 Section 9 IEEE 1149.1 Test Access Port 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.6 Overview.............................................................................................................9-1 TAP Controller...................................................................................................9-2 Boundary Scan Register .................................................................................9-3 Instruction Register...........................................................................................9-9 EXTEST (000) ...............................................................................................9-10 SAMPLE/PRELOAD (001) ..........................................................................9-10 BYPASS (X1X, 101).....................................................................................9-11 HI-Z (100) .......................................................................................................9-11 MC68340 Restrictions......................................................................................9-11 Non-IEEE 1149.1 Operation...........................................................................9-12 Section 10 Applications 10.1 10.1.1 MOTOROLA Minimum System Configuration...................................................................10-1 Processor Clock Circuitry..........................................................................10-1 MC68340 USER'S MANUAL xv 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 TABLE OF CONTENTS (Concluded) Paragraph Number 10.1.2 10.1.3 10.1.4 10.1.5 10.2 10.2.1 10.2.2 10.2.3 10.2.4 Title Page Number 10.3 10.3.1 10.3.2 Reset Circuitry .............................................................................................10-3 SRAM Interface ...........................................................................................10-3 ROM Interface..............................................................................................10-4 Serial Interface............................................................................................10-4 Memory Interface Information.......................................................................10-5 Using an 8-Bit Boot ROM...........................................................................10-5 Access Time Calculations.........................................................................10-6 Calculating Frequency-Adjusted Output ................................................10-7 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode..................................................................10-10 Power Consumption Considerations..........................................................10-10 MC68340 Power Reduction at 5V ..........................................................10-11 MC68340V (3.3 V) .....................................................................................10-13 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 Section 11 Electrical Characteristics Maximum Rating .............................................................................................11-1 Thermal Characteristics.................................................................................11-1 Power Considerations ...................................................................................11-2 AC Electrical Specification Definitions .......................................................11-2 DC Electrical Specifications .........................................................................11-5 AC Electrical Specifications Control Timing..............................................11-6 AC Timing Specifications..............................................................................11-8 DMA Module AC Electrical Specifications.................................................11-19 Timer Module Electrical Specifications ......................................................11-20 Serial Module Electrical Specifications......................................................11-22 IEEE 1149.1 Electrical Specifications.........................................................11-25 Section 12 Ordering Information and Mechanical Data 12.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 Standard MC68340 Ordering Information .................................................12-1 Pin Assignment ...............................................................................................12-2 144-Lead Ceramic Quad Flat Pack (FE Suffix).....................................12-2 145-Lead Plastic Pin Grid Array (RP Suffix) ..........................................12-4 Package Dimensions.....................................................................................12-6 FE Suffix .......................................................................................................12-6 RP Suffix.......................................................................................................12-7 Index xvi MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS Figure Number Title Page Number 1-1 Block Diagram.........................................................................................................1-1 2-1 Functional Signal Groups .....................................................................................2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 Input Sample Window............................................................................................3-2 MC68340 Interface to Various Port Sizes..........................................................3-7 Long-Word Operand Read Timing from 8-Bit Port............................................3-11 Long-Word Operand Write Timing to 8-Bit Port.................................................3-12 Long-Word and Word Read and Write Timing—16-Bit Port ...........................3-13 Fast Termination Timing........................................................................................3-15 Word Read Cycle Flowchart .................................................................................3-16 Word Write Cycle Flowchart..................................................................................3-18 Read-Modify-Write Cycle Timing .........................................................................3-19 CPU Space Address Encoding............................................................................3-21 Breakpoint Operation Flowchart ..........................................................................3-24 Breakpoint Acknowledge Cycle Timing (Opcode Returned)..........................3-25 Breakpoint Acknowledge Cycle Timing (Exception Signaled) ......................3-26 Interrupt Acknowledge Cycle Flowchart.............................................................3-28 Interrupt Acknowledge Cycle Timing ..................................................................3-29 Autovector Operation Timing................................................................................3-31 Bus Error without DSACK≈ ...................................................................................3-35 Late Bus Error with DSACK≈ ................................................................................3-36 Retry Sequence ......................................................................................................3-37 Late Retry Sequence .............................................................................................3-38 HALT Timing............................................................................................................3-39 Bus Arbitration Flowchart for Single Request....................................................3-41 Bus Arbitration Timing Diagram—Idle Bus Case..............................................3-42 Bus Arbitration Timing Diagram—Active Bus Case .........................................3-42 Bus Arbitration State Diagram..............................................................................3-45 Show Cycle Timing Diagram................................................................................3-46 Timing for External Devices Driving RESET ......................................................3-47 Power-Up Reset Timing Diagram........................................................................3-48 4-1 4-2 4-3 4-4 SIM40 Module Register Block..............................................................................4-3 System Configuration and Protection Function ................................................4-5 Software Watchdog Block Diagram ....................................................................4-7 Clock Block Diagram for Crystal Operation .......................................................4-10 MOTOROLA MC68340 USER'S MANUAL xvii 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number 4-5 4-6 4-7 4-8 MC68340 Crystal Oscillator..................................................................................4-10 Clock Block Diagram for External Oscillator Operation...................................4-11 Full Interrupt Request Multiplexer........................................................................4-16 SIM40 Programming Model..................................................................................4-19 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 CPU32 Block Diagram...........................................................................................5-3 Loop Mode Instruction Sequence .......................................................................5-3 User Programming Model.....................................................................................5-9 Supervisor Programming Model Supplement ..................................................5-9 Status Register........................................................................................................5-10 Instruction Word General Format.........................................................................5-12 Table Example 1.....................................................................................................5-30 Table Example 2.....................................................................................................5-31 Table Example 3.....................................................................................................5-33 Exception Stack Frame..........................................................................................5-42 Reset Operation Flowchart....................................................................................5-45 Format $0—Four-Word Stack Frame..................................................................5-60 Format $2—Six-Word Stack Frame ....................................................................5-60 Internal Transfer Count Register..........................................................................5-61 Format $C—BERR Stack for Prefetches and Operands..................................5-62 Format $C—BERR Stack on MOVEM Operand................................................5-62 Format $C—Four- and Six-Word BERR Stack..................................................5-63 In-Circuit Emulator Configuration ........................................................................5-64 Bus State Analyzer Configuration .......................................................................5-64 BDM Block Diagram...............................................................................................5-65 BDM Command Execution Flowchart.................................................................5-68 Debug Serial I/O Block Diagram..........................................................................5-70 Serial Interface Timing Diagram..........................................................................5-71 BKPT Timing for Single Bus Cycle......................................................................5-72 BKPT Timing for Forcing BDM .............................................................................5-72 BKPT/DSCLK Logic Diagram ..............................................................................5-72 Command-Sequence Diagram............................................................................5-75 Functional Model of Instruction Pipeline ............................................................5-87 Instruction Pipeline Timing Diagram...................................................................5-88 Block Diagram of Independent Resources ........................................................5-90 Simultaneous Instruction Execution....................................................................5-91 Attributed Instruction Times...................................................................................5-92 Example 1—Instruction Stream ...........................................................................5-95 Example 2—Branch Taken...................................................................................5-95 Example 2—Branch Not Taken............................................................................5-96 Example 3—Branch Negative Tail ......................................................................5-96 xviii MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 DMA Block Diagram...............................................................................................6-1 Single-Address Transfers .....................................................................................6-3 Dual-Address Transfer...........................................................................................6-3 DMA External Connections to Serial Module....................................................6-6 Single-Address Read Timing (External Burst) ..................................................6-8 Single-Address Read Timing (Cycle Steal).......................................................6-9 Single-Address Write Timing (External Burst)...................................................6-10 Single-Address Write Timing (Cycle Steal).......................................................6-11 Dual-Address Read Timing (External Burst—Source Requesting)...............6-13 Dual-Address Read Timing (Cycle Steal—Source Requesting)...................6-14 Dual-Address Write Timing (External Burst—Destination Requesting)........6-16 Dual-Address Write Timing (Cycle Steal—Destination Requesting)............6-17 Fast Termination Option (Cycle Steal)................................................................6-21 Fast Termination Option (External Burst—Source Requesting) ....................6-22 DMA Module Programming Model......................................................................6-23 Packing and Unpacking of Operands.................................................................6-35 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 Simplified Block Diagram......................................................................................7-1 External and Internal Interface Signals ..............................................................7-5 Baud Rate Generator Block Diagram..................................................................7-8 Transmitter and Receiver Functional Diagram.................................................. 7-9 Transmitter Timing Diagram .................................................................................7-10 Receiver Timing Diagram......................................................................................7-12 Looping Modes Functional Diagram...................................................................7-15 Multidrop Mode Timing Diagram .........................................................................7-16 Serial Module Programming Model....................................................................7-19 Serial Module Programming Flowchart..............................................................7-41 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 Simplified Block Diagram......................................................................................8-1 Timer Functional Diagram.....................................................................................8-3 External and Internal Interface Signals ..............................................................8-5 Input Capture/Output Compare Mode.................................................................8-7 Square-Wave Generator Mode............................................................................8-8 Variable Duty-Cycle Square-Wave Generator Mode ......................................8-10 Variable-Width Single-Shot Pulse Generator Mode........................................8-11 Pulse-Width Measurement Mode ........................................................................8-12 Period Measurement Mode ..................................................................................8-14 Event Count Mode..................................................................................................8-15 Timer Module Programming Model.....................................................................8-18 9-1 9-2 Test Access Port Block Diagram..........................................................................9-2 TAP Controller State Machine..............................................................................9-3 MOTOROLA MC68340 USER'S MANUAL xix 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 LIST OF ILLUSTRATIONS (Continued) Figure Number 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Title Page Number Output Latch Cell (O.Latch)...................................................................................9-7 Input Pin Cell (I.Pin)................................................................................................9-7 Active-High Output Control Cell (IO.Ctl1)...........................................................9-8 Active-Low Output Control Cell (IO.Ctl0)............................................................9-8 Bidirectional Data Cell (IO.Cell)...........................................................................9-9 General Arrangement for Bidirectional Pins......................................................9-9 Bypass Register ......................................................................................................9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 Minimum System Configuration Block Diagram.............................................10-1 Sample Crystal Circuit.........................................................................................10-2 Statek Corporation Crystal Circuit.....................................................................10-2 XFC and VCCSYN Capacitor Connections........................................................10-3 SRAM Interface .....................................................................................................10-3 ROM Interface........................................................................................................10-4 Serial Interface......................................................................................................10-5 External Circuitry for 8-Bit Boot ROM ................................................................10-5 8-Bit Boot ROM Timing.........................................................................................10-6 Access Time Computation Diagram..................................................................10-6 Signal Relationships to CLKOUT ......................................................................10-7 Signal Width Specifications................................................................................10-8 Skew between Two Outputs...............................................................................10-9 Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in Single-Address DMA Mode..............................................................................10-10 10-15 MC68340 Current vs. Activity at 5 V..................................................................10-11 10-16 MC68340 Current vs. Voltage/Temperature....................................................10-12 10-17 MC68340 Current vs. Clock Frequency at 5 V................................................10-12 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 xx Drive Levels and Test Points for AC Specifications.......................................11-4 Read Cycle Timing Diagram...............................................................................11-11 Write Cycle Timing Diagram...............................................................................11-12 Fast Termination Read Cycle Timing Diagram ...............................................11-13 Fast Termination Write Cycle Timing Diagram................................................11-14 Bus Arbitation Timing—Active Bus Case .........................................................11-15 Bus Arbitration Timing—Idle Bus Case ............................................................11-16 Show Cycle Timing Diagram..............................................................................11-16 IACK Cycle Timing Diagram...............................................................................11-17 Background Debug Mode Serial Port Timing .................................................11-18 Background Debug Mode FREEZE Timing .....................................................11-18 DMA Signal Timing Diagram..............................................................................11-19 Timer Module Clock Signal Timing Diagram ..................................................11-20 Timer Module Signal Timing Diagram..............................................................11-21 Serial Module General Timing Diagram ..........................................................11-22 MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS (Concluded) Figure Number 11-16 11-17 11-18 11-19 11-20 11-21 Title Page Number Serial Module Asynchronous Mode Timing (X1)............................................11-23 Serial Module Asynchronous Mode Timing (SCLK–16X)............................11-23 Serial Module Synchronous Mode Timing Diagram .....................................11-23 Test Clock Input Timing Diagram.......................................................................11-25 Boundary Scan Timing Diagram .......................................................................11-26 Test Access Port Timing Diagram......................................................................11-26 MOTOROLA MC68340 USER'S MANUAL xxi 11/2/95 SECTION 1: OVERVIEW UM Rev.1.0 LIST OF TABLES Table Number Title Page Number 2-1 2-2 2-3 2-4 2-5 Signal Index.............................................................................................................2-2 Address Space Encoding .....................................................................................2-5 DSACK≈ Encoding.................................................................................................2-6 SIZx Signal Encoding............................................................................................2-7 Signal Summary.....................................................................................................2-14 3-1 3-2 3-3 3-4 SIZx Signal Encoding............................................................................................3-3 Address Space Encoding .....................................................................................3-3 DSACK≈ Encoding.................................................................................................3-5 DSACK≈, BERR, and HALT Assertion Results..................................................3-33 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 Clock Operating Modes.........................................................................................4-9 System Frequencies from 32.768-kHz Reference............................................4-13 Clock Control Signals............................................................................................4-13 Port A Pin Assignment Register ...........................................................................4-15 Port B Pin Assignment Register ...........................................................................4-16 SHENx Control Bits................................................................................................4-22 Deriving Software Watchdog Timeout................................................................4-25 BMTx Encoding.......................................................................................................4-26 PIRQL Encoding......................................................................................................4-26 DDx Encoding .........................................................................................................4-32 PSx Encoding..........................................................................................................4-32 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 Instruction Set..........................................................................................................5-6 Instruction Set Summary.......................................................................................5-16 Condition Code Computations.............................................................................5-20 Data Movement Operations..................................................................................5-21 Integer Arithmetic Operations...............................................................................5-23 Logic Operations.....................................................................................................5-24 Shift and Rotate Operations..................................................................................5-25 Bit Manipulation Operations .................................................................................5-25 Binary-Coded Decimal Operations .....................................................................5-26 Program Control Operations.................................................................................5-26 System Control Operations...................................................................................5-28 Condition Tests .......................................................................................................5-29 Standard Usage Entries........................................................................................5-30 Compressed Table Entries ...................................................................................5-32 xxii MC68340 USER'S MANUAL MOTOROLA 11/2/95 SECTION 1: OVERVIEW UM Rev 1 LIST OF TABLES (Continued) Table Number Title Page Number 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 8-Bit Independent Variable Entries .....................................................................5-33 Exception Vector Assignments.............................................................................5-40 Exception Priority Groups......................................................................................5-43 Tracing Control........................................................................................................5-50 BDM Source Summary..........................................................................................5-67 Polling the BDM Entry Source..............................................................................5-68 CPU Generated Message Encoding...................................................................5-70 Size Field Encoding...............................................................................................5-74 BDM Command Summary....................................................................................5-77 Register Field for RSREG and WSREG..............................................................5-79 6-1 6-2 6-3 6-4 6-5 6-6 FRZx Control Bits ....................................................................................................6-24 SSIZEx Encoding ...................................................................................................6-28 DSIZEx Encoding ...................................................................................................6-29 REQx Encoding.......................................................................................................6-29 BBx Encoding and Bus Bandwidth......................................................................6-29 Address Space Encoding .....................................................................................6-32 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 FRZx Control Bits ....................................................................................................7-20 PMx and PT Control Bits........................................................................................7-23 B/Cx Control Bits.....................................................................................................7-24 RCSx Control Bits...................................................................................................7-26 TCSx Control Bits ...................................................................................................7-27 MISCx Control Bits .................................................................................................7-28 TCx Control Bits ......................................................................................................7-29 RCx Control Bits......................................................................................................7-30 CMx Control Bits .....................................................................................................7-38 SBx Control Bits......................................................................................................7-39 8-1 8-2 8-3 8-4 8-5 8-6 OCx Encoding .........................................................................................................8-17 FRZx Control Bits ....................................................................................................8-19 IEx Encoding............................................................................................................8-21 POTx Encoding .......................................................................................................8-22 MODEx Encoding ...................................................................................................8-22 OCx Encoding .........................................................................................................8-22 9-1 9-2 9-3 Boundary Scan Control Bits .................................................................................9-4 Boundary Scan Bit Definitions .............................................................................9-5 Instructions...............................................................................................................9-10 10-1 10-2 Memory Access Times at 16.78 MHz................................................................10-7 Typical Electrical Characteristics.......................................................................10-13 MOTOROLA MC68340 USER'S MANUAL xxiii SECTION 1 DEVICE OVERVIEW The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing. Systems requiring very high-speed block transfers of data can especially benefit from the MC68340. The MC68340's high level of functional integration results in significant reductions in component count, power consumption, board space, and cost while yielding much higher system reliability and shorter design time. The 3.3-V MC68340V is particularly attractive to applications requiring a very tight power budget. Complete code compatibility with the MC68000 and MC68010 affords the designer access to a broad base of established realtime kernels, operating systems, languages, applications, and development tools—many oriented towards embedded control. SYSTEM INTEGRATION MODULE (SIM40) SYSTEM PROTECTION TWOCHANNEL SERIAL I/O CPU32 68020– BASED PROCESSOR CHIP SELECTS AND WAIT STATES CLOCK SYNTHESIZER INTERMODULE BUS EXTERNAL BUS INTERFACE BUS ARBITRATION TWO-CHANNEL DMA CONTROLLER TIMER TIMER IEEE TEST Figure 1-1. Block Diagram MOTOROLA MC68340 USER’S MANUAL 1-1 The primary features of the MC68340, illustrated in Figure 1-1, are as follows: • High Functional Integration on a Single Piece of Silicon • CPU32—MC68020-Derived 32-Bit Central Processor Unit — Upward Object-Code Compatible with MC68000 and MC68010 — Additional MC68020 Instructions and Addressing Modes — Unique Embedded Control Instructions — Fast Two-Clock Register Instructions—10,045 Dhrystones • Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers — Single- or Dual-Address Transfers — 32-Bit Addresses and Counters — 8-, 16-, and 32-Bit Data Transfers — 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory) • Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART) — Baud Rate Generators — Modem Control — MC68681/MC2681 Compatible — 9.8 Mbits/Sec Maximum Transfer Rate • Two Independent Counter/Timers — 16-Bit Counter — Up to 8-Bit Prescaler — Multimode Operation — 80-ns Resolution • System Integration Module Incorporates Many Functions Typically Relegated to External PALs, TTL, and ASIC, such as: — System Configuration — External Bus Interface — System Protection — Periodic Interrupt Timer — Chip Select and Wait State Generation — Interrupt Response — Clock Generation — Bus Arbitration — Dynamic Bus Sizing — IEEE 1149.1 Boundary Scan (JTAG) — Up to 16 Discrete I/O Lines — Power-On Reset • 32 Address Lines, 16 Data Lines • Power Consumption Control — Static HCMOS Technology Reduces Power in Normal Operation — Low Voltage Operation at 3.3 V ±0.3 V (MC68340V only) — Programmable Clock Generator Throttles Frequency — Unused Peripherals Can Be Turned Off — LPSTOP Provides an Idle State for Lowest Standby Current • 0–16.78 MHz or 0–25.16 MHz Operation • 144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA) As a low voltage part, the MC68340V can operate with a 3.3-V power supply. MC68340 is used throughout this manual to refer to both the low voltage and standard 5-V parts since both are functionally equivalent. 1.1 M68300 FAMILY The MC68340 is one of a series of components in the M68300 family. Other members of the family include the MC68302, MC68330, MC68331, MC68332, and MC68333. 1-2 MC68340 USER’S MANUAL MOTOROLA 1.1.1 Organization The M68300 family of integrated processors and controllers is built on an M68000 core processor, an on-chip bus, and a selection of intelligent peripherals appropriate for a set of applications. The CPU32 is a powerful central processor with nearly the performance of the MC68020. A system integration module incorporates the external bus interface and many of the smaller circuits that typically surround a microprocessor for address decoding, wait-state insertion, interrupt prioritization, clock generation, arbitration, watchdog timing, and power-on reset timing. Each member of the M68300 family is distinguished by its selection of peripherals. Peripherals are chosen to address specific applications but are often useful in a wide variety of applications. The peripherals may be highly sophisticated timing or protocol engines that have their own processors, or they may be more traditional peripheral functions, such as UARTs and timers. Since each major function is designed in a standalone module, each module might be found in many different M68300 family parts. Driver software written for a module on one M68300 part can be used to run the same module that appears on another part. 1.1.2 Advantages By incorporating so many major features into a single M68300 family chip, a system designer can realize significant savings in design time, power consumption, cost, board space, pin count, and programming. The equivalent functionality can easily require 20 separate components. Each component might have 16–64 pins, totaling over 350 connections. Most of these connections require interconnects or are duplications. Each connection is a candidate for a bad solder joint or misrouted trace. Each component is another part to qualify, purchase, inventory, and maintain. Each component requires a share of the printed circuit board. Each component draws power—often to drive large buffers to get the signal to another chip. The cumulative power consumption of all the components must be available from the power supply. The signals between the CPU and a peripheral might not be compatible nor run from the same clock, requiring time delays or other special design considerations. In a M68300 family component, the major functions and glue logic are all properly connected internally, timed with the same clock, fully tested, and uniformly documented. Power consumption stays well under a watt, and a special standby mode drops current well under a milliamp during idle periods. Only essential signals are brought out to pins. The primary package is the surface-mount quad flat pack for the smallest possible footprint; pin grid arrays are also available. 1.2 CENTRAL PROCESSOR UNIT The CPU32 is a powerful central processor that supervises system functions, makes decisions, manipulates data, and directs I/O. A special debugging mode simplifies processor emulation during system debug. MOTOROLA MC68340 USER’S MANUAL 1-3 1.2.1 CPU32 The CPU32 is an M68000 family processor specially designed for use as a 32-bit core processor and for operation over the intermodule bus (IMB). Designers used the MC68020 as a model and included advances of the later M68000 family processors, resulting in an instruction execution performance of 4 MIPS (VAX-equivalent) at 25.16 MHz. The powerful and flexible M68000 architecture is the basis of the CPU32. MC68000 (including the MC68HC000 and the MC68EC000) and MC68010 user programs will run unmodified on the CPU32. The programmer can use any of the eight 32-bit data registers for fast manipulation of data and any of the eight 32-bit address registers for indexing data in memory. The CPU32 can operate on data types of single bits, binary-coded decimal (BCD) digits, and 8, 16, and 32 bits. Peripherals and data in memory can reside anywhere in the 4-Gbyte linear address space. A supervisor operating mode protects system-level resources from the more restricted user mode, allowing a true virtual environment to be developed. Flexible instructions for data movement, arithmetic functions, logical operations, shifts and rotates, bit set and clear, conditional and unconditional program branches, and overall system control are supported, including a fast 32 × 32 multiply and 32-bit conditional branches. New instructions, such as table lookup and interpolate and low power stop, support the specific requirements of embedded control applications. Many addressing modes complement these instructions, including predecrement and postincrement, which allow simple stack and queue maintenance and scaled indexed for efficient table accesses. Data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes. Position-independent code is easily written. The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most instructions execute in one-half the number of clocks compared to the original MC68000, yielding an overall 1.6 times the performance of the same-speed MC68000 and measuring 10,045 Dhrystones/sec @ 25.16 MHz (6,742 Dhrystones/sec @ 16.78 MHz). Like all M68000 family processors, the CPU32 recognizes interrupts of seven different priority levels and allows the peripheral to vector the processor to the desired service routine. Internal trap exceptions ensure proper instruction execution with good addresses and data, allow operating system intervention in special situations, and permit instruction tracing. Hardware signals can either terminate or rerun bad memory accesses before instructions process data incorrectly. The CPU32 offers the programmer full 32-bit data processing performance with complete M68000 compatibility, yet with more compact code than is available with RISC processors. The CPU32 is identical in all CPU32-based M68300 family products. 1.2.2 Background Debug Mode A special operating mode is available in the CPU32 in which normal instruction execution is suspended while special on-chip microcode performs the functions of a debugger. 1-4 MC68340 USER’S MANUAL MOTOROLA Commands are received over a dedicated, high-speed, full-duplex serial interface. Commands allow the manual reading or writing of CPU32 registers, reading or writing of external memory locations, and diversion to user-specified patch code. This background debug mode permits a much simpler emulation environment while leaving the processor chip in the target system, running its own debugging operations. 1.3 ON-CHIP PERIPHERALS To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller, a serial module, and two timers. The processor communicates with these modules over the on-chip intermodule bus (IMB). This backbone of the chip is similar to traditional external buses with address, data, clock, interrupt, arbitration, and handshake signals. Because bus masters (like the CPU32 and DMA), peripherals, and the SIM40 are all on the chip, the IMB ensures that communication between these modules is fully synchronized and that arbitration and interrupts can be handled in parallel with data transfers, greatly improving system performance. Internal accesses across the IMB may be monitored from outside of the chip, if desired. Each module operates independently. No direct connections between peripheral modules are made inside the chip; however, external connections could, for instance, link a serial output to a DMA control line. Modules and their registers are accessed in the memory map of the CPU32 (and DMA) for easy access by general M68000 instructions and are relocatable. Each module may be assigned its own interrupt level, response vector, and arbitration priority. Since each module is a self-contained design and adheres to the IMB interface specifications, the modules may appear on other M68300 family products, retaining the investment in the software drivers for the module. 1.3.1 System Integration Module The MC68340 SIM40 provides the external bus interface for both the CPU32 and the DMA. It also eliminates much of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. The SIM40 provides programmable circuits to perform address decoding and chip selects, wait-state insertion, interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O, and power-on reset timing. A boundary scan test capability is also provided. 1.3.1.1 EXTERNAL BUS INTERFACE. The external bus interface (EBI) handles the transfer of information between the internal CPU32 or DMA controller and memory, peripherals, or other processing elements in the external address space. Based on the MC68030 bus, the external bus provides up to 32 address lines and 16 data lines. Address extensions identify each bus cycle as CPU32 or DMA initiated, supervisor or user privilege level, and instruction or data access. The data bus allows dynamic sizing for 8- or 16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers from the CPU32 or the DMA can be made in as little as two clock cycles. Asynchronous transfers allow the MOTOROLA MC68340 USER’S MANUAL 1-5 memory system to signal the CPU32 or DMA when the transfer is complete and to note the number of bits in the transfer. An external master can arbitrate for the bus using a three-line handshaking interface. 1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. System configuration and various monitors and timers are provided in the MC68340. Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system does not lock up when there is no response to a memory access. The bus fault monitor can reset the processor when a catastrophic bus failure occurs. Spurious interrupts are detected and handled appropriately. A software watchdog can pull the processor out of an infinite loop. An interrupt can be sent to the CPU32 with programmable regularity for DRAM refresh, time-of-day clock, task switching, etc. 1.3.1.3 CLOCK SYNTHESIZER. The clock synthesizer generates the clock signals used by all internal operations as well as a clock output used by external devices. The clock synthesizer can operate with an inexpensive 32768-Hz watch crystal or an external oscillator for reference, using an internal phase-locked loop and voltage-controlled oscillator. At any time, software can select clock frequencies from 131 kHz to 16.78 MHz or 25.16 MHz, favoring either low power consumption or high performance. Alternately, an external clock can drive the clock signal directly at the operating frequency. With its fully static HCMOS design, it is possible to completely stop the system clock without losing the contents of the internal registers. 1.3.1.4 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip selects provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals with up to 175-ns access times with a 25-MHz system clock (265 ns @ 16.78 MHz). Each chip select signal has an associated base address and an address mask that determine the addressing characteristics of that chip select. Address space and write protection can be selected for each. The block size can be selected from 256 bytes up to 4 Gbytes in increments of 2 n. Accesses can be preselected for either 8- or 16-bit transfers. Fast synchronous termination or up to three wait states can be programmed, whether or not the chip select signals are used. External handshakes can also signal the end of a bus transfer. A system can boot from reset out of 8-bit-wide memory, if desired. 1.3.1.5 INTERRUPT HANDLING. Seven input signals are provided to trigger an external interrupt, one for each of the seven priority levels supported. Seven separate outputs can indicate the priority level of the interrupt being serviced. An input can direct the processor to a default service routine, if desired. Interrupts at each priority level can be preprogrammed to go to the default service routine. For maximum flexibility, interrupts can be vectored to the correct service routine by the interrupting device. 1.3.1.6 DISCRETE I/O PINS. When not used for other functions, 16 pins can be programmed as discrete input or output lines. Additionally, in other peripheral modules, pins for otherwise unused functions can often be used for general input/output. 1-6 MC68340 USER’S MANUAL MOTOROLA 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). 1.3.2 Direct Memory Access Module The most distinguishing MC68340 characteristic is the high-speed 32-bit DMA controller, used to quickly move large blocks of data between internal peripherals, external peripherals, or memory without processor intervention. The DMA module consists of two, independent, programmable channels. Each channel has separate request, acknowledge, and done signals. Each channel can operate in a single-address or a dual-address (flyby) mode. In single-address mode, only one (the source or the destination) address is provided, and a peripheral device such as a serial communications controller receives or supplies the data. An external request must start a single-address transfer. In this mode, each channel supports 32 bits of address and 8, 16, or 32 bits of data. In dual-address mode, two bus transfers occur, one from a source device and the other to a destination device. Dual-address transfers can be started by either an internal or external request. In this mode, each channel supports 32 bits of address and 8 or 16 bits of data (32 bits require external logic). The source and destination port size can be selected independently; when they are different, the data will be packed or unpacked. An 8-bit disk interface can be read twice before the concatenated 16-bit result is passed into memory. Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and transfer counters are 32 bits. Addresses increment or remain constant, as programmed. The DMA channels support two external request modes, burst transfer and cycle steal. Internal requests can be programmed to occupy 25, 50, 75, or 100 percent of the data bus bandwidth. Interrupts can be programmed to postpone DMA completion. The DMA module can sustain a transfer rate of 12.5 Mbytes/sec in dual-address mode and nearly 50 Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec @ 16.78 MHz, respectively). The DMA controller arbitrates with the CPU32 for the bus in parallel with existing bus cycles and is fully synchronized with the CPU32, eliminating all delays normally associated with bus arbitration by allowing DMA bus cycles to butt seamlessly with CPU bus cycles. 1.3.3 Serial Module Most digital systems use serial I/O to communicate with host computers, operator terminals, or remote devices. The MC68340 contains a two-channel, full-duplex USART. An on-chip baud rate generator provides standard baud rates up to 76.8k baud independently to each channel's receiver and transmitter. The module is functionally equivalent to the MC68681/MC2681 DUART. MOTOROLA MC68340 USER’S MANUAL 1-7 Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided on each channel. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be selected. Multidrop applications are supported. A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel can be programmed for a different baud rate, or an external 1 × and 16× clock input can be selected. Full modem support is provided with separate request-to-send (RTS) and clearto-send (CTS) signals for each channel. One channel also provides service request signals. The two serial ports can sustain rates of 9.8 Mbps with a 25-MHz system clock in 1× mode, 612 kbps in 16× mode (6.5 Mbps and 410 kbps @ 16.78 MHz). 1.3.4 Timer Modules Timers and counters are used in a system to monitor elapsed time, generate waveforms, measure signals, keep time-of-day clocks, initiate DRAM refresh cycles, count events, and provide “time slices” to ensure that no task dominates the activity of the processor. A counter that counts clock pulses makes a timer, which is most useful when it causes certain actions to occur in response to reaching desired counts. The MC68340 has two, identical, versatile, on-chip counter/timers as well as a simple timer in the SIM40. These general-purpose counter/timers can be used for precisely timed events without the errors to which software-based counters and timers are susceptible— e.g., errors caused by dynamic memory refreshing, DMA cycle steals, and interrupt servicing. The programmable timer operating modes are input capture, output compare, square-wave generation, variable duty-cycle square-wave generation, variable-width single-shot pulse generation, event counting, period measurement, and pulse-width measurement. Each timer consists of a 16-bit countdown counter with an 8-bit countdown prescaler for a composite 24-bit resolution. The two timers can be externally cascaded for a maximum count width of 48 bits. The counter/timer can be clocked by the internal system clock generated by the SIM40 (÷2) or by an external clock input. Either the processor or external stimuli can trigger the starting and stopping of the counter. When a counter reaches a predetermined value, either an external output signal can be driven, or an interrupt can be made to the CPU32. The finest resolution of the timer is 80 ns with a 25-MHz system clock (125 ns @ 16.78 MHz). 1.4 POWER CONSUMPTION MANAGEMENT The MC68340 is very power efficient due to its advanced 0.8-µ HCMOS process technology and its static logic design. The resulting power consumption is typically 900 mW in full operation @ 25 MHz (650 mW @ 16.78 MHz)—far less than the comparable discrete component implementation the MC68340 can replace. For applications employing reduced voltage operation, selection of the MC68340V, which 1-8 MC68340 USER’S MANUAL MOTOROLA requires only a 3.3-V power supply, reduces current consumption by 40–60% in all modes of operation (as well as reducing noise emissions). The MC68340 has many additional methods of dynamically controlling power consumption during operation. The frequency of operation can be lowered under software control to reduce current consumption when performance is less critical. Idle internal peripheral modules can be turned off to save power (5–10% each). Running a special low power stop (LPSTOP) instruction shuts down the active circuits in the CPU and peripheral modules, halting instruction execution. Power consumption in this standby mode is reduced to about 350 µW. Processing and power consumption can be resumed by resetting the part or by generating an interrupt with the SIM40's periodic interrupt timer. 1.5 PHYSICAL The MC68340 is available as 0–16.78 MHz and 0–25.16 MHz, 0°C to +70°C and -40°C to +85°C, and 5.0 V ±5% and 3.3 V ±0.3 supply voltages (reduced frequencies at 3.3 V) . Thirty-two power and ground leads minimize ground bounce and ensure proper isolation of different sections of the chip, including the clock oscillator. A 144 pins are used for signals and power. The MC68340 is available in a gull-wing ceramic quad flat pack (CQFP) with 25.6-mil (0.001-in) lead spacing or a 15 × 15 plastic pin grid array (PPGA) with 0.1-in pin spacing. 1.6 COMPACT DISC-INTERACTIVE The MC68340 was designed to meet the needs of many markets, including compact discinteractive (CD-I). CD-I is an emerging standard for a publishing medium that will bring multimedia to a broad general audience—the consumer. CD-I players combine television and stereo systems as output devices, with interactive control using a TV remote-controllike device to provide a multimedia experience selected from software “titles” contained in compressed form on standard compact discs. The highly integrated MC68340 is ideal as the central processor for CD-I players. It provides the M68000 microprocessor code compatibility and DMA functions required by the CD-I Green Book specification as well as many other useful on-chip functions for a very cost-effective solution. The extra demands of full-motion video CD-I systems make the best use of the MC68340 high performance. The MC68340 is CD-I compliant and has been CD-I qualified. With its low voltage operation, the MC68340V is the only practical choice for portable CD-I. MOTOROLA MC68340 USER’S MANUAL 1-9 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number BR1114/D MC68340/D MC68340UM/AD M68000PM/AD AN1063/D AN453 1-10 Document Name M68300 Integrated Processor Family MC68340 Technical Summary MC68340 User's Manual M68000 Family Programmer's Reference Manual DRAM Controller for the MC68340 Software Implementation of SPI on the MC68340 BR573/D M68340 Evaluation System Product Brief BR729/D The 68K Source BR1407/D 3.3 Volt Logic and Interface Circuits MC68340 USER’S MANUAL MOTOROLA SECTION 2 SIGNAL DESCRIPTIONS SCLK X2 X1 PORT A TCK TMS TDI TDO A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 A27/PORT A3/IACK3 A26/PORT A2/IACK2 A25/PORT A1/IACK1 A24/PORT A0 BKPT/DSCLK FREEZE IPIPE/DSO IFETCH/DSI This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1. TWO-CHANNEL SERIAL I/O CPU32 CORE TEST A23–A0 RxDA TxDA CTSA RxDB TxDB CTSB D15–D0 FC3–FC0 OUTPUT PORT SYSTEM INTEGRATION MODULE BUS ARBITRATION TIMER MODULE CLKOUT XFC XTAL EXTAL TIMER MODULE TGATE2 TIN2 TOUT2 CLOCK TWO-CHANNEL DMA CONTROLLER PORT B DREQ1 DACK1 DONE1 DREQ2 DACK2 DONE2 IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 CS3/IRQ4/PORT B4 CS2/IRQ2/PORT B2 CS1/IRQ1/PORT B1 CS0/AVEC MODCK/PORT B0 TxRDYA/OP6 RxRDYA/FFULLA/OP4 RTSB/OP1 RTSA/OP0 IMB TIN1 TOUT1 BR BG BGACK RMC EXTERNAL BUS INTERFACE TGATE1 RESET BERR HALT AS DS R/W SIZ1 SIZ0 DSACK1 DSACK0 Figure 2-1. Functional Signal Groups MOTOROLA MC68340 USER’S MANUAL 2-1 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics. Table 2-1. Signal Index Signal Name Address Bus Mnemonic Function A23–A0 Lower 24 bits of the address bus Input/ Output Out Address Bus/Port A7–A0/ Interrupt Acknowledge A31–A24 Upper eight bits of the address bus, parallel I/O port, or interrupt acknowledge lines Out/I/O/Out Data Bus D15–D0 The 16-bit data bus used to transfer byte or word data I/O Function Codes FC3–FC0 Identify the processor state and the address space of the current bus cycle Out Chip Select 3–1/ Interrupt Request Level/ Port B4, B2, B1 CS3–CS1 Enables peripherals at programmed addresses, interrupt priority level to the CPU32, or parallel I/O port Out/In/ I/O Chip Select 0/Autovector CS0 Enables peripherals at programmed addresses or requests an automatic vector Out/In Bus Request BR Indicates that an external device requires bus mastership Bus Grant BG Indicates that current bus cycle is complete and the MC68340 has relinquished the bus Out BGACK Indicates that an external device has assumed bus mastership In Provides asynchronous data transfers and dynamic bus sizing In Bus Grant Acknowledge Data and Size Acknowledge DSACK1, DSACK0 In RMC Identifies the bus cycle as part of an indivisible read modify-write operation Out Address Strobe AS Indicates that a valid address is on the address bus Out Data Strobe DS During a read cycle, DS indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that valid data is on the data bus. Out SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred for this cycle Out R/ W Indicates the direction of data transfer on the bus Out IRQ7, IRQ6, IRQ5, IRQ3 Provides an interrupt priority level to the CPU32 or becomes a parallel I/O port In/I/O Read-Modify-Write Cycle Size Read/Write Interrupt Request Level/ Port B7, B6, B5, B3 RESET System reset I/O Halt HALT Suspends external bus activity I/O Bus Error BERR Indicates an invalid bus operation is being attempted In Reset System Clock Crystal Oscillator External Filter Capacitor 2-2 CLKOUT System clock out EXTAL, XTAL XFC Connections for an external crystal or oscillator to the internal oscillator circuit Connection pin for an external capacitor to filter the circuit of the phase-locked loop MC68340 USER’S MANUAL Out In, Out In MOTOROLA Table 2-1. Signal Index (Continued) Signal Name Input/ Output Mnemonic Function MODCK Selects the source of the internal system clock upon reset or becomes a parallel I/O port In/I/O Instruction Fetch/ Development Serial In IFETCH/DSI Indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed or provides background debug mode serial in Out/In Instruction Pipe/ Development Serial Out IPIPE/DSO Used to track movement of words through the instruction pipeline or provides background debug mode serial out Out/Out Breakpoint/Development Serial Clock BKPT/DSCLK Signals a hardware breakpoint to the CPU32 or provides background debug mode serial clock In/— FREEZE Indicates that the CPU32 has entered background debug mode Out Out Clock Mode Select/ Port B0 Freeze Transmit Data TxDA, TxDB Transmitter serial data output from the serial module Clear-to-Send CTSA, CTSB Serial module clear-to-send inputs Request-to-Send/ OP1, OP0 RTSB, RTSA Channel request-to-send outputs or discrete outputs Serial Crystal Oscillator X1, X2 Connections for an external crystal to the serial module internal oscillator circuit Serial Clock SCLK External serial module clock input Transmitter Ready/OP6 T≈RDYA Indicates transmit buffer has a character or becomes a parallel output Receiver Ready/ FIFO Full/OP4 R≈RDYA Indicates receive buffer has a character, the receiver FIFO buffer is full or becomes a parallel output DMA Request DRE Input that starts a DMA process In Out/Out In Out/Out Out/Out/Out In Q2, DREQ1 DMA Acknowledge DACK2, DACK1 Output that signals an access during DMA Out DMA Done DONE2, DONE1 Bi-directional signal that indicates the last transfer I/O Timer Gate TGATE2, TGATE1 Counter enable input to timer In Timer Input TIN2, TIN1 Time reference input to timer In TOUT2, TOUT1 Output waveform from timer Out Timer Output Test Clock TCK Provides a clock for IEEE 1149.1 test logic In Test Mode Select TMS Controls test mode operations In Test Data In TDI Shifts in instructions and test data In Test Data Out TDO Shifts out instructions and test data Synchronizer Power System Power Supply and Ground MOTOROLA VCCSYN VCC , GND Out Quiet power supply to VCO; also used to control synthesizer mode after reset. — Power supply and ground to the MC68340 — MC68340 USER’S MANUAL 2-3 NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 2.2 ADDRESS BUS The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. The address bus consists of the following two groups. Refer to Section 3 Bus Operation for information on the address bus and its relationship to bus operation. 2.2.1 Address Bus (A23–A0) These three-state outputs (along with A31–A24) provide the address for the current bus cycle, except in the CPU address space. 2.2.2 Address Bus (A31–A24) These pins can be programmed as the most significant eight address bits, port A parallel I/O, or interrupt acknowledge signals. These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions. A31–A24 These pins can function as the most significant eight address bits. Port A7–A0 These eight pins can serve as a dedicated parallel I/O port. See Section 4 System Integration Module for more information on programming these pins. IACK7– IACK1 The MC68340 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the IACK≈ signals instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level. 2.3 DATA BUS (D15–D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the 2-4 MC68340 USER’S MANUAL MOTOROLA last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 2.4 FUNCTION CODES (FC3–FC0) These signals are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. The function code signals are valid while AS is asserted. See Table 2-2 for more information. Table 2-2. Address Space Encoding Function Code Bits 3 2 1 0 Address Spaces 0 0 0 0 Reserved (Motorola) 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved (User ) 0 1 0 0 Reserved (Motorola) 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space 2.5 CHIP SELECTS (CS3–CS0) These pins can be programmed to be chip select output signals, port B parallel I/O and autovector input, or additional interrupt request lines. Refer to Section 4 System Integration Module for more information on these signals. CS3– CS0 The chip select output signals enable peripherals at programmed addresses. These signals are inactive high (not high impedance) after reset. CS0 is the chip select for a boot ROM containing the reset vector and initialization program. It functions as the boot chip select immediately after reset. IRQ4, IRQ2, IRQ1 Interrupt request lines are external interrupt lines to the CPU32. These additional interrupt request lines are selected by the FIRQ bit in the module configuration register. MOTOROLA MC68340 USER’S MANUAL 2-5 Port B4, B2, B1, AVEC This signal group functions as three bits of parallel I/O and the autovector input. AVEC requests an automatic vector during an interrupt acknowledge cycle. 2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3) These pins can be programmed to be either prioritized interrupt request lines or port B parallel I/O. IRQ7, IRQ6, IRQ5, IRQ3 IRQ7 , the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines. Port B7, B6, B5, B3 These pins can be used as port B parallel I/O. Refer to Section 4 System Integration Module for more information on parallel I/O signals. 2.7 BUS CONTROL SIGNALS These signals control the bus transfer operations of the MC68340. Refer to Section 3 Bus Operation for more information on these signals. 2.7.1 Data and Size Acknowledge ( DSACK1, DSACK0) These two active-low input signals allow asynchronous data transfers and dynamic data bus sizing between the MC68340 and external devices as listed in Table 2-3. During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. Table 2-3. DSACK≈ Encoding DSACK 1 1 1 0 0 DSACK 0 1 0 1 0 Result Insert Wait States in Current Bus Cycle Complete Cycle—Data Bus Port Size Is 8 Bits Complete Cycle—Data Bus Port Size Is 16 Bits Reserved—Defaults to 16-Bit Port Size Can Be Used for 32-Bit DMA Cycles 2.7.2 Address Strobe ( AS) AS is an output timing signal that indicates the validity of both an address on the address bus and many control signals. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle. 2-6 MC68340 USER’S MANUAL MOTOROLA 2.7.3 Data Strobe (DS) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle. 2.7.4 Transfer Size (SIZ1, SIZ0) These output signals are driven by the bus master to indicate the number of operand bytes remaining to be transferred in the current bus cycle as noted in Table 2-4. Table 2-4. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Byte 0 0 Long Word 2.7.5 Read/Write (R/ W) This active-high output signal is driven by the bus master to indicate the direction of a data transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. 2.8 BUS ARBITRATION SIGNALS The following signals are the bus arbitration control signals used to determine the bus master. Refer to Section 3 Bus Operation for more information on these signals. 2.8.1 Bus Request (BR) This active-low input signal indicates that an external device needs to become the bus master. 2.8.2 Bus Grant (BG) Assertion of this active-low output signal indicates that the MC68340 has relinquished the bus. 2.8.3 Bus Grant Acknowledge (BGACK) Assertion of this active-low input indicates that an external device has become the bus master. MOTOROLA MC68340 USER’S MANUAL 2-7 2.8.4 Read-Modify-Write Cycle (RMC) This output signal identifies the bus cycle as part of an indivisible read-modify-write operation. It remains asserted during all bus cycles of the read-modify-write operation to indicate that bus ownership cannot be transferred. 2.9 EXCEPTION CONTROL SIGNALS These signals are used by the MC68340 to recover from an exception. 2.9.1 Reset ( RESET) This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM40) resets the MC68340 and all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices; the internal state of the CPU32 is not affected. The on-chip modules are reset, except for the SIM40. However, the module configuration register for each on-chip module is not altered. When asserted by the MC68340, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3 Bus Operation for a description of bus reset operation and Section 5 CPU32 for information about the reset exception. 2.9.2 Halt (HALT) This active-low, open-drain, bidirectional signal is asserted to suspend external bus activity, to request a retry when used with BERR, or to perform a single-step operation. As an output, HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus Operation for a description of the effects of HALT on bus operation. 2.9.3 Bus Error (BERR) This active-low input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to Section 3 Bus Operation for a description of the effects of BERR on bus operation. 2.10 CLOCK SIGNALS These signals are used by the MC68340 for controlling or generating the system clocks. See Section 4 System Integration Module for more information on the various clocking methods and frequencies. 2.10.1 System Clock (CLKOUT) This output signal is the system clock output and is used as the bus timing reference by external devices. CLKOUT can be varied in frequency or slowed in low power stop mode to conserve power. 2-8 MC68340 USER’S MANUAL MOTOROLA 2.10.2 Crystal Oscillator (EXTAL, XTAL) These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to EXTAL, with XTAL left open. 2.10.3 External Filter Capacitor (XFC) This pin is used to add an external capacitor to the filter circuit of the phase-locked loop. The capacitor should be connected between XFC and VCCSYN. 2.10.4 Clock Mode Select (MODCK) This pin selects the source of the internal system clock during reset. After reset, it can be programmed to be port B parallel I/O. MODCK The state of this active-high input signal during reset selects the source of the internal system clock. If MODCK is high during reset, the internal voltage-controlled oscillator (VCO) furnishes the system clock in crystal mode. If MODCK is low during reset, an external clock source at the EXTAL pin furnishes the system clock output in external clock mode. Port B0 This pin can be used as a port B parallel I/O. 2.11 INSTRUMENTATION AND EMULATION SIGNALS These signals are used for test or software debugging. See Section 5 CPU32 for more information on these signals and background debug mode. 2.11.1 Instruction Fetch (IFETCH) This pin functions as IFETCH in normal operation and as DSI in background debug mode. IFETCH This active-low output signal indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed. DSI This development serial input signal helps to provide serial communications for background debug mode. 2.11.2 Instruction Pipe (IPIPE) This pin functions as IPIPE in normal operation and as DSO in background debug mode. MOTOROLA MC68340 USER’S MANUAL 2-9 IPIPE This active-low output signal is used to track movement of words through the instruction pipeline. DSO This development serial output signal helps to provide serial communications for background debug mode. 2.11.3 Breakpoint (BKPT) This pin functions as BKPT in normal operation and as DSCLK in background debug mode. BKPT This active-low input signal is used to signal a hardware breakpoint to the CPU32. DSCLK This development serial clock input helps to provide serial communications for background debug mode. 2.11.4 Freeze (FREEZE) Assertion of this active-high output signal indicates that the CPU32 has acknowledged a breakpoint and has initiated background mode operation. 2.12 DMA MODULE SIGNALS The following signals are used by the direct memory access (DMA) controller module to provide external handshake for either a source or destination. See Section 6 DMA Module for additional information on these signals. 2.12.1 DMA Request (DREQ2, DREQ1) This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ≈ starts the DMA process. The assertion level in external burst mode is level sensitive; in external cycle steal mode, it is falling-edge sensitive. 2.12.2 DMA Acknowledge (DACK2, DACK1) This active-low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request. 2.12.3 DMA Done (DONE2, DONE1) This active-low bidirectional signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed. DONE≈ is an active input in any mode. As an output, it is only active in external request mode. An external pullup resistor is required even during operation in the internal request mode. 2-10 MC68340 USER’S MANUAL MOTOROLA 2.13 SERIAL MODULE SIGNALS The following signals are used by the serial module for data and clock signals. See Section 7 Serial Module for more information on these signals. 2.13.1 Serial Crystal Oscillator (X2, X1) These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock is connected to the X1 pin; X2 is left floating. 2.13.2 Serial External Clock Input (SCLK) This input can be used as the external clock input for channel A or channel B, bypassing the baud rate generator. 2.13.3 Receive Data (RxDA, RxDB) These signals are the receiver serial data input for each channel. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. 2.13.4 Transmit Data (TxDA, TxDB) These signals are the transmitter serial data output for each channel. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first. 2.13.5 Clear to Send (CTSA, CTSB) These active-low signals can be programmed as the clear-to-send inputs for each channel. 2.13.6 Request to Send (RTSA, RTSB) These active-low signals can be programmed as request-to-send outputs or used as discrete outputs. RTSB, RTSA When used for this function, these signals function as the request-to-send outputs. OP1, OP0 When used for this function, these outputs are controlled by the value of bit 1 and bit 0, respectively, in the output port data registers. 2.13.7 Transmitter Ready (T≈RDYA) This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output. MOTOROLA MC68340 USER’S MANUAL 2-11 T≈RDYA When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the output port data registers. 2.13.8 Receiver Ready (R≈RDYA) This active-low output signal can be programmed as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output. R≈RDYA When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character. FFULLA When used for this function, this signal reflects the complement of the status of bit 1 of the interrupt status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full. OP4 When used for this function, this output is controlled by bit 4 in the output port data registers. 2.14 TIMER SIGNALS The following external signals are used by the timer modules. See Section 8 Timer Modules for additional information on these signals. 2.14.1 Timer Gate (TGATE2, TGATE1) These active-low inputs can be programmed to enable and disable the counters and prescalers. TGATE≈ can also be programmed as a simple input. 2.14.2 Timer Input (TIN2, TIN1) These inputs can be programmed as clocks that cause events to occur in the counters and prescalers. 2.14.3 Timer Output (TOUT2, TOUT1) These outputs drive the various output waveforms generated by the timers. 2-12 MC68340 USER’S MANUAL MOTOROLA 2.15 TEST SIGNALS The following signals are used with the on-board test logic defined by the IEEE 1149.1 standard. See Section 9 IEEE 1149.1 Test Access Port for more information on the use of these signals. 2.15.1 Test Clock (TCK) This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard. 2.15.2 Test Mode Select (TMS) This input controls test mode operations for on-board test logic defined by the IEEE 1149.1 standard. 2.15.3 Test Data In (TDI) This input is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard. 2.15.4 Test Data Out (TDO) This output is used for serial test instructions and test data for on-board test logic defined by the IEEE 1149.1 standard. 2.16 SYNTHESIZER POWER (V CCSYN ) This pin supplies a quiet power source to the VCO to provide greater frequency stability. It is also used to control the synthesizer mode after reset. See Section 4 System Integration Module for more information. 2.17 SYSTEM POWER AND GROUND (V CC AND GND) These pins provide system power and ground to the MC68340. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 2.18 SIGNAL SUMMARY Table 2-5 presents a summary of all the signals discussed in the preceding paragraphs. MOTOROLA MC68340 USER’S MANUAL 2-13 Table 2-5. Signal Summary Signal Name Mnemonic Input/Output A23–A0 Out — Yes Address Bus Port A7–A0/ Interrupt Acknowledge A31–A24 Out/I/O/Out —/—/Low Yes Data Bus D15–D0 I/O — Yes Function Codes FC3–FC0 Out — Yes Chip Select 3/Interrupt Request Level/Port B4, B2, B1 CS3–CS1 Out/In/I/O Low/Low/— No CS0 Out/In Low/Low No Bus Request BR In Low — Bus Grant BG Out Low No BGACK In Low — DSACK1, DSACK0 In Low — RMC Out Low Yes Address Strobe AS Out Low Yes Data Strobe DS Out Low Yes SIZ1, SIZ0 Out — Yes R/ W Out High/Low Yes IRQ7, IRQ6, IRQ5, IRQ3 In/I/O Low/— — Reset RESET I/O Low No Halt HALT I/O Low No Bus Error BERR In Low — CLKOUT Out — No EXTAL, XTAL In, Out — — XFC In — — MODCK In/I/O —/— — Instruction Fetch/ Development Serial In IFETCH/DSI Out/In Low/— No/— Instruction Pipe/ Development Serial Out IPIPE/DSO Out/Out Low/— No/— BKPT/DSCLK In/In Low/— —/— FREEZE Out High No RxDA, RxDB In — — Address Bus Chip Select 0/Autovector Bus Grant Acknowledge Data and Size Acknowledge Read-Modify-Write Cycle Size Read/Write Interrupt Request Level/ Port B7, B6, B5, B3 System Clock Crystal Oscillator External Filter Capacitor Clock Mode Select/Port B0 Breakpoint/ Development Serial Clock Freeze Receive Data 2-14 MC68340 USER’S MANUAL Active State Three-State MOTOROLA Table 2-5. Signal Summary (Continued) Signal Name Mnemonic Input/Output Active State Three-State Transmit Data TxDA, TxDB Out — No Clear-to-Send CTSA, CTSB In Low — Request-to-Send/ OP1, OP0 RTSB, RTSA Out/Out Low/— No SCLK In — — Transmitter Ready/OP6 T≈RDYA Out/Out Low/— No Receiver Ready/ FIFO Full/OP4 R≈RDYA Out/Out/Out Low/Low/— No DMA Request DREQ2, DREQ1 In Low — DMA Acknowledge DACK2, DACK1 Out Low No DMA Done DONE2, DONE1 I/O Low No Timer Gate TGATE2, TGATE1 In Low — Timer Input TIN2, TIN1 In — — TOUT2, TOUT1 Out — Yes Test Clock TCK In — — Test Mode Select TMS In High — TDI In High — TDO Out High — VCCSYN – — — VCC , GND – — — Serial Clock Timer Output Test Data In Test Data Out Synchronizer Power System Power Supply and Return MOTOROLA MC68340 USER’S MANUAL 2-15 SECTION 3 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68340 or an external device is the bus master; the names and descriptions of bus cycles are from the viewpoint of the bus master. For exact timing specifications, refer to Section 11 Electrical Characteristics. The MC68340 architecture supports byte, word, and long-word operands allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the SIZ1/SIZ0 outputs and DSACK1/DSACK0 inputs. The MC68340 requires word and longword operands to be located in memory on word boundaries. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. For an 8-bit port, multiple bus cycles may be required for an operand transfer due to either misalignment or a word or long-word operand. 3.1 BUS TRANSFER SIGNALS The bus transfers information between the MC68340 and external memory or a peripheral device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. Both asynchronous and synchronous operation is possible for any port width. In asynchronous operation, the bus and control input signals are internally synchronized to the MC68340 clock, introducing a delay. This delay is the time required for the MC68340 to sample an input signal, synchronize the input to the internal clocks, and determine whether it is high or low. In synchronous mode, the bus and control input signals must be timed to setup and hold times. Since no synchronization is needed, bus cycles can be completed in three clock cycles in this mode. Additionally, using the fast-termination option of the chip select signals, two-clock operation is possible. Furthermore, for all inputs, the MC68340 latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 3-1, where t su and t h are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during MOTOROLA MC68340 USER’S MANUAL 3-1 the sample window. If an input makes a transition during the window time period, the level recognized by the MC68340 is not predictable; however, the MC68340 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. t su th CLKOUT EXT SAMPLE WINDOW Figure 3-1. Input Sample Window NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 3.1.1 Bus Control Signals The MC68340 initiates a bus cycle by driving the A31–A0, SIZx, FCx, and R/W outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with FC3–FC0. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 3-1 lists the encoding of the SIZx signal. These signals are valid while AS is asserted. The R/ W signal determines the direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/ W is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. 3-2 MC68340 USER’S MANUAL MOTOROLA Table 3-1. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Bytes 0 0 Long Word 3.1.2 Function Code Signals FC3–FC0 are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. FC3–FC0 are valid while AS is asserted. Function codes (see Table 3-2) can be considered as extensions of the 32-bit address that can provide up to 16 different 4-Gbyte address spaces. Function codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels, a CPU address space for processor functions, and an alternate master address space. User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information. The S-bit in the CPU32 status register is set for supervisor accesses and cleared for user accesses to provide differentiation. Refer to 3.4 CPU Space Cycles for more information. Table 3-2. Address Space Encoding Function Code Bits MOTOROLA 3 2 1 0 Address Spaces 0 0 0 0 Reserved (Motorola) 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved (User ) 0 1 0 0 Reserved (Motorola) 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space MC68340 USER’S MANUAL 3-3 3.1.3 Address Bus (A31–A0) These signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. 3.1.4 Address Strobe ( AS) This output timing signal indicates the validity of many control signals and the address on the address bus. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle. 3.1.5 Data Bus (D15–D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 3.1.6 Data Strobe (DS) DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle. 3.1.7 Bus Cycle Termination Signals The following signals can terminate a bus cycle. 3.1.7.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS ( DSACK1 AND DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer to 3.3.1 Read Cycle for timing relationships of DSACK1 and DSACK0. Additionally, the system integration module (SIM40) chip select address mask register can be programmed to internally generate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate these signals. However, if external DSACK≈ signals are returned earlier than indicated by the DD bits in the chip select address mask register, the cycle will terminate sooner than programmed. Refer to Section 4 System Integration Module for additional information. The SIM40 can alternatively be programmed to generate a fast termination cycle, providing a two-cycle external access. Refer to 3.2.6 Fast Termination Cycles for additional information on these cycles. 3-4 MC68340 USER’S MANUAL MOTOROLA 3.1.7.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK≈ to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK≈ to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.5 Bus Exception Control Cycles for additional information on the use of these signals. The internal bus monitor can be used to generate an internal bus error signal for internal and internal-to-external transfers. If the bus cycles of an external bus master are to be monitored, external BERR generation must be provided since the internal bus error monitor has no information about transfers initiated by an external bus master. 3.1.7.3 AUTOVECTOR (AVEC ).This signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68340 should internally generate a vector (autovector) number to locate an interrupt handler routine. AVEC can be generated either externally or internally by the SIM40 (see Section 4 System Integration Module for additional information). AVEC is ignored during all other bus cycles. 3.2 DATA TRANSFER MECHANISM The MC68340 supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACK0 . The MC68340 also supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM40. 3.2.1 Dynamic Bus Sizing The MC68340 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACK≈ inputs. Refer to Table 3-3 for DSACK≈ encoding. Table 3-3. DSACK≈ Encoding MOTOROLA DSACK1 DSACK0 1 (Negated) 1 (Negated) Insert Wait States in Current Bus Cycle 1 (Negated) 0 (Asserted) Complete Cycle—Data Bus Port Size Is 8 Bits 0 (Asserted) 1 (Negated) Complete Cycle—Data Bus Port Size Is 16 Bits 0 (Asserted) 0 (Asserted) Reserved—Defaults to 16-Bit Port Size Can Be Used for 32-Bit DMA cycles Result MC68340 USER’S MANUAL 3-5 For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK≈ to indicate the port width. For instance, a 16-bit device always returns DSACK≈ for a 16-bit port (regardless of whether the bus cycle is a byte or word operation). Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits 15–0, and an 8-bit port must reside on data bus bits 15–8. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68340 correctly transfers valid data. The MC68340 always attempts to transfer the maximum amount of data on all bus cycles; for a word operation, it always assumes that the port is 16 bits wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0. These designations are used in the figures and descriptions that follow. Figure 3-2 shows the required organization of data ports on the MC68340 bus for both 8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the internal data bus and data multiplexer to the external data bus. The data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. The positioning of bytes is determined by the SIZ1/SIZ0 and A0 outputs. The SIZ1/SIZ0 outputs indicate the number of bytes to be transferred during the current bus cycle (see Table 3-1). The number of bytes transferred during a read or write bus cycle is equal to or less than the size indicated by the SIZ1/SIZ0 outputs, depending on port width. For example, during the first bus cycle of a long-word transfer to a word port, the size outputs indicate that four bytes are to be transferred although only two bytes are moved on that bus cycle. The address line A0 also affects the operation of the data multiplexer. During an operand transfer, A31–A1 indicate the word base address of that portion of the operand to be accessed, and A0 indicates the byte offset from the base (i.e., either odd or even byte). Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1/SIZ0 and A0 for the bus cycle. 3-6 MC68340 USER’S MANUAL MOTOROLA OPERAND OP0 OP1 OP0 31 OP3 OP2 OP1 OP0 OP2 OP1 OP0 23 15 7 Case (a) (b) (c) (d) (e) (f) (g) Transfer Case Byte to Byte Byte to Word (Even) Byte to Word (Odd) Word to Byte (Aligned) Word to Word (Aligned) Long Word to Byte (Aligned) Long Word to Word (Aligned) SIZ1 0 0 0 1 1 0 0 SIZ0 1 1 1 0 0 0 0 A0 X 0 1 0 0 0 0 DSACK1 DSACK0 1 0 0 X 0 X 1 0 0 X 1 0 0 X 0 Data Bus D8 D7 D0 (OP0) OP0 (OP0) OP0 (OP0) OP0 (OP1) OP0 OP1 OP0 (OP1) OP0 OP0 OP1 D15 NOTES: 1. Operands in parentheses are ignored by the MC68340 during read cycles. 2. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer. Figure 3-2. MC68340 Interface to Various Port Sizes 3.2.2 Misaligned Operands In this architecture, the basic operand size is 16 bits. Operand misalignment refers to whether an operand is aligned on a word boundary or overlaps the word boundary, determined by address line A0. When A0 is low, the address is even and is a word and byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte operand is properly aligned at any address; a word or long-word operand is misaligned at an odd address. At most, each bus cycle can transfer a word of data aligned on a word boundary. If the MC68340 transfers a long-word operand over a 16-bit port, the most significant operand word is transferred on the first bus cycle, and the least significant operand word is transferred on a following bus cycle. The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word and long-word operands must be located on a word or long-word boundary, respectively. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the CPU32 generates an address error exception, and enters exception processing. Refer to Section 5 CPU32 for more information on exception processing. 3.2.3 Operand Transfer Cases The following cases are examples of the allowable alignments of operands to ports. 3.2.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a singlebyte operand. MOTOROLA MC68340 USER’S MANUAL 3-7 BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 OP0 (OP0) SIZ1 0 SIZ0 1 A0 X DSACK1 DSACK0 1 0 For a read operation, the slave responds by placing data on bits 15–8 of the data bus, asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68340 then reads the operand byte from bits 15–8 and ignores bits 7–0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK≈ signals are read. The slave device reads the byte operand from bits 15–8 and places the operand in the specified location. The slave then asserts DSACK0 to terminate the bus cycle. 3.2.3.2 BYTE OPERAND TO 16-BIT PORT, EVEN (A0 = 0). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 OP0 D8 D7 D0 (OP0) SIZ1 0 SIZ0 1 A0 0 DSACK1 DSACK0 0 X For a read operation, the slave responds by placing data on bits 15–8 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 15–8 and ignores bits 7–0. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK≈ signals are read. The slave device reads the operand from bits 15–8 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle. 3-8 MC68340 USER’S MANUAL MOTOROLA 3.2.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND OP0 0 7 DATA BUS CYCLE 1 D15 D8 D7 D0 (OP0) OP0 SIZ1 0 SIZ0 1 A0 1 DSACK1 DSACK0 0 X For a read operation, the slave responds by placing data on bits 7–0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 7–0 and ignores bits 15–8. For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACK≈ signals are read. The slave device reads the operand from bits 7–0 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle. 3.2.3.4 WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a word operand. WORD OPERAND OP0 15 OP1 87 0 DATA BUS D15 D8 D7 D0 (OP1) OP0 CYCLE 1 (OP1) OP1 CYCLE 2 SIZ1 1 0 SIZ0 0 1 A0 0 1 DSACK1 DSACK0 1 0 1 0 For a read operation, the slave responds by placing the most significant byte of the operand on bits 15–8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand from bits 15–8 and ignores bits 7–0. The MC68340 then decrements the transfer size counter, increments the address, and reads the least significant byte of the operand from bits 15–8 of the data bus. For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15–8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port. The MC68340 then decrements the transfer size counter, increments the address, and writes the least significant byte of the operand to bits 15–8 of the data bus. MOTOROLA MC68340 USER’S MANUAL 3-9 3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand. WORD OPERAND OP0 OP1 15 0 D15 D8 D7 D0 DATA BUS CYCLE 1 OP0 OP1 SIZ1 1 SIZ0 0 A0 0 DSACK1 DSACK0 0 X For a read operation, the slave responds by placing the data on bits 15–0 of the data bus and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MC68340 reads the data on the data bus and terminates the cycle. For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus. The slave device then reads the entire operand from bits 15–0 of the data bus and asserts DSACK1 to terminate the bus cycle. 3.2.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a long-word operand. OP0 LONG-WORD OPERAND 31 DATA BUS D15 CYCLE 1 CYCLE 2 CYCLE 3 CYCLE 4 OP1 23 OP0 OP1 OP2 OP3 D8 D7 D0 (OP1) (OP1) (OP3) (OP3) OP2 15 OP3 7 SIZ1 0 1 1 0 0 SIZ0 0 1 0 1 A0 0 1 0 1 DSACK1 DSACK0 1 0 1 0 1 0 1 0 For a read operation, shown in Figure 3-3, the slave responds by placing the most significant byte of the operand on bits 15–8 of the data bus and asserting DSACK0 to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand (byte 0) from bits 15–8 and ignores bits 7–0. The MC68340 then decrements the transfer size counter, increments the address, initiates a new cycle, and reads byte 1 of the operand from bits 15–8 of the data bus. The MC68340 repeats the process of decrementing the transfer size counter, incrementing the address, initiating a new cycle, and reading a byte to transfer the remaining two bytes. For a write operation, shown in Figure 3-4, the MC68340 drives the two most significant bytes of the operand on bits 15–0 of the data bus. The slave device then reads only the most significant byte of the operand (byte 0) from bits 15–8 of the data bus and asserts DSACK0 to indicate reception and an 8-bit port. The MC68340 then decrements the transfer size counter, increments the address, and writes byte 1 of the operand to bits 15–8 of the data bus. The MC68340 continues to decrement the transfer size counter, increment the address, and write a byte to transfer the remaining two bytes to the slave device. 3-10 MC68340 USER’S MANUAL MOTOROLA S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS SIZ0 4 BYTES 3 BYTES 2 BYTES 1 BYTE SIZ1 DSACK0 DSACK1 OP0 D15–D8 OP1 OP3 OP2 D7–D0 BYTE READ BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS BYTE READ Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA MC68340 USER’S MANUAL 3-11 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS SIZ0 3 BYTES 4 BYTES 1 BYTE 2 BYTES SIZ1 DSACK0 DSACK1 D15–D8 OP0 OP1 OP2 OP3 D7–D0 (OP1) (OP1) (OP3) (OP3) WRITE WRITE WRITE WRITE LONG-WORD OPERAND WRITE TO 8-BIT BUS Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port 3.2.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED. Figure 3-5 shows both long-word and word read and write timing to a 16-bit port. LONG-WORD OPERAND OP0 31 D15 DATA BUS CYCLE 1 CYCLE 2 3-12 OP1 OP2 23 15 D8 D7 OP0 OP2 D0 OP1 OP3 OP3 7 0 SIZ1 0 1 SIZ0 0 0 MC68340 USER’S MANUAL A0 0 0 DSACK1 DSACK0 0 X 0 X MOTOROLA S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S4 S2 CLKOUT A31–A0 FC3–FC0 R/W AS DS SIZ0 2 BYTES 4 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES SIZ1 DSACK0 DSACK1 D15–D8 OP0 OP2 OP0 OP0 OP2 OP0 D7–D0 OP1 OP3 OP1 OP1 OP3 OP1 LONG WORD READ FROM 16-BIT BUS WORD READ FROM 16-BIT BUS LONG WORD WRITE TO 16-BIT BUS WORD WRITE TO 16-BIT BUS Figure 3-5. Long-Word and Word Read and Write Timing—16-Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15–0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15–0. The MC68340 then decrements the transfer size counter by 2, increments the address by 2, initiates a new cycle, and reads bytes 2 and 3 of the operand from bits 15–0 of the data bus. For a write operation, the MC68340 drives the two most significant bytes of the operand on bits 15–0 of the data bus. The slave device then reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15–0 of the data bus and asserts DSACK1 to indicate reception and a 16-bit port. The MC68340 then decrements the transfer size counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits 15–0 of the data bus. MOTOROLA MC68340 USER’S MANUAL 3-13 3.2.4 Bus Operation The MC68340 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340. Bus operation uses the handshake lines (AS, DS, DSACK1/DSACK0, BERR, and HALT ) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle. Decoding the SIZx outputs and lower address line A0 provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) responds by placing the requested data on the correct portion of the data bus for a read cycle or by latching the data on a write cycle; the slave asserts the DSACK1/DSACK0 combination that corresponds to the port size to terminate the cycle. Alternatively, the SIM40 can be programmed to assert the DSACK1/ DSACK0 combination internally and respond for the slave. If no slave responds or the access is invalid, external control logic may assert BERR to abort the bus cycle or BERR with HALT to retry the bus cycle. DSACK≈ can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACK≈ may precede data must not exceed a specified value in any asynchronous system to ensure that valid data is latched into the MC68340. (See Section 11 Electrical Characteristics for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACK≈ . Although the MC68340 can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK≈ , the MC68340 inserts wait cycles in clock-period increments until DSACK≈ is recognized. BERR and/or HALT can be asserted after DSACK≈ is asserted. BERR and or HALT must be asserted within the time specified after DSACK≈ is asserted in any asynchronous system. If this maximum delay time is violated, the MC68340 may exhibit erratic behavior. 3.2.5 Synchronous Operation with DSACK≈ Although cycles terminated with DSACK≈ are classified as asynchronous, cycles terminated with DSACK≈ can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these cycles must synchronize the response to the MC68340 clock (CLKOUT) to be synchronous. Since the devices terminate bus cycles with DSACK≈, the dynamic bus sizing capabilities of the MC68340 are available. The minimum cycle time for these cycles is also three clocks. To support systems that use the system clock to generate DSACK≈ and other asynchronous inputs, the asynchronous input setup time and the asynchronous input hold time are given. If the setup and hold times are met for the assertion or negation of a signal such as DSACK≈, the MC68340 is guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACK≈ is recognized on a particular falling edge of the clock, valid data is latched into the MC68340 (for a read cycle) on the next falling clock edge if the data meets the data setup time. In this case, the parameter for asynchronous operation can be ignored. The timing parameters are described in Section 11 Electrical Characteristics. 3-14 MC68340 USER’S MANUAL MOTOROLA If a system asserts DSACK≈ for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK≈ (and/or BERR/ HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK≈ (three clocks per cycle). When BERR (or BERR and HALT) is asserted after DSACK≈, BERR (and HALT) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK≈ is recognized. This setup time is critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS. 3.2.6 Fast Termination Cycles With an external device that has a fast access time, the chip select circuit fast termination enable (FTE) can provide a two-clock external bus transfer. Since the chip select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. Refer to Section 4 System Integration Module for more information on chip selects.When fast termination is selected, the DD bits of the corresponding address mask register are overridden. Fast termination can only be used with zero wait states. To use the fast termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the DSACK≈ timing for a read with two wait states, followed by a fast termination read and write. When using the fast termination option, DS is asserted only in a read cycle, not in a write cycle. S0 S1 S2 S3 SW SW* SW SW* S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 CLKOUT AS DS R/W DSACKx D15–D0 TWO WAIT STATES IN READ FAST TERMINATION READ FAST TERMINATION WRITE * DSACKx only internally asserted for fast termination cycles. Figure 3-6. Fast Termination Timing MOTOROLA MC68340 USER’S MANUAL 3-15 3.3 DATA TRANSFER CYCLES The transfer of data between the MC68340 and other devices involves the following signals: • Address Bus A31–A0 • Data Bus D15–D0 • Control Signals The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. Each bus cycle is defined as a succession of states that apply to the bus operation. These states are different from the MC68340 states described for the CPU32. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states. 3.3.1 Read Cycle During a read cycle, the MC68340 receives data from a memory or peripheral device. If the instruction specifies a long-word or word operation, the MC68340 attempts to read two bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal A0, and the port size. Refer to 3.2.1 Dynamic Bus Sizing and 3.2.2 Misaligned Operands for more information. Figure 3-7 is a flowchart of a word read cycle. SLAVE BUS MASTER ADDRESS DEVICE 1. 2. 3. 4. 5. SET R/W TO READ DRIVE ADDRESS ON A31–A0 DRIVE FUNCTION CODE ON FC3–FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS AND DS ACQUIRE DATA PRESENT DATA 1. DECODE ADDRESS 2. PLACE DATA ON D15–D0 3. DRIVE DSACKx SIGNALS 1. LATCH DATA 2. NEGATE AS AND DS START NEXT CYCLE TERMINATE CYCLE 1. REMOVE DATA FROM D15–D0 2. NEGATE DSACKx Figure 3-7. Word Read Cycle Flowchart 3-16 MC68340 USER’S MANUAL MOTOROLA State 0—The read cycle starts in state 0 (S0). During S0, the MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The MC68340 drives R/ W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1—One-half clock later, in state 1 (S1), the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1. The selected device uses R/ W, SIZ1 or SIZ0, A0, and DS to place its information on the data bus. One or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0 and A0. State 2—As long as at least one of the DSACK≈ signals is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates. State 3—If DSACK≈ is not recognized by the start of state 3 (S3), the MC68340 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK≈ on the falling edges of the clock until one is recognized. State 4—At the falling edge of state 4 (S4), the MC68340 latches the incoming data and samples DSACK≈ to get the port size. State 5—The MC68340 negates AS and DS during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/ W , SIZ1 and SIZ0, and FC3–FC0 also remain valid throughout S5. The external device keeps its data and DSACK≈ signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK≈ within approximately one clock period after sensing the negation of AS or DS . DSACK≈ signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68340 USER’S MANUAL 3-17 3.3.2 Write Cycle During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure 3-8 is a flowchart of a word write cycle. BUS MASTER SLAVE ADDRESS DEVICE 1. 2. 3. 4. 5. 6. 7. SET R/W TO WRITE DRIVE ADDRESS ON A31–A0 DRIVE FUNCTION CODE ON FC3–FC0 DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS PLACE DATA ON D15–D0 ASSERT DS TERMINATE OUTPUT TRANSFER ACCEPT DATA 1. DECODE ADDRESS 2. LATCH DATA FROM D15–D0 3. ASSERT DSACKx SIGNALS 1. NEGATE DS AND AS 2. REMOVE DATA FROM D15–D0 TERMINATE CYCLE 1. NEGATE DSACKx START NEXT CYCLE Figure 3-8. Word Write Cycle Flowchart State 0—The write cycle starts in S0. During S0, the MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The MC68340 drives R/W low for a write cycle. SIZ1/SIZ0 become valid, indicating the number of bytes to be transferred. State 1—One-half clock later during S1, the MC68340 asserts AS, indicating a valid address on the address bus. State 2—During S2, the MC68340 places the data to be written onto D15–D0, and samples DSACK≈ at the end of S2. State 3—The MC68340 asserts DS during S3, indicating that data is stable on the data bus. As long as at least one of the DSACK≈ signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK≈ is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK≈ on the falling edges of the clock until one is recognized. The selected device uses R/W, SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15–D8 and D7–D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done so, the device asserts DSACK≈ to signal that it has successfully stored the data. 3-18 MC68340 USER’S MANUAL MOTOROLA State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W, SIZ1/SIZ0, and FC3– FC0 also remain valid throughout S5. The external device must keep DSACK≈ asserted until it detects the negation of AS or DS (whichever it detects first). The device must negate DSACK≈ within approximately one clock period after sensing the negation of AS or DS . DSACK≈ signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 3.3.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68340, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68340 asserts RMC to indicate that an indivisible operation is occurring. The MC68340 does not issue a BG signal in response to a BR signal during this operation. Figure 3-9 is an example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods. S0 S2 S0 S4 S2 S4 S0 CLK OUT A31–A30 FC3–FC0 SIZ1–SIZ0 R/W RMC AS DS DSACKx D15–D0 READ WRITE INDIVISIBLE CYCLE Figure 3-9. Read-Modify-Write Cycle Timing MOTOROLA MC68340 USER’S MANUAL 3-19 State 0—The MC68340 asserts RMC in S0 to identify a read-modify-write cycle. The MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0 to indicate the operand size. The MC68340 drives R/W high for the read cycle. State 1—One-half clock later during S1, the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1. State 2—The selected device uses R/W, SIZ1/SIZ0, A0, and DS to place information on the data bus. Either or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0 and A0. Concurrently, the selected device may assert DSACK≈. State 3—As long as at least one of the DSACK≈ signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK≈ is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample the DSACK≈ signals on the falling edges of the clock until one is recognized. State 4—At the end of S4, the MC68340 latches the incoming data. State 5—The MC68340 negates AS and DS during S5. If more than one read cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When finished reading, the MC68340 holds the address, R/W, and FC3–FC0 valid in preparation for the write portion of the cycle. The external device keeps its data and DSACK≈ signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACK≈ within approximately one clock period after sensing the negation of AS or DS. DSACK≈ signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. Idle States—The MC68340 does not assert any new control signals during the idle states, but it may internally begin the modify portion of the cycle at this time. S0–S5 are omitted if no write cycle is required. If a write cycle is required, R/W remains in the read mode until S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S2. State 0—The MC68340 drives R/ W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S0. State 1—In S1, the MC68340 asserts AS, indicating a valid address on the address bus. State 2—During S2, the MC68340 places the data to be written onto D15–D0. State 3—The MC68340 asserts DS during S3, indicating stable data on the data bus. As long as at least one of the DSACK≈ signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK≈ is not recognized by the start of S3, the MC68340 inserts wait states instead of 3-20 MC68340 USER’S MANUAL MOTOROLA proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK≈ on the falling edges of the clock until one is recognized. The selected device uses R/ W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15–D8 and D7–D0. SIZ1/SIZ0 and A0 select the data bus sections. If it has not already done so, the device asserts DSACK≈ when it has successfully stored the data. State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/ W and FC3–FC0 also remain valid throughout S5. If more than one write cycle is required, states S0–S5 are repeated for each write cycle. The external device keeps DSACK≈ asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK≈ within approximately one clock period after sensing the negation of AS or DS. 3.4 CPU SPACE CYCLES FC3–FC0 select user and supervisor program and data areas. The area selected by FC3– FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP broadcast, module base address register access, and interrupt acknowledge cycles described in the following paragraphs use CPU space. The CPU space type, which is encoded on A19–A16 during a CPU space operation, indicates the function that the MC68340 is performing. On the MC68340, four of the encodings are implemented as shown in Figure 3-10. All unused values are reserved by Motorola for additional CPU space types. CPU SPACE CYCLES FUNCTION CODE BREAKPOINT ACKNOWLEDGE LOW-POWER STOP BROADCAST MODULE BASE ADDRESS REGISTER ACCESS INTERRUPT ACKNOWLEDGE ADDRESS BUS 3 0 0 1 1 1 19 16 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0 3 0 0 1 1 1 19 16 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 3 0 0 1 1 1 31 19 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 3 31 0 19 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1 0 0 1 1 1 CPU SPACE TYPE FIELD Figure 3-10. CPU Space Address Encoding MOTOROLA MC68340 USER’S MANUAL 3-21 3.4.1 Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of the BKPT pin. The T-bit state (shown in Figure 3-10) differentiates a software breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1). When a BKPT instruction is executed (software breakpoint), the MC68340 performs a word read from CPU space, type 0, at an address corresponding to the breakpoint number (bits [2–0] of the BKPT opcode) on A4–A2, and the T-bit (A1) is cleared. If this bus cycle is terminated with BERR (i.e., no instruction word is available), the MC68340 then performs illegal instruction exception processing. If the bus cycle is terminated by DSACK≈ , the MC68340 uses the data on D15–D0 (for 16-bit ports) or two reads from D15–D8 (for 8-bit ports) to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction. When the CPU32 acknowledges a BKPT pin assertion (hardware breakpoint) with background mode disabled, the CPU32 performs a word read from CPU space, type 0, at an address corresponding to all ones on A4–A2 (BKPT#7), and the T-bit (A1) is set. If this bus cycle is terminated by BERR, the MC68340 performs hardware breakpoint exception processing. If this bus cycle is terminated by DSACK≈, the MC68340 ignores data on the data bus and continues execution of the next instruction. NOTE The BKPT pin is sampled on the same clock phase as data and is latched with data as it enters the CPU32 pipeline. If BKPT is asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32, BKPT is ignored. To ensure detection of BKPT by the CPU32, BKPT can be asserted until a breakpoint acknowledge cycle is recognized. The breakpoint operation flowchart is shown in Figure 3-11. Figures 3-12 and 3-13 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively. 3-22 MC68340 USER’S MANUAL MOTOROLA 3.4.2 LPSTOP Broadcast Cycle The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure. The CPU space type 3 cycle waits for the bus to be available, and is shown externally to indicate to external devices that the MC68340 is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT. The SIM40 provides internal DSACK≈ response to this cycle. For more information on how the SIM40 responds to LPSTOP mode, see Section 4 System Integration Module. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — — — I2 I1 I0 I2–I0—Interrupt Mask Level The interrupt mask level is encoded on bits 2–0 of the data bus during an LPSTOP broadcast. MOTOROLA MC68340 USER’S MANUAL 3-23 BREAKPOINT OPERATION FLOW EXTERNAL DEVICE PROCESSOR ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19–A16 4. PLACE BREAKPOINT NUMBER ON A2–A4 5. CLEAR T-BIT (A1) 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BKPT PIN ASSERTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19–A16 4. PLACE ALL ONE'S ON A4–A2 5. SET T-BIT (A-1) TO ONE 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BREAKPOINT INSTRUCTION EXECUTED AND DSACKx IS ASSERTED: 1. LATCH DATA 2. NEGATE AS AND DS 3. GO TO (A) IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED: 1. NEGATE AS AND DS 2. GO TO (A) IF BERR ASSERTED: 1. NEGATE AS AND DS 2. GO TO (B) (A) IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE REPLACEMENT OPCODE ON DATA BUS 2. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1. ASSERT DSACKx -OR1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING (B) 1. NEGATE DSACKx or BERR IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2. CONTINUE PROCESSING IF BKPT PIN ASSERTED: 1. CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED: 1. INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1. INITIATE HARDWARE BREAKPOINT PROCESSING Figure 3-11. Breakpoint Operation Flowchart 3-24 MC68340 USER’S MANUAL MOTOROLA S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31–A20 A19–A16 BREAKPOINT ENCODING (0000) A4–A1 BREAKPOINT NUMBER/T-BIT A15–A5,A0 FC3–FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH FETCHED INSTRUCTION EXECUTION Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned) MOTOROLA MC68340 USER’S MANUAL 3-25 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 CLKOUT A31–A20 BREAKPOINT ENCODING (0000) A19–A16 BREAKPOINT NUMBER/T-BIT A4–A1 A15–A5, A0 FC3–FC0 CPU SPACE SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS READ BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED EXCEPTION STACKING Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 3-26 MC68340 USER’S MANUAL MOTOROLA 3.4.3 Module Base Address Register Access All internal module registers, including the SIM40, occupy a single 4-Kbyte block that is relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base address of the SIM40 block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space (FC3–FC0 = $7), using the MOVEC instruction, before accessing the module base address register. Refer to Section 4 System Integration Module for additional information on the module base address register. 3.4.4 Interrupt Acknowledge Bus Cycles The CPU32 makes an interrupt pending in three cases. The first case occurs when a peripheral device signals the CPU32 (with IRQ7–IRQ1) that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register. The second case occurs when a transition has occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon returning from servicing a level 7 interrupt, the request level stays at 7 and the processor mask level changes from 7 to a lower level, a second level 7 is recognized. The CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the types of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing. 3.4.4.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the CPU32 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.4.4.2 Autovector Interrupt Acknowledge Cycle. MOTOROLA MC68340 USER’S MANUAL 3-27 The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. 2. A3, A2, and A1 are set to the interrupt request level, and the IACK≈ strobe corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACK≈ strobes can be monitored to determine that an interrupt acknowledge cycle is in progress and the current interrupt level.) 3. The CPU32 space type field (A19–A16) is set to $F (interrupt acknowledge). 4. Other address signals (A31–A20, A15–A4, and A0) are set to one. 5. The SIZ0/SIZ1 and R/ W signals are driven to indicate a single-byte read cycle. The responding device places the vector number on the least significant byte of its data port (for an 8-bit port, the vector number must be on D15–D8; for a 16-bit port, the vector must be on D7–D0) during the interrupt acknowledge cycle. The cycle is then terminated normally with DSACK≈. Figure 3-14 is a flowchart of the interrupt acknowledge cycle; Figure 3-15 shows the timing for an interrupt acknowledge cycle terminated with DSACK≈. INTERRUPTING DEVICE MC68340 REQUEST INTERRUPT GRANT INTERRUPT 1. SYNCHRONIZE IRQ7–IRQ1 2. COMPARE IRQ1–IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3. PLACE INTERRUPT LEVEL ON A3–A1; TYPE FIELD (A19–A16) = $F 4. SET R/W TO READ 5. SET FC3–FC0 TO 0111 6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE TRANSFER 7. ASSERT AS AND DS 8. ASSERT THE CORRESPONDING IACKx STROBE. PROVIDE VECTOR NUMBER 1. PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS 2. ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER) ACQUIRE VECTOR NUMBER RELEASE 1. LATCH VECTOR NUMBER 2. NEGATE DS AND AS 1. NEGATE DSACKx START NEXT CYCLE Figure 3-14. Interrupt Acknowledge Cycle Flowchart 3-28 MC68340 USER’S MANUAL MOTOROLA S0 S2 S4 S0 0–2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31–A4 A3–A1 INTERRUPT LEVEL A0 FC3–FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS VECTOR FROM 16-BIT PORT DSACKx VECTOR FROM 8-BIT PORT D7–D0 D15–D8 IRQ7–IRQ1 IACK7–IACK1 READ CYCLE WRITE STACK INTERNAL ARBITRATION IACK CYCLE *Internal Arbitration may take between 0–2 clock cycles. Figure 3-15. Interrupt Acknowledge Cycle Timing 3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector). Instead of placing a vector number on the data bus and asserting DSACK≈, the device asserts AVEC to terminate the cycle. If the DSACK≈ signals are asserted during an interrupt acknowledge cycle terminated by AVEC, the DSACK≈ signals and MOTOROLA MC68340 USER’S MANUAL 3-29 data will be ignored if AVEC is asserted before or at the same time as the DSACK≈ signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK≈ during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)). AVEC is multiplexed with CS0. The FIRQ bit in the SIM40 module configuration register controls whether the AVEC /CS0 pin is used as an autovector input or as CS0 (refer to Section 4 System Integration Module for additional information). AVEC is only sampled during an interrupt acknowledge cycle. During all other cycles, AVEC is ignored. Additionally, AVEC can be internally generated for external devices by programming the autovector register. Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7–IRQ1. Figure 3-16 shows the timing for an autovector operation. 3.4.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM40, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The MC68340 automatically generates the spurious interrupt vector number (24) instead of the interrupt vector number in this case. When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACK≈ , a bus monitor must assert BERR , which results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68340 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector. 3-30 MC68340 USER’S MANUAL MOTOROLA S0 S2 S4 S0 0–2 CLOCKS* S1 S2 S4 S0 S2 CLKOUT A31–A4 A3–A1 INTERRUPT LEVEL A0 FC3–FC0 CPU SPACE SIZ0 1 BYTE SIZ1 R/W AS DS DSACKx D15–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 CYCLE READ WRITE STACK INTERNAL ARBITRATION IACK CYCLE * Internal Arbitration may take between 0–2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA MC68340 USER’S MANUAL 3-31 3.5 BUS EXCEPTION CONTROL CYCLES The bus architecture requires assertion of DSACK≈ from an external device to signal that a bus cycle is complete. Neither DSACK≈ nor AVEC is asserted in the following cases: • DSACK≈/AVEC is programmed to respond internally. • The external device does not respond. • Various other application-dependent errors occur. The MC68340 provides BERR when no device responds by asserting DSACK≈ / AVEC within an appropriate period of time after the MC68340 asserts AS . This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition. HALT is also used for bus exception control. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation, or, in combination with BERR, a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACK≈, BERR, and HALT can be asserted and negated with the rising edge of the MC68340 clock. This assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68340 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK≈ assertion as follows (case numbers refer to Table 3-4): • Normal Termination: DSACK≈ is asserted; BERR and HALT remain negated (case 1). • Halt Termination: HALT is asserted at the same time as or before DSACKx, and BERR remains negated (case 2). • Bus Error Termination: BERR is asserted in lieu of, at the same time as, or before DSACK≈ (case 3) or after DSACK≈ (case 4), and HALT remains negated; BERR is negated at the same time as or after DSACK≈. • Retry Termination: HALT and BERR are asserted in lieu of, at the same time as, or before DSACK≈ (case 5) or after DSACK≈ (case 6); BERR is negated at the same time as or after DSACK≈, and HALT may be negated at the same time as or after BERR. Table 3-4 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to the specifications given in Section 11 Electrical Characteristics. DSACK≈ BERR, and HALT may be negated after AS. If DSACK≈ or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). 3-32 MC68340 USER’S MANUAL MOTOROLA EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK≈ until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK≈ (case 1). 2. Delay DSACK≈ until data is verified and assert BERR with or without DSACK≈ if data is in error (case 3). This initiates exception processing for software handling of the condition. 3. Return DSACK≈ prior to data verification; if data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition. 4. Return DSACK≈ prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry. Table 3-4. DSACK≈, BERR, and HALT Assertion Results Asserted on Rising Edge of State Case Num Control Signal N N+2 1 DSACK≈ BERR HALT A NA NA S NA X Normal cycle terminate and continue. 2 DSACK≈ BERR HALT A NA A/S S NA S Normal cycle terminate and halt; continue when HALT negated. 3 DSACK≈ BERR HALT NA/A A NA X S X Terminate and take bus error exception, possibly deferred. 4 DSACK≈ BERR HALT A NA NA X A NA Terminate and take bus error exception, possibly deferred. 5 DSACK≈ BERR HALT NA/A A A/S X S S Terminate and retry when HALT negated. 6 DSACK≈ BERR HALT A NA NA X A A Terminate and retry when HALT negated. NOTES: N — A — NA — X — S — MOTOROLA Result Number of the current even bus state (e.g., S2, S4, etc.) Signal is asserted in this bus state Signal is not asserted in this state Don't care Signal was asserted in previous state and remains asserted in this state MC68340 USER’S MANUAL 3-33 3.5.1 Bus Errors BERR can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK≈ provided it meets the timing constraints described in Section 11 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68340. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the MC68340 can enter exception processing immediately following the bus cycle, or it can defer processing the exception. The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the MC68340 does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. The bus error condition is recognized during a bus cycle in any of the following cases: • DSACK≈ and HALT are negated, and BERR is asserted. • HALT and BERR are negated, and DSACK≈ is asserted. BERR is then asserted within one clock cycle ( HALT remains negated). • BERR and HALT are asserted simultaneously, indicating a retry. When the MC68340 recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 3-17 shows the timing of a bus error for the case in which DSACK≈ is not asserted. Figure 3-18 shows the timing for a bus error that is asserted after DSACK≈. Exceptions are taken in both cases. Refer to Section 5 CPU32 for details of bus error exception processing. In the second case, in which BERR is asserted after DSACK≈ is asserted, BERR must be asserted within the time specified for purely asynchronous operation, or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK≈ is recognized. If BERR is not stable at this time, the MC68340 may exhibit erratic behavior. BERR has priority over DSACK≈ . In this case, data may be present on the bus, but it may not be valid. This sequence can be used by systems that have memory error detection and correction logic and by external cache memories. 3-34 MC68340 USER’S MANUAL MOTOROLA S0 S2 SW SW S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D0 BERR READ CYCLE WITH BUS ERROR INTERNAL PROCESSING STACK WRITE Figure 3-17. Bus Error without DSACK≈ MOTOROLA MC68340 USER’S MANUAL 3-35 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D0 BERR WRITE CYCLE INTERNAL PROCESSING STACK WRITE Figure 3-18. Late Bus Error with DSACK≈ 3.5.2 Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20). The MC68340 terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic. After a synchronization delay, the MC68340 retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. 3-36 MC68340 USER’S MANUAL MOTOROLA S0 S2 SW SW S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D0 DATA IGNORED BERR HALT READ CYCLE WITH RETRY HALT READ RERUN Figure 3-19. Retry Sequence The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the bus during a read-modify-write operation. Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR and BR (HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (see Section 5 CPU32) and take the appropriate action to resolve this type of fault when it occurs. MOTOROLA MC68340 USER’S MANUAL 3-37 S0 S2 S4 S0 S2 S4 CLKOUT A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D10 BERR HALT WRITE CYCLE HALT WRITE RERUN Figure 3-20. Late Retry Sequence 3.5.3 Halt Operation When HALT is asserted and BERR is not asserted, the MC68340 halts external bus activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT affects external bus cycles only, a program that does not require use of the external bus may continue executing. The single-cycle mode allows the user to proceed through (and debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a bus error while HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. When the MC68340 completes a bus cycle with HALT asserted, D15–D0 is placed in the high-impedance state, and bus control signals are negated (not high-impedance state); the A31–A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has no effect on bus arbitration (see 3.6 Bus Arbitration). When bus arbitration occurs while the MC68340 is halted, the address and control signals are also placed in the highimpedance state. Once bus mastership is returned to the MC68340, if HALT is still 3-38 MC68340 USER’S MANUAL MOTOROLA asserted, the A31–A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted. S0 S2 S0 S4 S2 S4 S0 CLKOUT A31–A0 FC3–FC0 R/W AS DS DSACKx D15–D10 HALT BR BG BGACK READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) READ Figure 3-21. HALT Timing 3.5.4 Double Bus Fault A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following: • A previous bus error • A previous address error • A reset For example, the MC68340 attempts to stack several words containing information about the state of the machine while processing a bus error exception. If a bus error exception MOTOROLA MC68340 USER’S MANUAL 3-39 occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68340 halts and asserts HALT. Only a reset operation can restart a halted MC68340. However, bus arbitration can still occur (see 3.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The MC68340 continues to retry the same bus cycle as long as the external hardware requests it. Reset can also be generated internally by the halt monitor (see Section 5 CPU32). 3.6 BUS ARBITRATION The bus design of the MC68340 provides for a single bus master at any one time, either the MC68340 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68340 internal bus. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MC68340 manages the bus arbitration signals so that the MC68340 has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs. Systems having several devices that can become bus master require external circuitry to assign priorities to the devices so that, when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol is as follows: 1. An external device asserts BR. 2. The MC68340 asserts BG to indicate that the bus is available. 3. The external device asserts BGACK to indicate that it has assumed bus mastership. NOTE The MC68340 does not place CS3–CS0 in a high-impedance state after reset or when the bus is granted to an external master. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of an operand transfer. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. When the external device assumes bus mastership, it asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: 1) it must have received BG through the arbitration process, and 2) BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. 3-40 MC68340 USER’S MANUAL MOTOROLA Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and 3-24 for bus arbitration timing diagrams. BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68340 and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, BR from each device can be wireORed to the MC68340. In such a system, more than one bus request could be asserted simultaneously. BG is negated a few clock cycles after the transition of BGACK. However, if bus requests are still pending after the negation of BG, the MC68340 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus. The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault. PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1. ASSERT BR 1. ASSERT BG ACKNOWLEDGE BUS MASTERSHIP TERMINATE ARBITRATION 1. NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) 1. EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2. NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3. NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4. BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1. PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP RE-ARBITRATE OR RESUME PROCESSOR OPERATION 1. NEGATE BGACK Figure 3-22. Bus Arbitration Flowchart for Single Request MOTOROLA MC68340 USER’S MANUAL 3-41 CLKOUT A31–A0 D15–D0 AS BR BG BGACK Figure 3-23. Bus Arbitration Timing Diagram—Idle Bus Case S0 S1 S2 S3 S4 S5 CLKOUT A31–A0 D15–D0 AS DS R/W DSACK0, DSACK1 BR BG BGACK Figure 3-24. Bus Arbitration Timing Diagram—Active Bus Case 3-42 MC68340 USER’S MANUAL MOTOROLA 3.6.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while the BR is active, the MC68340 remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership. 3.6.2 Bus Grant The MC68340 supports operand coherency; thus, if an operand transfer requires multiple bus cycles, the MC68340 does not release the bus until the entire transfer is complete. Therefore, assertion of BG is subject to the following constraints: • The minimum time for BG assertion after BR is asserted depends on internal synchronization (see Section 11 Electrical Characteristics). • During an external operand transfer, the MC68340 does not assert BG until after the last cycle of the transfer (determined by SIZx and DSACK≈). • During an external operand transfer, the MC68340 does not assert BG as long as RMC is asserted. • If the show cycle bits SHEN1–SHEN0 = 01, the MC68340 does not assert BG to an external master. Externally, the BG signal can be routed through a daisy-chained network or a priorityencoded network. The MC68340 is not affected by the method of arbitration as long as the protocol is obeyed. 3.6.3 Bus Grant Acknowledge An external device cannot request and be granted the external bus while another device is the active bus master. A device that asserts BGACK remains the bus master until it negates BGACK . BGACK should not be negated until all required bus cycles are completed. Bus mastership is terminated at the negation of BGACK. Once an external device receives the bus and asserts BGACK, it should negate BR. If BR remains asserted after BGACK is asserted, the MC68340 assumes that another device is requesting the bus and prepares to issue another BG. MOTOROLA MC68340 USER’S MANUAL 3-43 3.6.4 Bus Arbitration Control The bus arbitration control unit in the MC68340 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-25 input signals labeled R and A are internally synchronized versions of B R and BGACK respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the highimpedance state after the next rising edge following the negation of AS and RMC . All signals are shown in positive logic (active high) regardless of their true active voltage level. The state machine shown in Figure 3-25 does not have a state 1 or state 4. State changes occur on the next rising edge of the clock after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the MC68340 immediately following a state change, when bus mastership is returned to the MC68340. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68340 is bus master. R and A keep the arbiter in state 0 as long as they are both negated. The MC68340 does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the MC68340 ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence. 3.6.5 Show Cycles The MC68340 can perform data transfers with its internal modules without using the external bus, but, when debugging, it is desirable to have address and data information appear on the external bus. These external bus cycles, called show cycles, are distinguished by the fact that AS is not asserted externally. DS is used to signal address strobe timing in show cycles. After reset, show cycles are disabled and must be enabled by writing to the SHEN bits in the module configuration register (see 4.3.2.1 Module Configuration Register (MCR)). When show cycles are disabled, the A31–A0, FCx, SIZx, and R/ W signals continue to reflect internal bus activity. However, AS and DS are not asserted externally, and the external data bus remains in a high-impedance state. When show cycles are enabled, DS indicates address strobe timing and the external data bus contains data. The following paragraphs are a state-by-state description of show cycles, and Figure 3-26 illustrates a show cycle timing diagram. Refer to Section 11 Electrical Characteristics for specific timing information. 3-44 MC68340 USER’S MANUAL MOTOROLA RA + B GTV AB STATE 0 RA RAB RA G TV RA STATE 3 R+A G TV STATE 2 R A +A G TV R R STATE 5 RA G TV RA STATE 6 RA R - BUS REQUEST A - BUS GRANT ACKNOWLEDGE B - BUS CYCLE IN PROGRESS G - BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL Figure 3-25. Bus Arbitration State Diagram MOTOROLA MC68340 USER’S MANUAL 3-45 State 0—During state 0, the A31–A0 and FCx become valid, R/ W is driven to indicate a show read or write cycle, and the SIZx pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts. State 41—One-half clock cycle later, DS (rather than AS ) is asserted to indicate that address information is valid. State 42—No action occurs in state 42. The bus controller remains in state 42 (wait states will be inserted) until the internal read cycle is complete. State 43—When DS is negated, show data is valid on the next falling edge of the system clock. The external data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus. State 0—The A31–A0, FCx, R/W , and SIZx pins change to begin the next cycle. Data from the preceding cycle is valid through state 0. S0 S41 S42 S43 S0 S1 S2 CLKOUT A31–A0, FC2–FC0, SIZ1–SIZ0 R/W AS, CS DS D15–D0 BKPT SHOW CYCLE START OF EXTERNAL CYCLE Figure 3-26. Show Cycle Timing Diagram 3.7 RESET OPERATION The MC68340 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines: 1. EXTRST (external reset) drives the external RESET pin. 2. CLKRST (clock reset) resets the clock module. 3-46 MC68340 USER’S MANUAL MOTOROLA 3. INTRST (internal reset) goes to all other internal circuits. Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or word transfers are guaranteed valid for synchronous resets. An external or clock reset is a synchronous reset source. Asynchronous reset sources indicate a catastrophic failure, and the reset controller logic immediately resets the system. Resetting the MC68340 causes any bus cycle in progress to terminate as if DSACK≈ or BERR had been asserted. In addition, the MC68340 appropriately initializes registers for a reset exception. Asynchronous reset sources include power-up, software watchdog, double bus fault resets, and execution of the RESET instruction. If an external device drives RESET low, RESET should be asserted for at least 590 clock periods to ensure that the MC68340 resets. The reset control logic holds reset asserted internally until the external RESET is released. When the reset control logic detects that external RESET is no longer being driven, it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system. Figure 3-27 shows the RESET timing. 1 CLOCK RESET 590 CLOCK 512 CLOCK PULLED EXTERNAL DRIVEN BY MC68340 Figure 3-27. Timing for External Devices Driving RESET If reset is asserted from any other source, the reset control logic asserts RESET for 328 input clock periods plus 512 output clock periods, and until the source of reset is negated. After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence of an external reset. If no external reset is detected, the CPU32 begins its vector fetch. Figure 3-28 is a timing diagram of the power-up reset operation, showing the relationships between RESET, V CC , and bus signals. During the reset period, the entire bus threestates except for non-three-statable signals, which are driven to their inactive state. Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins. MOTOROLA MC68340 USER’S MANUAL 3-47 CLKOUT VCO LOCK VCC 328 × TCLKIN 512 × TCLKOUT ≤ 14 CLOCKS RESET BUS CYCLES ADDRESS AND CONTROL SIGNALS THREE-STATED BUS STATE UNKNOWN 1 2 3 4 NOTES: 1. Internal start-up time. 2. SSP read here. 3. PC read here. 4. First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles. The SIM40 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. 3-48 MC68340 USER’S MANUAL MOTOROLA SECTION 4 SYSTEM INTEGRATION MODULE The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities. The SIM40 includes the following functions: • System Configuration and Protection • Clock Synthesizer • Chip Selects and Wait States • External Bus Interface • Bus Arbitration • Dynamic Bus Sizing • IEEE 1149.1 Test Access Port 4.1 MODULE OVERVIEW The SIM40 is essentially identical to the SIM implemented in the MC68330. The SIM40 has similar features to the SIM in the MC68331, MC68332, and MC68333. The periodic interrupt timer, double bus fault monitor, software watchdog, internal bus monitor, and spurious interrupt monitor are identical. However, many of the other features in the SIM's differ in their use and details. The system configuration and protection function controls system configuration and provides various monitors and timers, including the internal bus monitor, double bus fault monitor, spurious interrupt monitor, software watchdog timer, and the periodic interrupt timer. The clock synthesizer generates the clock signals used by the SIM40 and the other onchip modules, as well as CLKOUT used by external devices. The programmable chip select function provides four chip select signals that can enable external memory and peripheral circuits, providing all handshaking and timing signals. Each chip select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select. Up to three wait states can be programmed by setting bits in the address mask register. MOTOROLA MC68340 USER’S MANUAL 4-1 The external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. The device signals its port size and indicates completion of the bus cycle through the use of the DSACK≈ inputs. Dynamic bus sizing allows a programmer to write code that is not buswidth specific. For a discussion on dynamic bus sizing, see Section 3 Bus Operation. The MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems associated with testing high-density circuit boards have led to the development of this standard under the sponsorship of the IEEE Test Technology Committee and Joint Test Action Group (JTAG). The MC68340 implementation supports circuit-board test strategies based on this standard. Refer to Section 9 IEEE 1149.1 Test Access Port for additional information. 4.2 MODULE OPERATION The following paragraphs describe the operation of the module base address register, system configuration and protection, clock synthesizer, chip select functions, and the external bus interface. NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 4.2.1 Module Base Address Register Operation The module base address register (MBAR) controls the location of all internal module registers (see 4.3.1 Module Base Address Register (MBAR)). The address stored in this register is the base address (starting location) for all internal registers. All internal module registers are contained in a single 4-Kbyte block (see Figure 4-1) that is relocatable along 4-Kbyte boundaries. The location of the internal registers is fixed by writing the desired base address of the 4-Kbyte block to the MBAR using the MOVES instruction to address $0003FF00 in CPU space. The source function code (SFC) and destination function code (DFC) registers contain the address space values (FC3–FC0) for the read or write operand of the MOVES instruction (see Section 5 CPU32 or M68000PM/AD, Programmer’s Reference Manual ). Therefore, the SFC or DFC register must indicate CPU space (FC3–FC0 = $7), using the MOVEC instruction, before accessing MBAR. The offset from the base address is shown above each register diagram. 4-2 MC68340 USER’S MANUAL MOTOROLA $FFFFFFFF $XXXXXFFF MC68340 RELOCATABLE MODULE BLOCK $FFF $7BF DMA $780 $721 $XXXXX000 SERIAL PORTS $700 . $67F TIMER MODULES $600 $07F SIM 40 $000 MBAR ($0003FF00 FC=0111) RAM (TYPICAL) $00000000 NOTE: $XXXXX is the value contained in the MBAR bits BA31-BA12. Figure 4-1. SIM40 Module Register Block 4.2.2 System Configuration and Protection Operation The SIM40 allows the user to control certain features of system configuration by writing bits in the module configuration register (MCR). This register also contains read-only status bits that show the state of the SIM40. All M68000 family members are designed to provide maximum system safeguards. As an extension of the family, the MC68340 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided by external circuits are incorporated in this device. The following features are provided in the system configuration and protection function: SIM40 Module Configuration The SIM40 allows the user to configure the system to the particular requirements. The functions include control of FREEZE and show cycle operation, the function of the CS≈ signals, the access privilege of the supervisor/user registers, the level of interrupt arbitration, and automatic vectoring for external interrupts. Reset Status The reset status register provides the user with information on the cause of the most recent reset. The possible causes of reset include: external, power-up, software watchdog, double bus fault, loss of clock, and RESET instruction. MOTOROLA MC68340 USER’S MANUAL 4-3 Internal Bus Monitor The SIM40 provides an internal bus monitor to monitor the DSACK≈ response time for all internal bus accesses. An option allows the monitoring of external bus accesses. For external bus accesses, four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system. A bus error signal is asserted internally if the DSACK≈ response limit is exceeded. BERR is not asserted externally. This monitor can be disabled for external bus cycles only. Double Bus Fault Monitor The double bus fault monitor causes a reset to occur if the internal HALT is asserted by the CPU32, indicating a double bus fault. A double bus fault results when a bus or address error occurs during the exception processing sequence for a previous bus or address error, a reset, or while the CPU32 is loading information from a bus error stack frame during an RTE instruction. This function can be disabled. See Section 3 Bus Operation for more information. Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge (IACK) cycle, the bus error signal is asserted internally. This function cannot be disabled. Software Watchdog The software watchdog asserts reset or a level 7 interrupt (as selected by the system protection and control register) if the software fails to service the software watchdog for a designated period of time (i.e., because it is trapped in a loop or lost). There are eight selectable timeout periods. This function can be disabled. Periodic Interrupt Timer The SIM40 provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 µs to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function. 4-4 MC68340 USER’S MANUAL MOTOROLA MODULE CONFIGURATION RESET STATUS DOUBLE BUS FAULT MONITOR BUS MONITOR HALT RESET REQUEST BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG CLOCK 29 PRESCALER PERIODIC INTERRUPT TIMER SOFTWARE RESET REQUEST or IRQ7 IRQ7-IRQ1 Figure 4-2. System Configuration and Protection Function 4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled by the MCR and the autovector register (AVR). The configuration of port B is controlled by the combination of the FIRQ bit in the MCR and the port B pin assignment register (PPARB). Port B pins can function as dedicated I/O lines, chip selects, interrupts, or autovector input. For debug purposes, internal bus accesses can be shown on the external bus. This function is called show cycles. The SHEN1, SHEN0 bits in the MCR control show cycles. Bus arbitration can be either enabled or disabled during show cycles. Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration (IARB) field of the MCR. Each module that generates interrupts, including the SIM40, has an IARB field. The value of the IARB field allows arbitration during an IACK cycle among modules that simultaneously generate the same interrupt level. No two modules should share the same IARB value. The IARB must contain a value other than $0 for all modules that can generate interrupts; interrupts with IARB = 0 are discarded as extraneous. The SIM40 arbitrates for both its own interrupts and externally generated interrupts. MOTOROLA MC68340 USER’S MANUAL 4-5 There are eight arbitration levels for access to the intermodule bus (IMB). The SIM40 is fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the lowest level (below level 0). The direct memory access (DMA) module is the only other module that can become bus master and arbitrate for the bus. It must be initialized with a level other than 0 or 7. The AVR contains bits that correspond to external interrupt levels that require an autovector response. The SIM40 supports up to seven discrete external interrupt requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM40 returns an autovector in response to the IACK cycle servicing that external interrupt request. Otherwise, external circuitry must either return an interrupt vector or assert the external AVEC signal. 4.2.2.2 INTERNAL BUS MONITOR. The internal bus monitor continually checks for the bus cycle termination response time by checking the DSACK≈, BERR, and HALT status or the AVEC status during an IACK cycle. The monitor initiates a bus error if the response time is excessive. The bus monitor feature cannot be disabled for internal accesses to an internal module. The internal bus monitor cannot check the DSACK≈ response on the external bus unless the MC68340 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles. If the system contains external bus masters whose bus cycles must be monitored, an external bus monitor must be implemented. In this case, the internal-to-external bus monitor option must be disabled. The bus cycle termination response time is measured in clock cycles, and the maximumallowable response time is programmable. The bus monitor response time period ranges from 8 to 64 system clocks (see Table 4-8). These options are provided to allow for different response times of peripherals that might be used in the system. 4.2.2.3 DOUBLE BUS FAULT MONITOR. A double bus fault is caused by a bus error or address error during the exception processing sequence. The double bus fault monitor responds to an assertion of HALT on the internal bus. Refer to Section 3 Bus Operation for more information. The DBF bit in the reset status register (RSR) indicates that the last reset was caused by the double bus fault monitor. The double bus fault monitor reset can be enabled by the DBFE bit in the SYPCR. 4.2.2.4 SPURIOUS INTERRUPT MONITOR. The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an IACK cycle. Normally, during an IACK cycle, one or more internal modules recognize that the CPU32 is responding to interrupt request(s) and arbitrate for the privilege of returning a vector or asserting AVEC . (The SIM40 reports and arbitrates for externally generated interrupts.) This feature cannot be disabled. 4.2.2.5 SOFTWARE WATCHDOG. The SIM40 provides a software watchdog option to prevent system lock-up in case the software becomes trapped in loops with no controlled exit. Once enabled by the SWE bit in the SYPCR, the software watchdog requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the software watchdog times out and issues a reset or a level 7 4-6 MC68340 USER’S MANUAL MOTOROLA interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register (PITR) and the SWT bits in the SYPCR. See Table 4-7 for a list of watchdog timeout periods. The software watchdog service sequence consists of the following steps: 1) write $55 to the software service register (SWSR) and 2) write $AA to the SWSR. Both writes must occur in the order listed prior to the watchdog timeout, but any number of instructions or accesses to the SWSR can be executed between the two writes. PITR SWP PTP FREEZE EXTAL CLOCK DISABLE PRESCALER (2 9 ) CLOCK MUX PITCLK . .4 PIT INTERRUPT MODULUS COUNTER PRECLK RESET SWCLK 15 STAGE DIVIDER CHAIN (215 ) LPSTOP 29 2 11 213 215 Figure 4-3. Software Watchdog Block Diagram 4.2.2.6 PERIODIC INTERRUPT TIMER. The periodic interrupt timer consists of an 8-bit modulus counter that is loaded with the value contained in the PITR (see Figure 4-3). The modulus counter is clocked by a signal derived from the EXTAL input pin unless an external frequency source is used. When an external frequency source is used (MODCK low during reset), the default state of the prescaler control bits (SWP and PTP) in the PITR is changed to enable both prescalers. Either clock source (EXTAL or EXTAL ÷ 512) is divided by 4 before driving the modulus counter (PITCLK). When the modulus counter value reaches zero, an interrupt is generated. The level of the generated interrupt is programmed into the PIRQL bits in the periodic interrupt control register (PICR). During the IACK cycle, the SIM40 places the periodic interrupt vector, programmed into the PIV bits in the PICR, onto the internal bus. The value of bits 7–0 in the PITR is then loaded again into the modulus counter, and the counting process starts over. If a new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed. MOTOROLA MC68340 USER’S MANUAL 4-7 4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period = PITR count value EXTAL frequency/prescaler value 22 Solving the equation using a crystal frequency of 32.768-kHz with the prescaler disabled gives: periodic interrupt timer period = periodic interrupt timer period = PITR count value 32768/1 22 PITR count value 8192 This gives a range from 122 µs, with a PITR value of $01 (00000001 binary), to 31.128 ms, with a PITR value of $FF (11111111 binary). Solving the equation with the prescaler enabled (PTP=1 in the PITR) gives the following values: periodic interrupt timer period = periodic interrupt timer period = PITR count value 32768/512 22 PITR count value 16 This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a PITR value of $FF. For fast calculation of periodic timer period using a 32.768-kHz crystal, the following equations can be used: With prescaler disabled: programmable interrupt timer period = PITR (122 µs) = PITR (62.5 ms) With prescaler enabled: programmable interrupt timer period 4-8 MC68340 USER’S MANUAL MOTOROLA 4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting it up to generate an interrupt with a one-second period. Rearranging the periodic timer period equation to solve for the desired count value: PITR count value = (PIT period) (EXTAL frequency) (Prescaler value) (2 2) PITR count value = (1) (32768) (512) (2 2) PITR count value = 16 (decimal) Therefore, when using a 32.768-kHz crystal, the PITR should be loaded with a value of $10 with the prescaler enabled to generate interrupts at a one-second rate. 4.2.2.7 SIMULTANEOUS INTERRUPTS BY SOURCES IN THE SIM40. If multiple interrupt sources at the same interrupt level are simultaneously asserted in the SIM40, it will prioritize and service the interrupts in the following order: 1) software watchdog, 2) periodic interrupt timer, and 3) external interrupts. 4.2.3 Clock Synthesizer Operation The clock synthesizer can operate with either an external crystal or an external oscillator for reference, using the internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO), or an external clock can directly drive the clock signal at the operating frequency. The four modes of clock operation are listed in Table 4-1. Table 4-1. Clock Operating Modes Mode Description MODCK Reset Value VCCSYN Operating Value Crystal Mode External crystal or oscillator used with the on-chip PLL and VCO to generate a system clock and CLKOUT of programmable rates. 5V 5V External Clock Mode without PLL The desired operating frequency is driven into EXTAL resulting in a system clock and CLKOUT of the same frequency, not tightly coupled. 0V 0V External Clock Mode with PLL The desired operating frequency is driven into EXTAL, resulting in a system clock and CLKOUT of the same frequency, with a tight skew between input and output signals. 0V 5V Limp Mode Upon input signal loss for either clock mode using the PLL, operation continues at approximately one-half operating speed (affected by the value of the X-bit in the SYNCR). X 5V In crystal mode (see Figure 4-4), the clock synthesizer can operate from the on-chip PLL and VCO, using a parallel resonant crystal connected between the EXTAL and XTAL pins, or an external oscillator connected to EXTAL as a reference frequency source. The oscillator circuit is shown in Figure 4-5. A 32.768-kHz watch crystal provides an inexpensive reference, but the reference crystal or external oscillator frequency can be any frequency in the range specified in Section 11 Electrical Characteristics. When MOTOROLA MC68340 USER’S MANUAL 4-9 using crystal mode, the system clock frequency is programmable (using the W, X, and Y bits in the SYNCR) over the range specified in Section 11 Electrical Characteristics (see Table 4-2.). VDDSYN XFC 1 330 K 20 pF 20 pF 0.1 µF 20 M EXTAL XTAL CRYSTAL OSCILLATOR 0.1 µF V DDSYN XFC PIN LOW-PASS FILTER PHASE COMPARATOR 0.01 µF MUX 1 VCO CLKOUT ÷2 ÷64 MUX 1 MODULUS DIVIDER 0 SEL 0 ÷4 ÷8 0 X SEL 6 0 $3F FEEDBACK DIVIDER Y W NOTE 1: Must be low-leakage capacitor. Figure 4-4. Clock Block Diagram for Crystal Operation 60 kΩ XTAL EXTAL . 60 kΩ Figure 4-5. MC68340 Crystal Oscillator A separate power pin (VCCSYN ) is used to allow the clock circuits to run with the rest of the device powered down and to provide increased noise immunity for the clock circuits. The source for VCCSYN should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the VCCSYN pin to ensure a stable operating frequency. Figure 4-4 shows typical values for the bypass and PLL external capacitors. The crystal manufacturer's documentation should be consulted for specific recommendations for external components. 4-10 MC68340 USER’S MANUAL MOTOROLA To use an external clock source (see Figure 4-6), the operating clock frequency can be driven directly into the EXTAL pin (the XTAL pin must be left floating for this case). This approach results in a system clock and CLKOUT that are the same as the input signal frequency, but not tightly coupled to it. To enable this mode, MODCK must be held low during reset, and VCCSYN held at 0 V while the chip is in operation. VCCSYN XFC 1 0.1 µF EXTERNAL CLOCK EXTAL XTAL CRYSTAL OSCILLATOR XFC PIN PHASE COMPARATOR VCCSYN LOW-PASS FILTER .01 µF VCO FEEDBACK DIVIDER 2 CLKOUT CLOCK CONTROL SYSTEM CLOCK NOTES: 1. Must be low-leakage capacitor. 2. External mode uses this path only. Figure 4-6. Clock Block Diagram for External Oscillator Operation Alternatively, an external clock signal can be directly driven into EXTAL (with XTAL left floating) using the on-chip PLL. This configuration results in an internal clock and CLKOUT signal of the same frequency as the input signal, with a tight skew between the external clock and the internal clock and CLKOUT signals. To enable this mode, MODCK must be held low during reset, and V CCSYN should be connected to a quiet 5-V source. If an input signal loss for either of the clock modes utilizing the PLL occurs, chip operation can continue in limp mode with the VCO running at approximately one-half the operating speed (affected by the value of the X-bit in the SYNCR), using an internal voltage reference. The SLIMP bit in the SYNCR indicates that a loss of input signal reference has been detected. The RSTEN bit in the SYNCR controls whether an input signal loss causes a system reset or causes the device to operate in limp mode. The SLOCK bit in the SYNCR indicates when the VCO has locked onto the desired frequency or if an external clock is being used. 4.2.3.1 PHASE COMPARATOR AND FILTER. The phase comparator takes the output of the frequency divider and compares it to an external input signal reference. The result of MOTOROLA MC68340 USER’S MANUAL 4-11 this compare is low-pass filtered and used to control the VCO. The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock. The PLL requires an external low-leakage filter capacitor, typically in the range from 0.01 to 0.1 µF, connected between the XFC and VCCSYN pins. The XFC capacitor should provide 50-MΩ insulation but should not be electrolytic. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. For external clock mode without PLL, the XFC pin can be left open. 4.2.3.2 FREQUENCY DIVIDER. The frequency divider circuits divide the VCO frequency down to the reference frequency for the phase comparator. The frequency divider consists of 1) a 2-bit prescaler controlled by the W-bit in the SYNCR and 2) a 6-bit modulo downcounter controlled by the Y-bits in the SYNCR. Several factors are important to the design of the system clock. The resulting system clock frequency must be within the limits specified for the device. The frequency of the system clock is given by the following equation: FSYSTEM = FCRYSTAL [2(2+2W+X) ] × (Y+1) The maximum VCO frequency limit must also be observed. The VCO frequency is given by the following equation: FVCO = FSYSTEM [2(2–X)] Since clearing the X-bit causes the VCO to run at twice the system frequency, the VCO upper frequency limit must be considered when programming the SYNCR. Both the system clock and VCO frequency limits are given in Section 11 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz. 4-12 MC68340 USER’S MANUAL MOTOROLA Table 4-2. System Frequencies from 32.768-kHz Reference Y W = 0; X = 0 W = 0; X = 1 W = 1; X = 0 W = 1; X = 1 000000 131 262 524 1049 000101 786 1573 3146 6291 001010 1442 2884 5767 11534 001111 2097 4194 8389 16777 010100 2753 5505 11010 22020 011001 3408 6816 13631 – 011111 4194 8389 16777 – 100011 4719 9437 18874 – 101000 5374 10748 21496 – 101101 6029 12059 24117 – 110010 6685 13369 – – 110111 7340 14680 – – 111100 7995 15991 – – 111111 8389 16777 – – NOTE: System frequencies are in kHz. 4.2.3.3 CLOCK CONTROL. The clock control circuits determine the source used for both internal and external clocks during special circumstances, such as low-power stop (LPSTOP) execution. Table 4-3 summarizes the clock activity during LPSTOP in crystal mode operation. Any clock in the off state is held low. The STEXT and STSIM bits in the SYNCR control clock activity during LPSTOP. Refer to 4.2.6 Low-Power Stop for additional information. Table 4-3. Clock Control Signals Control Bits Clock Outputs STSIM STEXT SIMCLK CLKOUT 0 0 EXTAL Off 0 1 EXTAL EXTAL 1 0 VCO Off 1 1 VCO VCO NOTE: SIMCLK runs the periodic interrupt RESET and IRQ≈ pin synchronizers in LPSTOP mode. 4.2.4 Chip Select Operation Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. The MC68340 integrates these functions on chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip select function contains register pairs for each external chip select signal. The pair consists of a base address register and an address mask register that define the characteristics of a single chip select. The register pair provides flexibility for a wide variety of chip select functions. MOTOROLA MC68340 USER’S MANUAL 4-13 4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following programmable features: Four Programmable Chip Select Circuits All four chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select. The base address register selects the starting address for the address block in 256-byte increments. The address mask register specifies the size of the address block range. The base address register V-bit indicates that the register information for that chip select is valid. A global chip select ( CS0) allows address decode for a boot ROM before system initialization occurs. Variable Block Sizes The block size, starting from the specified base address, can vary in size from 256 bytes up to 4 Gbytes in 2n increments. The specified base address must be on a multiple of the the block size. The block size is specified in the address mask register. Both 8- and 16-Bit Ports Supported The 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 15–8; the 16-bit ports can be accessed as odd bytes, even bytes, or even words. The port size is specified by the PS bits in the address mask register. Write Protect Capability The WP bit in each base address register can restrict write access to its range of addresses. Fast Termination Option Programming the FTE bit in the base address register for the fast termination option causes the chip select to terminate the cycle by asserting the internal DSACK≈ early, providing a two-cycle external access. Internal DSACK≈ Generation for External Accesses with Programmable Wait States DSACK≈ can be generated internally with up to three wait states for a particular device using the DD bits in the address mask register. Full 32-Bit Address Decode with Address Space Checking The FC bits in the base address register and FCM bits in the address mask register are used to select address spaces for which the chip selects will be asserted. 4.2.4.2 GLOBAL CHIP SELECT OPERATION. Global chip select operation allows address decode for a boot ROM before system initialization occurs. CS0 is the global chip select output, and its operation differs from the other external chip select outputs following reset. When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register. 4-14 MC68340 USER’S MANUAL MOTOROLA NOTE If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. Global chip select provides a 16-bit port with three wait states, which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at $00000000 and $00000004, respectively. Global chip select does not provide write protection and responds to all function codes. While CS0 is a global chip select, no other chip select (CS1, CS2, CS3 ) can be used. CS0 operates in this manner until the V-bit is set in the CS0 base address register, which will then allow the use of CS3–CS1. Provided the desired address range is first loaded into the CS0 base address register, CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, After the V-bit is set for CS0, global chip select can only be restarted with a system reset. A system can use an 8-bit boot ROM if an external 8-bit DSACK≈ that responds in two or less wait states is generated. The 8-bit DSACK≈ must respond in two or less wait states so that the global chip select, which responds with three wait states, will not be used. See Section 10 Applications for a detailed discussion. 4.2.5 External Bus Interface Operation This section describes port A and port B functions. Refer to Section 3 Bus Operation for more information about the EBI. 4.2.5.1 PORT A. Port A pins can be independently programmed to function as either addresses A31–A24, discrete I/O pins, or IACKx pins. The port A pin assignment registers (PPARA1 and PPARA2) control the function of the port A pins as listed in Table 4-4. Upon reset, port A is configured as input pins. If the system uses these signals as addresses, pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed. Table 4-4. Port A Pin Assignment Register Pin Function Signal MOTOROLA PPARA1 = 0 PPARA1 = 1 PPARA1 = 0 PPARA2 = 0 PPARA2 = X PPARA2 = 1 A31 A31 PORT A7 IACK7 A30 A30 PORT A6 IACK6 A29 A29 PORT A5 IACK5 A28 A28 PORT A4 IACK4 A27 A27 PORT A3 IACK3 A26 A26 PORT A2 IACK2 A25 A25 PORT A1 IACK1 A24 A24 PORT A0 — MC68340 USER’S MANUAL 4-15 4.2.5.2 PORT B. Port B pins can be independently programmed to function as chip selects, IRQ ≈ and MODCK pins, or discrete I/O pins. These pins are multiplexed as shown in Figure 4-7. Selection of a pin function is accomplished by a combination of the port B pin assignment register (PPARB) and the FIRQ bit of the MCR. See Table 4-5 for port B combinations. By changing the value of the FIRQ bit and the corresponding bits in the PPARB for a particular signal, the port B pins can be configured for different pin functions. Upon reset, port B is configured as MODCK, IRQ7, IRQ6, IRQ5, IRQ3, and CS3–CS0. INTERRUPT PORT LOGIC MODCK/PORT B0 IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 IRQ4/PORT B4 IRQ2/PORT B2 IRQ1/PORT B1 CS3/IRQ4/PORT B4 CS2/IRQ2/PORT B2 AVEC FULL IRQ MUX CHIPSELECT MODULE CS1/IRQ1/PORT B1 CS0/AVEC CS3 CS2 CS1 CS0 FIRQ Figure 4-7. Full Interrupt Request Multiplexer Table 4-5. Port B Pin Assignment Register Pin Function Signal FIRQ = 0 FIRQ = 0 FIRQ = 1 FIRQ = 1 PPARB = 0 PPARB = 1 PPARB = 0 PPARB = 1 IRQ7 PORTB7 IRQ7 PORTB7 IRQ7 IRQ6 PORTB6 IRQ6 PORTB6 IRQ6 IRQ5 PORTB5 IRQ5 PORTB5 IRQ5 IRQ3 PORTB3 IRQ3 PORTB3 IRQ3 CS3 CS3 CS3 PORTB4 IRQ4 CS2 CS2 CS2 PORTB2 IRQ2 CS1 CS1 CS1 PORTB1 IRQ1 CS0 CS0 CS0 AVEC AVEC MODCK PORTB0 MODCK PORTB0 MODCK NOTE: MODCK has no function after reset. 4-16 MC68340 USER’S MANUAL MOTOROLA The number of wait states programmed into the internal wait state generation logic by a chip select can be used even though the pin is not used as a C S ≈ signal. The programmed number of wait states in the CS≈ signal applies to the port B pins configured as IRQ≈ or I/O pins. This is done by programming the chip select with the number of wait states to be added, as though it were to be used. The DD1/DD0 and PS1/PS0 bits in the chip select address mask register must be set to add the desired number of wait states (the V-bit in the module base address register should be set). 4.2.6 Low-Power Stop Executing the LPSTOP instruction provides reduced power consumption when the MC68340 is idle; only the SIM40 remains active. Operation of the SIM40 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR (see Table 4-3). LPSTOP disables the clock to the software watchdog in the low state. The software watchdog remains stopped until the LPSTOP mode ends; it begins to run again on the next rising clock edge. NOTE When the CPU32 executes the STOP instruction (as opposed to LPSTOP), the software watchdog continues to run. If the software watchdog is enabled, it issues a reset or interrupt when timeout occurs. The periodic interrupt timer does not respond to an LPSTOP instruction; thus, it can be used to exit LPSTOP as long as the interrupt request level is higher than the CPU32 interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inactive during LPSTOP. The STP bit in the MCR of each on-chip module (DMA, timers, and serial modules) should be set prior to executing the LPSTOP instruction. Setting the STP bit stops all clocks within each of the modules, except for the clock from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR of each module. The system clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or until reset. For more information, see the description of the MCR STP bit for each module. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT (see 3.4.2 LPSTOP Broadcast Cycle ). 4.2.7 Freeze FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode enabled. Refer to Section 5 CPU32 for more information on the background mode. When FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue to operate normally. However, the software watchdog, the periodic interrupt timer and the internal bus monitor will be affected. When FREEZE is asserted, setting the FRZ1 bit in MOTOROLA MC68340 USER’S MANUAL 4-17 the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor. 4.3 PROGRAMMING MODEL Figure 4-8 is a programming model (register map) of all registers in the SIM40. For more information about a particular register, refer to the description of the module or function indicated in the right column. The ADDR (address) column indicates the offset of the register from the address stored in the module base address register. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). For the registers discussed in the following pages, the number in the upper right-hand corner indicates the offset of the register from the address stored in the module base address register. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. NOTE: A CPU32 RESET instruction will not affect any of the SIM40 registers. 4-18 MC68340 USER’S MANUAL MOTOROLA ADDR FC 000 S 15 8 7 0 MODULE CONFIGURATION REGISTER (MCR) SYSTEM PROTECTION 004 S 006 S CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) AUTOVECTOR REGISTER (AVR) RESET STATUS REGISTER (RSR) CLOCK SYSTEM PROTECTION 010 S/U 012 S/U 014 S 016 S 018 RESERVED PORT A DATA (PORTA) EBI RESERVED PORT A DATA DIRECTION (DDRA) EBI RESERVED PORT A PIN ASSIGNMENT 1 (PPRA1) EBI RESERVED PORT A PIN ASSIGNMENT 2 (PPRA2) EBI S/U RESERVED PORT B DATA (PORTB) EBI 01A S/U RESERVED PORT B DATA (PORTB1) EBI 01C S/U RESERVED PORT B DATA DIRECTION (DDRB) EBI 01E S RESERVED PORT B PIN ASSIGNMENT (PPARB) EBI 020 S SW INTERRUPT VECTOR (SWIV) SYSTEM PROTECTION CONTROL (SYPCR) PROTECTION SYSTEM 022 S PERIODIC INTERRUPT CONTROL REGISTER (PICR) SYSTEM PROTECTION 024 S PERIODIC INTERRUPT TIMING REGISTER (PITR) SYSTEM PROTECTION 026 S RESERVED SOFTWARE SERVICE (SWSR) SYSTEM PROTECTION 040 S ADDRESS MASK 1 CS0 CHIP SELECT 042 S ADDRESS MASK 2 CS0 CHIP SELECT 044 S BASE ADDRESS 1 CS0 CHIP SELECT 046 S BASE ADDRESS 2 CS0 CHIP SELECT 048 S ADDRESS MASK 1 CS1 CHIP SELECT 04A S ADDRESS MASK 2 CS1 CHIP SELECT 04C S BASE ADDRESS 1 CS1 CHIP SELECT 04E S BASE ADDRESS 2 CS1 CHIP SELECT 050 S ADDRESS MASK 1 CS2 CHIP SELECT 052 S ADDRESS MASK 2 CS2 CHIP SELECT 054 S BASE ADDRESS 1 CS2 CHIP SELECT 056 S BASE ADDRESS 2 CS2 CHIP SELECT 058 S ADDRESS MASK 1 CS3 CHIP SELECT 05A S ADDRESS MASK 2 CS3 CHIP SELECT 05C S BASE ADDRESS 1 CS3 CHIP SELECT 05E S BASE ADDRESS 2 CS3 CHIP SELECT Figure 4-8. SIM40 Programming Model MOTOROLA MC68340 USER’S MANUAL 4-19 4.3.1 Module Base Address Register (MBAR) MBAR 1 $0003FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 IBA18 BA17 BA16 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only MBAR 2 $0003FF02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 0 0 AS8 AS7 AS6 AS5 AS4 AS3 AS2 AS1 AS0 V RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only BA31–BA12—Base Address Bits 31–12 The base address field is the upper 20 bits of the MBAR that provides for block starting locations in increments of 4-Kbytes. Bits 11, 10—Reserved AS8–AS0—Address Space Bits 8–0 The address space field allows particular address spaces to be masked, placing the 4K module block into a particular address space(s). If an address space is masked, an access to the register block location in that address space becomes an external access. The module block is not accessed. The address space bits are as follows: AS8—mask DMA Space address space (FC3–FC0 = 1xxx) AS7—mask CPU Space address space (FC3–FC0 = 0111) AS6—mask Supervisor Program address space (FC3–FC0 = 0110) AS5—mask Supervisor Data address space (FC3–FC0 = 0101) AS4—mask Reserved [Motorola] address space (FC3–FC0 = 0100) AS3—mask Reserved [User] address space (FC3–FC0 = 0011) AS2—mask User Program address space (FC3–FC0 = 0010) AS1—mask User Data address space (FC3–FC0 = 0001) AS0—mask Reserved [Motorola] address space (FC3–FC0 = 0000) For each address space bit: 1 = Mask this address space from the internal module selection. The bus cycle goes external. 0 = Decode for the internal module block. V—Valid Bit This bit indicates when the contents of the MBAR are valid. The base address value is not used; therefore, all internal module registers are not accessible until the V-bit is set. 1 = Contents are valid. 0 = Contents are not valid. 4-20 MC68340 USER’S MANUAL MOTOROLA NOTE An access to this register does not affect external space since the cycle is not run externally. Example code for accessing the MBAR is as follows: Register D0 will contain the value of MBAR. MBAR can be read using the following code: MOVE.L MOVEC.L LEA.L MOVES.L #7,D0 D0,SFC $0003FF00,A0 (A0),D0 load D0 with the CPU space function code load SFC to indicate CPU space load A0 with the address of MBAR load D0 with the contents of MBAR Address $0003FF00 in CPU space (MBAR) will be loaded with the value $FFFFF001. This value will set the base address of the internal registers to $FFFFF. MBAR can be written to using the following code: MOVE.L MOVEC.L LEA.L MOVE.L MOVES.L #7,D0 D0,DFC $0003FF00,A0 #$FFFFF001,D0 D0,(A0) load D0 with the CPU space function code load DFC to indicate CPU space load A0 with the address of MBAR load D0 with the value to be written into MBAR write the value contained in D0 into MBAR 4.3.2 System Configuration and Protection Registers The following paragraphs provide descriptions of the system configuration and protection registers. 4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the SIM40 configuration, can be read or written at any time. MCR $000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FRZ1 FRZ0 FIRQ 0 0 SHEN1 SHEN0 SUPV 0 0 0 IARB3 IARB2 IARB1 IARB0 RESET: 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 Supervisor Only Bits 15, 11, 10, 6–4—Reserved FRZ1—Freeze Software Enable 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts from occurring during software debug. 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. See 4.2.7 Freeze for more information. MOTOROLA MC68340 USER’S MANUAL 4-21 FRZ0—Freeze Bus Monitor Enable 1 = When FREEZE is asserted, the bus monitor is disabled. 0 = When FREEZE is asserted, the bus monitor continues to operate as programmed. FIRQ—Full Interrupt Request Mode 1 = Configures port B for seven interrupt request lines, autovector, and no external chip selects. 0 = Configures port B for four interrupt request lines and four external chip selects. See Table 4-5 for pin function selection. SHEN1, SHEN0—Show Cycle Enable These two control bits determine what the EBI does with the external bus during internal transfer operations (see Table 4-6). A show cycle allows internal transfers to be externally monitored. The address, data, and control signals (except for AS) are driven externally. DS is used to signal address strobe timing for show cycles. Data is valid on the next falling clock edge after DS is negated. However, data is not driven externally, and AS and DS are not asserted externally for internal accesses unless show cycles are enabled. If external bus arbitration is disabled, the EBI will not recognize an external bus request until arbitration is enabled again. To prevent bus conflicts, external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled. Table 4-6. SHENx Control Bits SHEN1 SHEN0 ACTION 0 0 Show cycles disabled, external arbitration enabled 0 1 Show cycles enabled, external arbitration disabled 1 X Show cycles enabled, external arbitration enabled SUPV—Supervisor/User Data Space The SUPV bit defines the SIM40 registers as either supervisor data space or user (unrestricted) data space. 1 = The SIM40 registers defined as supervisor/user are restricted to supervisor data access (FC3–FC0 = $5). An attempted user-space write is ignored and returns BERR. 0 = The SIM40 registers defined as supervisor/user data are unrestricted (FC2 is a don't care). IARB3–IARB0—Interrupt Arbitration Bits 3–0 These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level. No two modules can share the same IARB value. The reset value of IARB is $F, allowing the SIM40 to arbitrate during an IACK cycle immediately after reset. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A 4-22 MC68340 USER’S MANUAL MOTOROLA value of $0 prevents arbitration and causes all SIM40 interrupts, including external interrupts, to be discarded as extraneous. 4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM40 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level. This register can be read and written at any time. AVR $006 7 6 5 4 3 2 1 0 AV7 AV6 AV5 AV4 AV3 AV2 AV1 0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only NOTE: The IARB field in the MCR must contain a value other than $0 for the SIM40 to autovector for external interrupts. 4.3.2.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source to the SIM40. A set bit indicates the last type of reset that occurred, and only one bit can be set in the register. The RSR is updated by the reset control logic when the SIM40 comes out of reset. This register can be read at any time; a write has no effect. For more information, see Section 3 Bus Operation. RSR $007 7 6 5 4 3 2 1 0 EXT POW SW DBF 0 LOC SYS 0 Supervisor Only EXT—External Reset 1 = The last reset was caused by an external signal driving RESET. POW—Power-Up Reset 1 = The last reset was caused by the power-up reset circuit. SW—Software Watchdog Reset 1 = The last reset was caused by the software watchdog circuit. DBF—Double Bus Fault Monitor Reset 1 = The last reset was caused by the double bus fault monitor. Bits 3, 0—Reserved MOTOROLA MC68340 USER’S MANUAL 4-23 LOC—Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled. SYS—System Reset 1 = The last reset was caused by the CPU32 executing a RESET instruction. The system reset does not load a reset vector or affect any internal CPU32 registers, SIM40 configuration registers, or the MCR in each internal peripheral module (DMA, timers, and serial modules). It will, however, reset external devices and all other registers in the peripheral modules. 4.3.2.4 SOFTWARE INTERRUPT VECTOR REGISTER (SWIV). The SWIV contains the 8-bit vector that is returned by the SIM40 during an IACK cycle in response to an interrupt generated by the software watchdog. This register can be read or written at any time. This register is set to the uninitialized vector, $0F, at reset. SWIV $020 7 6 5 4 3 2 1 0 SWIV7 SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 SWIV0 RESET: 0 0 0 0 1 1 1 1 Supervisor Only 4.3.2.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls the system monitors, the prescaler for the software watchdog, and the bus monitor timing. This register can be read at any time, but can be written only once after reset. SYPCR $021 7 6 5 4 3 2 1 0 SWE SWRI SWT1 SWT0 DBFE BME BMT1 BMT0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only SWE—Software Watchdog Enable 1 = Software watchdog is enabled. 0 = Software watchdog is disabled. See 4.2.2.5 Software Watchdog for more information. SWRI—Software Watchdog Reset/Interrupt Select 1 = Software watchdog causes a system reset. 0 = Software watchdog causes a level 7 interrupt to the CPU32. 4-24 MC68340 USER’S MANUAL MOTOROLA SWT1, SWT0—Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: divide count EXTAL frequency The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator. Table 4-7. Deriving Software Watchdog Timeout SWP SWT1 SWT0 Software Timeout Period 32.768-kHz Crystal Period 16.777-MHz External Clock Period 0 0 0 29/EXTAL Input Frequency 15.6 ms 30 µs 62.5 ms 122 µs 0 0 1 211 /EXTAL Input Frequency 0 1 0 213 /EXTAL Input Frequency 250 ms 488 µs 0 1 1 215 /EXTAL Input Frequency 1s 1.95 ms 0 218 /EXTAL Input Frequency 8s 15.6 ms 32 s 62.5 ms 1 0 1 0 1 220 /EXTAL Input Frequency 1 1 0 222 /EXTAL Input Frequency 128 s 250 ms 1 1 1 224 /EXTAL Input Frequency 512 s 1s NOTE: When the SWP and SWT bits are modified to select a software timeout other than the default, the software service sequence ($55 followed by $AA written to the software service register) must be performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for more information. DBFE—Double Bus Fault Monitor Enable 1 = Enable double bus fault monitor function. 0 = Disable double bus fault monitor function. For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32. BME—Bus Monitor External Enable 1 = Enable bus monitor function for an internal-to-external bus cycle. 0 = Disable bus monitor function for an internal-to-external bus cycle. For more information see 4.2.2.2 Internal Bus Monitor. BMT1, BMT0—Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the bus monitor is set to 64 system clocks. MOTOROLA MC68340 USER’S MANUAL 4-25 Table 4-8. BMTx Encoding BMT1 BMT0 0 0 64 system clocks (CLKOUT) Bus Monitor Timeout Period 0 1 32 system clocks 1 0 16 system clocks 1 1 8 system clocks 4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time. Bits 15–11 are unimplemented and always return zero; a write to these bits has no effect. PICR $022 15 14 13 12 11 0 0 0 0 0 RESET: 0 0 0 0 0 10 9 8 PIRQL2 PIRQL1 PIRQL0 0 0 0 7 6 5 4 3 2 1 0 PIV7 PIV6 PIV5 PIV4 PIV3 PIV2 PIV1 PIV0 0 0 0 0 1 1 1 1 Supervisor Only Bits 15–11—Reserved PIRQL2–PIRQL0—Periodic Interrupt Request Level These bits contain the periodic interrupt request level. Table 4-9 lists which interrupt request level is asserted during an IACK cycle when a periodic interrupt is generated. The periodic timer continues to run when the interrupt is disabled. Table 4-9. PIRQL Encoding PIRQL2 PIRQL1 PIRQL0 Interrupt Request Level 0 0 0 Periodic Interrupt Disabled 0 0 1 Interrupt Request Level 1 0 1 0 Interrupt Request Level 2 0 1 1 Interrupt Request Level 3 1 0 0 Interrupt Request Level 4 1 0 1 Interrupt Request Level 5 1 1 0 Interrupt Request Level 6 1 1 1 Interrupt Request Level 7 NOTE: Use caution with a level 7 interrupt encoding due to the SIM40's interrupt servicing order. See 4.2.2.7 Simultaneous Interrupts by Sources in the SIM40 for the servicing order. 4-26 MC68340 USER’S MANUAL MOTOROLA PIV7–PIV0—Periodic Interrupt Vector Bits 7–0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer. When the SIM40 responds to the IACK cycle, the periodic interrupt vector from the PICR is placed on the bus. This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector. 4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for prescaling the software watchdog and periodic timer as well as the count value for the periodic timer. This register can be read or written at any time. Bits 15–10 are not implemented and always return zero when read. A write does not affect these bits. PITR $024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SWP PTP PITR7 PITR6 PITR5 PITR4 PITR3 PITR2 PITR1 PITR0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET: 0 MODCK MODCK Supervisor Only Bits 15–10—Reserved SWP—Software Watchdog Prescale This bit controls the software watchdog clock source as shown in 4.3.2.5 System Protection Control Register (SYPCR). 1 = Software watchdog clock prescaled by a value of 512. 0 = Software watchdog clock not prescaled. The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset. PTP—Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer. 1 = Periodic timer clock prescaled by a value of 512. 0 = Periodic timer clock not prescaled. The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset. PITR7–PITR0—Periodic Interrupt Timer Register Bits 7–0 The remaining bits of the PITR contain the count value for the periodic timer. A zero value turns off the periodic timer. MOTOROLA MC68340 USER’S MANUAL 4-27 4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but returns all zeros when read. SWSR 7 $027 6 5 4 3 2 1 0 SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only 4.3.3 Clock Synthesizer Control Register (SYNCR) The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768kHz reference signal. The system frequency is controlled by the frequency control bits in the upper byte of the SYNCR as follows: FSYSTEM = FCRYSTAL [2(2+2W+X) ] × (Y+1) SYNCR $004 15 14 13 12 11 10 9 8 7 6 5 W X Y5 Y4 Y3 Y2 Y1 Y0 RSVD 0 0 RESET: 0 0 1 1 1 1 1 1 0 0 0 U = Unaffected by reset 4 3 SLIMP SLOCK U U 2 1 0 RSTEN STSIM STEXT 0 0 0 Supervisor Only W—Frequency Control Bit This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO speed by a factor of 4, requiring a time delay for the VCO to relock (see equation for determining system frequency). X—Frequency Control Bit This bit controls a divide-by-two prescaler, which is not in the synthesizer feedback loop. Setting the bit doubles the system clock speed without changing the VCO speed, as specified in the equation for determining system frequency; therefore, no delay is incurred to relock the VCO. Y5–Y0—Frequency Control Bits The Y-bits, with a value from 0–63, control the modulus downcounter in the synthesizer feedback loop, causing it to divide by the value of Y+1 (see the equation for determining system frequency). Changing these bits requires a time delay for the VCO to relock. Bits 7–5—Reserved Bit 7 is reserved for factory testing. 4-28 MC68340 USER’S MANUAL MOTOROLA SLIMP—Limp Mode 1 = A loss of input signal reference has been detected, and the VCO is running at approximately one-half the maximum speed (affected by the X-bit ), determined from an internal voltage reference. 0 = External input signal frequency is at VCO reference. SLOCK—Synthesizer Lock 1 = VCO has locked onto the desired frequency (or system clock is driven externally). 0 = VCO is enabled, but has not yet locked. RSTEN—Reset Enable 1 = Loss of input signal causes a system reset. 0 = Loss of input signal causes the VCO to operate at a nominal speed without external reference (limp mode), and the device continues to operate at that speed. STSIM—Stop Mode System Integration Clock 1 = When LPSTOP is executed, the SIM40 clock is driven from the VCO. 0 = When LPSTOP is executed, the SIM40 clock is driven from an external crystal or oscillator, and the VCO is turned off to conserve power. STEXT—Stop Mode External Clock 1 = When the LPSTOP instruction is executed, the external clock pin (CLKOUT) is driven from the SIM40 clock as determined by the STSIM bit. 0 = When the LPSTOP instruction is executed, the external clock (CLKOUT) is held low to conserve power. No external clock will be driven in LPSTOP mode. 4.3.4 Chip Select Registers The following paragraphs provide descriptions of the registers in the chip select function, and an example of how to program the registers. The chip select registers cannot be used until the V-bit in the MBAR is set. MOTOROLA MC68340 USER’S MANUAL 4-29 4.3.4.1 BASE ADDRESS REGISTERS. There are four 32-bit base address registers in the chip select function, one for each chip select signal. Base Address 1 $044, $04C, $054, $05C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 RESET: U U U U U U U U U U U U U U U U Supervisor Only Base Address 2 $046, $04E, $056, $05E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BFC3 BFC2 BFC1 BFC0 WP FTE NCS V RESET: U U U U U U U U U U U U U U 0 0 U = Unaffected by reset Supervisor Only BA31–BA8—Base Address Bits 31–8 The base address field, the upper 24 bits of each base address register, selects the starting address for the chip select. The specified base address must be on a multiple of the selected block size. The corresponding bits, AM31–AM8, in the address mask register define the size of the block for the chip select. The base address field (and the base function code field) is compared to the address on the address bus to determine if a chip select should be generated. BFC3–BFC0—Base Function Code Bits 3–0 The value programmed into this field causes a chip select to be asserted for a certain address space type. There are nine function code address spaces (see Section 3 Bus Operation) specified as either user or supervisor, program or data, CPU, and DMA. These bits should be used to allow access to one type of address space. If access to more than one type of address space is desired, the FCMx bits should be used in addition to the BFCx bits. To prevent access to CPU space, set the NCS bit. WP—Write Protect This bit can restrict write accesses to the address range in a base address register. An attempt to write to the range of addresses specified in a base address register that has this bit set returns BERR. 1 = Only read accesses are allowed. 0 = Either read or write accesses are allowed. FTE—Fast-Termination Enable This bit causes the cycle to terminate early with an internal DSACK≈, giving a fast twoclock external access. When clear, all external cycles are at least three clocks. If fast termination is enabled, the DD bits of the corresponding address mask register are overridden (see Section 3 Bus Operation). 1 = Fast termination cycle enabled (termination determined by PS bits). 0 = Fast termination cycle disabled (termination determined by DD and PS bits). 4-30 MC68340 USER’S MANUAL MOTOROLA NCS—No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle (FC3–FC0 = $7 or $F). If both supervisor data and program accesses are desired, while ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at reset. 1 = Suppress the chip select on a CPU space access. 0 = Assert the chip select on a CPU space access. V—Valid Bit This bit indicates that the contents of its base address register and address mask register pair are valid. The programmed chip selects do not assert until the V-bit is set. A reset clears the V-bit in each base address register, but does not change any other bits in the base address and address mask registers ( CS0 is a special case, see 4.2.4.2 Global Chip Select Operation). 1 = Contents are valid. 0 = Contents are not valid. 4.3.4.2 ADDRESS MASK REGISTERS. There are four 32-bit address mask registers in the chip select function, one for each chip select signal. Address Mask 1 $040, $048, $050, $058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AM31 AM30 AM29 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 AM20 AM19 AM18 AM17 AM16 RESET: U U U U U U U U U U U U U U U U Supervisor Only Address Mask 2 $042, $04A, $052, $05A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AM15 AM14 AM13 AM12 AM11 AM10 AM9 AM8 FCM3 FCM2 FCM1 FCM0 DD1 DD0 PS1 PS0 RESET: U U U U U U U U U U U U U U U U U = Unaffected by reset Supervisor Only AM31–AM8—Address Mask Bits 31–8 The address mask field, the upper 24 bits of each address mask register, defines the chip select block size. The block size is equal to 2n , where n = (number of bits set in the address mask field) + 8. Any set bit masks the corresponding base address register bit (the base address register bit becomes a don’t care). By masking the address bits independently, external devices of different size address ranges can be used. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time. MOTOROLA MC68340 USER’S MANUAL 4-31 FCM3–FCM0—Function Code Mask Bits 3–0 This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit. DD1, DD0—DSACK Delay Bits 1 and 0 This field determines the number of wait states added before an internal DSACK≈ is returned for that entry. Table 4-10 lists the encoding for the DD bits. NOTE: The port size field must be programmed for an internal DSACK ≈ response and the FTE bit in the base address register must be cleared for the DDx bits to have significance. If external DSACK≈ signals are returned earlier than indicated by the DDx bits, the cycle will terminate sooner than programmed. See 4.2.5.2 PORT B for a discussion on using the internal DSACK≈ generation without using the CS≈ signal. Table 4-10. DDx Encoding DD1 DD0 Response 0 0 Zero Wait State 0 1 One Wait State 1 0 Two Wait States 1 1 Three Wait States PS1, PS0—Port Size Bits 1 and 0 This field determines whether a given chip select responds with DSACK≈ and, if so, what port size is returned. Table 4-11 lists the encoding for the PSx bits. Table 4-11. PSx Encoding PS1 PS0 Mode 0 0 Reserved* 0 1 16-Bit Port 1 0 8-Bit Port 1 1 External DSACK≈ Response *Use only for 32-bit DMA transfers. To use the external DSACK≈ response, PS1–PS0 = 11 should be selected to suppress internal DSACK≈ generation. The DDx bits then have no significance. 4-32 MC68340 USER’S MANUAL MOTOROLA 4.3.4.3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is an example of programming a chip select at starting address $00040000, for a block size of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two wait states. There will be no write protection, no fast termination, and no CPU space accesses. base address 1 = $0004 base address 2 = $0013 address mask 1 = $0003 address mask 2 = $FF49 NOTE If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. 4.3.5 External Bus Interface Control The following paragraphs describe the registers that control the I/O pins used with the EBI. Refer to the Section 3 Bus Operation for more information about the EBI. For a list of pin numbers used with port A and port B, see the pinout diagram in Section 12 Ordering Information and Mechanical Data. Section 2 Signal Descriptions shows a block diagram of the port control circuits. 4.3.5.1 PORT A PIN ASSIGNMENT REGISTER 1 (PPARA1). PPARA1 selects between an address and discrete I/O function for the port A pins. Any set bit defines the corresponding pin to be an I/O pin, controlled by the port A data and data direction registers. Any cleared bit defines the corresponding pin to be an address bit as defined in the following register diagram. Bits set in this register override the configuration setting of PPARA2. The $FF reset value of PPARA1 configures it as an input port. This register can be read or written at any time. PPARA1 $015 7 6 5 4 3 2 1 0 PRTA7 (A31) PRTA6 (A30) PRTA5 (A29) PRTA4 (A28) PRTA3 (A27) PRTA2 (A26) PRTA1 (A25) PRTA0 (A24) RESET: 1 1 1 1 1 1 1 1 Supervisor Only MOTOROLA MC68340 USER’S MANUAL 4-33 4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between an address and IACK≈ function for the port A pins. Any set bit defines the corresponding pin to be an IACK ≈ output pin. Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram. Any set bits in PPARA1 override the configuration set in PPARA2. Bit 0 has no function in this register because there is no level 0 interrupt. This register can be read or written at any time. PPARA2 $017 7 6 5 4 3 2 1 0 IACK7 (A31) IACK6 (A30) IACK5 (A29) IACK4 (A28) IACK3 (A27) IACK2 (A26) IACK1 (A25) 0 RESET: 0 0 0 0 0 0 0 0 Supervisor Only The IACK ≈ signals are asserted if a bit in PPARA2 is set and the CPU32 services an external interrupt at the corresponding level. IACK ≈ signals have the same timing as address strobes. NOTE: Upon reset, port A is configured as an input port. 4.3.5.3 PORT A DATA DIRECTION REGISTER (DDRA). DDRA controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output. Any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRA $013 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 RESET: 0 0 0 0 0 0 0 0 Supervisor/User 4.3.5.4 PORT A DATA REGISTER (PORTA). PORTA affects only pins configured as discrete I/O. A write to PORTA is stored in the internal data latch, and if any port A pin is configured as an output, the value stored for that bit is driven on the pin. A read of PORTA returns the value at the pin only if the pin is configured as discrete input. Otherwise, the value read is the value stored in the internal data latch. This register can be read or written at any time. PORTA $011 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 RESET: U U U U U U U U Supervisor/User 4-34 MC68340 USER’S MANUAL MOTOROLA 4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin to be an IRQ≈ input or CS≈ as defined in Table 4-5. Any cleared bit defines the corresponding pin to be a discrete I/O pin (or CS ≈ if the FIRQ bit of the MCR is zero) controlled by the port B data and data direction registers. The MODCK signal has no function after reset. PPARB is configured to all ones at reset to provide for MODCK, IRQ7, IRQ6, IRQ5, IRQ3, and CS3– CS0. This register can be read or written at any time. PPARB $01F 7 6 5 4 3 2 1 0 PPARB7 (IRQ7) PPARB6 (IRQ6) PPARB5 (IRQ5) PPARB4 (IRQ4) PPARB3 (IRQ3) PPARB2 (IRQ2) PPARB1 (IRQ1) PPARB0 (MODCK) RESET: 1 1 1 1 1 1 1 1 Supervisor Only 4.3.5.6 PORT B DATA DIRECTION REGISTER (DDRB). DDRB controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output; any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRB $01D 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 RESET: 0 0 0 0 0 0 0 0 Supervisor/User 4.3.5.7 PORT B DATA REGISTER (PORTB, PORTB1). This is a single register that can be accessed at two different addresses. This register affects only those pins configured as discrete I/O. A write is stored in the internal data latch, and if any port B pin is configured as an output, the value stored for that bit is driven on the pin. A read of this register returns the value stored in the register only if the pin is configured as a discrete output. Otherwise, the value read is the value of the pin. This register can be read or written at any time. PORTB, PORTB1 $019, 01B 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 RESET: U U U U U U U U Supervisor/User MOTOROLA MC68340 USER’S MANUAL 4-35 4.4 MC68340 INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the MC68340 after power-up. 4.4.1 Startup RESET is asserted by the MC68340 during the time in which V CC is ramping up, the VCO is locking onto the frequency, and the MC68340 is going through the reset operation. After RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the 32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot ROM. Until programmed differently, CS0 is a global, 16-bit-wide, three-wait-state chip select. CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, provided the desired address range is first loaded into the CS0 base address register. After the V-bit is set for CS0 , global chip select can only be restarted with a system reset. After the SSP and the PC are fetched, the module base address register (MBAR) should be initialized, and the MBAR V-bit should be set (CPU space address $0003FF00) with the desired base address for the internal modules. 4.4.2 SIM40 Module Configuration The order of the following SIM40 register initializations is not important; however, time can be saved by initializing the SYNCR first to quickly increase to the desired processor operating frequency. The module base address register must be initialized prior to any of following steps. Clock Synthesizer Control Register (SYNCR): • Set frequency control bits (W, X, Y) to specify frequency. • Select action taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp mode. • Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits). Module Configuration Register (MCR) • If using the software watchdog, periodic interrupt timer, and/or the bus monitor, select action taken when FREEZE is asserted (FRZx bits). • Select port B configuration (FIRQ bit). Note that this bit is used in combination with the bits in the PPARB to program the function of the port B pins. • Select the access privilege for the supervisor/user registers (SUPV bit). • Select the interrupt arbitration level for the SIM40 (IARBx bits). Autovector Register (AVR) • Select the desired external interrupt levels for internal autovectoring. 4-36 MC68340 USER’S MANUAL MOTOROLA System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.) • Enable the software watchdog, if desired (SWE bit). • If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit). • If the watchdog is enabled, select the timeout period (SWTx bits). • Enable the double bus fault monitor, if desired (DBFE bit). • Enable the external bus monitor, if desired (BME bit). • Select timeout period for bus monitor (BMTx bits). Software Watchdog Interrupt Vector Register (SWIV) • If using the software watchdog, program the vector number for a software watchdog interrupt. Periodic Interrupt Timer Register (PITR) • If using the software watchdog, select whether or not to prescale (SWP bit). • If using the periodic interrupt timer, select whether or not to prescale (PTP bit). • Program the count value for the periodic timer, or program a zero value to turn off the periodic timer (PITRx bits). Periodic Interrupt Control Register (PICR) • If using the periodic timer, program the desired interrupt level for the periodic interrupt timer (PIRQLx bits). • If using the periodic timer, program the vector number for a periodic timer interrupt. Chip Select Base Address and Address Mask Registers • Initialize and set the V-bits in the necessary chip select base address and address mask registers. Following this step, other system resources requiring the CS≈ signals can be accessed. Care must be exercised when changing the address for CS0. The address of the instruction following the MOVE instruction to the CS0 base address register must match the value of the PC at that time. CS0 must be taken out of global chip select mode by setting the V-bit in the base address register before CS3–CS1 can be used. Port A and B Registers • Program the desired function of the port A signals (PPARA1 and PPARA2 registers). • Program the desired function of the port B signals (PPARB register). MOTOROLA MC68340 USER’S MANUAL 4-37 4.4.3 SIM40 Example Configuration Code The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation. * It includes chip select programming for external devices. * This code would be programmed beginning at offset $0 into ROM which is * relocated to address $60000 by the initialization code. * The SSP_VEC and RST_VEC vectors used to initialize the system stack * pointer and initial PC, respectively, are located at offset $0 after * reset. *************************************************************************** * equates *************************************************************************** SSP_INIT EQU $10000 Stack pointer initial value - top of RAM MBAR EQU $0003FF00 Address of Module Base Address Reg. MODBASE EQU $FFFFF000 Default Module Base address value **************************************** * SIM40 register offsets from MBAR base address MCR EQU $00 SYNCR EQU $04 SYPCR EQU $21 CSAM0 EQU $40 CSBAR0 EQU $44 CSAM1 EQU $48 CSBAR1 EQU $4c CSAM2 EQU $50 CSBAR2 EQU $54 CSAM3 EQU $58 CSBAR3 EQU $5c *************************************************************************** * Reset vectors * These two vectors should be located at addresses $0 and $4 after a processor * hardware reset. *************************************************************************** ORG $60000 SSP_VEC DC.L SSP_INIT Supervisor stack pointer - initial value RST_VEC DC.L INIT340 Reset vector pointing to initialization code 4-38 MC68340 USER’S MANUAL MOTOROLA *************************************************************************** * Initialization code *************************************************************************** * Start Chip Select Initialization: INIT340 MOVE.W #$2700,SR Init SR - interrupts masked *************************************************************************** * Set up default module base address value MOVEQ.L #7,D0 MBAR is in CPU space MOVEC.L D0,DFC load DFC to indicate CPU space MOVE.L #MODBASE+1,D0 Set address/valid bit MOVES.L D0,MBAR write to MBAR *************************************************************************** * Set up system protection register: * Software watchdog disabled, double bus fault monitor disabled, bus * monitor BERR after 16 clocks. MOVE.B #6,SYPCR+MODBASE *************************************************************************** * Clock synthesizer control register: * Switch from 8.3 to 16.7 MHZ MOVE.W #$7F00,SYNCR+MODBASE X-bit doubles the default speed *************************************************************************** * Module configuration register: * When FREEZE is asserted, software watchdog and periodic interrupt timer * are disabled, bus monitor is enabled. Port B = 4 IRQs, 4 chip selects. * Show Cycles enabled, external arbitration enabled. Supervisor/user * SIM registers unrestricted, Interrupt Arbitration at priority $F MOVE.W #$420F,MCR+MODBASE *************************************************************************** * Now, set up Address masks and base addresses for the chip selects: LEA CSAM0+MODBASE,A0 Point to CS0 addr. mask location. MOVEQ #7,D Set up a loop counter. LEA CSAM0$,A1 Point to addr mask memory location. LOOP MOVE.L (A1)+,(A0)+ Init. addr mask and base addr reg DBRA D0,LOOP MOTOROLA MC68340 USER’S MANUAL 4-39 *************************************************************************** * Data table for chip select initialization *************************************************************************** * CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit term., write protect CSAM0$ DC.L $0001FFFD CSBAR0$ DC.L $00060009 * CS1 - RAM - 00000000-0000ffff, fast termination CSAM1$ DC.L $0000FFF0 CSBAR1$ DC.L $00000005 * CS2 - external device - 00FFE8xx, external termination CSAM2$ DC.L $000000F3 CSBAR2$ DC.L $00FFE801 * CS3 - secondary memory - 00000000-0003ffff, 3-wait states, 16-bit term. CSAM3$ DC.L $0003FFFD CSBAR3$ DC.L $00000001 *************************************************************************** END 4-40 MC68340 USER’S MANUAL MOTOROLA SECTION 5 CPU32 The CPU32, the first-generation instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family. 5.1 OVERVIEW The CPU32 is designed to interface to the intermodule bus (IMB), allowing interaction with other IMB submodules. In this manner, integrated processors can be developed that contain useful peripherals on chip. This integration provides high-speed accesses among the IMB submodules, increasing system performance. Another advantage of the CPU32 is low power consumption. The CPU32 is implemented in high-speed complementary metal-oxide semiconductor (HCMOS) technology, providing low power use during normal operation. During periods of inactivity, the LPSTOP instruction can be executed, shutting down the CPU32 and other IMB modules, greatly reducing power consumption. Ease of programming is an important consideration when using an integrated processor. The CPU32 instruction format reflects a predominate register-memory interaction philosophy. All data resources are available to all operations that require them. The programming model includes eight multifunction data registers and seven general-purpose addressing registers. The data registers readily support 8-bit (byte), 16-bit (word), and 32bit (long-word) operand lengths for all operations. Address manipulation is supported by word and long-word operations. Although the program counter (PC) and stack pointers (SP) are special-purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level. As processor applications become more complex and programs become larger, high-level language (HLL) will become the system designer's choice in programming languages. HLL aids in the rapid development of complex algorithms with less error and is readily portable. The CPU32 instruction set will efficiently support HLL. MOTOROLA MC68340 USER’S MANUAL 5-1 5.1.1 Features Features of the CPU32 are as follows: • Fully Upward Object-Code Compatible with M68000 Family • Virtual Memory Implementation • Loop Mode of Instruction Execution • Fast Multiply, Divide, and Shift Instructions • Fast Bus Interface with Dynamic Bus Port Sizing • Improved Exception Handling for Embedded Control Applications • Additional Addressing Modes — Scaled Index — Address Register Indirect with Base Displacement and Index — Expanded PC Relative Modes — 32-Bit Branch Displacements • Instruction Set Additions — High-Precision Multiply and Divide — Trap On Condition Codes — Upper and Lower Bounds Checking • Enhanced Breakpoint Instruction • Trace on Change of Flow • Table Lookup and Interpolate Instruction • LPSTOP Instruction • Hardware BKPT Signal, Background Mode • Fully Static Implementation A block diagram of the CPU32 is shown in Figure 5-1. The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit. 5.1.2 Virtual Memory A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The 5-2 MC68340 USER’S MANUAL MOTOROLA CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the page fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program. SEQUENCER CONTROL UNIT DATA BUS ADDRESS BUS INSTRUCTION PREFETCH AND DECODE 16 BUS CONTROL EXECUTION UNIT BUS CONTROL 32 Figure 5-1. CPU32 Block Diagram 5.1.3 Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops. One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is implemented in conjunction with the DBcc instruction. Figure 5-2 shows the required form of an instruction loop for the processor to enter loop mode. ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 Figure 5-2. Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed and the loop displacement is –4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination MOTOROLA MC68340 USER’S MANUAL 5-3 condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions. 5.1.4 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize the supervisor stack pointer (SSP) and the address used to initialize the PC. The address of an interrupt exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; other numbers are supplied automatically by the processor. The processor multiplies the vector number by 4 to calculate the vector offset, which is added to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Refer to 5.5 Exception Processing for additional details. 31 0 VECTOR BASE REGISTER (VBR) 5.1.5 Exception Handling The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary internal copy of the status register (SR) is made, and the SR is set for exception processing. During the second step, the exception vector is determined. During the third step, the current processor context is saved. During the fourth step, a new context is obtained, and the processor then proceeds with instruction processing. Exception processing saves the most volatile portion of the current context by pushing it on the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes the SR and PC context of the processor when the exception occurred. To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. 5-4 MC68340 USER’S MANUAL MOTOROLA 5.1.6 Addressing Modes Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: • Register Direct • Register Indirect • Register Indirect with Index • Program Counter Indirect with Displacement • Program Counter Indirect with Index • Absolute • Immediate Included in the register indirect addressing modes are the capabilities to postincrement, predecrement, and offset. The PC relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the SR, SP and/or PC. Addressing is explained fully in the M68000PM/AD, M68000 Family Programmer’s Reference Manual . 5.1.7 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 (see Table 5-1). Two new instructions have been added to facilitate embedded control applications: LPSTOP and table lookup and interpolate (TBL). The following M68020 instructions are not implemented on the CPU32: BFxxx — Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) CALLM, RTM — Call Module, Return Module CAS, CAS2 — Compare and Set (Read-Modify-Write Instructions) cpxxx — Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc) PACK, UNPK — Pack, Unpack BCD Instructions The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define specialpurpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. MOTOROLA MC68340 USER’S MANUAL 5-5 Table 5-1. Instruction Set Mnemonic ABCD ADD ADDA ADDI ADDQ AND ANDI ASL ASR Bcc BCHG BCLR BGND BKPT BRA BSET BSR BTST CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LPSTOP LSL, LSR MOVE 5-6 Description Mnemonic Add Decimal with Extend Add Add Address Add Immediate Add Quick Logical AND Logical AND Immediate Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally (16 Tests) Bit Test and Change Bit Test and Clear Enter Background Mode Breakpoint Branch Always Bit Test and Set Branch to Subroutine Bit Test Check Register against Bounds Check Register against Upper and Lower Bounds Clear Operand Compare Compare Address Compare Immediate Compare Memory Compare Register against Upper and Lower Bounds Test Condition, Decrement and Branch (16 Tests) Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Low-Power Stop Logical Shift Left and Right Move MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEG NEGX NOP NOT OR ORI PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TBLS, TBLSN Description Move Address Move Condition Code Register Move to/from Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Data Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Ones Complement Logical Inclusive OR Logical Inclusive OR Immediate Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return and Restore Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Data Register Halves Test and Set Operand Table Lookup and Interpolate, Signed TBLU, TBLUN Table Lookup and Interpolate, Unsigned TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink MC68340 USER’S MANUAL MOTOROLA 5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize throughput for real-time applications, reference data is often “particulated” and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, thus reducing memory requirements. Intermediate values are recovered with this instruction via linear interpolation. The results may be rounded by a round-to-nearest algorithm. 5.1.7.2 LOW-POWER STOP INSTRUCTION. In applications where power consumption is a consideration, the CPU32 forces the device into a low-power standby mode when immediate processing is not required. The low-power stop mode is entered by executing the LPSTOP instruction. The processor will remain in this mode until a user-specified (or higher) interrupt level or reset occurs. 5.1.8 Processing States The processor is always in one of four processing states: normal, exception, halted, or background. The normal processing state is that associated with instruction execution; the bus is used to fetch instructions and operands and to store results. The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. The background processing state is initiated by breakpoints, execution of special instructions, or a double bus fault. Background processing allows interactive debugging of the system via a simple serial interface. Refer to 5.4 Processing States for details. 5.1.9 Privilege States The processor operates at one of two levels of privilege—supervisor or user. The supervisor level has higher privileges than the user level. Not all instructions are permitted to execute in the lower privileged user level, but all instructions are available at the supervisor level. This scheme allows the supervisor to protect system resources from uncontrolled access. The processor uses the privilege level indicated by the S-bit in the SR to select either the user or supervisor privilege level and either the user stack pointer (USP) or SSP for stack operations. MOTOROLA MC68340 USER’S MANUAL 5-7 5.2 ARCHITECTURE SUMMARY The CPU32 is upward source- and object-code compatible with the MC68000 and MC68010. It is downward source- and object-code compatible with the MC68020. Within the M68000 family, architectural differences are limited to the supervisory operating state. User state programs can be executed unchanged on upward-compatible devices. The major CPU32 features are as follows: • 32-Bit Internal Data Path and Arithmetic Hardware • 32-Bit Address Bus Supported by 32-Bit Calculations • Rich Instruction Set • Eight 32-Bit General-Purpose Data Registers • Seven 32-Bit General-Purpose Address Registers • Separate User and Supervisor Stack Pointers • Separate User and Supervisor State Address Spaces • Separate Program and Data Address Spaces • Many Data Types • Flexible Addressing Modes • Full Interrupt Processing • Expansion Capability 5.2.1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can only use the registers of the user model. The supervisor programming model, which supplements the user programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of MC68010 and later processors. The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC, separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32-bit VBR (see Figures 5-3 and 5-4). 5-8 MC68340 USER’S MANUAL MOTOROLA 31 16 15 8 7 0 D0 D1 D2 D3 DATA REGISTERS D4 D5 D6 D7 31 16 15 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 31 16 15 0 A7 (USP) 31 USER STACK POINTER 0 15 8 7 PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 0 Figure 5-3. User Programming Model 31 16 15 15 0 8 7 SUPERVISOR STACK POINTER SR STATUS REGISTER PC PROGRAM COUNTER SFC ALTERNATE FUNCTION CODE REGISTERS 0 (CCR) 31 31 A7' (SSP) 0 3 2 0 DFC Figure 5-4. Supervisor Programming Model Supplement MOTOROLA MC68340 USER’S MANUAL 5-9 5.2.2 Registers Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level. In addition, address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D7–D0, A7–A0) may be used as index registers. The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. The SR (see Figure 5-5) contains condition codes, an interrupt priority mask (three bits), and three control bits. Condition codes reflect the results of a previous operation. The codes are contained in the low byte (CCR) of the SR. The interrupt priority mask determines the level of priority an interrupt must have to be acknowledged. The control bits determine trace mode and privilege level. At user privilege level, only the CCR is available. At supervisor privilege level, software can access the full SR. The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. Alternate source and destination function code registers (SFC and DFC) contain 3-bit function codes. The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. USER BYTE (CONDITION CODE REGISTER) SYSTEM BYTE 15 T1 14 T0 13 S 12 0 TRACE ENABLE 11 0 10 I2 9 I1 8 I0 7 0 6 0 5 0 INTERRUPT PRIORITY MASK 4 X 3 N 2 Z 1 V 0 C EXTEND NEGATIVE ZERO SUPERVISOR/USER STATE OVERFLOW CARRY Figure 5-5. Status Register 5-10 MC68340 USER’S MANUAL MOTOROLA 5.3 INSTRUCTION SET The following paragaphs describe the set of instructions provided in the CPU32 and demonstrate their use. Descriptions of the instruction format and the operands used by instructions are included. After a summary of the instructions by category, a detailed description of each instruction is listed in alphabetical order. Complete programming information is provided, as well as a description of condition code computation and an instruction format summary. The CPU32 instructions include machine functions for all the following operations: • Data Movement • Arithmetic Operations • Logical Operations • Shifts and Rotates • Bit Manipulation • Conditionals and Branches • System Control The large instruction set encompasses a complete range of capabilities and, combined with the enhanced addressing modes, provides a flexible base for program development. 5.3.1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user-mode programs can execute unchanged on a more advanced processor and that supervisor-mode programs and exception handlers should require only minimal alteration. The CPU32 can be thought of as an intermediate member of the M68000 family. Object code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also supported. 5.3.1.1 NEW INSTRUCTIONS. Two instructions have been added to the M68000 instruction set for use in embedded control applications: LPSTOP and table lookup and interpolation (TBL). 5.3.1.1.1 Low-Power Stop (LPSTOP). In applications where power consumption is a consideration, the CPU32 can force the device into a low-power standby mode when immediate processing is not required. The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs. MOTOROLA MC68340 USER’S MANUAL 5-11 5.3.1.1.2 Table Lookup and Interpolation (TBL). To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, and thus conserves memory. When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them. Byte, word, and longword operand sizes are supported. The result can be rounded according to a round-tonearest algorithm or returned unrounded along with the fractional portion of the calculated result (byte and word results only). This extra precision can be used to reduce cumulative error in complex calculations. See 5.3.4 Using the TBL Instructions for examples. 5.3.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details. 5.3.2 Instruction Format and Notation All instructions consist of at least one word. Some instructions can have as many as seven words, as shown in Figure 5-6. The first word of the instruction, called the operation word, specifies instruction length and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argument counts. 15 0 OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO THREE WORDS) Figure 5-6. Instruction Word General Format 5-12 MC68340 USER’S MANUAL MOTOROLA Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: • Register Specification A register field of the instruction contains the number of the register. • Effective Address An effective address field of the instruction contains address mode information. • Implicit Reference The definition of an instruction implies the use of specific registers. The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register is an address or data register and how it is to be used. The M68000PM/AD, M68000 Family Programmer’s Reference Manual , contains detailed register information. Except where noted, the following notation is used in this section: Data Immediate data from an instruction Destination Destination contents Source Source contents Vector Location of exception vector An Any address register (A7–A0) Ax, Ay Address registers used in computation Dn Any data register (D7–D0) Rc Control register (VBR, SFC, DFC) Rn Any address or data register Dh, Dl Data registers, high- and low-order 32 bits of product Dr, Dq Data registers, division remainder, division quotient Dx, Dy Data registers, used in computation Dym, Dyn Data registers, table interpolation values Xn Index register [An] Address extension cc Condition code d# Displacement Example: d16 is a 16-bit displacement 〈ea〉 Effective address #〈data〉 Immediate data; a literal integer label Assembly program label list List of registers Example: D3–D0 [...] Bits of an operand Examples: [7] is bit 7; [31:24] are bits 31–24 MOTOROLA MC68340 USER’S MANUAL 5-13 (...) CCR PC SP SR SSP USP FC DFC SFC + – / × = ≠ > ≥ < ≤ Λ V ⊕ ~ BCD LSW MSW {R/W} Contents of a referenced location Example: (Rn) refers to the contents of Rn Condition code register (lower byte of SR) X—extend bit N—negative bit Z—zero bit V—overflow bit C—carry bit Program counter Active stack pointer Status register Supervisor stack pointer User stack pointer Function code Destination function code register Source function code register Arithmetic addition or postincrement Arithmetic subtraction or predecrement Arithmetic division or conjunction symbol Arithmetic multiplication Equal to Not equal to Greater than Greater than or equal to Less than Less than or equal to Logical AND Logical OR Logical exclusive OR Invert; operand is logically complemented Binary-coded decimal, indicated by subscript Example: Source10 is a BCD source operand. Least significant word Most significant word Read/write indicator In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow (⇒). 5-14 MC68340 USER’S MANUAL MOTOROLA 5.3.3 Instruction Summary The instructions form a set of tools to perform the following operations: Data movement Bit manipulation Integer arithmetic Binary-coded decimal arithmetic Logic Program control Shift and rotate System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2. MOTOROLA MC68340 USER’S MANUAL 5-15 Table 5-2. Instruction Set Summary Opcode Syntax Source 10 + Destination10 + X ⇒ Destination ABCD Dy,Dx ABCD –(Ay),–(Ax) ADD Source + Destination ⇒ Destination ADD 〈ea〉,Dn ADD Dn,〈ea〉 ADDA Source + Destination ⇒ Destination ADDA 〈ea〉,An ADDI Immediate Data + Destination ⇒ Destination ADDI #〈 data〉,〈 ea〉 ADDQ Immediate Data + Destination ⇒ Destination ADDQ # 〈data 〉,〈ea〉 ADDX Source + Destination + X ⇒ Destination ADDX Dy,Dx ADDX –(Ay),–(Ax) AND Source Λ Destination ⇒ Destination AND 〈ea〉, Dn AND Dn,〈ea〉 ANDI Immediate Data Λ Destination ⇒ Destination ANDI #〈data〉,〈 ea〉 Source Λ CCR ⇒ CCR ANDI #〈data〉,CCR If supervisor state the Source Λ SR ⇒ SR else TRAP ANDI #〈data〉,SR Destination Shifted by 〈 count〉 ⇒ Destination ASd Dx,Dy ASd # 〈data 〉,Dy ASd 〈ea〉 If (condition true) then PC + d ⇒ PC Bcc 〈label〉 BCHG ~(〈number 〉 of Destination) ⇒ Z; ~(〈number 〉 of Destination) ⇒ 〈bit number〉 of Destination BCHG Dn,〈ea〉 BCHG # 〈data 〉,〈ea〉 BCLR ~(〈number 〉 of Destination) ⇒ Z; 0 ⇒ 〈bit number〉 of Destination BCLR Dn, 〈ea〉 BCLR # 〈data 〉,〈ea〉 BGND If (background mode enabled) then enter background mode else Format/Vector offset ⇒ –(SSP) PC ⇒ –(SSP) SR ⇒ –(SSP) (Vector) ⇒ PC BGND BKPT Run breakpoint acknowledge cycle; TRAP as illegal instruction BKPT #〈 data〉 BRA PC + d ⇒ PC BRA 〈label〉 BSET ~(〈number 〉 of Destination) ⇒ Z; 1 ⇒ 〈bit number〉 of Destination BSET Dn,〈 ea〉 BSET #〈 data〉,〈 ea〉 BSR SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC BSR 〈label〉 BTST – (〈number 〉 of Destination) ⇒ Z; BTST Dn, 〈ea〉 BTST # 〈data 〉,〈ea〉 CHK If Dn < 0 or Dn > Source then TRAP CHK 〈ea〉,Dn CHK2 If Rn < lower bound or If Rn > upper bound then TRAP CHK2 〈ea〉,Rn 0 ⇒ Destination CLR 〈ea〉 ABCD ANDI to CCR ANDI to SR ASL,ASR Bcc CLR Destination — Source ⇒ cc CMP 〈ea〉,Dn CMPA Destination — Source CMPA 〈ea〉,An CMPI Destination — Immediate Data CMPI # 〈data〉,〈 ea〉 Destination — Source ⇒ cc CMPM (Ay)+,(Ax)+ CMP CMPM 5-16 Operation MC68340 USER’S MANUAL MOTOROLA Table 5-2. Instruction Set Summary (Continued) Opcode Operation Syntax CMP2 Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes CMP2 〈ea〉,Rn DBcc If condition false then (Dn – 1 ⇒ Dn; If Dn ≠ –1 then PC + d ⇒ PC) DBcc Dn,〈 label〉 DIVS DIVSL Destination/Source ⇒ Destination DIVS.W 〈ea〉,Dn DIVS.L 〈 ea〉,Dq DIVS.L 〈 ea〉,Dr:Dq DIVSL.L 〈 ea〉,Dr:Dq 32/16 ⇒ 16r:16q 32/32 ⇒ 32q 64/32 ⇒ 32r:32q 32/32 ⇒ 32r:32q DIVU DIVUL Destination/Source ⇒ Destination DIVU.W 〈ea〉,Dn DIVU.L 〈ea〉,Dq DIVU.L 〈ea〉,Dr:Dq DIVUL.L 〈ea〉,Dr:Dq 32/16 ⇒ 16r:16q 32/32 ⇒ 32q 64/32 ⇒ 32r:32q 32/32 ⇒ 32r:32q EOR Source ⊕ Destination ⇒ Destination EOR Dn,〈 ea〉 EORI Immediate Data ⊕ Destination ⇒ Destination EORI # 〈data 〉,〈ea〉 Source ⊕ CCR ⇒ CCR EORI # 〈data 〉,CCR EORI to SR If supervisor state the Source ⊕ SR ⇒ SR else TRAP EORI # 〈data 〉,SR EXG Rx ⇔ Ry EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT EXTB Destination Sign-Extended ⇒ Destination EXT.W Dn EXT.L Dn EXTB.L Dn LLEGAL SSP – 2 ⇒ SSP; Vector Offset ⇒ (SSP); SSP – 4 ⇒ SSP; PC ⇒ (SSP); SSp – 2 ⇒ SSP; SR ⇒ (SSP); Illegal Instruction Vector Address ⇒ PC ILLEGAL EORI to CCR JMP Destination Address ⇒ PC JMP 〈ea〉 JSR SP–4 ⇒ SP; PC ⇒ (SP) Destination Address ⇒ PC JSR 〈ea〉 extend byte to word extend word to long word extend byte to long word LEA 〈ea〉 ⇒ An LEA 〈ea〉,An LINK SP – 4 ⇒ SP; An ⇒ (SP) SP ⇒ An, SP + d ⇒ SP LINK An,#〈 displacement〉 LPSTOP If supervisor state Immediate Data ⇒ SR Interrupt Mask ⇒ External Bus Interface (EBI) STOP else TRAP LPSTOP #〈 data〉 LSL,LSR Destination Shifted by 〈 count〉 ⇒ Destination LSd1 Dx,Dy LSd1 # 〈data 〉,Dy LSd1 〈ea〉 MOVE Source ⇒ Destination MOVE 〈ea〉,〈ea〉 MOVEA Source ⇒ Destination MOVEA 〈 ea〉,An CCR ⇒ Destination MOVE CCR, 〈ea〉 MOVE from CCR MOTOROLA MC68340 USER’S MANUAL 5-17 Table 5-2. Instruction Set Summary (Continued) Opcode Operation Syntax MOVE to CCR Source ⇒ CCR MOVE 〈 ea〉,CCR MOVE from SR If supervisor state then SR ⇒ Destination else TRAP MOVE SR,〈 ea〉 MOVE to SR If supervisor state then Source ⇒ SR else TRAP MOVE 〈ea〉,SR MOVE USP If supervisor state then USP ⇒ An or An ⇒ USP else TRAP MOVE USP,An MOVE An,USP MOVEC If supervisor state then Rc ⇒ Rn or Rn ⇒ Rc else TRAP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM Registers ⇒ Destination Source ⇒ Registers MOVEM register list,〈 ea〉 MOVEM 〈ea〉,register list MOVEP Source ⇒ Destination MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ Immediate Data ⇒ Destination MOVEQ #〈 data〉,Dn MOVES If supervisor state then Rn ⇒ Destination [DFC] or Source [SFC] ⇒Rn else TRAP MOVES Rn,〈 ea〉 MOVES 〈 ea〉,Rn MULS Source × Destination ⇒ Destination MULS.W 〈ea〉,Dn MULS.L 〈 ea〉,Dl MULS.L 〈 ea〉,Dh:Dl 16 × 16 ⇒ 32 32 × 32 ⇒ 32 32 × 32 ⇒ 64 MULU Source × Destination ⇒ Destination MULU.W 〈ea〉,Dn MULU.L 〈ea〉,Dl MULU.L 〈ea〉,Dh:Dl 16 × 16 ⇒ 32 32 × 32 ⇒ 32 32 × 32 ⇒ 64 NBCD 0 – (Destination10) – X ⇒ Destination NBCD 〈ea〉 0 – (Destination) ⇒ Destination NEG 〈ea〉 NEG 0 – (Destination) – X ⇒ Destination NEGX 〈ea〉 NOP None NOP NOT ~Destination ⇒ Destination NOT 〈ea〉 OR Source V Destination ⇒ Destination OR 〈ea〉,Dn OR Dn, 〈ea〉 ORI Immediate Data V Destination ⇒ Destination ORI # 〈data 〉,〈ea〉 Source V CCR ⇒ CCR ORI # 〈data 〉,CCR ORI to SR If supervisor state then Source V SR ⇒ SR else TRAP ORI # 〈data 〉,SR PEA Sp – 4 ⇒ SP; 〈ea〉 ⇒ (SP) PEA 〈ea〉 If supervisor state then Assert RESET else TRAP RESET Destination Rotated by 〈count 〉⇒ Destination ROd 1 Rx,Dy ROd 1 # 〈data 〉,Dy ROd 1 〈ea〉 NEGX ORI to CCR RESET ROL,ROR 5-18 MC68340 USER’S MANUAL MOTOROLA Table 5-2. Instruction Set Summary (Concluded) Opcode ROXL,ROXR Operation Syntax Destination Rotated with X by 〈count〉 ⇒ Destination ROXd 1 Rx,Dy ROXd 1 # 〈data 〉,Dy ROXd 1 〈ea〉 RTD (SP) ⇒ PC; SP + 4 + d ⇒ SP RTE If supervisor state RTE the (SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP; restore state and deallocate stack according to (SP) else TRAP RTR (SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP RTR RTS (SP) ⇒ PC; SP + 4 ⇒ SP RTS Destination10 – Source 10 – X ⇒ Destination SBCD Dx,Dy SBCD –(Ax),–(Ay) If Condition True then 1s ⇒ Destination else 0s ⇒ Destination Scc 〈ea〉 STOP If supervisor state then Immediate Data ⇒ SR; STOP else TRAP STOP #〈 data〉 SUB Destination – Source ⇒ Destination SUB 〈ea〉,Dn SUB Dn,〈 ea〉 SBCD Scc RTD # 〈displacement〉 SUBA Destination – Source ⇒ Destination SUBA 〈 ea〉,An SUBI Destination – Immediate Data ⇒ Destination SUBI # 〈data 〉,〈ea〉 SUBQ Destination – Immediate Data ⇒ Destination SUBQ #〈 data〉,〈ea〉 SUBX Destination – Source – X ⇒ Destination SUBX Dx,Dy SUBX –(Ax),–(Ay) SWAP Register [31:16] ⇔ Register [15:0] SWAP Dn Destination Tested ⇒ Condition Codes; 1 ⇒ bit 7 of Destination TAS 〈ea〉 ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) * Dx[7:0]} / 256 ⇒ Dx TBLS.〈size〉 〈ea〉, Dx TBLS.〈size〉 Dym:Dyn, Dx ENTRY(n) × 256 + {(ENTRY(n + 1) – ENTRY(n)) * Dx [7:0]} ⇒ Dx TBLSN. 〈size〉 〈ea〉,Dx TBLSN. 〈size〉 Dym:Dyn, Dx ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) * Dx[7:0]} / 256 ⇒ Dx TBLU. 〈size〉 〈ea〉,Dx TBLU. 〈size〉 Dym:Dyn, Dx TBLUN ENTRY(n) • 256 + {(ENTRY(n + 1) – ENTRY(n)) • Dx[7:0]} ⇒ Dx TBLUN. 〈size〉 〈ea〉,Dx TBLUN. 〈size〉 Dym:Dyn,Dx TRAP SSP – 2 ⇒ SSP; Format/Offset ⇒ (SSP); SSP – 4 ⇒ SSP; PC ⇒ (SSP); SSP – 2 ⇒ SSP; SR ⇒ (SSP); Vector Address ⇒ PC TRAP # 〈vector 〉 TRAPcc If cc then TRAP TRAPcc TRAPcc.W #〈 data 〉 TRAPcc.L #〈 data〉 TRAPV If V then TRAP TRAPV Destination Tested ⇒ Condition Codes TST 〈ea〉 TAS TBLS TBLSN TBLU TST UNLK An ⇒ SP; (SP) ⇒ An; SP + 4 ⇒ SP NOTE 1: d is direction, L or R. MOTOROLA UNLK An MC68340 USER’S MANUAL 5-19 5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5-7 as an example. Table 5-3. Condition Code Computations Operations 5-20 X N Z V C ABCD * U ? U ? C = Decimal Carry Z = Z Λ R∂Λ ... Λ R0 ADD, ADDI, ADDQ * * * ? ? V = Sm Λ Dm Λ R∂ V S∂ Λ D∂ Λ Rm C = Sm Λ Dm V R∂ Λ Dm V Sm Λ R∂ ADDX * * ? ? ? V = Sm Λ Dm Λ R∂ V S∂ Λ D∂ Λ Rm C = Sm Λ Dm V R∂ Λ Dm V Sm Λ R∂ Z = Z Λ R∂ Λ ... Λ R0 AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI, CLR, EXT, NOT, TAS, TST — * * 0 0 CHK — * U U U CHK2, CMP2 — U ? U ? Z = (R = LB) V (R = UB) C = (LB < UB) Λ (IR < LB) V (R > UB) V (UB < LB) Λ (R > UB) Λ (R < LB) SUB, SUBI, SUBQ * * * ? ? V = S∂ Λ Dm Λ R∂ V Sm Λ D∂ Λ Rm C = Sm Λ D∂ V Rm Λ D∂ V Sm Λ Rm SUBX * * ? ? ? V = S∂ Λ Dm Λ R∂ V Sm Λ D∂ Λ Rm C = Sm Λ D∂ V Rm Λ D∂ V Sm Λ Rm Z = Z Λ R∂ Λ ... Λ R0 CMP, CMPI, CMPM — * * ? ? V = S∂ Λ Dm Λ R∂ V Sm Λ D∂ Λ Rm C = Sm Λ D∂ V Rm Λ D∂ V Sm Λ Rm DIVS, DIVU — * * ? 0 V = Division Overflow MULS, MULU — * * ? 0 V = Multiplication Overflow SBCD, NBCD * U ? U ? C = Decimal Borrow Z = Z Λ R∂ Λ ... Λ R0 NEG * * * ? ? V = Dm Λ Rm C = Dm V Rm NEGX * * ? ? ? V = Dm Λ Rm C = Dm V Rm Z = Z Λ R∂ Λ ... Λ R0 ASL * * * ? ? V = Dm Λ (D∂ – 1 V ... V D∂ – r ) V D∂ Λ (Dm–1 V ... + Dm – r) C = D∂ – r + 1 ASL (r = 0) — * * 0 0 LSL, ROXL * * * 0 ? LSR (r = 0) — * * 0 0 ROXL (r = 0) — * * 0 ? C=X C = Dm – r + 1 ROL — * * 0 ? ROL (r = 0) — * * 0 0 ASR, LSR, ROXR * * * 0 ? ASR, LSR (r = 0) — * * 0 0 ROXR (r = 0) — * * 0 ? Special Definition C = Dm – r + 1 C = Dr – 1 C=X MC68340 USER’S MANUAL MOTOROLA Table 5-3. Condition Code Computations (Continued) X N Z V C ROR Operations — ∗ ∗ 0 ? ROR (r = 0) — ∗ ∗ 0 0 Special Definition C = Dr – 1 NOTE : The following notations apply to this table only. — = Not affected Sm = Source operand MSB U = Undefined Dm = Destination operand MSB ? = See special definition Rm = Result operand MSB ∗ = General case R = Register tested X = C n = Bit Number N = Rm r = Shift count Z = LB = Lower bound Λ = Upper bound = UB Rm = V Rm Λ ... Λ R0 Boolean AND Boolean OR = NOT Rm 5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several special data movement instructions—move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the data movement operations. Table 5-4. Data Movement Operations Instruction Operand Syntax Operand Size EXG Rn, Rn 32 Rn ⇒ Rn LEA 〈ea〉, An 32 〈ea〉 ⇒ An LINK An, #〈d〉 16, 32 Operation SP – 4 ⇒ SP, An ⇒ (SP); SP ⇒ An, SP + d ⇒ SP MOVE 〈ea〉, 〈ea〉 8, 16, 32 Source ⇒ Destination MOVEA 〈ea〉, An 16, 32 ⇒ 32 Source ⇒ Destination MOVEM list, 〈ea〉 〈ea〉, list 16, 32 16, 32 ⇒ 32 Listed registers ⇒ Destination Source ⇒ Listed registers MOVEP Dn, (d16, An) 16, 32 Dn [31:24] ⇒ (An + d); Dn [23:16] ⇒ (An + d + 2); Dn [15:8] ⇒ (An + d + 4); Dn [7:0] ⇒ (An + d + 6) (An + d) ⇒ Dn [31:24]; (An + d + 2) ⇒ Dn [23:16]; (An + d + 4) ⇒ Dn [15:8]; (An + d + 6) ⇒ Dn [7:0] Immediate Data ⇒ Destination (d 16, An), Dn MOVEQ #〈data〉, Dn 8 ⇒ 32 PEA 〈ea〉 32 SP – 4 ⇒ SP; 〈ea〉 ⇒ SP UNLK An 32 An ⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP MOTOROLA MC68340 USER’S MANUAL 5-21 5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include: • Word multiply to produce a long-word product • Long-word multiply to produce a long-word or quad-word product • Division of a long-word dividend by a word divisor (word quotient and word remainder) • Division of a long-word or quad-word dividend by a long-word divisor (long-word quotient and long-word remainder) A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations. 5-22 MC68340 USER’S MANUAL MOTOROLA Table 5-5. Integer Arithmetic Operations Operand Syntax Operand Size ADD Dn, 〈ea〉 〈ea〉, Dn 8, 16, 32 8, 16, 32 Source + Destination ⇒ Destination ADDA 〈ea〉, An 16, 32 Source + Destination ⇒ Destination ADDI #〈data〉, 〈 ea〉 8, 16, 32 Immediate Data + Destination ⇒ Destination ADDQ #〈data〉, 〈 ea〉 8, 16, 32 Immediate Data + Destination ⇒ Destination ADDX Dn, Dn – (An), – (An) 8, 16, 32 8, 16, 32 Source + Destination + X ⇒ Destination Instruction Operation CLR 〈ea〉 8, 16, 32 0 ⇒ Destination CMP 〈ea〉, Dn 8, 16, 32 (Destination – Source), CCR shows results CMPA 〈ea〉, An 16, 32 (Destination – Source), CCR shows results CMPI #〈data〉, 〈 ea〉 8, 16, 32 CMPM (An) +, (An) + 8, 16, 32 (Destination – Source), CCR shows results CMP2 〈ea〉, Rn 8, 16, 32 Lower bound ≤ Rn ≤ Upper Bound, CCR shows results DIVS/DIVU 〈ea〉, Dn 〈ea〉, Dr:Dq 〈ea〉, Dq 〈ea〉, Dr:Dq 32/16 ⇒ 16:16 64/32 ⇒ 32:32 32/32 ⇒ 32 32/32 ⇒ 32:32 EXT Dn Dn 8 ⇒ 16 16 ⇒ 32 Sign Extended Destination ⇒ Destination EXTB Dn 8 ⇒ 32 Sign Extended Destination ⇒ Destination MULS/MULU 〈ea〉, Dn 〈ea〉, Dl 〈ea〉, Dh:Dl 16 × 16 ⇒ 32 32 × 32 ⇒ 32 32 × 32 ⇒ 64 DIVSL/DIVUL (Destination – Immediate Data), CCR shows results Destination/Source ⇒ Destination (signed or unsigned) Source × Destination ⇒ Destination (signed or unsigned) NEG 〈ea〉 8, 16, 32 0 – Destination ⇒ Destination NEGX 〈ea〉 8, 16, 32 0 – Destination – X ⇒ Destination SUB 〈ea〉, Dn Dn, 〈ea〉 8, 16, 32 Destination – Source ⇒ Destination SUBA 〈ea〉, An 16, 32 Destination – Source ⇒ Destination SUBI #〈data〉, 〈 ea〉 8, 16, 32 Destination – Immediate Data ⇒ Destination SUBQ #〈data〉, 〈 ea〉 8, 16, 32 Destination – Immediate Data ⇒ Destination SUBX Dn, Dn – (An), – (An) 8, 16, 32 8, 16, 32 Destination – Source – X ⇒ Destination TBLS/TBLU 〈ea〉, Dn Dym:Dyn, Dn 8, 16, 32 Dyn – Dym ⇒ Temp (Temp × Dn [7:0]) ⇒ Temp (Dym × 256) + Temp ⇒ Dn TBLSN/TBLUN 〈ea〉, Dn Dym:Dyn, Dn 8, 16, 32 Dyn – Dym ⇒ Temp (Temp × Dn [7:0]) / 256 ⇒ Temp Dym + Temp ⇒ Dn MOTOROLA MC68340 USER’S MANUAL 5-23 5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR. Table 5-6 summarizes the logical operations. Table 5-6. Logic Operations Operand Syntax Operand Size AND 〈ea〉, Dn Dn, 〈ea〉 8, 16, 32 8, 16, 32 Source Λ Destination ⇒ Destination ANDI #〈data〉, 〈 ea〉 8, 16, 32 Immediate Data Λ Destination ⇒ Destination EOR Dn, 〈ea〉 8, 16, 32 Source ⊕ Destination ⇒ Destination EORI #〈data〉, 〈 ea〉 8, 16, 32 Immediate Data ⊕ Destination ⇒ Destination NOT 〈ea〉 8, 16, 32 Destination ⇒ Destination OR 〈ea〉, Dn Dn, 〈ea〉 8, 16, 32 8, 16, 32 Source V Destination ⇒ Destination ORI #〈data〉, 〈 ea〉 8, 16, 32 Immediate Data V Destination ⇒ Destination TST 〈ea〉 8, 16, 32 Source – 0, to set condition codes Instruction Operation 5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory. Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift count). Memory shift and rotate operations shift word-length operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations. 5-24 MC68340 USER’S MANUAL MOTOROLA Table 5-7. Shift and Rotate Operations Instruction ASL ASR LSL LSR ROL ROR ROXL ROXR SWAP Operand Syntax Operand Size Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn, Dn #〈data〉, Dn 〈ea〉 8, 16, 32 8, 16, 32 16 Dn 16 Operation X/C 0 X/C 0 X/C 0 X/C C C C X X C MSW LSW 5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits long, and memory operands are 8 bits long. Table 5-8 is a summary of bit manipulation instructions. Table 5-8. Bit Manipulation Operations Operand Syntax Operand Size BCHG Dn, 〈ea〉 #〈data〉, 〈 ea〉 8, 32 8, 32 ~(〈bit number 〉 of destination) ⇒ Z ⇒ bit of destination BCLR Dn, 〈ea〉 #〈data〉, 〈 ea〉 8, 32 8, 32 ~(〈bit number 〉 of destination) ⇒ Z; 0 ⇒ bit of destination BSET Dn, 〈ea〉 #〈data〉, 〈 ea〉 8, 32 8, 32 ~(〈bit number 〉 of destination) ⇒ Z; 1 ⇒ bit of destination BTST Dn, 〈ea〉 #〈data〉, 〈 ea〉 8, 32 8, 32 ~(〈 bit number 〉 of destination) ⇒ Z Instruction MOTOROLA Operation MC68340 USER’S MANUAL 5-25 5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 5-9 is a summary of the BCD operations. Table 5-9. Binary-Coded Decimal Operations Operand Syntax Operand Size ABCD Dn, Dn – (An), – (An) 8 8 Source 10 + Destination10 + X ⇒ Destination NBCD 〈ea〉 8 8 0 – Destination10 – X ⇒ Destination SBCD Dn, Dn – (An), – (An) 8 8 Destination10 – Source10 – X ⇒ Destination Instruction Operation 5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. Table 5-10 summarizes these instructions. Table 5-10. Program Control Operations Instruction Operand Syntax Operand Size Bcc 〈label〉 8, 16, 32 If condition true, then PC + d ⇒ PC DBcc Dn , 〈label〉 16 If condition false, then Dn – 1 ⇒ PC; if Dn ≠ (– 1), then PC + d ⇒ PC Scc 〈ea〉 8 If condition true, then destination bits are set to 1; else destination bits are cleared to 0 BRA 〈label〉 8, 16, 32 PC + d ⇒ PC BSR 〈label〉 8, 16, 32 SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC JMP 〈ea〉 none Destination ⇒ PC JSR 〈ea〉 none SP – 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC NOP none none PC + 2 ⇒ PC Operation Conditional Unconditional Returns 5-26 (SP) ⇒ PC; SP + 4 + d ⇒ SP RTD #〈d〉 16 RTR none none (SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP RTS none none (SP) ⇒ PC; SP + 4 ⇒ SP MC68340 USER’S MANUAL MOTOROLA To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. CC — Carry clear LS — Low or same CS — Carry set LT — Less than EQ — Equal MI — Minus F False* NE — Not equal GE — Greater or equal PL — Plus GT — Greater than T True HI High VC — Overflow clear Less or equal VS — Overflow set — — LE — — *Not applicable to the Bcc instruction 5.3.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instructions, and instructions that use or modify the CCR provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA MC68340 USER’S MANUAL 5-27 Table 5-11. System Control Operations Instruction Operand Syntax Operand Size Operation Privileged ANDI #〈data〉, SR 16 Immediate Data Λ SR ⇒ SR EORI #〈data〉, SR 16 Immediate Data ⊕ SR ⇒ SR MOVE 〈ea〉, SR SR, 〈ea〉 16 16 Source ⇒ SR SR ⇒ Destination MOVEA USP, An An, USP 32 32 USP ⇒ An An ⇒ USP MOVEC Rc, Rn Rn, Rc 32 32 Rc ⇒ Rn Rn ⇒ Rc MOVES Rn, 〈ea〉 〈ea〉, Rn 8, 16, 32 Rn ⇒ Destination using DFC Source using SFC ⇒ Rn ORI #〈data〉, SR 16 Immediate Data V SR ⇒ SR RESET none none Assert RESET line RTE none none (SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP; restore stack according to format STOP #〈data〉 16 LPSTOP #〈data〉 none Immediate Data ⇒ SR; STOP Immediate Data ⇒ SR; interrupt mask ⇒ EBI; STOP Trap Generating BKPT #〈data〉 none If breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction. BGND none none If background mode enabled, then enter background mode, else format/vector offset ⇒ – (SSP); PC ⇒ – (SSP); SR ⇒ – (SSP); (vector) ⇒ PC CHK 〈ea〉, Dn 16, 32 CHK2 〈ea〉, Rn 8, 16, 32 ILLEGAL none none SSP – 2 ⇒ SSP; vector offset ⇒ (SSP); SSP – 4 ⇒ SSP; PC ⇒ (SSP); SSP – 2 ⇒ SSP; SR ⇒ (SSP); llegal instruction vector address ⇒ PC TRAP #〈data〉 none SSP – 2 ⇒ SSP; format/vector offset ⇒ (SSP); SSP – 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP); vector address ⇒ PC TRAPcc none #〈data〉 none 16, 32 TRAPV none none If Dn < 0 or Dn < (ea), then CHK exception If Rn < lower bound or Rn > upper bound, then CHK exception If cc true, then TRAP exception If V set, then overflow TRAP exception Condition Code Register 5-28 ANDI #〈data〉, CCR 8 Immediate Data Λ CCR ⇒ CCR EORI #〈data〉, CCR 8 Immediate Data ⊕ CCR ⇒ CCR MOVE 〈ea〉, CCR CCR, 〈ea〉 16 16 Source ⇒ CCR CCR ⇒ Destination ORI #〈data〉, CCR 8 Immediate Data V CCR ⇒ CCR MC68340 USER’S MANUAL MOTOROLA 5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test. Table 5-12. Condition Tests Mnemonic Condition Encoding Test T True 0000 1 F* False 0001 0 HI High 0010 C•Z LS Low or Same 0011 C+Z CC Carry Clear 0100 C CS Carry Set 0101 C NE Not Equal 0110 Z EQ Equal 0111 Z VC Overflow Clear 1000 V VS Overflow Set 1001 V PL Plus 1010 N MI Minus 1011 N GE Greater or Equal 1100 N • V + N• V LT Less Than 1101 N • V+ N•V GT Greater Than 1110 N • V • Z+ N • V • Z LE Less or Equal * Not available for the Bcc instruction. • = Boolean AND + = Boolean OR N = Boolean NOT 1111 Z + N • V+ N • V 5.3.4 Using the TBL Instructions There are four TBL instructions. TBLS returns a signed, rounded byte, word, or long-word result. TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an unsigned, rounded byte, word, or long-word result. TBLUN returns an unsigned, unrounded byte, word, or long-word result. All four instructions support two types of interpolation data: an n-element table stored in memory and a two-element range stored in a pair of data registers. The latter form provides a means of performing surface (3D) interpolation between two previously calculated linear interpolations. The following examples show how to compress tables and use fewer interpolation levels between table entries. Example 1 (see Figure 5-7) demonstrates TBL for a 257-entry table, allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-8) reduces table length for the same data to four entries. Example 3 (see Figure 5-9) demonstrates use of an 8-bit independent variable with an instruction. MOTOROLA MC68340 USER’S MANUAL 5-29 Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-7, the function is linear within the range 32768 ≤ X ≤ 49152. Table entries within this range are as given in Table 5-13 . Table 5-13. Standard Usage Entries Entry Number X Value Y Value 128* 32768 1311 162 41472 1659 163 41728 1669 164 41984 1679 165 42240 1690 192* 49152 1966 *These values are the end points of the range. All entries between these points fall on the line. DEPENDENT VARIABLE Y 16384 32768 49152 65536 X INDEPENDENT VARIABLE Figure 5-7. Table Example 1 5-30 MC68340 USER’S MANUAL MOTOROLA The table instruction is executed with the following bit pattern in Dx: 31 16 NOT USED 15 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 Table Entry Offset ⇒ Dx [8:15] = $A3 = 163 Interpolation Fraction ⇒ Dx [0:7] = $80 = 128 Using this information, the table instruction calculates dependent variable Y: Y = 1669 + (128 (1679 – 1669)) / 256 = 1674 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0 ≤ X = 65535, X is limited to 0 ≤ X ≤ 1023. The table has been compressed to only five entries, but up to 256 levels of interpolation are allowed between entries. DEPENDENT VARIABLE Y 256 512 786 1024 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 NOTE Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are listed in Table 5-14. MOTOROLA MC68340 USER’S MANUAL 5-31 Table 5-14. Compressed Table Entries Entry Number X Value Y Value 2 512 1311 3 786 1966 Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction: LSR.W #6,Dx Thus, Dx now contains the following bit pattern: 31 16 NOT USED 15 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 Table Entry Offset ⇒ Dx [8:15] = $02 = 2 Interpolation Fraction ⇒ Dx [0:7] = $8E = 142 Using this information, the table instruction calculates dependent variable Y: Y = 1331 + (142 (1966 – 1311)) / 256 = 1674 The function chosen for Examples 1 and 2 is linear between data points. If another function had been been used, interpolated values might not have been identical. 5.3.4.3 TABLE EXAMPLE 3: 8-BIT INDEPENDENT VARIABLE. This example shows how to use a table instruction within an interpolation subroutine. Independent variable X is calculated as an 8-bit value, allowing 16 levels of interpolation on a 17-entry table. X is passed to the subroutine, which returns an 8-bit result. The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. 5-32 MC68340 USER’S MANUAL MOTOROLA INDEPENDENT VARIABLE Y 2048 1024 4096 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 Table 5-15. 8-Bit Independent Variable Entries X (Subroutine) X (Instruction) Y 0 0 0 1 256 16 2 512 32 3 768 48 4 1024 64 5 1280 80 6 1536 96 7 1792 112 8 2048 128 9 2304 112 10 2560 96 11 2816 80 12 3072 64 13 3328 48 14 3584 32 15 3840 16 16 4096 0 The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. MOTOROLA MC68340 USER’S MANUAL 5-33 The following value has been calculated for independent variable X: 31 16 NOT USED 15 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 Since X is an 8-bit value, the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction. The following results are obtained from the subroutine: Table Entry Offset ⇒ Dx [4:7] = $B = 11 Interpolation Fraction ⇒ Dx [0:3] = $D = 13 Thus, Y is calculated as follows: Y = 80 + (13 (64 – 80)) / 16 = 67 If the 8-bit value for X were used directly by the table instruction, interpolation would be incorrectly performed between entries 0 and 1. Data must be shifted to the left four places before use: LSL.W #4, Dx The new range for X is 0 ≤ X ≤ 4096; however, since a left shift fills the least significant digits of the word with zeros, the interpolation fraction can only have one of 16 values. After the shift operation, Dx contains the following value: 31 16 NOT USED 15 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 Execution of the table instruction using the new value in Dx yields: Table Entry Offset ⇒ Dx [8:15] = $0B = 11 Interpolation Fraction ⇒ Dx [0:7] = $D0 = 208 Thus, Y is calculated as follows: Y = 80 + (208 (64 – 80)) / 256 = 67 5.3.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three TBL operations are performed and the results are summed. The calculation is done once with the result of each TBL rounded before addition and once with only the final result rounded. Assume that the result of the three interpolations are as follows (a ".'' indicates the binary radix point). 5-34 TBL # 1 0010 0000 . 0111 0000 TBL# 2 0011 1111 . 0111 0000 TBL # 3 0000 0001 . 0111 0000 MC68340 USER’S MANUAL MOTOROLA First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS: TBL # 1 TBL # 2 TBL # 3 0010 0000 . 0011 1111 . 0000 0001 . Summing, the following result is obtained: 0010 0011 0000 0110 0000 . 1111 . 0001 . 0000 . Now, using the same TBL results, the sum is first calculated and then rounded according to the same algorithm: 0010 0011 0000 0110 0000 . 0111 1111 . 0111 0001 . 0111 0001 . 0101 0000 0000 0000 0000 Rounding yields: 0110 0001 . The second result is preferred. The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results: L0: TBLSN.B TBLSN.B TBLSN.B ADD.L ADD.L ASR.L BCC.B ADDQ.B L1: . . . MOTOROLA 〈ea〉, Dx 〈ea〉, Dx 〈ea〉, Dl Dx, Dm Dm, Dl #8, Dl L1 #1, Dl Long addition avoids problems with carry Move radix point Fraction MSB in carry MC68340 USER’S MANUAL 5-35 5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be used to perform surface (3D) TBLs. However, since the calculation must be split into a series of 2D TBLs, the possibility of losing precision in the intermediate results is possible. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility. L0: MOVE.W TBLSN.B TBLSN.B TBLS.W ASR.L BCC.B ADDQ.B L1: . . . Dx, Dl 〈ea〉, Dx 〈ea〉, Dl Dx:Dl, Dm #8, Dm L1 #1, Dl Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up Before execution of this code sequence, Dx must contain fraction and entry numbers for the two TBL, and Dm must contain the fraction for surface interpolation. The 〈ea〉 fields in the TBLSN instructions point to consecutive columns in a 3D table. The TBLS size parameter must be word if the TBLSN size parameter is byte, and must be long word if TBLSN is word. Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 2D TBL. 5.3.5 Nested Subroutine Calls The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack for use. Using this instruction in a series of subroutine calls will generate a linked list of stack frames. The UNLK instruction removes a stack frame from the end of the list by loading an address into the SP and pulling the value at that address from the stack. When the instruction operand is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from both the stack and the linked list. 5.3.6 Pipeline Synchronization with the NOP Instruction Although the no operation (NOP) instruction performs no visible operation, it does force synchronization of the instruction pipeline, since all previous instructions must complete execution before the NOP begins. 5.4 PROCESSING STATES This section describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions. 5-36 MC68340 USER’S MANUAL MOTOROLA 5.4.1 State Transitions The processor is in normal, background, or exception state unless halted. When the processor fetches instructions and operands or executes instructions, it is in the normal processing state. The stopped condition, which the processor enters when a STOP or LPSTOP instruction is executed, is a variation of the normal state in which no further bus cycles are generated. Background state is an alternate operational mode used for system debugging. Refer to 5.6 Development Support for more information. Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes the stack operations, the exception vector fetch, and the filling of the instruction pipeline caused by an exception. Exception processing ends when execution of an exception handler routine begins. Refer to 5.5 Exception Processing for comprehensive information. A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if a bus error occurs during exception processing caused by a bus error, the CPU32 assumes that the system is not operational and halts. The halted condition should not be confused with the stopped condition. After the processor executes a STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs. 5.4.2 Privilege Levels To protect system resources, the processor can operate with either of two levels of access—user or supervisor. Supervisor level is more privileged than user level. All instructions are available at the supervisor level, but execution of some instructions is not permitted at the user level. There are separate SPs for each level. The S-bit in the SR indicates privilege level and determines which SP is used for stack operations. The processor identifies each bus access (supervisor or user mode) via function codes to enforce supervisor and user access levels. In a typical system, most programs execute at the user level. User programs can access only their own code and data areas and are restricted from accessing other information. The operating system executes at the supervisor privilege level, has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities. 5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege level applies, and all instructions are executable. The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on FC2–FC0 refer to supervisor address spaces. MOTOROLA MC68340 USER’S MANUAL 5-37 All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP. Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions. To prevent a user program from gaining privileged access, except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction provides controlled user access to operating system services. 5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor executes instructions at the user privilege level. The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FC2–FC0 specify user address spaces. While the processor is at the user level, implicit references to the system SP and explicit references to address register seven (A7) refer to the USP. 5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor privilege level, a condition that causes exception processing must occur. When exception processing begins, the current values in the SR, including the S-bit, are saved on the supervisor stack, and then the S-bit is set to enable supervisory access. Execution continues at supervisor privilege level until exception processing is complete. To return to user access level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute only at supervisor privilege level and can modify the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed, then refilled from the appropriate address space. The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR and PC are restored to the values saved on the supervisor stack, and execution resumes at the restored PC address, with access level determined by the S-bit of the restored SR. If the frame was generated by a bus error or an address error exception, the entire processor state is restored from the stack. 5.5 EXCEPTION PROCESSING An exception is a special condition that preempts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception. The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines. 5-38 MC68340 USER’S MANUAL MOTOROLA 5.5.1 Exception Vectors An exception vector is the address of a routine that handles an exception. The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector which is two long words, each vector in the table is one long word. Refer to Table 5-16 for information on vector assignment. Table 5-16. Exception Vector Assignments Vector Offset Vector Number Dec Hex Space Assignment 0 0 000 SP Reset: Initial Stack Pointer 1 4 004 SP Reset: Initial Program Counter 2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Division 6 24 018 SD CHK, CHK2 Instructions 7 28 01C SD TRAPcc, TRAPV Instructions 8 32 020 SD Privilege Violation 9 36 024 SD Trace 10 40 028 SD Line 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Hardware Breakpoint 13 52 034 SD (Reserved for Coprocessor Protocol Violation) 14 56 038 SD Format Error 15 60 03C SD Uninitialized Interrupt 16–23 64 92 040 05C SD (Unassigned, Reserved) — 24 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Autovector 26 104 068 SD Level 2 Interrupt Autovector 27 108 06C SD Level 3 Interrupt Autovector 28 112 070 SD Level 4 Interrupt Autovector 29 116 074 SD Level 5 Interrupt Autovector 30 120 078 SD Level 6 Interrupt Autovector 31 124 07C SD Level 7 Interrupt Autovector 32–47 128 188 080 0BC SD Trap Instruction Vectors (0–15) — 48–58 192 232 0C0 0E8 SD (Reserved for Coprocessor) — 59–63 236 252 0EC 0FC SD (Unassigned, Reserved) 256 1020 100 3FC SD 64–255 MOTOROLA — User-Defined Vectors (192) MC68340 USER’S MANUAL 5-39 CAUTION Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map. When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an operating system. Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied by the processor. The processor multiplies the vector number by 4 to calculate vector offset, then adds the offset to the contents of the VBR. The sum is the memory address of the vector. 5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external events. An internal exception can be generated by an instruction or by an error. The TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions. Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset for details of reset processing. As exception processing begins, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority mask is also updated. Next, the exception number is obtained. For interrupts, the number is fetched from CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic provides a vector number. Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame. 5-40 MC68340 USER’S MANUAL MOTOROLA Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by 4, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the PC. If no other exception is pending, the processor will resume normal execution at the new address in the PC. 5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile portion of the current context is saved on the top of the supervisor stack. This context is organized in a format called the exception stack frame. The exception stack frame always includes the contents of SR and PC at the time the exception occurred. To support generic handlers, the processor also places the vector offset in the exception stack frame and marks the frame with a format code. The format field allows an RTE instruction to identify stack information so that it can be properly restored. The general form of the exception stack frame is illustrated in Figure 5-10. Although some formats are peculiar to a particular M68000 Family processor, format 0000 is always legal and always indicates that only the first four words of a frame are present. See 5.5.4 CPU32 Stack Frames for a complete discussion of exception stack frames. 15 0 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION (0, 2, OR 8 WORDS) STACKING ORDER HIGHER ADDRESSES SP Figure 5-10. Exception Stack Frame 5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on its relative importance to system operation. Priority assignments are shown in Table 5-17. Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities. Exception processing for exceptions that occur simultaneously is done by priority, from highest to lowest. It is important to be aware of the difference between exception processing mode and execution of an exception handler. Each exception has an assigned vector that points to an associated handler routine. Exception processing includes steps described in 5.5.1.2 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. MOTOROLA MC68340 USER’S MANUAL 5-41 When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception or execution of a handler routine. Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed. Table 5-17. Exception Priority Groups Group/ Priority 0 Exception and Relative Priority Characteristics Reset Aborts all processing (instruction or exception); does not save old context. Address Error Bus Error Suspends processing (instruction or exception); saves internal context. 2 BKPT#n, CHK, CHK2, Division by Zero, RTE, TRAP#n, TRAPcc, TRAPV Exception processing is a part of instruction execution. 3 Illegal Instruction, Line A, Unimplemented Line F, Privilege Violation Exception processing begins before instruction execution. Trace Hardware Breakpoint Interrupt Exception processing begins when current instruction or previous exception processing is complete. 1.1 1.2 4.1 4.2 4.3 As a general rule, when simultaneous exceptions occur, the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions. For example, consider the arrival of an interrupt during execution of a TRAP instruction, while tracing is enabled. Trap exception processing (2) is done first, followed immediately by exception processing for the trace (4.1), and then by exception processing for the interrupt (4.3). Each exception places a new context on the stack. When the processor resumes normal instruction execution, it is vectored to the interrupt handler, which returns to the trace handler that returns to the trap handler. There are special cases to which the general rule does not apply. The reset exception will always be the first exception handled since reset clears all other exceptions. It is also possible for high-priority exception processing to begin before low-priority exception processing is complete. For example, if a bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing is completed. 5-42 MC68340 USER’S MANUAL MOTOROLA 5.5.2 Processing of Specific Exceptions The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception. Reset is used for system initialization and for recovery from catastrophic failure. The reset exception aborts any processing in progress when it is recognized, and that processing cannot be recovered. Reset performs the following operations: 1. Clears T0 and T1 in the SR to disable tracing 2. Sets the S-bit in the SR to establish supervisor privilege 3. Sets the interrupt priority mask to the highest priority level (%111) 4. Initializes the VBR to zero ($00000000) 5. Generates a vector number to reference the reset exception vector 6. Loads the first long word of the vector into the interrupt SP 7. Loads the second long word of the vector into the PC 8. Fetches and initiates decode of the first instruction to be executed Figure 5-11 is a flowchart of the reset exception After initial instruction prefetches, normal program execution begins at the address in the PC. The reset exception does not save the value of either the PC or the SR. If a bus error or address error occurs during reset exception processing sequence, a double bus fault occurs, the processor halts, and the HALT signal is asserted to indicate the halted condition. Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register. The SIM40 registers and the MCR in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other internal peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA MC68340 USER’S MANUAL 5-43 ENTRY 1 0 $7 $0 ➧S ➧ T0,T1 ➧ I2:I0 ➧ VBR .✎ FETCH VECTOR # 0 OTHERWISE SP ➧ (VECTOR # 0) BUS ERROR FETCH VECTOR # 1 OTHERWISE PC BUS ERROR ➧ (VECTOR # 1) PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT Figure 5-11. Reset Operation Flowchart 5-44 MC68340 USER’S MANUAL MOTOROLA 5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. The BERR signal can be asserted by one of three sources: 1. External logic by assertion of the BERR input pin 2. Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no exception occurs. When the aborted bus cycle is a data access, the processor initiates exception processing immediately, except in the case of released operand writes. Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted. Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing. Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault. First, any register altered by a faulted-instruction EA calculation is restored to its initial value. Then a special status word (SSW) is placed on the stack. The SSW contains specific information about the aborted access—size, type of access (read or write), bus cycle type, and function code. Finally, fault address, bus error exception vector number, PC value, and a copy of the SR are saved. If a bus error occurs during exception processing for a bus error, an address error, a reset, or while the processor is loading stack information during RTE execution, the processor halts. This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory. Only assertion of RESET can restart a halted processor. 5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts to access an instruction, word operand, or long-word operand at an odd address. The effect is much the same as an internally generated bus error. The exception processing sequence is the same as that for bus error, except that the vector number refers to the address error exception vector. Address error exception processing begins when the processor attempts to use information from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the MOTOROLA MC68340 USER’S MANUAL 5-45 case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access. An address exception on a branch to an odd address is delayed until the PC is changed. No exception occurs if the branch is not taken. In this case, the fault address and return PC value placed in the exception stack frame are the odd address, and the current instruction PC points to the instruction that caused the exception. If an address error occurs during exception processing for a bus error, another address error, or a reset, the processor halts. 5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise from either processor recognition of abnormal conditions during instruction execution or from use of specific trapping instructions. Traps are generally used to handle abnormal conditions that arise in control routines. The TRAP instruction, which always forces an exception, is useful for implementing system calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force exceptions when a program detects a run-time error. The DIVS and DIVU instructions force an exception if a division operation is attempted with a divisor of zero. Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced (the trap exception will be processed first, then the trace exception). The vector number for the TRAP instruction is internally generated—part of the number comes from the instruction itself. The trap vector number, PC value, and a copy of the SR are saved on the supervisor stack. The saved PC value is the address of the instruction that follows the instruction that generated the trap. For all instruction traps other than TRAP, a pointer to the instruction causing the trap is also saved in the fifth and sixth words of the exception stack frame. 5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32 must provide a means of inserting breakpoints into target code and of announcing when a breakpoint is reached. The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location. Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector address is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848–$484F). When a breakpoint instruction is executed, the CPU32 performs a read from CPU space $0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by BERR, the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK≈, the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations. 5-46 MC68340 USER’S MANUAL MOTOROLA 5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing, but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed. A pending breakpoint can be acknowledged between instructions or at the end of exception processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at location $1E (see Section 3 Bus Operation). If the bus cycle terminates normally, instruction execution continues with the next instruction, as if no breakpoint request occurred. If the bus cycle is terminated by BERR, the CPU begins exception processing. Data returned during this bus cycle is ignored. Exception processing follows the regular sequence. Vector number 12 (offset $30) is internally generated. The PC of the currently executing instruction, the PC of the next instruction to execute, and a copy of the SR are saved on the supervisor stack. 5.5.2.7 FORMAT ERROR. The processor checks certain data values for control operations. The validity of the stack format code and, in the case of a bus cycle fault format, the version number of the processor that generated the frame are checked during execution of the RTE instruction. This check ensures that the program does not make erroneous assumptions about information in the stack frame. If the format of the control data is improper, the processor generates a format error exception. This exception saves a four-word format exception frame and then vectors through vector table entry number 14. The stacked PC is the address of the RTE instruction that discovered the format error. 5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits 5–4 = 00 or bits 3–0 ≠ 0000. If an illegal instruction is fetched during instruction execution, an illegal instruction exception occurs. This facility allows the operating system to detect program errors or to emulate instructions in software. Word patterns with bits 15–12 = 1010 (referred to as A-line opcodes) are unimplemented instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented instructions to permit efficient emulation. Word patterns with bits 15–12 = 1111 (referred to as F-line opcodes) are used for M68000 family instruction set extensions. They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector. MOTOROLA MC68340 USER’S MANUAL 5-47 All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc., should use this opcode. Exception processing for illegal and unimplemented instructions is similar to that for traps. The instruction is fetched and decoding is attempted. When the processor determines that execution of an illegal instruction is being attempted, exception processing begins. No registers are altered. Exception processing follows the regular sequence. The vector number is generated to refer to the illegal instruction vector or in the case of an unimplemented instruction, to the corresponding emulation vector. The illegal instruction vector number, current PC, and a copy of the SR are saved on the supervisor stack, with the saved value of the PC being the address of the illegal or unimplemented instruction. 5.5.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be executed only at the supervisor access level. An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows: • AND Immediate to SR • EOR Immediate to SR • LPSTOP • MOVE from SR • MOVE to SR • MOVE USP • MOVEC • MOVES • OR Immediate to SR • RESET • RTE • STOP Exception processing for privilege violations is nearly identical to that for illegal instructions. The instruction is fetched and decoded. If the processor determines that a privilege violation has occurred, exception processing begins before instruction execution. Exception processing follows the regular sequence. The vector number (8) is generated to reference the privilege violation vector. Privilege violation vector offset, current PC, and SR are saved on the supervisor stack. The saved PC value is the address of the first word of the instruction causing the privilege violation. 5-48 MC68340 USER’S MANUAL MOTOROLA 5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing. When T1–T0 = 00, tracing is disabled, and instruction execution proceeds normally (see Table 5-18). Table 5-18. Tracing Control T1 T0 0 0 Tracing Function No tracing 0 1 Trace on change of flow 1 0 Trace on instruction execution 1 1 Undefined; reserved When T1–T0 = 01 at the beginning of instruction execution, a trace exception will be generated if the PC changes sequence during execution. All branches, jumps, subroutine calls, returns, and SR manipulations can be traced in this way. No exception occurs if a branch is not taken. When T1–T0 = 10 at the beginning of instruction execution, a trace exception will be generated when execution is complete. If the instruction is not executed, either because an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. At the present time, T1–T0 = 11 is an undefined condition. It is reserved by Motorola for future use. Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. Exception processing follows the regular sequence; tracing is disabled so that the trace exception itself is not traced. A vector number is generated to reference the trace exception vector. The address of the instruction that caused the trace exception, the trace exception vector offset, the current PC, and a copy of the SR are saved on the supervisor stack. The saved value of the PC is the address of the next instruction to be executed. A trace exception can be viewed as an extension to the function of any instruction. If a trace exception is generated by an instruction, the execution of that instruction is not complete until the trace exception processing associated with it is also complete. If an instruction is aborted by a bus error or address error exception, trace exception processing is deferred until the suspended instruction is restarted and completed normally. An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault. MOTOROLA MC68340 USER’S MANUAL 5-49 If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception. If an instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint. If an attempt is made to execute an illegal, unimplemented, or privileged instruction while tracing is enabled, no trace exception will occur because the instruction is not executed. This is particularly important to an emulation routine that performs an instruction function, adjusts the stacked PC to beyond the unimplemented instruction, and then returns. The SR on the stack must be checked to determine if tracing is on before the return is executed. If tracing is on, trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction. Tracing also affects normal operation of the STOP and LPSTOP instructions. If either instruction begins execution with T1 set, a trace exception will be taken after the instruction loads the SR. Upon return from the trace handler routine, execution will continue with the instruction following STOP (LPSTOP), and the processor will not enter the stopped condition. 5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor. Interrupt recognition and subsequent processing are based on internal interrupt request signals ( IRQ7 – IRQ1 ) and the current priority set in SR priority mask I2–I0. Interrupt request level zero (IRQ7– IRQ1 negated) indicates that no service is requested. When an interrupt of level one through six is requested via IRQ6– IRQ1, the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed. Interrupt requests are inhibited for all priority levels less than or equal to the current priority. Level seven interrupts are nonmaskable. IRQ7– IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock. To be valid, an interrupt request must be held constant for at least two consecutive clock periods. Interrupt requests do not force immediate exception processing, but are left pending. A pending interrupt is detected between instructions or at the end of exception processing— all interrupt requests must be held asserted until they are acknowledged by the CPU. If the priority of the interrupt is greater than the current priority level, exception processing begins. Exception processing occurs as follows. First, the processor makes an internal copy of the SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling 5-50 MC68340 USER’S MANUAL MOTOROLA tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus. If an interrupting device requests automatic vectoring, the processor generates a vector number (25 to 31) determined by the interrupt level number. If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken to be spurious, and the spurious interrupt vector number (24) is generated. The exception vector number, PC, and SR are saved on the supervisor stack. The saved value of the PC is the address of the instruction that would have executed if the interrupt had not occurred. Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts (NMI). Level 7 requests are transition sensitive to eliminate redundant servicing and resultant stack overflow. Transition sensitive means that the level 7 input must change state before the CPU will detect an interrupt. An NMI is generated each time the interrupt request level changes to level 7 (regardless of priority mask value), and each time the priority mask changes from 7 to a lower number while the request level remains at 7. Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request/acknowledge mechanism. If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request, the peripheral should return the uninitialized interrupt vector number (15). See Section 3 Bus Operation for detailed information on interrupt acknowledge cycles. 5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all pending exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore the system context in existence prior to the exception. The RTE instruction is designed to accomplish this task. When RTE is executed, the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed. See 5.5.4 CPU32 Stack Frames for a description of stack frames. For a normal four-word frame, the processor updates the SR and PC with data pulled from the stack, increments the SSP by 8, and resumes normal instruction execution. For a sixword frame, the SR and PC are updated from the stack, the active SSP is incremented by 12, and normal instruction execution resumes. For a bus fault frame, the format value on the stack is first checked for validity. In addition, the version number on the stack must match the version number of the processor that is MOTOROLA MC68340 USER’S MANUAL 5-51 attempting to read the stack frame. The version number is located in the most significant byte (bits 15–8) of the internal register word at location SP + $14 in the stack frame. The validity check ensures that stack frame data will be properly interpreted in multiprocessor systems. If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken. Otherwise, the processor reads the entire frame into the proper internal registers, de-allocates the stack (12 words), and resumes normal processing. Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame. If an error occurs during any of the bus cycles required by rewrite, the processor halts. If a format error occurs during RTE execution, the processor creates a normal four-word fault stack frame below the frame that it was attempting to use. If a bus error occurs, a bus-error stack frame will be created. The faulty stack frame remains intact, so that it may be examined and repaired by an exception handler or used by a different type of processor (e.g., MC68010, MC68020, or future M68000 processor) in a multiprocessor system. 5.5.3 Fault Recovery There are four phases of recovery from a fault: recognizing the fault, saving the processor state, repairing the fault (if possible), and restoring the processor state. Saving and restoring the processor state are described in the following paragraphs. The stack contents are identified by the special status word (SSW). In addition to identifying the fault type represented by the stack frame, the SSW contains the internal processor state corresponding to the fault. 15 14 13 12 11 10 9 8 7 6 5 TP MV 0 TR B1 B0 RR RM IN RW LG 4 3 SIZ 2 1 0 FUNC TP—BERR frame type MV—MOVEM in progress TR—Trace pending B1—Breakpoint channel 1 pending B0—Breakpoint channel 0 pending RR—Rerun write cycle after RTE RM—Faulted cycle was read-modify-write IN—Instruction/other RW—Read/write of faulted bus cycle LG—Original operand size was long word SIZ—Remaining size of faulted bus cycle FUNC—Function code of faulted bus cycle 5-52 MC68340 USER’S MANUAL MOTOROLA The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking: 0 = Operand or prefetch bus fault 1 = Exception processing bus fault MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM opcode and extension word, both the MV and IN bits will be set. 0 = MOVEM was not in progress when fault occurred 1 = MOVEM was in progress when fault occurred TR indicates that a trace exception was pending when a bus error exception was processed. The instruction that generated the trace will not be restarted upon return from the exception handler. This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW. 0 = Trace not pending 1 = Trace pending B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint source) when a bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception. 0 = Breakpoint not pending 1 = Breakpoint pending RR will be set if the faulted bus cycle was a released write. A released write is one that is overlapped. If the write is completed (rerun) in the exception handler, the RR bit should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon return from the exception handler. 0 = Faulted cycle was read, RMW, or unreleased write 1 = Faulted cycle was a released write Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking. 0 = Faulted cycle was non-RMW cycle 1 = Faulted cycle was either the read or write of an RMW cycle Instruction prefetch faults are distinguished from operand (both read and write) faults by the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on an instruction prefetch. IN is ignored during unstacking. 0 = Operand 1 = Prefetch MOTOROLA MC68340 USER’S MANUAL 5-53 Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is set during unstacking. 0 = Faulted cycle was an operand write 1 = Faulted cycle was a prefetch or operand read The LG bit indicates an original operand size of long word. LG is cleared if the original operand was a byte or word—SIZ will indicate original (and remaining) size. LG is set if the original was a long word—SIZ will indicate the remaining size at the time of fault. LG is ignored during unstacking. 0 = Original operand size was byte or word 1 = Original operand size was long word The SSW SIZ field shows operand size remaining when a fault was detected. This field does not indicate the initial size of the operand, nor does it necessarily indicate the proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the external bus and is transparent to the CPU. Byte size is shown only when the original operand was a byte. The field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ field is encoded as follows: 00—Long word 01—Byte 10—Word 11—Unused, reserved The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is a copy of FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle. 5.5.3.1.1 Type I—Released Write Faults. CPU32 instruction pipelining can cause a final instruction write to overlap the execution of a following instruction. A write that is overlapped is called a released write. A released write fault occurs when a bus error or some other fault occurs on the released write. Released write faults are taken at the next instruction boundary. The stacked PC is that of the next unexecuted instruction. If a subsequent instruction attempts an operand access while a released write fault is pending, the instruction is aborted and the write fault is acknowledged. This action prevents stale data from being used by the instruction. 5-54 MC68340 USER’S MANUAL MOTOROLA The SSW for a released write fault contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 0 0 TR B1 B0 1 0 0 0 LG 4 3 2 SIZ 0 FUNC TR, B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and FUNC fields. The remainder of the stack contains the PC of the next unexecuted instruction, the current SR, the address of the faulted memory location, and the contents of the data buffer that was to be written to memory. This data is written on the stack in the format depicted in Figure 5-15. When a released write fault exception handler executes, the machine will complete the faulted write and then continue executing instructions wherever the PC indicates. 5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus error exceptions are included in this category—all instruction prefetches, all operand reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the last write of a MOVEP Rn,〈ea〉 or the last write of MOVEM, which are type I faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not considered released. All type II faults cause an immediate exception that aborts the current instruction. Any registers that were altered as the result of an EA calculation (i.e., postincrement or predecrement) are restored prior to processing the bus cycle fault. The SSW for faults in this category contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0 B1 B0 0 RM IN RW LG 4 3 SIZ 2 0 FUNC The trace pending bit is always cleared, since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be taken prior to restarting the instruction. If the exception handler does not alter the stacked SR trace bits, the trace is requeued when the instruction is started. The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted upon return from the handler. This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location. If this response is not desired, the exception handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ fields all reflect the type of bus cycle that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit will show whether the fault was on a read or write. MOTOROLA MC68340 USER’S MANUAL 5-55 5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults. Type III faults cause an immediate exception that aborts the current instruction. None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler. This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction execution. Since postincremented registers are not updated until the end of an instruction, the register retains its pre-instruction value unless overwritten by operand movement. The SSW for faults in this category contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 0 1 0 TR B1 B0 RR 0 IN RW LG 4 3 2 SIZ 0 FUNC MV is set, indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler. TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. IN is set if a bus fault occurs while prefetching an opcode or an extension word during instruction restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR bit set to indicate that the write should be rerun upon return from the exception handler. The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer. The address of the next operand to be transferred, incremented or decremented by operand size, is stored in the faulted address location ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted (including the faulted cycle). Refer to Figure 5-12 for the stacking format. 5.5.3.1.4 Type IV—Faults During Exception Processing. The fourth type of fault occurs during exception processing. If this exception is a second address or bus error, the machine halts in the double bus fault condition. However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. The SSW for a fault within an exception contains the following bit pattern: 15 14 13 12 11 10 9 8 7 6 5 1 0 0 TR B1 B0 0 0 0 1 LG 4 3 SIZ 2 0 FUNC TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception is taken. The contents of the faulted exception stack frame are included in the bus fault stack frame. The pre-exception SR and the format/vector word of the faulted frame are stacked. The type of exception can be determined from the format/vector word. If the faulted exception stack frame contains six words, the PC of the instruction that caused the initial 5-56 MC68340 USER’S MANUAL MOTOROLA exception is also stacked. This data is placed on the stack in the format shown in Figure 5-13. The return address from the initial exception is stacked for RTE . 5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via RTE. Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted. There are three varieties of type III operand fault recovery. The first is completion of an instruction in software. The second is conversion to type II with restart via RTE. The third is continuation from the fault via RTE. 5.5.3.2.1 Type I—Completing Released Writes via Software. To complete a bus cycle in software, a handler must first read the SSW function code field to determine the appropriate address space, access the fault address pointer on the stack, and then transfer data from the stacked image of the output buffer to the fault address. Because the CPU32 has a 16-bit internal data bus, long operands require two bus accesses. A fault during the second access of a long operand causes the LG bit in the SSW to be set. The SIZ field indicates remaining operand size. If operand coherency is important, the complete operand must be rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the RR bit can cause the RTE instruction to rerun the bus cycle. Following rewrite, it is not necessary to adjust the PC (or other stack contents) before executing RTE. 5.5.3.2.2 Type I—Completing Released Writes via RTE. An exception handler can use the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address, data output buffer, PC, and SR are restored from the stack. Any pending breakpoint or trace exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are requeued during SSW restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set, the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to RTE execution. The fault address must be decremented by 2 if LG is set and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields should be left unchanged. The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle. Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control bits could cause the bus cycle to be a read instead of a write or could cause access to a different address space than the original bus cycle. If the rerun bus cycle is a read, returned data will be ignored. MOTOROLA MC68340 USER’S MANUAL 5-57 5.5.3.2.3 Type II—Correcting Faults via RTE. Instructions aborted because of a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved. An RTE instruction terminates the exception handler. After unstacking the machine state, the instruction is refetched and restarted. 5.5.3.2.4 Type III—Correcting Faults via Software. Sufficient information is contained in the stack frame to complete MOVEM in software. After the cause of the fault is corrected, the faulted bus cycle must be rerun. Perform the following procedures to complete an instruction through software: A. Setup for Rerun Read the MOVEM opcode and extension from locations pointed to by stackframe PC and PC + 2. The EA need not be recalculated since the next operand address is saved in the stack frame. However, the opcode EA field must be examined to determine how to update the address register and PC when the instruction is complete. Adjust the mask to account for operands already transferred. Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred. Scan the mask using this count value. Each time a set bit is found, clear it and decrement the counter. When the count is zero, the mask is ready for use. Adjust the operand address. If the predecrement addressing mode is in effect, subtract the operand size from the stacked value; otherwise, add the operand size to the stacked value. B. Rerun Instruction Scan the mask for set bits. Read/write the selected register from/to the operand address as each bit is found. As each operand is transferred, clear the mask bit and increment (decrement) the operand address. When all bits in the mask are cleared, all operands have been transferred. If the addressing mode is predecrement or postincrement, update the register to complete the execution of the instruction. If TR is set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either B1 or B0 is set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. De-allocate the stack and return control to the faulted program. 5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart. In some situations it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand. Clearing the MV bit in the stacked SSW converts a type III fault into a type II fault. Consequently, MOVEM, like all other type II 5-58 MC68340 USER’S MANUAL MOTOROLA exceptions, will be restarted upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an EA calculation is overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart. 5.5.3.2.6 Type III—Correcting Faults via RTE. The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents. The RTE recognizes that MOVEM was in progress when a fault occurred, restores the appropriate machine state, refetches the instruction, repeats the faulted transfer, and continues the instruction. MOVEM is the only instruction continued upon return from an exception handler. Although the instruction is refetched, the EA is not recalculated, and the mask is rescanned the same number of times as before the fault; modifying the code prior to RTE can cause unexpected results. 5.5.3.2.7 Type IV—Correcting Faults via Software. Bus error exceptions can occur during exception processing while the processor is fetching an exception vector or while it is stacking. The same stack frame and SSW are used in both cases, but each has a distinct fault address. The stacked faulted exception format/vector word identifies the type of faulted exception and the contents of the remainder of the frame. A fault address corresponding to the vector specified in the stacked format/vector word indicates that the processor could not obtain the address of the exception handler. A bus error exception handler should execute RTE after correcting a fault. RTE restores the internal machine state, fetches the address of the original exception handler, recreates the original exception stack frame, and resumes execution at the exception handler address. If the fault is intractable, the exception handler should rewrite the faulted exception stack frame at SP + $14 + $06 and then jump directly to the original exception handler. The stack frame can be generated from the information in the bus error frame: the preexception SR (SP + $0C), the format/vector word (SP + $0E), and, if the frame being written is a six-word frame, the PC of the instruction causing the exception (SP + $10). The return PC value is available at SP + $02. A stacked fault address equal to the current SP may indicate that, although the first exception received a bus error while stacking, the bus error exception stacking successfully completed. This occurrence is extremely improbable, but the CPU32 supports recovery from it. Once the exception handler determines that the fault has been corrected, recovery can proceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted exception frame on top of the stack, and resume execution at the exception handler address. MOTOROLA MC68340 USER’S MANUAL 5-59 5.5.4 CPU32 Stack Frames The CPU32 generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions. Depending on the exception type, the PC value is either the address of the next instruction to be executed or the address of the instruction that caused the exception (see Figure 5-12). 15 0 SP ⇒ STATUS REGISTER +$02 PROGRAM COUNTER HIGH PROGRAM COUNTER LOW +$06 0 0 0 0 VECTOR OFFSET Figure 5-12. Format $0—Four-Word Stack Frame 5.5.4.2 SIX-WORD STACK FRAME. This stack frame (see Figure 5-13) is created by instruction-related traps, which include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero, and by trace exceptions. The faulted instruction PC value is the address of the instruction that caused the exception. The next PC value (the address to which RTE returns) is the address of the next instruction to be executed. 15 0 SP ⇒ STATUS REGISTER +$02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 +$08 0 0 1 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 5-13. Format $2—Six-Word Stack Frame Hardware breakpoints also utilize this format. The faulted instruction PC value is the address of the instruction executing when the breakpoint was sensed. Usually this is the address of the instruction that caused the breakpoint, but, because released writes can overlap following instructions, the faulted instruction PC may point to an instruction following the instruction that caused the breakpoint. The address to which RTE returns is the address of the next instruction to be executed. 5.5.4.3 BUS ERROR STACK FRAME. This stack frame is created when a bus cycle fault is detected. The CPU32 bus error stack frame differs significantly from the equivalent stack frames of other M68000 Family members. The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register. 5-60 MC68340 USER’S MANUAL MOTOROLA Bus operation in progress at the time of a fault is conveyed by the SSW. 15 14 13 12 11 10 9 8 7 6 5 4 TP MV 0 TR B1 B0 RR RM IN RW LG 3 SIZ 2 1 0 FUNC The bus error stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields. An internal transfer count register appears at location SP + $14 in all bus error stack frames. The register contains an 8-bit microcode revision number, and, for type III faults, an 8-bit transfer count. Register format is shown in Figure 5-14. 15 8 7 MICROCODE REVISION NUMBER 0 TRANSFER COUNT Figure 5-14. Internal Transfer Count Register The microcode revision number is checked before a bus error stack frame is restored via RTE. In a multiprocessor system, this check ensures that a processor using stacked information is at the same revision level as the processor that created it. The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is set, the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution. For faults occurring during normal instruction execution (both prefetches and non-MOVEM operand accesses) SSW TP, MV = 00. Stack frame format is shown in Figure 5-15. Faults that occur during the operand portion of the MOVEM instruction are identified by SSW TP, MV = 01. Stack frame format is shown in Figure 5-16. When a bus error occurs during exception processing, SSW TP, MV = 10. The frame shown in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to by SP – 6 (SP value is the value before initial stacking on the faulted frame). The frame can have either four or six words, depending on the type of error. Four-word stack frames do not include the faulted instruction PC (the internal transfer count register is located at SP + $10 and the SSW is located at SP + $12). The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error. MOTOROLA MC68340 USER’S MANUAL 5-61 15 0 SP ⇒ STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 1 1 0 0 +$08 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 0 0 SPECIAL STATUS WORD Figure 5-15. Format $C—BERR Stack for Prefetches and Operands 15 0 SP ⇒ STATUS REGISTER +$02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW +$06 1 1 +$08 0 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C DBUF HIGH DBUF LOW +$10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 0 1 SPECIAL STATUS WORD Figure 5-16. Format $C—BERR Stack on MOVEM Operand 5-62 MC68340 USER’S MANUAL MOTOROLA 15 0 SP ⇒ STATUS REGISTER +$02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW +$06 1 1 0 0 VECTOR OFFSET +$08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW +$0C PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) +$14 +$16 INTERNAL TRANSFER COUNT REGISTER 1 0 SPECIAL STATUS WORD Figure 5-17. Format $C—Four- and Six-Word BERR Stack 5.6 DEVELOPMENT SUPPORT All M68000 family members have the following special features that facilitate applications development. Trace on Instruction Execution—All M68000 processors include an instruction-byinstruction tracing facility to aid in program development. The MC68020, MC68030, and CPU32 can also trace those instructions that change program flow. In trace mode, an exception is generated after each instruction is executed, allowing a debugger program to monitor execution of a program under test. See 5.5.2.10 Tracing for more information. Breakpoint Instruction—An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32, this function is provided via illegal instructions ($4848–$484F) that serve as breakpoint instructions. See 5.5.2.5 Software Breakpoints for more information. Unimplemented Instruction Emulation—When an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, Aline) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more information. 5.6.1 CPU32 Integrated Development Support In addition to standard MC68000 family capabilities, the CPU32 has features to support advanced integrated system development. These features include background debug mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a single-chip environment. MOTOROLA MC68340 USER’S MANUAL 5-63 5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode. BDM incorporates a full set of debug options—registers can be viewed and/or altered, memory can be read or written, and test features can be invoked. A resident debugger simplifies implementation of an in-circuit emulator. In a common setup (see Figure 5-18), emulator hardware replaces the target system processor. A complex, expensive pod-and-cable interface provides a communication path between target system and emulator. IN-CIRCUIT EMULATOR TARGET SYSTEM TARGET MCU .. . Figure 5-18. In-Circuit Emulator Configuration By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for incircuit emulation. The processor remains in the target system (see Figure 5-19), and the interface is simplified. The BSA monitors target processor operation and the on-chip debugger controls the operating environment. Emulation is much closer to target hardware; thus, many interfacing problems (i.e., limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable length) are minimized. TARGET SYSTEM TARGET MCU BUS STATE ANALYZER . Figure 5-19. Bus State Analyzer Configuration 5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32 function code outputs are augmented by two supplementary signals that monitor the instruction pipeline. The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and signals pipeline flushes. The IPIPE output signal indicates when each mid-instruction pipeline advance occurs and when instruction execution begins. These signals allow a BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode Tracking for complete information. 5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input and an on-chip hardware breakpoint capability permit breakpoint trap on any 5-64 MC68340 USER’S MANUAL MOTOROLA memory access. Off-chip address comparators will not detect breakpoints on internal accesses unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed from the pipeline before execution, are not acknowledged, but operand breakpoints are always acknowledged. Acknowledged breakpoints can initiate either exception processing or BDM. See 5.5.2.6 Hardware Breakpoints for more information. 5.6.2 Background Debug Mode BDM is an alternate CPU32 operating mode. During BDM, normal instruction execution is suspended, and special microcode performs debugging functions under external control. Figure 5-20 is a BDM block diagram. BDM can be initiated in several ways—by externally generated breakpoints, by internal peripheral breakpoints, by the background instruction (BGND), or by catastrophic exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated, high-speed, SPI-type serial command interface. SERIAL INTERFACE IPIPE/DSO MICROCODE SEQUENCER IFETCH/DSI IRC IRB IR BERR BERR BERR BKPT BKPT BKPT BKPT/DSCLK BUS CONTROL DATA BUS BERR FREEZE . . ... EXECUTION UNIT ADDRESS BUS Figure 5-20. BDM Block Diagram 5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment could lock up the CPU32 since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the BKPT signal. MOTOROLA MC68340 USER’S MANUAL 5-65 BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM remains enabled until the next system reset. A high BKPT on the trailing edge of RESET disables BDM. BKPT is relatched on each rising transition of RESET . BKPT is synchronized internally and must be held low for at least two clock cycles prior to negation of RESET. BDM enable logic must be designed with special care. If hold time on BKPT (after the trailing edge of RESET) extends into the first bus cycle following reset, this bus cycle could be tagged with a breakpoint. Refer to Section 3 Bus Operation for timing information. 5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the transition from normal mode to BDM. These sources include external BKPT hardware, the BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled when an exception condition occurs, the exception is processed normally. Table 5-19 summarizes the processing of each source for both enabled and disabled cases. As depicted in the table, the BKPT instruction never causes a transition into BDM. Table 5-19. BDM Source Summary Source BDM Enabled BDM Disabled BKPT Background Breakpoint Exception Double Bus Fault Background Halted BGND Instruction Background Illegal Instruction BKPT Instruction Opcode Substitution/ Illegal Instruction Opcode Substitution/ Illegal Instruction 5.6.2.2.1 External BKPT Signal. Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered. 5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal instruction traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions. 5.6.2.2.3 Double Bus Fault. The CPU32 normally treats a double bus fault (two bus faults in succession) as a catastrophic system error and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can be isolated and eliminated. 5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE output. FREEZE assertion is the first indication that the processor has entered BDM. Once FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command. 5-66 MC68340 USER’S MANUAL MOTOROLA The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (see Table 5-20) by issuing a read system register command (RSREG). ATEMP is used in most debugger commands for temporary storage—it is imperative that the RSREG command be the first command issued after transition into BDM. Table 5-20. Polling the BDM Entry Source Source ATEMP 31–16 ATEMP 15–0 Double Bus Fault SSW* $FFFF BGND Instruction $0000 $0001 Hardware Breakpoint $0000 $0000 *SSW is described in detail in 5.5.3 Fault Recovery. A double bus fault during initial SP/PC fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register. 5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution. Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each command until the CPU returns to normal operating mode. 5.6.2.5 BDM REGISTERS. BDM processing uses three special-purpose registers to track program context during development. A description of each register follows. 5.6.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulting bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the address of the last bus cycle. The address of the first fault (if one occurred) is not visible to the user. 5.6.2.5.2 Return Program Counter (RPC). The RPC points to the location where fetching will commence after transition from BDM to normal mode. This register should be accessed to change the flow of a program under development. Changing the RPC to an odd value will cause an address error when normal mode prefetching begins. 5.6.2.5.3 Current Instruction Program Counter (PCC). The PCC holds a pointer to the first word of the last instruction executed prior to transition into BDM. Due to instruction pipelining, the instruction pointed to may not be the instruction which caused the transition. An example is a breakpoint on a released write. The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer. A BKPT asserted during this cycle will not be acknowledged until the end of the instruction MOTOROLA MC68340 USER’S MANUAL 5-67 executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset. CPU32 ACTIVITY DEVELOPMENT SYSTEM ACTIVITY . ENTER (BDM) • ASSERT FREEZE SIGNAL • WAIT FOR COMMAND SEND INITIAL COMMAND • LOAD COMMAND REGISTER • ENABLE SHIFT CLOCK • SHIFT OUT 17 BITS • DISABLE SHIFT CLOCK EXECUTE COMMAND • LOAD: NOT READY/ RESPONSE • PERFORM COMMAND • STORE RESULTS READ RESULTS/NEW COMMAND • LOAD COMMAND REGISTER • ENABLE SHIFT CLOCK • SHIFT IN/OUT 17 BITS • DISABLE SHIFT CLOCK • READ RESULT REGISTER IF RESULTS = "NOT READY" YES NO CONTINUE Figure 5-21. BDM Command Execution Flowchart 5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC. The return PC and the memory space referred to by the SR SUPV bit reflect any changes made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE and IFETCH functionality. 5.6.2.7 SERIAL INTERFACE. Communication with the CPU32 during BDM occurs via a dedicated serial interface, which shares pins with other development features. The BKPT signal becomes the DSCLK; DSI is received on IFETCH , and DSO is transmitted on IPIPE. 5-68 MC68340 USER’S MANUAL MOTOROLA The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency. The serial interface operates in full-duplex mode—i.e., data is transmitted and received simultaneously by both master and slave devices. In general, data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first and is latched on the rising edge of DSCLK. The serial data word is 17 bits wide—16 data bits and a status/control (S/C) bit. 16 15 0 S/C DATA FIELD Bit 16 indicates the status of CPU-generated messages as shown in Table 5-21. Table 5-21. CPU Generated Message Encoding Encoding Data Message Type 0 xxxx Valid Data Transfer 0 FFFF Command Complete; Status OK 1 0000 Not Ready with Response; Come Again 1 0001 BERR Terminated Bus Cycle; Data Invalid 1 FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements. 5.6.2.7.1 CPU Serial Logic. CPU serial logic, shown in the left-hand portion of Figure 522, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter. Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the chance of propagating metastable states into the serial state machine. Data is sampled during the high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to internal logic. If there is no synchronization between CPU32 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT. MOTOROLA MC68340 USER’S MANUAL 5-69 CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS DATA 16 16 0 . RCV DATA LATCH SERIAL IN PARALLEL OUT COMMAND LATCH DSI PARALLEL IN SERIAL OUT DSO SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT 16 STATUS RESULT LATCH EXECUTION UNIT 16 STATUS SYNCHRONIZE MICROSEQUENCER CONTROL LOGIC DSCLK DATA CONTROL LOGIC SERIAL CLOCK Figure 5-22. Debug Serial I/O Block Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK (see Figure 5-23). Synchronized serial data is transferred to the input shift register, and the received bit counter is decremented. One-half clock period later, the output shift register is updated, bringing the next output bit to the DSO signal. DSO changes relative to the rising edge of DSCLK and does not necessarily remain stable until the falling edge of DSCLK. One clock period after the synchronized DSCLK has been seen internally, the updated counter value is checked. If the counter has reached zero, the receive data latch is updated from the input shift register. At this same time, the output shift register is reloaded with the “not ready/come again” response. Once the receive data latch has been loaded, the CPU is released to act on the new data. Response data overwrites the “not ready” response when the CPU has completed the current operation. Data written into the output shift register appears immediately on the DSO signal. In general, this action changes the state of the signal from a high (“not ready” response status bit) to a low (valid data status bit) logic level. However, this level change only occurs if the command completes successfully. Error conditions overwrite the “not ready” response with the appropriate response that also has the status bit set. 5-70 MC68340 USER’S MANUAL MOTOROLA CLKOUT FREEZE DSCLK DSI SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO . CLKOUT Figure 5-23. Serial Interface Timing Diagram A user can use the state change on DSO to signal hardware that the next serial transfer may begin. A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design. Hardware interlocks in the CPU prevent result data from corrupting serial transfers in progress. 5.6.2.7.2 Development System Serial Logic. The development system, as the master of the serial data link, must supply the serial clock. However, normal and BDM operations could interact if the clock generator is not properly designed. Breakpoint requests are made by asserting BKPT to the low state in either of two ways. The primary method is to assert BKPT during a single bus cycle for which an exception is desired. Another method is to assert BKPT , then continue to assert it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transition into BDM when the bus is not being monitored. Each method requires a slightly different serial logic design to avoid spurious serial clocks. Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle. MOTOROLA MC68340 USER’S MANUAL 5-71 SHIFT_CLK FORCE_BGND BKPT_TAG BKPT . . .... .. . . . . .. . . . . FREEZE Figure 5-24. BKPT Timing for Single Bus Cycle Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned previously, all timing within the CPU is derived from the rising edge of the clock; the falling edge is effectively ignored. SHIFT_CLK FORCE_BGND BKPT_TAG BKPT . . .... .. . . . . .. . . . .. . FREEZE Figure 5-25. BKPT Timing for Forcing BDM Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the name implies, FORCE_BGND is used to force a transition into BDM by the assertion of BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is applied. BKPT_TAG SHIFT_CLK ... BKPT/DSCLK S1 RESET FORCE_BGND Q S2 R Q Figure 5-26. BKPT/DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first DSCLK. 5-72 MC68340 USER’S MANUAL MOTOROLA DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it remains high until the start of the next transmission. Clock frequency is implementation dependent and may range from DC to the maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions can be used provided serial bus timing is maintained. 5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in BDM. 5.6.2.8.1 Command Format. The following standard bit format is utilized by all BDM commands. 15 10 OPERATION 9 8 0 R/W 7 6 OP SIZE 5 4 3 0 0 A/D 2 0 REGISTER EXTENSION WORD(S) Bits 15–0—Operation Field The operation field specifies the commands. This 6-bit field provides for a maximum of 64 unique commands. R/W Field The R/W field specifies the direction of operand transfer. When the bit is set, the transfer is from CPU to development system. When the bit is cleared, data is written to the CPU or to memory from the development system. Operand Size For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 5-22. Table 5-22. Size Field Encoding Encoding Operand Size 00 Byte 01 Word 10 Long 11 Reserved Address/Data (A/D) Field The A/D field is used by commands that operate on address and data registers. It determines whether the register field specifies a data or address register. One indicates an address register; zero indicates a data register. For other commands, this field may be interpreted differently. MOTOROLA MC68340 USER’S MANUAL 5-73 Register Field: In most commands, this field specifies the register number for operations performed on an address or data register. Extension Word(s) (as required): At this time, no command requires an extension word to specify fully the operation to be performed, but some commands require extension words for addresses or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Immediate data can be either one or two words in length—byte and word data each require a single extension word, long-word data requires two words. Both operands and addresses are transferred most significant word first. 5.6.2.8.2 Command Sequence Diagram. A command sequence diagram (see Figure 527) illustrates the serial bus traffic for each command. Each bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each diagram corresponds to the data transmitted by the development system to the CPU; the bottom half corresponds to the data returned by the CPU in response to the development system commands. Command and result transactions are overlapped to minimize latency. The cycle in which the command is issued contains the development system command mnemonic (in this example, read memory location). During the same cycle, the CPU responds with either the lowest order results of the previous command or with a command complete status (if no results were required). During the second cycle, the development system supplies the high-order 16 bits of the memory address. The CPU returns a "not ready" response unless the received command was decoded as unimplemented, in which case the response data is the illegal command encoding. If an illegal command response occurs, the development system should retransmit the command. NOTE The “not ready” response can be ignored unless a memory bus cycle is in progress. Otherwise, the CPU can accept a new serial transfer with eight system clock periods. In the third cycle, the development system supplies the low-order 16 bits of a memory address. The CPU always returns the “not ready” response in this cycle. At the completion of the third cycle, the CPU initiates a memory read operation. Any serial transfers that begin while the memory access is in progress return the “not ready” response. Results are returned in the two serial transfer cycles following the completion of memory access. The data transmitted to the CPU during the final transfer is the opcode for the following command. Should a memory access generate either a bus or address error, an error status is returned in place of the result data. 5-74 MC68340 USER’S MANUAL MOTOROLA COMMANDS TRANSMITTED TO THE CPU32 COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" NEXT COMMAND CODE XXX XXX MS RESULT NEXT CMD LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY CPU32 RESULTS FROM PREVIOUS COMMAND HIGH- AND LOW-ORDER 16 BITS OF RESULT . . .... .. . . . . .. . . . .. .. .. . RESPONSES FROM THE CPU Figure 5-27. Command-Sequence Diagram 5.6.2.8.3 Command Set Summary. The BDM command set is summarized in Table 5-23. Subsequent paragraphs contain detailed descriptions of each command. MOTOROLA MC68340 USER’S MANUAL 5-75 Table 5-23. BDM Command Summary Command Mnemonic Description Read A/D Register Read the selected address or data register and return the results via the serial interface. RAREG/RDREG Write A/D Register WAREG/WDREG The data operand is written to the specified address or data register. Read System Register RSREG The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. Write System Register WSREG The operand data is written into the specified system control register. Read Memory Location READ Read the sized data at the memory location specified by the longword address. The SFC register determines the address space accessed. Write Memory Location WRITE Write the operand data to the memory location specified by the long-word address. The DFC register determines the address space accessed. Dump Memory Block DUMP Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. Fill Memory Block FILL Used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. Resume Execution GO The pipeline is flushed and refilled before resuming instruction execution at the return PC. Call User Code CALL Current PC is stacked at the location of the current SP. Instruction execution begins at user patch code. Reset Peripherals RST Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction. No Operation NOP NOP performs no operation and may be used as a null command. 5.6.2.8.4 Read A/D Register (RAREG/RDREG). Read the selected address or data register and return the results via the serial interface. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 1 0 0 0 0 1 1 0 0 0 A/D 2 1 0 REGISTER Command Sequence: RDREG/RAREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None 5-76 MC68340 USER’S MANUAL MOTOROLA Result Data: The contents of the selected register are returned as a long-word value. The data is returned most significant word first. 5.6.2.8.5 Write A/D Register (WAREG/WDREG). The operand (long-word) data is written to the specified address or data register. All 32 bits of the register are altered by the write. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 1 0 0 0 0 0 1 0 0 0 A/D 2 0 REGISTER Command Sequence: WDREG/WAREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Operand Data: Long-word data is written into the specified address or data register. The data is supplied most significant word first. Result Data: Command complete status ($0FFFF) is returned when register write is complete. 5.6.2.8.6 Read System Register (RSREG). The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM. Several internal temporary registers are also accessible. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 0 0 1 0 0 1 0 0 1 0 0 0 3 0 REGISTER Command Sequence: RSREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None MOTOROLA MC68340 USER’S MANUAL 5-77 Result Data: Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended. Register Field: The system control register is specified by the register field (see Table 5-24). Table 5-24. Register Field for RSREG and WSREG System Register Select Code Return Program Counter (RPC) 0000 Current Instruction Program Counter (PCC) 0001 Status Register (SR) 1011 User Stack Pointer (USP) 1100 Supervisor Stack Pointer (SSP) 1101 Source Function Code Register (SFC) 1110 Destination Function Code Register (DFC) 1111 Temporary Register A (ATEMP) 1000 Fault Address Register (FAR) 1001 Vector Base Register (VBR) 1010 5.6.2.8.7 Write System Register (WSREG). Operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in BDM. Several internal temporary registers are also accessible. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 0 0 1 0 0 1 0 0 1 0 0 0 3 0 REGISTER Command Sequence: WSREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Operand Data: The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used. Result Data: “Command complete” status is returned when register write is complete. 5-78 MC68340 USER’S MANUAL MOTOROLA Register Field: The system control register is specified by the register field (see Table 5-24). The FAR is a read-only register—any write to it is ignored. 5.6.2.8.8 Read Memory Location (READ). Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space accessed. Valid data sizes include byte, word, or long word. Command Format: 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 0 0 1 OP SIZE 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: READ (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT XXX BERR/AERR READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION NEXT CMD "NOT READY" XXX "NOT READY" XXX MS RESULT NEXT CMD LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: The single operand is the long-word address of the requested memory location. Result Data: The requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result, with the upper byte cleared. Word results return 16 bits of significant data; long-word results return 32 bits. A successful read operation returns data bit 16 cleared. If a bus or address error is encountered, the returned data is $10001. 5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The DFC register determines the address MOTOROLA MC68340 USER’S MANUAL 5-79 space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word. Command Format: 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 0 0 0 OP SIZE 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY" WRITE (LONG) ??? MS ADDR "NOT READY" XXX "ILLEGAL" LS ADDR "NOT READY" MS DATA "NOT READY" NEXT CMD "NOT READY" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT XXX CMD "CMD COMPLETE" XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: Two operands are required for this instruction. The first operand is a long-word absolute address that specifies a location to which the operand data is to be written. The second operand is the data. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Successful write operations return a status of $0FFFF. Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of $0001. 5.6.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the 5-80 MC68340 USER’S MANUAL MOTOROLA starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE The DUMP command does not check for a valid address in the temporary register—DUMP is a valid command only when preceded by another DUMP or by a READ command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is given, allowing the operand size to be altered dynamically. Command Format: 15 14 13 12 11 10 9 8 7 0 0 0 1 1 1 0 1 OP SIZE 6 5 4 3 2 1 0 0 0 0 0 0 0 Command Sequence: DUMP (LONG) ??? READ MEMORY LOCATION XXX "NOT READY" NEXT CMD RESULT DUMP (LONG) ??? READ MEMORY LOCATION XXX BERR/AERR NEXT CMD "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD MS RESULT MOTOROLA NEXT CMR LS RESULT XXX BERR/AERR NEXT CMD "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" MC68340 USER’S MANUAL 5-81 Operand Data: None Result Data: Requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result. Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $0xxxx for success, $10001 for bus or address errors. 5.6.2.8.11 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. The initial address is incremented by the operand size (1, 2, or 4) and is saved in a temporary register. Subsequent FILL commands use this address, increment it by the current operand size, and store the updated address back in the temporary register. NOTE The FILL command does not check for a valid address in the temporary register—FILL is a valid command only when preceded by another FILL or by a WRITE command. Otherwise, the results are undefined. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a FILL command is given, allowing the operand size to be altered dynamically. Command Format: 15 14 13 12 11 10 9 8 7 0 0 0 1 1 1 0 0 OP SIZE 5-82 6 MC68340 USER’S MANUAL 5 4 3 2 1 0 0 0 0 0 0 0 MOTOROLA Command Sequence: FILL (B/W) ??? WRITE MEMORY LOCATION LS DATA "NOT READY" MS DATA "NOT READY" XXX "ILLEGAL" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR/AERR FILL (LONG) ??? DATA "NOT READY" WRITE MEMORY LOCATION XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR/AERR Operand Data: A single operand is data to be written to the memory location. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively. Result Data: Status is returned as in the WRITE command: $0FFFF for a successful operation and $10001 for a bus or address error during write. 5.6.2.8.12 Resume Execution (GO). The pipeline is flushed and refilled before normal instruction execution is resumed. Prefetching begins at the return PC and current privilege level. If either the PC or SR is altered during BDM, the updated value of these registers is used when prefetching commences. NOTE The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new PC—the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MOTOROLA MC68340 USER’S MANUAL 5-83 Command Sequence: GO ??? NORMAL MODE XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: None 5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch user code. The return PC is stacked at the location pointed to by the current SP. The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine. After stacking is complete, the 32-bit operand data is loaded into the PC. The pipeline is flushed and refilled from the location pointed to by the new PC, BDM is exited, and normal mode instruction execution begins. NOTE If a bus error or address error occurs during return address stacking, the CPU returns an error status via the serial interface and remains in BDM. If a bus error or address error occurs on the first instruction prefetch from the new PC, the processor exits BDM and the error is trapped as a normal mode exception. The stacked value of the current PC may not be valid in this case, depending on the state of the machine prior to entering BDM. For address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5-84 MC68340 USER’S MANUAL MOTOROLA Command Sequence: CALL ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" STACK RETURN PC FREEZE NEGATED PREFETCH STARTED NORMAL MODE XXX BERR/AERR NEXT CMD "NOT READY" Operand Data: The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting BDM. Result Data: None As an example, consider the following code segment. It outputs a character from the MC68340 serial module channel A. CHKSTAT: MOVE.B BNE.B MOVE.B SRA,D0 CHKSTAT TBA,OUTPUT Move serial status to D0 Loop until condition true Transmit character MISSING: ANDI.B RTS #3,D0 Check for TxEMP flag BDM and the CALL command can be used to patch the code as follows: 1. 2. 3. 4. 5. 6. Breakpoint user program at CHKSTAT Enter BDM Execute CALL command to MISSING Exit BDM Execute MISSING code Return to user program 5.6.2.8.14 Reset Peripherals (RST). RST asserts RESET for 512 clock cycles. The CPU is not reset by this command. This command is synonymous with the CPU RESET instruction. MOTOROLA MC68340 USER’S MANUAL 5-85 Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Command Sequence: RESET ??? ASSERT RESET XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: The “command complete” response ($0FFFF) is loaded into the serial shifter after negation of RESET. 5.6.2.8.15 No Operation (NOP). NOP performs no operation and may be used as a null command where required. Command Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Command Sequence: NOP ??? NEXT CMD "CMD COMPLETE" XXX "ILLEGAL" NEXT CMD "NOT READY" Operand Data: None Result Data: The “command complete” response ($0FFFF) is returned during the next shift operation. 5-86 MC68340 USER’S MANUAL MOTOROLA 5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL command response. 5.6.3 Deterministic Opcode Tracking The CPU32 utilizes deterministic opcode tracking to trace program execution. Two signals, IPIPE and IFETCH, provide all information required to analyze instruction pipeline operation. 5.6.3.1 INSTRUCTION FETCH (IFETCH ) . IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline. IFETCH is pulse-width modulated to multiplex two indications on a single pin. Asserted for a single clock cycle, IFETCH indicates that the data from the current bus cycle is to be routed to the instruction pipeline. IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushed. The data from the bus cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are signaled by IFETCH. Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine. On a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch followed immediately by a second prefetch. That is, IFETCH remains asserted for three clocks, two clocks indicating the flush/fetch and a third clock signaling the second fetch. These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT, which follow the AS ( DS during show cycles) falling edge. Three-clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation. 5.6.3.2 INSTRUCTION PIPE (IPIPE ) . The internal instruction pipeline can be modeled as a three-stage FIFO (see Figure 5-28). Stage A is an input buffer—data can be used out of stages B and C. IPIPE signals advances of instructions in the pipeline. Instruction register A (IRA) holds incoming words as they are prefetched. No decoding takes place in the buffer. Instruction register B (IRB) provides initial decoding of the opcode and decoding of extension words; it is a source of immediate data. Instruction register C (IRC) supplies residual opcode decoding during instruction execution. DATA BUS I I I R R R A B C EXTENSION WORDS OPCODES RESIDUAL . Figure 5-28. Functional Model of Instruction Pipeline MOTOROLA MC68340 USER’S MANUAL 5-87 Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regardless of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is asserted. If IRA contains valid data, the data is copied into IRB (IRA ⇒ IRB), and the IRB stage is revalidated. Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB ⇒ IRC and IRA ⇒ IRB). IRA is refilled during the next instruction fetch bus cycle. Data loaded into IRA propagates automatically through subsequent empty pipeline stages. Signals that show the progress of instructions through IRB and IRC are necessary to accurately monitor pipeline operation. These signals are provided by IRA and IRB validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set, and the validity bit of the stage supplying the data is negated. Because instruction execution is not timed to bus activity, IPIPE is synchronized with the system clock, not the bus. Figure 5-29 illustrates the timing in relation to the system clock. IR IR IR IRB IR IRC IR IRB .. . IR IR IR IRC CLKOUT IPIPE EXTENSION WORD USED INSTRUCTION START EXTENSION WORD USED INSTRUCTION START Figure 5-29. Instruction Pipeline Timing Diagram IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB (advance of IRA into IRB). Assertion for two clock cycles indicates that a new instruction has started (IRB ⇒ IRC and IRA ⇒ IRB transfers have occurred). Loading IRC always indicates that an instruction is beginning execution—the opcode is loaded into IRC by the transfer. In some cases, instructions using immediate addressing begin executing and initiate a second pipeline advance simultaneously at the same time. IPIPE will not be negated between the two indications, which implies the need for a state machine to track the state of IPIPE. The state machine can be resynchronized during periods of inactivity on the signal. 5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work normally during loop mode. IFETCH indicates all instruction fetches up through the point that data begins recirculating within the instruction pipeline. IPIPE continues to signal the start of instructions and the use of extension words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode. 5-88 MC68340 USER’S MANUAL MOTOROLA 5.7 INSTRUCTION EXECUTION TIMING This section describes the instruction execution timing of the CPU32. External clock cycles are used to provide accurate execution and operation timing guidelines, but not exact timing for every possible circumstance. This approach is used because exact execution time for an instruction or operation depends on concurrence of independently scheduled resources, on memory speeds, and on other variables. An assembly language programmer or compiler writer can use the information in this section to predict the performance of the CPU32. Additionally, timing for exception processing is included so that designers of multitasking or real-time systems can predict task-switch overhead, maximum interrupt latency, and similar timing parameters. Instruction timing is given in clock cycles to eliminate clock frequency dependency. 5.7.1 Resource Scheduling The CPU32 contains several independently scheduled resources. The organization of these resources within the CPU32 is shown in Figure 5-30. Some variation in instruction execution timing results from concurrent resource utilization. Because resource scheduling is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing. 5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or awaits completion of accesses necessary to continue microcode execution. The microsequencer supervises the bus controller, instruction execution, and internal processor operations such as calculation of EA and setting of condition codes. It also initiates instruction word prefetches after a change of flow and controls validation of instruction words in the instruction pipeline. 5.7.1.2 INSTRUCTION PIPELINE. The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties. Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before stage B empties are temporarily stored in this buffer. Instruction words (instruction operation words and all extension words) are decoded at stage B. Residual decoding and execution occur in stage C. Each pipeline stage has an associated status bit that shows whether the word in that stage was loaded with data from a bus cycle that terminated abnormally. 5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction prefetch controller, the write pending buffer, and the microbus controller. These three resources transact all reads, writes, and instruction prefetches required for instruction execution. MOTOROLA MC68340 USER’S MANUAL 5-89 The bus controller and microsequencer operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation or sets condition codes. The microsequencer can also request a bus cycle that the bus controller cannot perform immediately. When this happens, the bus cycle is queued, and the bus controller runs the cycle when the current cycle is complete. INSTRUCTION PIPELINE MICROSEQUENCER AND CONTROL STAGE B STAGE C CONTROL STORE CONTROL LOGIC EXECUTION UNIT PROGRAM COUNTER SECTION DATA SECTION WRITE-PENDING BUFFER DATA BUS PREFETCH CONTROLLER ADDRESS BUS MICROBUS CONTROLLER BUS CONTROL SIGNALS Figure 5-30. Block Diagram of Independent Resources 5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address. Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated, either through instruction completion or through use of extension words. Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer. Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow (e.g., a jump or branch instruction) is anticipated. In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each time a change occurs, the instruction pipeline must be flushed and refilled from the new instruction stream. If instruction prefetches, rather than operand accesses, were given 5-90 MC68340 USER’S MANUAL MOTOROLA priority, many instruction words would be flushed unused, and necessary operand cycles would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction and when there is room in the pipeline for the prefetch. 5.7.1.3.2 Write Pending Buffer. The CPU32 incorporates a single-operand write pending buffer. The buffer permits the microsequencer to continue execution after a request for a write cycle is queued in the bus controller. The time needed for a write at the end of an instruction can overlap the head cycle time for the following instruction, thus reducing overall execution time. Interlocks prevent the microsequencer from overwriting the buffer. 5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by the microsequencer. Operand accesses always have priority over instruction prefetches. Word and byte operands are accessed in a single CPU-initiated bus cycle, although the external bus interface may be required to initiate a second cycle when a word operand is sent to a byte-sized external port. Long operands are accessed in two bus cycles, most significant word first. The instruction pipeline is capable of recognizing instructions that cause a change of flow. It informs the bus controller when a change of flow is imminent, and the bus controller refrains from starting prefetches that would be discarded due to the change of flow. 5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock cycles, that an instruction executes concurrently with the previous instruction. As shown in Figure 5-31, portions of instructions A and B execute simultaneously, reducing total execution time. Because portions of instructions B and C also overlap, overall execution time for all three instructions is also reduced. Each instruction contributes to the total overlap time. The portion of execution time at the end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A. The portion of execution time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B. The total overlap time between instructions A and B is the smaller tail of A and the head of B. INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP OVERLAP Figure 5-31. Simultaneous Instruction Execution MOTOROLA MC68340 USER’S MANUAL 5-91 The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-32. The overlap time is attributed to the execution time of the completing instruction. The following equation shows the method for calculating the overlap time: Overlap = min (Tail N, HeadN+1 ) INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP PERIOD OVERLAP PERIOD (ABSORBED BY INSTRUCTION A) (ABSORBED BY INSTRUCTION B) Figure 5-32. Attributed Instruction Times 5.7.1.5 EFFECTS OF WAIT STATES. The CPU32 access time for on-chip peripherals is two clocks. While two-clock external accesses are possible when the bus is operated in a synchronous mode, a typical external memory speed is three or more clocks. All instruction times listed in this section are for word access only (unless an explicit exception is given), and are based on the assumption that both instruction fetches and operand cycles are to a two-clock memory. Any time a long access is made, time for the additional bus cycle(s) must be added to the overall execution time. Wait states due to slow external memory must be added to the access time for each bus cycle. A typical application has a mixture of bus speeds—program execution from an off-chip ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and accesses to external peripherals with speeds ranging from moderate to very slow. To arrive at an accurate instruction time calculation, each bus access must be individually considered. Many instructions have a head cycle count, which can overlap the cycles of an operand fetch to slower memory started by a previous instruction. In these cases, an increase in access time has no effect on the total execution time of the pair of instructions. To trace instruction execution time by monitoring the external bus, note that the order of operand accesses for a particular instruction sequence is always the same provided bus speed is unchanged and the interleaving of instruction prefetches with operands within each sequence is identical. 5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time for an instruction depends on the amount of overlap with previous and subsequent instructions. To calculate an instruction time estimate, the entire code sequence must be 5-92 MC68340 USER’S MANUAL MOTOROLA analyzed. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for overlap. The formula for this calculation is as follows: C1 − min (T1 , H2 ) + C 2 − min (T2 , H3 ) + C 3 − min (T3 , H4 ) + .. .. . where: CN is the number of cycles listed for instruction N TN is the tail time for instruction N HN is the head time for instruction N min (T N, HM) is the minimum of parameters T N and HM The number of cycles for the instruction (CN) can include one or two EA calculations in addition to the raw number in the cycles column. In these cases, calculate overall instruction time as if it were for multiple instructions, using the following equation: 〈CEA〉 − min (T EA, HOP) + C OP where: 〈CEA〉 is the instruction’s EA time COP is the instruction’s operation time TEA is the EA’s tail time HOP is the instruction operation’s head time min (T N, HM) is the minimum of parameters T N and HM The overall head for the instruction is the head for the EA, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation for execution time becomes: COP1 − min (TOP1 , HEA2 ) + 〈CEA〉2 − min (TEA2 , HOP2 ) + C OP2 − min (TOP2 , HEA3 ) + . . . Every instruction must prefetch to replace itself in the instruction pipe. Usually, these prefetches occur during or after an instruction. A prefetch is permitted to begin in the first clock of any indexed EA mode operation. Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used. If the bus is being used, then the prefetch occurs at the next available time when the bus would otherwise be idle. 5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle period can be used to prefetch an additional word on the new instruction path. MOTOROLA MC68340 USER’S MANUAL 5-93 Because of the stipulation that each instruction must prefetch to replace itself, the concept of negative tails has been introduced to account for these free clocks on the bus. On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential extra prefetch. The cycle times of the microsequencer and bus are matched, and no additional benefit or penalty is obtained. In the instruction execution time equations, a zero should be used instead of a negative number. Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing the length of prefetch bus cycles directly affects the cycle count and tail values found in the tables. In the following equations, negative tail values are used to negate the effects of a slower bus. The equations are generalized, however, so that they may be used on any speed bus with any tail value. NEW_TAIL = OLD_TAIL + (NEW_CLOCK – 2) IF ((NEW_CLOCK – 4) >0) THEN NEW_CYCLE = OLD_CYCLE + (NEW_CLOCK -2) + (NEW_CLOCK – 4) ELSE NEW_CYCLE = OLD_CYCLE + (NEW _CLOCK – 2) where: NEW_TAIL/NEW_CYCLE OLD_TAIL/OLD_CYCLE NEW_CLOCK is the adjusted tail/cycle at the slower speed is the value listed in the instruction timing tables is the number of clocks per cycle at the slower speed Note that many instructions listed as having negative tails are change-of-flow instructions and that the bus speed used in the calculation is that of the new instruction stream. 5.7.2 Instruction Stream Timing Examples The following programming examples provide a detailed examination of timing effects. In all examples, the memory access is from external synchronous memory, the bus is idle, and the instruction pipeline is full at the start. 5.7.2.1 TIMING EXAMPLE 1—EXECUTION OVERLAP. Figure 5-33 illustrates execution overlap caused by the bus controller's completion of bus cycles while the sequencer is calculating the next EA. One clock is saved between instructions since that is the minimum time of the individual head and tail numbers. Instructions MOVE.W ADDQ.W CLR.W 5-94 A1, (A0) + #1, (A0) $30 (A1) MC68340 USER’S MANUAL MOTOROLA 1 2 3 4 5 6 7 8 9 0 1 2 4 3 5 6 7 8 CLOCK 1 PREFETCH BUS CONTROLLER WRITE FOR 1 INSTRUCTION CONTROLLER MOVE A1,(AO)+ EXECUTION TIME READ FOR 2 EA FETCH ADDQ 2 PREFETCH WRITE FOR 2 ADDQ TO MOVE.W A1,(AO)+ 3 PREFETCH EA CALC CLR 3 PREFETCH WRITE FOR 3 CLR CLR.W $30(A1) ADDQ.W #1,(AO) Figure 5-33. Example 1—Instruction Stream 5.7.2.2 TIMING EXAMPLE 2—BRANCH INSTRUCTIONS. Example 2 shows what happens when a branch instruction is executed for both the taken and not-taken cases. (see Figures 5-34 and 5-35). The instruction stream is for a simple limit check with the variable already in a data register. Instructions MOVEQ CMP.L BLE.B MOVE.L 1 2 3 4 5 6 #7, D1 D1, D0 NEXT D1, (A0) 7 8 9 0 1 2 4 3 CLOCK BUS CONTROLLER 1 PREFETCH 2 PREFETCH INSTRUCTION CONTROLLER MOVEQ CMP EXECUTION TIME MOVEQ #7,D1 CMP D1,D0 OFFSET CALC PREFETCH PREFETCH TAKEN TAKEN PREFETCH TAKEN WRITE FOR 3 NEXT INST. BLE.B NOT TAKEN Figure 5-34. Example 2—Branch Taken MOTOROLA MC68340 USER’S MANUAL 5-95 1 2 3 4 5 6 7 8 9 0 1 2 4 3 CLOCK BUS CONTROLLER 1 PREFETCH 2 PREFETCH INSTRUCTION CONTROLLER MOVEQ CMP EXECUTION TIME MOVEQ #7,D1 CMP D1,D0 OFFSET CALC 3 PREFETCH 4 PREFETCH NOT TAKEN MOVE TO (A0) BLE.B NOT TAKEN WRITE FOR 4 WRITE FOR 4 MOVE.L D1,(AO) Figure 5-35. Example 2—Branch Not Taken 5.7.2.3 TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows how to use negative tail figures for branches and other change-of-flow instructions. In this example, bus speed is assumed to be four clocks per access. Instruction three is at the branch destination. Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus; on a slower bus, there is no extra time for the third word. Instructions MOVEQ BRA.W MOVE.L 1 2 3 4 5 6 7 #7, D1 FARAWAY D1, D0 8 9 0 1 2 3 4 5 6 7 8 9 CLOCK BUS CONTROLLER INSTRUCTION CONTROLLER EXECUTION TIME BRANCH OFFSET MOVEQ MOVEQ #7,D1 FETCH MOVE.L OFFSET CALC TAKEN FETCH NEXT INSTRUCTION TAKEN BRA.W FARAWAY PREFETCH MOVE TO D0 MOVE.L D1,D0 Figure 5-36. Example 3—Branch Negative Tail 5-96 MC68340 USER’S MANUAL MOTOROLA Example 3 illustrates three different aspects of instruction time calculation: 1. The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself. 2. The negative tail allows execution to begin sooner than a three-word pipeline would allow. 3. There is a one-clock delay due to late arrival of the displacement at the CPU. Only changes of flow require negative tail calculation, but the concept can be generalized to any instruction—only two words are required to be in the pipeline, but up to three words may be present. When there is an opportunity for an extra prefetch, it is made. A prefetch to replace an instruction can begin ahead of the instruction, resulting in a faster processor. 5.7.3 Instruction Timing Tables The following assumptions apply to the times shown in the subsequent tables. —A 16-bit data bus is used for all memory accesses. —Memory access times are based on two clock bus cycles with no wait states. —The instruction pipeline is full at the beginning of the instruction and is refilled by the end of the instruction. Three values are listed for each instruction and addressing mode: Head: The number of cycles available at the beginning of an instruction to complete a previous instruction write or to perform a prefetch. Tail: The number of cycles an instruction uses to complete a write. Cycles: Four numbers per entry, three contained in parentheses. The outer number is the minimum number of cycles required for the instruction to complete. Numbers within the parentheses represent the number of bus accesses performed by the instruction. The first number is the number of operand read accesses performed by the instruction. The second number is the number of instruction fetches performed by the instruction, including all prefetches that keep the instruction and the instruction pipeline filled. The third number is the number of write accesses performed by the instruction. As an example, consider an ADD.L (12, A3, D7.W ∗ 4), D2 instruction. Paragraph 5.7.3.5 Arithmetic/Logic Instructions shows that the instruction has a head = 0, a tail = 0, and cycles = 2 (0/1/0). However, in indexed, address register indirect addressing mode, additional time is required to fetch the EA. Paragraph 5.7.3.1 Fetch Effective Address gives addressing mode data. For (d 8 , An, Xn.Sz ∗ Scale), head = 4, tail = 2, cycles = 8 (2/1/0). Because this example is for a long access and the fetch EA table lists data for word accesses, add two clocks to the tail and to the number of cycles (“X” in table notation) to obtain head = 4, tail = 4, cycles = 10 (2/1/0). Assuming that no trailing write exists from the previous instruction, EA calculation requires six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of MOTOROLA MC68340 USER’S MANUAL 5-97 four. If there is no time in the head to perform a prefetch due to a previous trailing write, then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail. 8 (2 /1 /0) TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES The total number of clocks for bus activity is as follows: (2 Reads × 2 Clocks/Read) + (1 Instruction Access × 2 Clocks/Access) + (0 Writes × 2 Clocks/Write) = 6 Clocks of Bus Activity The number of internal clocks (not overlapped by bus activity) is as follows: 10 Clocks Total − 6 Clocks Bus Activity = 4 Internal Clocks Memory read requires two bus cycles at two clocks each. This read time, implied in the tail figure for the EA, cannot be overlapped with the instruction because the instruction has a head of zero. An additional two clocks are required for the ADD instruction itself. The total is 6 + 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an appropriate number of clocks to each memory access. The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example of overlapped execution. The MOVE instruction has a head of zero and a tail of four because it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero and a tail of zero, and a total execution of 8 rather than 12 clocks. General observations regarding calculation of execution time are as follows: • Any time the number of bus cycles is listed as "X", substitute a value of one for byte and word cycles and a value of two for long cycles. For long bus cycles, usually add a value of two to the tail. • The time calculated for an instruction on a three-clock (or longer) bus is usually longer than the actual execution time. All times shown are for two-clock bus cycles. • If the previous instruction has a negative tail, then a prefetch for the current instruction can begin during the execution of that previous instruction. • Certain instructions requiring an immediate extension word (immediate word EA, absolute word EA, address register indirect with displacement EA, conditional branches with word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements. 5-98 MC68340 USER’S MANUAL MOTOROLA 5.7.3.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock periods needed for the processor to calculate and fetch the specified EA. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Instruction Head Tail Cycles Notes Dn – – 0(0/0/0) – An – – 0(0/0/0) – (An) 1 1 3(X/0/0) 1 (An) + 1 1 3(X/0/0) 1 −(An) 2 2 4(X/0/0) 1 (d 16 ,An) or (d16 ,PC) 1 3 5(X/1/0) 1,3 (xxx).W 1 3 5(X/1/0) 1 (xxx).L 1 5 7(X/2/0) 1 #〈data〉.B 1 1 3(0/1/0) 1 #〈data〉.W 1 1 3(0/1/0) 1 #〈data〉.L 1 3 5(0/2/0) 1 (d 8,An,Xn.Sz × Sc) or (d8,PC,Xn.Sz × Sc) 4 2 8(X/1/0) 1,2,3,4 (0) (All Suppressed) 2 2 6(X/1/0) 1,4 (d 16 ) 1 3 7(X/2/0) 1,4 (d 32 ) 1 5 9(X/3/0) 1,4 (An) 1 1 5(X/1/0) 1,2,4 (Xm.Sz × Sc) 4 2 8(X/1/0) 1,2,4 (An,Xm.Sz × Sc) 4 2 8(X/1/0) 1,2,3,4 (d 16 ,An) or (d16 ,PC) 1 3 7(X/2/0) 1,3,4 (d 32 ,An) or (d32 ,PC) 1 5 9(X/3/0) 1,3,4 (d 16 ,An,Xm) or (d16 ,PC,Xm) 2 2 8(X/2/0) 1,3,4 (d 32 ,An,Xm) or (d32 ,PC,Xm) 1 3 9(X/3/0) 1,3,4 (d 16 ,An,Xm.Sz × Sc) or (d16 ,PC,Xm.Sz × Sc) 2 2 8(X/2/0) 1,2,3,4 (d 32 ,An,Xm.Sz × Sc) or (d32 ,PC,Xm.Sz × Sc) 1 3 9(X/3/0) 1,2,3,4 X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. The read of the EA and replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. MOTOROLA MC68340 USER’S MANUAL 5-99 5.7.3.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA. The timing is equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by the amount of time the read would occupy. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Head Tail Cycles Notes Dn Instruction – – 0(0/0/0) – An – – 0(0/0/0) – (An) 1 0 2(0/0/0) – (An) + 1 0 2(0/0/0) – −(An) 2 0 2(0/0/0) – (d 16 ,An) or (d16 ,PC) 1 1 3(0/1/0) 1,3 (xxx).W 1 1 3(0/1/0) 1 (xxx).L 1 3 5(0/2/0) 1 (d 8,An,Xn.Sz × Sc) or (d 8,PC,Xn.Sz × Sc) 4 0 6(0/1/0) 2,3,4 (0) (All Suppressed) 2 0 4(0/1/0) 4 (d 16 ) 1 1 5(0/2/0) 1,4 (d 32 ) 1 3 7(0/3/0) 1,4 (An) 1 0 4(0/1/0) 4 (Xm.Sz × Sc) 4 0 6(0/1/0) 2,4 (An,Xm.Sz × Sc) 4 0 6(0/1/0) 2,4 (d 16 ,An) or (d16 ,PC) 1 1 5(0/2/0) 1,3,4 (d 32 ,An) or (d32 ,PC) 1 3 7(0/3/0) 1,3,4 (d 16 ,An,Xm) or (d16 ,PC,Xm) 2 0 6(0/2/0) 3,4 (d 32 ,An,Xm) or (d32 ,PC,Xm) 1 1 7(0/3/0) 1,3,4 (d 16 ,An,Xm.Sz × Sc) or (d16 ,PC,Xm.Sz × Sc) 2 0 6(0/2/0) 2,3,4 (d 32 ,An,Xm.Sz × Sc) or (d32 ,PC,Xm.Sz × Sc) 1 1 7(0/3/0) 1,2,3,4 X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. NOTES: 1. Replacement fetches overlap the head of the operation by the amount specified in the tail. 2. Size and scale of the index register do not affect execution time. 3. The PC may be substituted for the base address register An. 4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts. 5-100 MC68340 USER’S MANUAL MOTOROLA 5.7.3.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate that portion of the instruction time. Destination EAs are divided by their formats (see 5.3.4.4 Effective Address Encoding Summary). The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. When using this table, begin at the top and move downward. Use the first entry that matches both source and destination addressing modes. Head Tail Cycles MOVE Rn, Rn Instruction 0 0 2(0/1/0) MOVE 〈FEA〉, Rn 0 0 2(0/1/0) MOVE Rn, (Am) 0 2 4(0/1/x) MOVE Rn, (Am) + 1 1 5(0/1/x) MOVE Rn, −(Am) 2 2 6(0/1/x) MOVE Rn, 〈CEA 〉 1 3 5(0/1/x) MOVE 〈FEA〉, (An) 2 2 6(0/1/x) MOVE 〈FEA〉, (An) + 2 2 6(0/1/x) MOVE 〈FEA〉, −(An) 2 2 6(0/1/x) MOVE #, 〈CEA〉 2 2 6(0/1/x) ∗ MOVE 〈CEA〉, 〈FEA 〉 2 2 6(0/1/x) X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles. ∗ = An # fetch EA time must be added for this instruction: 〈 FEA 〉 +〈CEA〉 + 〈 OPER〉 NOTE: For instructions not explicitly listed, use the MOVE 〈CEA 〉, 〈FEA〉 entry. The source EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA table, even though the bus cycle is for the source EA. 5.7.3.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate, and perform the special-purpose MOVE operation on control registers or a specified EA. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. MOTOROLA MC68340 USER’S MANUAL 5-101 Instruction Head Tail Cycles EXG Rn, Rm 2 0 4(0/1/0) MOVEC Cr, Rn 10 0 14(0/2/0) MOVEC Rn, Cr 12 0 14-16(0/1/0) MOVE CCR, Dn 2 0 4(0/1/0) MOVE CCR, 〈CEA 〉 0 2 4(0/1/1) MOVE Dn, CCR 2 0 4(0/1/0) MOVE 〈FEA〉, CCR 0 0 4(0/1/0) MOVE SR, Dn 2 0 4(0/1/0) MOVE SR, 〈CEA 〉 0 2 4(0/1/1) MOVE Dn, SR 4 −2 10(0/3/0) MOVE 〈FEA〉, SR 0 −2 10(0/3/0) MOVEM.W 〈CEA〉, RL 1 0 8 + n × 4 (n + 1, 2, 0) ∗ MOVEM.W RL, 〈CEA 〉 1 0 8 + n × 4 (0, 2, n) ∗ MOVEM.L 〈CEA〉, RL 1 0 12 + n × 4(2n + 2, 2, 0) MOVEM.L RL, 〈CEA 〉 1 2 10 + n × 4 (0, 2, 2n) MOVEP.W Dn, (d16 , An) 2 0 10(0/2/2) MOVEP.W (d 16 , An), Dn 1 2 11(2/2/0) MOVEP.L Dn, (d16 , An) 2 0 14(0/2/4) MOVEP.L (d 16 , An), Dn 1 2 19(4/2/0) MOVES (Save) 〈CEA〉, Rn 1 1 3(0/1/0) MOVES (Op) 〈CEA〉, Rn 7 1 11(X/1/0) MOVES (Save) Rn, 〈CEA 〉 1 1 3(0/1/0) MOVES (Op) Rn, 〈CEA 〉 9 2 12(0/1/X) MOVE USP, An 0 0 2(0/1/0) MOVE An, USP 0 0 2(0/1/0) SWAP Dn 4 0 6(0/1/0) X = There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles. ∗ = Each bus cycle may take up to four clocks without increasing total execution time. Cr = Control registers USP, VBR, SFC, and DFC n = Number of registers to transfer RL = Register List < = Maximum time (certain data or mode combinations may execute faster). NOTE: The MOVES instruction has an additional save step which other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times, and combine in the order listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation. 5.7.3.5 ARITHMETIC/LOGIC INSTRUCTIONS. The arithmetic/logic instruction table indicates the number of clock periods needed to perform the specified arithmetic/logical instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. 5-102 MC68340 USER’S MANUAL MOTOROLA The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes. Head Tail Cycles ADD(A) Instruction Rn, Rm 0 0 2(0/1/0) ADD(A) 〈FEA〉, Rn 0 0 2(0/1/0) ADD Dn, 〈FEA 〉 0 3 5(0/1/x) AND Dn, Dm 0 0 2(0/1/0) AND 〈FEA〉, Dn 0 0 2(0/1/0) AND Dn, 〈FEA 〉 0 3 5(0/1/x) EOR Dn, Dm 0 0 2(0/1/0) EOR Dn, 〈FEA 〉 0 3 5(0/1/x) OR Dn, Dm 0 0 2(0/1/0) OR 〈FEA〉, Dn 0 0 2(0/1/0) OR Dn, 〈FEA 〉 0 3 5(0/1/x) SUB(A) Rn, Rm 0 0 2(0/1/0) SUB(A) 〈FEA〉, Rn 0 0 2(0/1/0) SUB Dn, 〈FEA 〉 0 3 5(0/1/x) CMP(A) Rn, Rm 0 0 2(0/1/0) CMP(A) 〈FEA〉, Rn 0 0 2(0/1/0) CMP2 (Save) * 〈FEA〉, Rn 1 1 3(0/1/0) CMP2 (Op) 〈FEA〉, Rn 2 0 16-18(X/1/0) MUL(su).W 〈FEA〉, Dn 0 0 26(0/1/0) MUL(su).L (Save) * 〈FEA〉, Dn 1 1 3(0/1/0) MUL(su).L (Op) 〈FEA〉, Dl 2 0 46-52(0/1/0) MUL(su).L (Op) 〈FEA〉, Dn:Dl 2 0 46(0/1/0) DIVU.W 〈FEA〉, Dn 0 0 32(0/1/0) DIVS.W 〈FEA〉, Dn 0 0 42(0/1/0) DIVU.L (Save)* 〈FEA〉, Dn 1 1 3(0/1/0) DIVU.L (Op) 〈FEA〉, Dn 2 0