S-1323B1JPF-N9PTFU

S-1323 Series www.ablic.com www.ablicinc.com HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 © ABLIC Inc., 2002-2015 The S-1323 Series is a positive voltage regulator with a low dropout voltage, high-accuracy output voltage, and low current consumption developed based on CMOS technology. A built-in low on-resistance transistor provides a low dropout voltage and large output current, and a built-in overcurrent protection circuit prevents the load current from exceeding the current capacity of the output transistor. An ON/OFF circuit ensures a long battery life. Compared with the voltage regulators using the conventional CMOS technology, a larger variety of capacitors are available, including small ceramic capacitors. Small SNT-4A and SC-82AB packages realize high-density mounting.  Features  Output voltage:  Output voltage accuracy:  Current consumption:  Output current:  Input and output capacitors:  Ripple rejection:  Built-in overcurrent protection circuit:  Built-in ON/OFF circuit:  Operation temperature range:  Lead-free, Sn 100%, halogen-free*2 1.5 V to 5.5 V, selectable in 0.1 V step 1.0% During operation: 70 A typ., 90 A max. During power-off: 0.1 A typ., 1.0 A max. Possible to output 150 mA (VIN  VOUT(S)  1.0 V)*1 A ceramic capacitor of 1.0 F or more can be used. 70 dB typ. (f = 1.0 kHz) Limits overcurrent of output transistor. Ensures long battery life. Ta = 40°C to 85°C *1. Attention should be paid to the power dissipation of the package when the output current is large. *2. Refer to “ Product Name Structure” for details.  Applications  Constant-voltage power supply for battery-powered device  Constant-voltage power supply for personal communication device  Constant-voltage power supply for home electric appliance  Constant-voltage power supply for cellular phone  Packages  SNT-4A  SC-82AB 1 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Block Diagram *1 VIN VOUT Overcurrent protection circuit  ON/OFF circuit ON/OFF  Reference voltage circuit VSS *1. Parasitic diode Figure 1 2 Rev.5.1_02 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series  Product Name Structure Users can select the product type, output voltage, and package type for the S-1323 Series. Refer to “1. Product name” regarding the contents of product name, “2. Packages” regarding the package drawings and “3. Product name list” regarding details of product name. 1. Product name 1. 1 SNT-4A S-1323 x xx PF - xxx TF U Environmental code U: Lead-free (Sn 100%), halogen-free IC direction in tape specifications Product code *1 *2 Package code PF: SNT-4A Output voltage 15 to 55 (e.g. when the output voltage is 1.5 V, it is expressed as 15.) *3 Product type A: ON/OFF pin negative logic B: ON/OFF pin positive logic 1. 2 SC-82AB S-1323 x xx NB - xxx TF x Environmental code U: Lead-free (Sn 100%), halogen-free G: Lead-free (for details, please contact our sales office) IC direction in tape specifications *1 *2 Product code Package code NB: SC-82AB Output voltage 15 to 55 (e.g. when the output voltage is 1.5 V, it is expressed as 15.) Product type*3 A: ON/OFF pin negative logic B: ON/OFF pin positive logic *1. Refer to the tape drawing. *2. Refer to the product name list. *3. Refer to “3. ON/OFF Pin” in “ Operation”. 2. Packages Package Name SNT-4A Package PF004-A-P-SD SC-82AB NP004-A-P-SD Drawing Code Tape Reel PF004-A-C-SD PF004-A-R-SD NP004-A-C-SD NP004-A-R-SD NP004-A-C-S1 Land PF004-A-L-SD － 3 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series 3. Product name list Output Voltage 1.5V±1.0% 1.6V±1.0% 1.7V±1.0% 1.8V±1.0% 1.85V±1.0% 1.9V±1.0% 2.0V±1.0% 2.1V±1.0% 2.2V±1.0% 2.3V±1.0% 2.4V±1.0% 2.5V±1.0% 2.6V±1.0% 2.7V±1.0% 2.8V±1.0% 2.85V±1.0% 2.9V±1.0% 3.0V±1.0% 3.1V±1.0% 3.2V±1.0% 3.3V±1.0% 3.4V±1.0% 3.5V±1.0% 3.6V±1.0% 3.7V±1.0% 3.8V±1.0% 3.9V±1.0% 4.0V±1.0% 4.1V±1.0% 4.2V±1.0% 4.3V±1.0% 4.4V±1.0% 4.5V±1.0% 4.6V±1.0% 4.7V±1.0% 4.8V±1.0% 4.9V±1.0% 5.0V±1.0% 5.1V±1.0% 5.2V±1.0% 5.3V±1.0% 5.4V±1.0% 5.5V±1.0% Table 1 SNT-4A S-1323B15PF-N8ATFU S-1323B16PF-N8BTFU S-1323B17PF-N8CTFU S-1323B18PF-N8DTFU S-1323B1JPF-N9PTFU S-1323B19PF-N8ETFU S-1323B20PF-N8FTFU S-1323B21PF-N8GTFU S-1323B22PF-N8HTFU S-1323B23PF-N8ITFU S-1323B24PF-N8JTFU S-1323B25PF-N8KTFU S-1323B26PF-N8LTFU S-1323B27PF-N8MTFU S-1323B28PF-N8NTFU S-1323B2JPF-N9QTFU S-1323B29PF-N8OTFU S-1323B30PF-N8PTFU S-1323B31PF-N8QTFU S-1323B32PF-N8RTFU S-1323B33PF-N8STFU S-1323B34PF-N8TTFU S-1323B35PF-N8UTFU S-1323B36PF-N8VTFU S-1323B37PF-N8WTFU S-1323B38PF-N8XTFU S-1323B39PF-N8YTFU S-1323B40PF-N8ZTFU S-1323B41PF-N9ATFU S-1323B42PF-N9BTFU S-1323B43PF-N9CTFU S-1323B44PF-N9DTFU S-1323B45PF-N9ETFU S-1323B46PF-N9FTFU S-1323B47PF-N9GTFU S-1323B48PF-N9HTFU S-1323B49PF-N9ITFU S-1323B50PF-N9JTFU S-1323B51PF-N9KTFU S-1323B52PF-N9LTFU S-1323B53PF-N9MTFU S-1323B54PF-N9NTFU S-1323B55PF-N9OTFU SC-82AB S-1323B15NB-N8ATFx S-1323B16NB-N8BTFx S-1323B17NB-N8CTFx S-1323B18NB-N8DTFx  S-1323B19NB-N8ETFx S-1323B20NB-N8FTFx S-1323B21NB-N8GTFx S-1323B22NB-N8HTFx S-1323B23NB-N8ITFx S-1323B24NB-N8JTFx S-1323B25NB-N8KTFx S-1323B26NB-N8LTFx S-1323B27NB-N8MTFx S-1323B28NB-N8NTFx  S-1323B29NB-N8OTFx S-1323B30NB-N8PTFx S-1323B31NB-N8QTFx S-1323B32NB-N8RTFx S-1323B33NB-N8STFx S-1323B34NB-N8TTFx S-1323B35NB-N8UTFx S-1323B36NB-N8VTFx S-1323B37NB-N8WTFx S-1323B38NB-N8XTFx S-1323B39NB-N8YTFx S-1323B40NB-N8ZTFx S-1323B41NB-N9ATFx S-1323B42NB-N9BTFx S-1323B43NB-N9CTFx S-1323B44NB-N9DTFx S-1323B45NB-N9ETFx S-1323B46NB-N9FTFx S-1323B47NB-N9GTFx S-1323B48NB-N9HTFx S-1323B49NB-N9ITFx S-1323B50NB-N9JTFx S-1323B51NB-N9KTFx S-1323B52NB-N9LTFx S-1323B53NB-N9MTFx S-1323B54NB-N9NTFx S-1323B55NB-N9OTFx Remark 1. Please contact our sales office for type A products. 2. x: G or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products. 4 Rev.5.1_02 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series  Pin Configurations Table 2 SNT-4A Top view 1 4 2 3 Pin No. 1 2 3 4 Symbol VOUT VIN ON/OFF VSS Description Output voltage pin Input voltage pin ON/OFF pin GND pin Figure 2 Table 3 SC-82AB Top view 4 1 3 Pin No. 1 2 3 4 Symbol VOUT VSS ON/OFF VIN Description Output voltage pin GND pin ON/OFF pin Input voltage pin 2 Figure 3 5 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Absolute Maximum Ratings Table 4 Item Symbol VIN VON/OFF VOUT Input voltage Output voltage SNT-4A Power dissipation SC-82AB PD (Ta  25C unless otherwise specified) Absolute Maximum Rating Unit V VSS0.3  VSS7 V VSS0.3  VIN0.3 V VSS0.3  VIN0.3 mW 300*1 200 (When not mounted on board) mW *1 mW 400 °C 40  85 °C 40  125 Topr Operation ambient temperature Tstg Storage temperature *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. (2) When not mounted on board 500 Power Dissipation (PD) (mW) Power Dissipation (PD) (mW) (1) When mounted on board 500 400 SC-82AB 300 200 SNT-4A 100 0 0 50 100 150 Ambient Temperature (Ta) (C) 400 300 SC-82AB 200 100 0 0 50 150 Ambient Temperature (Ta) (C) Figure 4 Power Dissipation of Package 6 100 Rev.5.1_02 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series  Electrical Characteristics Table 5 (Ta  25C unless otherwise specified) Item Symbol Conditions Unit Test Circuit V 1 mA V 3 1 0.1 %/V 1 20 40 mV 1  100  ppm/ C 1  70 90 A 2  0.1 1.0 A 2 2.0  6.5 V  Min. Typ. Max. VOUT(S)  0.99 150*5  VOUT(S)  0.50 VOUT(S)  1.01  0.65  0.02  Output voltage*1 VOUT(E) VIN  VOUT(S)  1.0 V, IOUT  30 mA Output current*2 Dropout voltage*3 IOUT Vdrop VIN VIN  VOUT(S)  1.0 V IOUT  150 mA VOUT(S)  0.5 V  VIN  6.5 V, IOUT  30 mA VIN  VOUT(S)  1.0 V, 1.0 mA  IOUT  150 mA VIN  VOUT(S)  1.0 V, IOUT  30 mA, 40C  Ta  85C VIN  VOUT(S)  1.0 V, ON/OFF pin  ON, no load VIN  VOUT(S)  1.0 V, ON/OFF pin  OFF, no load  VSH VIN  VOUT(S)  1.0 V, RL  1.0 k 1.5   V 4 VSL VIN  VOUT(S)  1.0 V, RL  1.0 k   0.3 V 4 ISH VIN  6.5 V, VON/OFF  6.5 V 0.1  0.1 A 4 ISL VIN  6.5 V, VON/OFF = 0 V 0.1  0.1 A 4  70  dB 5  250  mA 3 Line regulation VOUT1 VIN VOUT Load regulation VOUT2 Output voltage *4 temperature coefficient Current consumption during operation Current consumption during power-off Input voltage ON/OFF pin input voltage “H” ON/OFF pin input voltage “L” ON/OFF pin input current “H” ON/OFF pin input current “L” VOUT Ta  VOUT Ripple rejection Short-circuit current ISS1 ISS2 RR Ishort VIN  VOUT(S)  1.0 V, f  1.0 kHz, Vrip  0.5 Vrms, IOUT  30 mA VIN  VOUT(S)  1.0 V, ON/OFF pin  ON, VOUT  0 V *1. VOUT(S): Set output voltage VOUT(E): Actual output voltage Output voltage when fixing IOUT( 30 mA) and inputting VOUT(S)  1.0 V *2. The output current at which the output voltage becomes 95% of VOUT(E) after gradually increasing the output current. *3. Vdrop  VIN1  (VOUT3  0.98) VOUT3 is the output voltage when VIN  VOUT(S)  1.0 V and IOUT  150 mA. VIN1 is the input voltage at which the output voltage becomes 98% of VOUT3 after gradually decreasing the input voltage. *4. A change in the temperature of the output voltage [mV/°C] is calculated using the following equation. VOUT mV/ C*1  VOUT(S)V *2  VOUT ppm/ C*3  1000 Ta Ta  VOUT *1. Change in temperature of output voltage *2. Set output voltage *3. Output voltage temperature coefficient *5. The output current can be at least this value. Due to restrictions on the package power dissipation, this value may not be satisfied. Attention should be paid to the power dissipation of the package when the output current is large. This specification is guaranteed by design. 7 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Test Circuits 1. + VOUT VIN A + V ON/OFF VSS Set to ON Figure 5 2.  A VIN ON/OFF VOUT VSS Set to VIN or GND Figure 6 3. VIN VOUT ON/OFF  A V VSS  Set to ON Figure 7 4. VIN  VOUT  A ON/OFF VSS V RL Figure 8 5. VIN VOUT  ON/OFF VSS Set to ON Figure 9 8 V RL Rev.5.1_02 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series  Standard Circuit Output Input VIN CIN VOUT ON/OFF VSS *1 Single GND *2 CL GND *1. CIN is a capacitor for stabilizing the input. *2. A ceramic capacitor of 1.0 F or more can be used in CL. Figure 10 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant.  Condition of Application Input capacitor (CIN): Output capacitor (CL): ESR of output capacitor: 1.0 F or more 1.0 F or more 10  or less Caution Generally a series regulator may cause oscillation, depending on the selection of external parts. Check that no oscillation occurs with the application using the above capacitor. 9 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Explanation of Terms 1. Low dropout voltage regulator This voltage regulator has the low dropout voltage due to its built-in low on-resistance transistor. 2. Low ESR A capacitor whose ESR (Equivalent Series Resistance) is low. The S-1323 Series enables use of a low ESR capacitor, such as a ceramic capacitor, for the output-side capacitor CL. A capacitor whose ESR is 10  or less can be used. 3. Output voltage (VOUT) The accuracy of the output voltage is ensured at 1.0% under the specified conditions of fixed input voltage*1, fixed output current, and fixed temperature. *1. Differs depending the product. Caution 4. If the above conditions change, the output voltage value may vary and exceed the accuracy range of the output voltage. Refer to “ Electrical Characteristics” and “ Characteristics (Typical Data)” for details. VOUT1  VINVOUT  Line regulation  Indicates the dependency of the output voltage on the input voltage. That is, the values show how much the output voltage changes due to a change in the input voltage with the output current remaining unchanged. 5. Load regulation (VOUT2) Indicates the dependency of the output voltage on the output current. That is, the values show how much the output voltage changes due to a change in the output current with the input voltage remaining unchanged. 6. Dropout voltage (Vdrop) Indicates the difference between input voltage (VIN1) and the output voltage when; decreasing input voltage (VIN) gradually until the output voltage has dropped out to the value of 98% of output voltage (VOUT3), which is at VIN = VOUT(S)  1.0 V. Vdrop  VIN1  (VOUT3  0.98) 10 Rev.5.1_02 7. HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series VOUT  Ta  VOUT  Output voltage temperature coefficient  The shaded area in Figure 11 is the range where VOUT varies in the operation temperature range when the output voltage temperature coefficient is 100 ppm/C. Example of S-1323B28 typ. product VOUT [V] 0.28 mV/C VOUT(E)*1 0.28 mV/C 40 25 85 Ta [C] *1. VOUT(E) is the value of the output voltage measured at Ta = 25C. Figure 11 A change in the temperature of the output voltage [mV/°C] is calculated using the following equation. V VOUT [mV/°C]*1 = VOUT(S) [V]*2  Ta OUT [ppm/°C]*3  1000 Ta VOUT *1. Change in temperature of output voltage *2. Set output voltage *3. Output voltage temperature coefficient 11 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Operation 1. Basic operation Figure 12 shows the block diagram of the S-1323 Series. The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the constant output voltage which is not influenced by the input voltage and temperature change, to the output transistor. VIN *1 Current supply Error amplifier Vref VOUT  Rf  Vfb Reference voltage circuit Rs VSS *1. Parasitic diode Figure 2. 12 Output transistor In the S-1323 Series, a low on-resistance P-channel MOS FET is used as the output transistor. Be sure that VOUT does not exceed VIN  0.3 V to prevent the voltage regulator from being damaged due to reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT became higher than VIN. 12 Rev.5.1_02 3. HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series ON/OFF pin This pin starts and stops the regulator. When the ON/OFF pin is set to OFF level, the entire internal circuit stops operating, and the built-in P-channel MOS FET output transistor between the VIN pin and the VOUT pin is turned off, reducing current consumption significantly. The VOUT pin becomes the VSS level due to the internally divided resistance of several hundreds k between the VOUT pin and the VSS pin. The structure of the ON/OFF pin is as shown in Figure 13. Since the ON/OFF pin is neither pulled down nor pulled up internally, do not use it in the floating status. In addition, note that the current consumption increases if a voltage of 0.3 V to VIN – 0.3 V is applied to the ON/OFF pin. When not using the ON/OFF pin, connect it to the VSS pin in the product A type, and connect it to the VIN pin in B type. Table 6 Product Type ON/OFF Pin Internal Circuit VOUT Pin Voltage Current Consumption A “L”: ON Operate Set value ISS1 A “H”: OFF Stop VSS level ISS2 B “L”: OFF Stop VSS level ISS2 B “H”: ON Operate Set value ISS1 VIN ON/OFF VSS Figure 13  Selection of Output Capacitor (CL) The S-1323 Series requires an output capacitor between the VOUT pin and VSS pin for phase compensation. A ceramic capacitor with a capacitance of 1.0 F or more can be used. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 1.0 F or more, and the ESR must be 10  or less. The value of the output overshoot or undershoot transient response varies depending on the value of the output capacitor. When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device. 13 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Precautions  Wiring patterns for the VIN pin, the VOUT pin and GND should be designed so that the impedance is low. When mounting an output capacitor between the VOUT pin and the VSS pin (CL) and a capacitor for stabilizing the input between the VIN pin and the VSS pin (CIN), the distance from the capacitors to these pins should be as short as possible.  Note that generally the output voltage may increase when a series regulator is used at low load current (1.0 mA or less).  Generally a series regulator may cause oscillation, depending on the selection of external parts. The following conditions are recommended for the S-1323 Series. However, be sure to perform sufficient evaluation under the actual usage conditions for selection, including evaluation of temperature characteristics. Input capacitor (CIN): 1.0 F or more Output capacitor (CL): 1.0 F or more Equivalent series resistance (ESR): 10  or less  The voltage regulator may oscillate when the impedance of the power supply is high and the input capacitance is small or an input capacitor is not connected.  Overshoot may occur in the output voltage momentarily if the voltage is rapidly raised at power-on or when the power supply fluctuates. Sufficiently evaluate the output voltage at power-on with the actual device.  The application conditions for the input voltage, the output voltage, and the load current should not exceed the package power dissipation.  Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.  In determining the output current, attention should be paid to the output current value specified in Table 5 in " Electrical Characteristics" and footnote *5 of the table.  ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 14 Rev.5.1_02 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series  Characteristics (Typical Data) (1) Output Voltage vs. Output current (when load current increases) S-1323B15 (Ta  25°C) S-1323B30 (Ta  25°C) 2.0 2.5 V VIN  1.8 V 1.0 VOUT [V] VOUT [V] 1.5 6.5 V 2.0 V 0.5 0 0 100 200 300 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4.0 V VIN  3.3 V 0 400 6.5 V 3.5 V 100 IOUT [mA] 200 300 400 IOUT [mA] S-1323B50 (Ta  25°C) 6 5 VOUT [V] 4 6.5 V VIN  5.3 V 3 5.5 V 2 6.0 V 1 0 0 100 200 300 400 Remark In determining the output current, attention should be paid to the following. 1) The minimum output current value in Table 5 in " Electrical Characteristics" and footnote *5 2) The package power dissipation IOUT [mA] (2) Output voltage vs. Input voltage S-1323B30 (Ta  25°C) 1.60 3.10 1.55 3.05 VOUT [V] VOUT [V] S-1323B15 (Ta  25°C) 1.50 IOUT  1 mA 30 mA 50 mA 1.45 1.40 1.0 1.5 2.0 2.5 3.00 IOUT  1 mA 30 mA 50 mA 2.95 3.0 3.5 VIN [V] 2.90 2.5 3.0 3.5 4.0 4.5 5.0 VIN [V] S-1323B50 (Ta  25°C) 5.10 VOUT [V] 5.05 5.00 IOUT  1 mA 30 mA 50 mA 4.95 4.90 4.5 5.0 5.5 6.0 6.5 7.0 VIN [V] 15 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series (3) Dropout voltage vs. Output current  S-1323B15 S-1323B30  0.6 85°C 0.5 25°C 0.4 Vdrop [V] Vdrop [V] 0.5 –40°C 0.3 0.2 0.1 0  0.6 85°C 25°C 0.4 0.3 –40°C 0.2 0.1 0 50 100  0 200 150 0 50 IOUT [mA] 100 200 150   IOUT [mA] S-1323B50 0.5 Vdrop [V]   0.6 85°C 25°C 0.4 0.3 –40°C 0.2 0.1 0 0 50 100 IOUT [mA]  (4) 200 150   Output voltage vs. Ambient temperature S-1323B15 S-1323B30  1.55 3.05 1.50 3.00 1.45 1.40 –40 –20 0  20 40 60 80 5.10  VOUT [V] 5.05 5.00 4.95  16 0 20 40 Ta [C] –20 0 20 40 Ta [C] S-1323B50 –20 2.95 2.90 –40 100 Ta [C] 4.90 –40  3.10 VOUT [V] VOUT [V] 1.60 60 80 100  60 80 100 Rev.5.1_02 (5) HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series Current consumption vs. Input voltage S-1323B30 120 120 100 100 80 85°C 25°C ISS1 [A] ISS1 [A] S-1323B15 60 40 –40°C 20 25°C 85°C 80 –40°C 60 40 20 0 2 0 6 4 0 8 0 2 6 4 VIN [V] 8 VIN [V] S-1323B50 120 –40°C 100 ISS1 [A] 80 25°C 85°C 60 40 20 0 2 0 6 4 8 VIN [V] (6) Ripple rejection S-1323B15 (Ta  25°C) S-1323B30 (Ta  25°C) VIN  2.5 V, COUT  1.0 F VIN  4.0 V, COUT  1.0 F IOUT  1 mA 80 60 30 mA 150 mA 40 20 0 10 100 1k 10k 100k 1M Frequency [Hz] 100 Ripple Rejection [dB] Ripple Rejection [dB] 100 80 IOUT  1 mA 60 150 mA 40 30 mA 20 0 10 100 1k 10k 100k 1M Frequency [Hz] S-1323B50 (Ta  25°C) VIN  6.0 V, COUT  1.0 F Ripple Rejection [dB] 100 80 IOUT  1 mA 60 150 mA 40 30 mA 20 0 10 100 1k 10k 100k 1M Frequency [Hz] 17 HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR Rev.5.1_02 S-1323 Series  Reference Data Input transient response characteristics VOUT [V] 3.03 3.02 3.01 3.00 VIN -20 VOUT -10 3.04 5 3.03 4 3.02 3 2 2.99 2.98 6 0 10 20 30 40 50 60 70 VIN [V] 3.04 IOUT  30 mA, tr  tf  5.0 s, COUT  1.0 F, CIN  0 F 3.01 3.00 1 2.99 0 2.98 80 -20 6 5 VIN 4 3 VOUT 2 VIN [V] IOUT  30 mA, tr  tf  5.0 s, COUT  0.47 F, CIN  0 F VOUT [V] (1) 1 -10 0 10 20 t [s] 30 40 50 60 70 0 80 t [s] IOUT  30 mA, tr  tf  5.0 s, COUT  2.2 F, CIN  0 F 3.04 3.02 3.01 3.00 6 5 VIN 4 3 VOUT 2 2.99 2.98 -20 VIN [V] VOUT [V] 3.03 1 -10 0 10 20 30 40 50 60 70 0 80 t [s] Load transient response characteristics 3.20 100 3.15 3.10 3.05 3.00 IOUT 50 0 VOUT –50 3.05 3.00 2.95 –100 2.95 2.90 –150 2.90 -2 0 2 4 6 8 10 12 14 16 -4 t [s] 3.20 3.10 3.05 3.00 150 100 IOUT 50 0 VOUT –50 –100 2.95 2.90 -4 –150 -2 0 2 4 6 t [s] 8 10 12 14 16 IOUT [mA] 3.15 100 IOUT 50 0 VOUT –50 –100 –150 -2 0 2 4 6 t [s] VIN  4.0 V, COUT  2.2 F, CIN  1.0 F, IOUT  50 mA 100 mA VOUT [V] 3.10 150 8 10 12 14 16 IOUT [mA] 150 3.15 -4 18 VIN  4.0 V, COUT  1.0 F, CIN  1.0 F, IOUT  50 mA 100 mA 3.20 IOUT [mA] VOUT [V] VIN  4.0 V, COUT  0.47 F, CIN  1.0 F, IOUT  50 mA 100 mA VOUT [V] (2) Rev.5.1_02 ON/OFF pin transient response characteristics S-1323B15 (Ta  25°C) S-1323B30 (Ta  25°C) VIN  2.5 V, tr  tf  1.0 s, COUT  1.0 F, CIN  1.0 F VIN  4.0 V, tr  tf  1.0 s, COUT  1.0 F, CIN  1.0 F 2.5 5 4 1 3 1.0 0 VON/OFF 0.5 –1 VOUT 0 –0.5 -10 -5 0 5 10 15 20 25 30 35 VOUT [V] 2 1.5 VON/OFF [V] VOUT [V] 2.0 3 2 0 1 0 –3 –1 –2 VOUT –4 –6 -10 t [s] 4 VON/OFF 2 –2 40 6 VON/OFF [V] (3) HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR S-1323 Series -5 0 5 10 15 20 25 30 35 40 t [s] S-1323B50 (Ta  25°C) 7 6 5 4 3 2 1 0 –1 8 6 4 2 0 –2 –4 –6 –8 VON/OFF VOUT -10 -5 0 5 10 15 20 25 30 35 VON/OFF [V] VOUT [V] VIN  6.0 V, tr  tf  1.0 s, COUT  1.0 F, CIN  1.0 F 40 t [s] 19 1.2±0.04 3 4 +0.05 0.08 -0.02 2 1 0.65 0.48±0.02 0.2±0.05 No. PF004-A-P-SD-6.0 TITLE SNT-4A-A-PKG Dimensions No. PF004-A-P-SD-6.0 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 4.0±0.1 2.0±0.05 0.25±0.05 +0.1 1.45±0.1 2 1 3 4 ø0.5 -0 4.0±0.1 0.65±0.05 Feed direction No. PF004-A-C-SD-2.0 TITLE SNT-4A-A-Carrier Tape No. PF004-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PF004-A-R-SD-1.0 TITLE SNT-4A-A-Reel No. PF004-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 1.16 2 0.52 0.35 1. 2. 0.3 1 (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) 0.03 mm 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) TITLE SNT-4A-A -Land Recommendation PF004-A-L-SD-4.1 No. No. PF004-A-L-SD-4.1 ANGLE UNIT mm ABLIC Inc. 2.0±0.2 1.3±0.2 4 3 0.05 0.3 +0.1 -0.05 +0.1 0.16 -0.06 2 1 +0.1 0.4 -0.05 No. NP004-A-P-SD-2.0 TITLE SC82AB-A-PKG Dimensions NP004-A-P-SD-2.0 No. ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 4.0±0.1 2.0±0.05 1.1±0.1 4.0±0.1 0.2±0.05 ø1.05±0.1 (0.7) 2.2±0.2 2 1 3 4 Feed direction No. NP004-A-C-SD-3.0 TITLE SC82AB-A-Carrier Tape No. NP004-A-C-SD-3.0 ANGLE UNIT mm ABLIC Inc. 4.0±0.1 2.0±0.1 ø1.5 1.1±0.1 +0.1 -0 4.0±0.1 0.2±0.05 ø1.05±0.1 2.3±0.15 2 1 3 4 Feed direction No. NP004-A-C-S1-2.0 TITLE SC82AB-A-Carrier Tape No. NP004-A-C-S1-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. NP004-A-R-SD-1.1 TITLE SC82AB-A-Reel No. NP004-A-R-SD-1.1 QTY. ANGLE UNIT mm ABLIC Inc. 3,000 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com