IS31CS8974-QFLS2-TR

IS31CS8974 MCU with 2KB ECC 2KB SRAM/32KB E-Flash for Touch Key Applications GENERAL DESCRIPTION FEATURES CS8974 is a general-purpose MCU with 32KB code memory (organized as 32Kx16) of embedded-flash memory and 2KB (organized as 2Kx13) SRAM for data manipulations. Both SRAM and e-Flash implement builtin ECC that correct 1-bit error and detect two-bit errs. CPU can access the e-Flash through program address read and through Flash Controller which can performs software read/writer operations of e-Flash for EEPROM emulations. CPU in CS8974 is 1-T 8051 with enhanced multiplication and division accelerator. There are two clock sources for system, one is a 16MHz IOSC (manufacturer calibrated +/- 2%) and another one is 128KHz SIOSC. Both clock sources have a clock programmable divider for scaling down the frequency to save power dissipations. The clock selections are combined with flexible power management schemes, including NORMAL, IDLE, and STOP, and SLEEP modes to balance speed and power consumption. There are T0/T1/T2/T3/T4/T5 timers coupled with CPU and two WDT where WDT0 is clocked by SYSCLK, and WDT2/WDT3 are clocked by a non-stop SIOSC. An 8-bit/16-bit checksum and 16-bit CRC accelerator is included. There are EUART/LIN controller and I2C master/Slave controller as well as SPI master/slave controller. The interfaces of these controllers are multiplexed with GPIO pins. Other useful peripherals include a buzzer/melody control, 6 channels of 8-bit PWM, and one channel of timer/capture and quadrature decoder. Analog peripherals include touch key controllers up to 20-bit resolution employing dual-slope chargesharing capacitance conversion. The touch key controller also has shield output capability for moisture immunity. The touch key controller allows sleep mode (5uA) and use auto detection for wakeup. The maximum number of key input can be scanned is 19. CS8974 also provides a flexible means of flash programming that supports ISP and IAP. The protection of data loss is implemented in hardware by access restriction of critical storage segments. The code security is reinforced with sophisticated writer commands and ISP commands. The on-chip break point processor also allows easy debugging which can be integrated with ISP. Reliable power-on-reset circuit and low supply voltage detection allows reliable operations under harsh environments. CPU and Memory  1-Cycle 8051 CPU core up to 16MHz  16-bit Timers T0/T1/T2/T3/T4 and 24-bit T5  Checksum and CRC accelerator  WDT1 by SYSCLK, WDT2/WDT3 by SIOSC  Clock fault monitoring  Integrated break point controller and debug port through I2C slave  Up to 20 external interrupts shared with GPIO pins  Power saving modes – Normal, IDLE, STOP, and SLEEP modes  256B IRAM and 1792B XRAM with ECC  32Kx16 Flash Memory and two 512x16 Information Block  Program read with hardware ECC  Software read/write direct access  Code security and data loss protection  100K Endurance and 10 years Retention Clock Sources  Internal oscillator at 16MHz of +/- 2% accuracy  Spread Spectrum option  Internal low power oscillator 128KHz  External clock option Digital Peripherals  6 CH 8-bit center-aligned PWM controller with trigger interrupt and polarity control  Timer/Capture and quadrature decoder  Buzzer and melody waveform generator  One I2C Master, two I2C Slave  I2CS1 allows address match wakeup and two address  I2CS2 for ISP and debug  One SPI Master/Slave Controllers  One 8051 UART and One full-duplex LIN-capable EUART2 Analog Peripherals  Capacitance sense touch-key controller  Dual slope charge transfer for higher PSRR and CMRR up to 20-bit resolutions.  Up to 19 key inputs with low power wake up (5uA) function.  Shield output for moisture immunity.  Power on reset and Low voltage detect (2.0V-4.5V) Miscellaneous  Up to 20 GPIO pins  Noise filters and Dual edge interrupt/wakeup  2.5V to 5.5V single supply  Active current < 150uA/MHz in Normal mode  Low power standby (1uA) in SLEEP mode  Operating temperature -40°C to 85°C  TSSOP-24 and QFN-24 package and RoHS compliant Applications  Touch key applications with high robustness and reliability requirements  Automotive and appliance Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 1 IS31CS8974 BLOCK DIAGRAM IOSC 16MHz WDT1 WDT2 WDT3 SIOSC 128KHz WAKE UP TIMER[0-4] CS/CRC 2KB IRAM/XRAM PORT0 PORT1 PORT2 FLASH CONTROL 4KB ECC Boot Code 28KB ECC Code FLASH TIMER[5] 1-CYCLE 8051 I2CS2 I2CS1 ISP I2CM0 UART0 512B IFB X2 EUART2 LIN 16-Bit PCA 8-Bit PCA TCC QEC 6-CH PWM 19-KEY TOUCH KEY CONTROLLER SPI M/S BUZZER MELODY I/O MULTIPLEXER AND BUFFERS AND PIN INTERRUPT LOW REGULATOR RESET SUPPLY DETECT I/O MULTIPLEXER AND BUFFERS AND PIN INTERRUPT Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 2 IS31CS8974 P00 19 18 24 P17 P20 P21/SDA P22/SCL P23 RSTN PIN OUT 1 P01 P15 P02 P14 CS8974 QFN-24 P03 P13 P04 P12 6 13 P06 P07 P06 P05 1 24 P05 P07 VSS P10 VDD P11 VDDC P12 P04 P13 P14 CS8974 TSSOP-24 P03 P02 P15 P01 P16 P00 P17 RSTN P20 P23 P21 12 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 12 VSS VDD 7 P11 P10 VDDC P16 13 P22 3 IS31CS8974 PIN Multifunction Table PIN# Q/S* 1/16 2/17 3/18 4/19 5/20 6/21 MFCFG 0 P00 P01 P02 P03 P04 VDDC 7/22 VDD 8/23 9/24 10/1 11/2 12/3 13/4 14/5 15/6 16/7 17/8 18/9 19/10 20/11 21/12 22/13 23/14 24/15 VSS P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 RSTN MFCFG MFCFG MFCFG MFCFG MFCFG MFCFG MFCFG ANIO ANIO 1 2 3 4 5 6 7 1 2 PHA XCAPT SSN BZ TX0 PWM0 KEY SHIELD PHB CC MOSI T0 RX0 PWM1 KEY SHIELD INDEX XCAPT MISO SSDA1 TX2 PWM2 KEY SHIELD XCAPT TC SCLK SSCL1 RX2 PWM3 KEY SHIELD PHA TC CC BZ TKC2 PWM4 XCLKIN KREF KREF Core supply 1.50V at normal mode, 1.40V at sleep mode. Connect 1uF and 0.1uF to VSS for decoupling. Power supply 2.2V to 5.5V. Ground supply 0V. PHB XCAPT MISO T0 TX2 PWM5 INDEX CC MOSI T1 RX2 PWM0 XCAPT TC SCLK T2 TX2 PWM1 PHA CC SSN T0 RX2 PWM2 PHB TC CC T1 BZ PWM3 INDEX XCAPT SSCL2 MSCL SSCL1 PWM4 XCAPT CC SSDA2 MSDA SSDA1 PWM5 PHA TC SSN CC TX2 PWM0 PHB XCAPT SSN T2 BZ PWM1 INDEX TC MISO CC RX2 PWM2 XCAPT TC MOSI CC TX2 PWM3 PHA XCAPT SCLK BZ RX2 PWM4 PHB CC SSDA2 MSDA SSDA1 PWM5 INDEX TC SSCL2 MSCL SSCL1 PWM0 XCAPT CC SSN RX2 TX2 PWM1 External reset input, low active. Internal 6K Ohm pull-up. XCLKIN - KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD 1. More than one function can be enabled. The outputs are OR-ed. 2. Input for GPIO port, interrupt/wakeup is always enabled. For other functions, the inputs are multiplexed to the specific function blocks. 3. Pin 21 (P21) as SDA and Pin 22 (P22) as SCL are used for In-System-Programming (ISP). 4. Pin 19 (P17) as CEB, Pin 20 (P20) as SCK, and Pin 21 (P21) as SDI, Pin 22 (P22) as SDO, along with Pin 24 (RSTN) are used in Writer Mode. Pin 23 (P23) for Flash TBIT ready output is optional for Writer Mode. RSTN is also necessary for Writer Mode. 5. Pin number is shown in QFN24/TSSOP24. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 4 IS31CS8974 MEMORY MAP There are total 256 bytes internal RAM in CS8974, the same as standard 8052. There are total 1792 bytes auxiliary RAM allocated in the 8051 extended RAM area at 0x0100h – 0x07FFh. Programs can use "MOVX" instruction to access the XRAM. There is a 32Kx16 (64KB) embedded Flash memory for code storage. For CPU program access (Read Only), the lower byte is used for actual access, and the upper byte is used for ECC check. The ECC is performed in nibble bases with each nibble in the high byte corresponds to the nibbles in the low byte. ECC in this case is capable of one-bit correction and two-bit detection for each nibble. This is significantly more robust than 8:5 ECC. ECC check in program access path is in hardware and performed automatically. The embedded Flash can also be accessed through Flash controller. For erase operations, the page size of the Flash is in 512x16. There are two 512x16 IFB blocks in the Flash. The first IFB is used for manufacturing and calibration data, and some area as user OTP data. The 2nd IFB is open for user application with no restriction. Also please note there are 8-byte of code security key located at the last of user program space for protection of pirate access of information. 0xFFFFH RESERVED 0xB000H 0xAFFFH XFR MOVX A, @DPTR 0xA000H RESERVED EMBEDDED FLASH 0x0400H 0x03FFH 0x7FFFH 0x7000H 4KB BOOT CODE 8B SEC KEY 512 x 16 IFB1 512 x 16 IFB2 RESET XRAM MOVX A, @DPTR 0x0100H 0x00FFH IRAM MOV A, @R 28KB USER CODE SFR MOV A, Direct 0x0080H 0x007FH IRAM MOC A, Direct Or MOV A, @R 0x0000H 0x0000H DATA MEMORY MAP Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 CODE MEMORY MAP 5 IS31CS8974 REGISTER MAP SFR (0x80 – 0xFF) The SFR address map maintains maximum compatibilities to most commonly used 8051 like MCU. The following table shows the SFR address map. Since SFR can be accessed by direct addressing mode, registers of built-in peripherals that require fast access are mostly located in SFR. XFR is mainly used for on-chip peripheral control and configurations. 0 1 2 3 4 5 6 7 0XF0 B - CLSR CHSR I2CMSA I2CMCR I2CMBUF I2CMTP 0XE0 ACC - - - - - - - 0XD0 PSW - - - - - - - 0XC0 - - SCON2 I2CMTO PMR STATUS MCON TA 0XB0 - - - - - - - - 0XA0 P2 SPICR SPIMR SPIST SPIDATA SFIFO2 SBUF2 SINT2 0X90 P1 EXIF WTST DPX - DPX1 - - 0X80 P0 SP DPL DPH DPL1 DPH1 DPS PCON 8 9 A B C D E F 0XF8 EXIP MD0 MD1 MD2 MD3 MD4 MD5 ARCON 0XE8 EXIE CH MXAX I2CSCON1A I2CSST1 I2CSADR1 I2CSDAT1 - 0XD8 WDCON CL DPXR I2CSCON2 I2CSST2 I2CSADR2 I2CSDAT2 - 0XC8 T2CON TB RLDL RLDH TL2 TH2 - T34CON 0XB8 IP - - - - - - - 0XA8 IE - - I2CSCON1B TL4 TH4 TL3 TH3 0X98 SCON0 SBUF0 - ESP - ACON I2CSADR3 WKMASK 0X88 TCON TMOD TL0 TL1 TH0 TH1 CKCON CKSEL Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 6 IS31CS8974 REGISTER MAP XFR (0xA000 – 0xAFFF) 0 A000 REGTRM A010 LVDCFG 1 2 3 4 5 6 7 - - - - SOSCTRM LVDHYS - TSTMON - BSTCMD RSTCMD FLSHADL FLSHADH FLSHECC FLSHCMD ISPCLKF FLSHPRTC IOSCITRM IOSCVTRM LVDTHD A020 FLSHDATL FLSHDATH A030 FLSHPRT0 FLSHPRT1 FLSHPRT2 FLSHPRT3 FLSHPRT4 FLSHPRT5 FLSHPRT6 FLSHPRT7 A040 NTAFRQL NTAFRQH NTADUR NTAPAU NTBFRQL NTBFRQH NTBDUR NTBPAU A050 TCCFG1 TCCFG2 TCCFG3 - TCPRDL TCPRDH TCCMPL TCCMPH A060 TCCPTRL TCCPTRH TCCPTFL TCCPTFH - - - - A070 QECFG1 QECFG2 QECFG3 - QECNTL QECNTH QEMAXL QEMAXH 8 9 A B C D E F A008 TK2CFGA TK2CFGB TK2CMD TK2CNTL TK2CNTH PECCCFG PECCADL PECCADH A018 TK3CFGA TK3CFGB TK3CFGC TK3CFGD TK3HDTYL TK3HDTYH TK3LDTYL TK3LDTYH A028 TK3BASEL TK3BASEH TK3THDL TK3THDH TK3PUD DECCCFG DECCADL DECCADH A038 - - - - - - - - A048 BZCFG NTPOW NOTETU - - - - - A058 - - - - - - - - A068 T5CON TL5 TH5 TT5 - - - - A078 CCCFG - - - CCDATA0 CCDATA1 CCDATA2 CCDATA3 0 1 2 3 4 5 6 7 - - - - - A080 PWMCFG1 PWMCFG2 PWMCFG3 A090 LINCTRL LINCNTRH LINCNTRL LINSBRH LINSBRL LININT LININTEN - A0A0 - SBAUD3H SBAUD3L SBAUD4H SBAUD4L - - - A0B0 LINTCON TXDTOL TXDTOH RXDTOL RXDTOH BSDCLRL BSDCLRH BSDWKC A0C0 - - - - - - - - A0D0 - - - - - - - - A0E0 BPINTF BPINTE BPINTC BPCTRL - - - - A0F0 PC1AL PC1AH PC1AT - PC2AL PC2AH PC2AT - 8 9 A B C D E F A088 PWM0DTY PWM1DTY PWM2DTY PWM3DTY PWM4DTY PWM5DTY - - A098 DBPCIDL DBPCIDH DBPCIDT DBPCNXL DBPCNXH DBPCNXT A0A8 - - - - - - - - A0B8 BSDACT - - - - - - - A0C8 - - - - - - - - A0D8 WDT2CF WDT2L WDT2H WDT3CF WDT3L WDT3H A0E8 - - - - - - - - A0F8 - - - - - - - - Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 STEPCTRL SI2CDBGID 7 IS31CS8974 0 1 2 3 4 5 6 7 A100 IOCFGO00 IOCFGO01 IOCFGO02 IOCFGO03 IOCFGO04 IOCFGO05 IOCFGO06 IOCFGO07 A110 IOCFGI00 IOCFGI01 IOCFGI02 IOCFGI03 IOCFGI04 IOCFGI05 IOCFGI06 IOCFGI07 A120 MFCFG00 MFCFG01 MFCFG02 MFCFG03 MFCFG04 MFCFG05 MFCFG06 MFCFG07 A130 IOCFGO20 IOCFGO21 IOCFGO22 IOCFGO23 IOCFGO24 IOCFGO25 IOCFGO26 IOCFGO27 A140 IOCFGI20 IOCFGI21 IOCFGI22 IOCFGI23 IOCFGI24 IOCFGI25 IOCFGI26 IOCFGI27 A150 MFCFG20 MFCFG21 MFCFG22 MFCFG23 MFCFG24 MFCFG25 MFCFG26 MFCFG27 A160 - - - - - - - - A170 - - - - - - - - 8 9 A B C D E F A108 IOCFGO10 IOCFGO11 IOCFGO12 IOCFGO13 IOCFGO14 IOCFGO15 IOCFGO16 IOCFGO17 A118 IOCFGI10 IOCFGI11 IOCFGI12 IOCFGI13 IOCFGI14 IOCFGI15 IOCFGI16 IOCFGI17 A128 MFCFG10 MFCFG11 MFCFG12 MFCFG13 MFCFG14 MFCFG15 MFCFG16 MFCFG17 A138 IOCFGO30 IOCFGO31 IOCFGO32 IOCFGO33 IOCFGO34 IOCFGO35 IOCFGO36 IOCFGO37 A148 IOCFGI30 IOCFGI31 IOCFGI32 IOCFGI33 IOCFGI34 IOCFGI35 IOCFGI36 IOCFGI37 A158 MFCFG30 MFCFG31 MFCFG32 MFCFG33 MFCFG34 MFCFG35 MFCFG36 MFCFG37 A168 - - - - - - - - A178 - - - - - - - - 0 1 2 3 4 5 6 7 A180 IOCFGO40 IOCFGO41 IOCFGO42 IOCFGO43 IOCFGO44 IOCFGO45 IOCFGO46 IOCFGO47 A190 IOCFGI40 IOCFGI41 IOCFGI42 IOCFGI43 IOCFGI44 IOCFGI45 IOCFGI46 IOCFGI47 A1A0 MFCFG40 MFCFG41 MFCFG42 MFCFG43 MFCFG44 MFCFG45 MFCFG46 MFCFG47 A1B0 IOCFGO60 IOCFGO61 IOCFGO62 IOCFGO63 IOCFGO64 IOCFGO65 IOCFGO66 IOCFGO67 A1C0 IOCFGI60 IOCFGI61 IOCFGI62 IOCFGI63 IOCFGI64 IOCFGI65 IOCFGI66 IOCFGI67 A1D0 MFCFG60 MFCFG61 MFCFG62 MFCFG63 MFCFG64 MFCFG65 MFCFG66 MFCFG67 A1E0 - - - - - - - - A1F0 - - - - - - - - 8 9 A B C D E F A188 IOCFGO50 IOCFGO51 IOCFGO52 IOCFGO53 IOCFGO54 IOCFGO55 IOCFGO56 IOCFGO57 A198 IOCFGI50 IOCFGI51 IOCFGI52 IOCFGI53 IOCFGI54 IOCFGI55 IOCFGI56 IOCFGI57 A1A8 MFCFG50 MFCFG51 MFCFG52 MFCFG53 MFCFG54 MFCFG55 MFCFG56 MFCFG57 A1B8 IOCFGO70 IOCFGO71 IOCFGO72 IOCFGO73 IOCFGO74 IOCFGO75 IOCFGO76 IOCFGO77 A1C8 IOCFGI70 IOCFGI71 IOCFGI72 IOCFGI73 IOCFGI74 IOCFGI75 IOCFGI76 IOCFGI77 A1D8 MFCFG70 MFCFG71 MFCFG72 MFCFG73 MFCFG74 MFCFG75 MFCFG76 MFCFG77 A1E8 - - - - - - - - A1F8 - - - - - - - - Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 8 IS31CS8974 1. 8051 CPU 1.1 CPU Register ACC (0xE0) Accumulator R/W (0x00) 7 6 5 4 3 RD ACC[7-0] WR ACC[7-0] 2 1 0 ACC is the CPU accumulator register and is involved in direct operations of many instructions. ACC is bit addressable. B (0xF0) B Register R/W (0x00) 7 6 5 4 3 RD B[7-0] WR B[7-0] 2 1 0 B register is used in standard 8051 multiply and divide instructions and also used as an auxiliary register for temporary storage. B is also bit addressable. PSW (0xD0) Program Status Word R/W (0x00) 7 6 5 4 3 2 1 0 RD CY AC FO RS1 RS0 OV UD P WR CY AC FO RS1 RS0 OV UD P 3 2 1 0 CY AC FO RS1, RS0 OV UD P Carry Flag Auxiliary Carry Flag (BCD Operations) General Purpose Register Bank Select Overflow Flag User Defined (reserved) Parity Flag SP (0x81) Stack Pointer R/W (0x00) 7 6 5 4 RD SP[7-0] WR SP[7-0] PUSH will result ACC to be written to SP+1 address. POP will load ACC from IRAM with the address of SP. ESP (0x9B) Extended Stack Pointer R/W (0x00) 7 6 5 4 3 RD ESP[7-0] WR ESP[7-0] 2 1 0 In FLAT address mode, ESP and SP together form a 16-bit address for stack pointer. ESP holds the higher byte of the 16-bit address. STATUS (0xC5) Program Status Word RO(0x00) 7 6 5 4 3 2 1 0 RD - HIP LIP - SPTA1 SPRA1 SPTA0 SPRA0 WR - - - - - - - - HIP LIP High Priority (HP) Interrupt Status HIP=0 indicates no HP interrupt HIP=1 indicates HP interrupt progressing Low Priority (LP) Interrupt Status LIP=0 indicates no LP interrupt LIP=1 indicates LP interrupt progressing Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 9 IS31CS8974 SPTA1 UART1 Transmit Activity Status SPTA1=0 indicates no UART1 transmit activity SPTA1=1 indicates UART1 transmit active SPRA1 UART1 Receive Activity Status SPRA1=0 indicates no UART1 receive activity SPRA1=1 indicates UART1 receive active SPTA0 UART0 Transmit Activity Status SPTA0=0 indicates no UART0 transmit activity SPTA0=1 indicates UART0 transmit active SPRA0 UART0 Receive Activity Status SPRA0=0 indicates no UART0 receive activity SPRA0=1 indicates UART0 receive active The program should check status conditions before entering SLEEP, STOP, or IDLE modes to prevent loss of intended functions from delayed entry until these events are finished. 1.2 Addressing Timing and Memory Modes The clock speed of an MCU with embedded flash memory is usually limited by the access time of on-chip flash memory. While in modern process technology, the CPU can operate much faster and the access time of flash memory is usually around 40 nanoseconds, which becomes a bottleneck for CPU performance. To mitigate this problem, a programmable wait state function is incorporated to allow faster CPU clock rate to access slower embedded flash memory. The wait state is controlled by WTST register as shown in the following, WTST (0x92) R/W (0x07) TA Protected 7 6 5 4 3 2 1 0 RD - - - - WTST3 WTST2 WTST1 WTST0 WR - - - - WTST3 WTST2 WTST1 WTST0 WTST[3-0] Wait State Control register. WTST sets the wait state in CPU clock period WTST3 WTST2 WTST1 WTST0 Wait State Cycle 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 The default setting of the program wait state register after reset is 0x07 and the software must initialize the setting to change the wait state setting. Using a SYSCLK of 4MHz, the WTST can be set to minimum because one clock period is 250ns, which is longer than the typical embedded flash access time. If SYSCLK is above 16MHz, then WTST should be set higher than 1 to allow enough read access time. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 10 IS31CS8974 MCON (0xC6) XRAM Relocation Register R/W (0x00) TA Protected 7 6 5 4 3 RD MCON[7-0] WR MCON[7-0] 2 1 0 MCON holds the starting address of XRAM in 2KB steps. For example, if MCON[7-0]=0x01, the starting address is 0x001000h. MCON is not meaningful in this chip because it only contains on-chip XRAM and MCON should not be modified from 0x00. The LARGE mode, addressing mode is compatible with standard 8051 in 16-bit address. FLAT mode extends the program address to 20-bit and expands the stack space to 16-bit data space. The data space is always 16-bit in either LARGE or FLAT mode. ACON (0x9D) R/W (0x00) TA Protected 7 6 5 4 3 2 1 0 RD - - IVECSEL - DPXREN SA AM1 AM0 WR - - IVECSEL - DPXREN SA AM1 AM0 ACON is addressing mode control register. IVECSEL Interrupt Vector Selection INTVSEC=1 maps the interrupt vector to B000 space. INTVSEC=0 maps to normal 0x0000 space DPXREN DPXR Register Control Bit. If DPXREN is 0, “MOVX, @Ri” instruction uses P2 (0xA0) register and XRAM Address [15-8]. If DPXREN is 1,DPXR (0xDA) register and XRAM Address [15-8] is used. SA Extended Stack Address Mode Indicator. This bit is read-only. 0 – 8051 standard stack mode where stack resides in internal 256-byte memory 1 – Extended stack mode. Stack pointer is ESP:SP in 16-bit addressing to data space. AM1, AM0 AM1 and AM0 Address Mode Control Bits 00 – LARGE address mode in 16-bit 1x – FLAT address mode with 20-bit program address 1.3 MOVX A, @Ri Instructions DPXR (0xDA) R/W (0x00) 7 6 5 4 3 RD DPXR[7-0] WR DPXR[7-0] 2 1 0 DPXRis used to replace P2[7-0] for high byte of XRAM address bit[15-7] for ”MOVX, @Ri” instructions only if DPXREN=1. MXAX (0xEA) MOVX Extended Address Register R/W (0x00) 7 6 5 4 3 RD MXAX[7-0] WR MXAX[7-0] 2 1 0 MXAX is used to provide top 8-bit address for“MOVX @Ri” instructions only. MXAX does not affect other MOVX instructions. When accessing XRAM using “MOVX, @DPTR” instruction, the address of XRAM access is formed by DPHi:DPLi depending on which data pointer is selected. Another form of MOVX instruction is “MOVX, @Ri”. This instruction provides an efficient programming method to move content within a 256-byte data block. In “@RI” instruction, the XRAM address [15-7] can be derived from two sources. If ACON.DPXREN = 0, the high order address [15-8] is from P2 (0xA0), if ACON.DPXREN = 1, the high order address is from DPXR (0xDA) register. The maximum addressing space of XRAM is up to 16MB thus requiring 24-bit address. For “MOVX, @DPTR”, the XRAMADDR [23-16] is from either DPX (0x93) or DPX1 (0x95) depending on which data pointer is selected. For “MOVX, @Ri”, the XRAMUADDR [23-16] is from MXAX (0xEA) register. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 11 IS31CS8974 1.4 Dual Data Pointers and MOVX operations In standard 8051, there is only one data pointers DPH:DPL to perform MOVX. The enhanced CPU provides 2nd data pointer DPH1:DPL1 to speed up the movement, or copying of data block. The active DPTR is selected by setting DPS (Data Pointer Select) register. Through the control DPS, efficient programming can be achieved. DPS (0x86) Data Pointer Select R/W (0x00) 7 6 5 4 3 2 1 0 RD ID1 ID0 TSL - - - - SEL WR ID1 ID0 TSL - - - - SEL Define the operation of Increment Instruction of DPTR, “INC DPTR”. Standard 8051 only have increment DPTR instruction. ID[1-0] changes the definitions of “INC DPTR” instruction and allows flexible modifications of DPTR when “INC DPTR” instructions is executed. ID[1:0] TSL ID1 ID0 SEL=0 SEL=1 0 0 INC DPTR INC DPTR1 0 1 DEC DPTR INC DPTR1 1 0 INC DPTR DEC DPTR1 1 1 DEC DPTR DEC DPTR1 Enable toggling selection of DPTR selection. When this bit is set, the selection of DPTR is toggled when DPTR is used in an instruction and executed. DPTR selection bit. Set to select DPTR1, and clear to select DPTR. SEL is also affected by the state of ID[1:0] and TSL after DPTR is used in an instruction. When read, SEL reflects the current selection of command. SEL DPL (0x82) Data Pointer Low R/W (0x00) 7 6 5 4 RD DPL[7-0] WR DPL[7-0] 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 DPL register holds the low byte of data pointer, DPTR. DPH (0x83) Data Pointer High R/W (0x00) 7 6 5 4 RD DPH[7-0] WR DPH[7-0] DPH register holds the high byte of data pointer, DPTR. DPL1 (0x84) Extended Data Pointer Low R/W (0x00) 7 6 5 4 RD DPL1[7-0] WR DPL1[7-0] DPL1 register holds the low byte of extended data pointer 1, DPTR1. DPH1 (0x85) Extended Data Pointer High R/W (0x00) 7 6 5 4 RD DPH1[7-0] WR DPH1[7-0] DPH1 register holds the high byte of extended data pointer 1, DPTR1. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 12 IS31CS8974 DPX (0x93) Data Pointer Top R/W (0x00) 7 6 5 4 3 RD DPX[7-0] WR DPX[7-0] 2 1 0 DPX is used to provide top 8-bit address of DPTR when address above 64KB. The lower 16-bit address is formed by DPH and DPL. DPX is not affected in LARGE mode, and will form full 24-bit address in FLAT mode, meaning auto increment and decrement when DPTR is changed. DPX value has no effect if on-chip data memory is less than 64KB. DPX1 (0x95) Extended Data Pointer Top R/W (0x00) 7 6 5 4 3 RD DPX1[7-0] WR DPX1[7-0] 2 1 0 DPX1 is used to provide top 8-bit address of DPTR when address above 64KB. The lower 16-bit address is formed by DPH1 and DP1L. DPX1 is not affected in LARGE mode, and will form full 24-bit address in Flat mode, meaning auto increment and decrement when DPTR is changed. DPX value has no effect if on-chip data memory is less than 64KB. 1.5 Interrupt System The CPU implements an enhanced Interrupt Control that allows total 15 interrupt sources and each with two programmable priority levels. The interrupts are sampled at rising edge of SYSCLK. If interrupts are present and enabled, the CPU enters interrupt service routine by vectoring to the highest priority interrupt. Of the 15 interrupt sources, 7 of them are from CPU internal integrated peripherals, 6 of them are for on-chip external peripherals, and 2 of them are used for external pin interrupt expansion. When an interrupt is shared, the interrupt service routine must determine which source is requesting the interrupt by examining the corresponding interrupt flags of sharing peripherals. The following table shows the interrupt sources and corresponding interrupt vectors. The Flag Reset column shows whether the corresponding interrupt flag is cleared by hardware (self-cleared) or software. Please note the software can only clear the interrupt flag but not set the interrupt flag. The Natural Priority column shows the inherent priority if more than one interrupts are assigned to the same priority level. Please note that the interrupts assigned with higher priority levels always get serviced first compared with interrupts assigned with lower priority levels regardless of the natural priority sequence. Interrupt Peripheral Source Description Vectors (*Note) IVECSEL=0/1 FLAG RESET Natural Priority PINT0 Expanded Pin INT0.x 0x0003/0xX003 Software 1 TF0 Timer 0 0x000B/0xX00B Hardware 2 PINT1 Expanded Pin INT1.x 0x0013/0xX013 Software 3 TF1 Timer 1 0x001B/0xX01B Hardware 4 TI0/RI0 UART0 0x0023/0xX023 Software 5 TF2 Timer 2 0x002B/0xX02B Software 6 TI2/RI2 EUART2/LIN/LIN_FAULT 0x0033/0xX033 Software 7 I2CM I2C Master 0x003B/0xX03B Software 8 INT2 LVT 0x0043/0xX043 Software 9 INT3 TKC2/TKC3 0x004B/0xX04B Software 10 INT4 Reserved 0x0053/0xX053 Software 11 WDIF Watchdog WDT1 0x005B/0xX05B Software 12 INT6 PWM/TCC/QE 0x0063/0xX063 Software 13 INT7 SPI/I2C Slave 0x006B/0xX06B Software 14 INT8 T3/T4/T5/Buzzer 0x0073/0xX073 Software 15 ECC ECC/WDT2 0x007B/0xX07B Software 0 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 13 IS31CS8974 BKP Break Point 0xX080 Software 0 DBG I2CS Debug 0xX0C0 Software 0 * Note: When IVECSEL=1, the interrupt vector is relocated to the top available 4KB memory space for boot code usage. Therefore, X=F, for 64K, and X=B for 48K program memory size, and X=7 for 32K, and X=3 for 16K sizes. In addition to the 15 peripheral interrupts, there are two highest priority interrupts associated with debugging and break point. DBG interrupt is generated when I2C slave is configured as a debug port and a debug request from the host matches the debug ID. BKP interrupt is generated when break point match condition occurs. DBG has higher priority than BKP. The BKP and DBG interrupts are not affected by global interrupt enable, EA bit, IE register (0xA8). The interrupt related registers are listed in the following. Each interrupt can be individually enabled or disabled by setting or clearing corresponding bits in IE, EXIE and integrated peripherals’ control registers. IE (0xA8) Interrupt Enable Register R/W (0x00) 7 6 5 4 3 2 1 0 RD EA ES2 ET2 ES0 ET1 PINT1EN ET0 PINT0EN WR EA ES2 ET2 ES0 ET1 PINT1EN ET0 PINT0EN EA ES2 ET2 ES0 ET1 PINT1EN ET0 PINT0EN Global Interrupt Enable bit. LIN-capable16550-likeUART2 Interrupt Enable bit. Timer 2 Interrupt Enable bit. UART0 Interrupt Enable bit. Timer 1 Interrupt Enable bit. Pin PINT1.x Interrupt Enable bit. Timer 0 Interrupt Enable bit. Pin PINT0.x Interrupt Enable bit. EXIE (0xE8) Extended Interrupt Enable Register R/W (0x00) RD WR 7 6 5 4 3 2 1 0 EINT8 EINT8 EINT7 EINT7 EINT6 EINT6 EWDI EWDI EINT4 EINT4 EINT3 EINT3 EINT2 EINT2 EI2CM EI2CM EINT8 EINT7 EINT6 Timer 3, Timer 4, Timer 5, and Buzzer Interrupt Enable bit. SPI and I2C Slave Interrupt Enable bit. PWM, Timer with Compare/Capture (TCC), Quadrature Encoder (QE) Interrupt Enable bit. EWD1 Watchdog Timer Interrupt Enable bit. EINT4 Reserved EINT3 Touch Key Controller II (TKC2) and Touch Key Controller III (TKC3) Interrupt Enable bit. EINT2 Low Voltage Detection (LVT) Interrupt Enable bit. EI2CM I2C Master Interrupt Enable bit. Each interrupt can be individually assigned to either high or low. When the corresponding bit is set to 1, it indicates it is of high priority. IP (0xB8) Interrupt Priority Register R/W (0x00) RD WR 7 6 5 4 3 2 1 0 - PS2 PS2 PT2 PT2 PS0 PS0 PT1 PT1 PX1 PX1 PT0 PT0 PX0 PX0 PS2 PT2 PS0 PT1 PX1 PT0 PX0 LIN-capable 16550-like UART2 Priority bit. Timer 2 Priority bit. UART 0 Priority bit. Timer 1 Priority bit. Pin Interrupt INT1 Priority bit. Timer 0 Priority bit. Pin Interrupt INT0 Priority bit. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 14 IS31CS8974 EXIP (0xF8) Extended Interrupt Priority Register R/W (0x00) 7 6 5 4 3 2 1 0 RD PINT8 PINT7 PINT6 PWDI PINT4 PINT3 PINT2 PI2CM WR PINT8 PINT7 PINT6 PWDI PINT4 PINT3 PINT2 PI2CM PINT8 PINT7 PINT6 INT8 Timer 3, Timer 4, Timer 5 and Buzzer Priority bit. INT7 SPI and I2C Slave Priority bit. INT6 PWM, Timer with Compare/Capture (TCC) and Quadrature Encoder (QE) Priority bit. Watchdog Priority bit. Reserved for INT4 Priority bit. INT3 Touch Key Controller II (TKC2) and Touch Key Controller III (TKC3) Priority bit. INT2 Low Voltage Detection (LVT) Priority bit. I2C Master Priority bit. PWDI PINT4 PINT3 PINT2 PI2CM EXIF (0x91) Extended Interrupt Flag R/W (0x00) RD WR 7 6 5 4 3 2 1 0 INT8F - INT7F - INT6F - - INT4F - INT3F - INT2F - I2CMIF I2CMIF INT8F INT7F INT6F INT8 Timer 3, Timer 4, Timer 5 and Buzzer Interrupt Flag bit INT7 SPI and I2C Slave interrupt Flag bit INT6 PWM, Timer with Compare/Capture (TCC) and Quadrature Encoder (QE) Interrupt Flag bit INT4F Reserved for INT4 Interrupt Flag bit INT3F INT3 Touch Key Controller II (TKC2) and Touch Key Controller III (TKC3) Interrupt Flag bit INT2F INT2 Low Voltage Detection (LVT) Interrupt Flag bit I2CMIF I2C Master Interrupt Flag bit. This bit must be cleared by software Note: Writing to INT2F to INT8F has no effect. The interrupt flag of internal peripherals are stored in the corresponding flag registers in the peripheral and EXIF registers. These peripherals include T0, T1, T2, and WDT. Software needs to clear the corresponding flags located in the peripherals (for T0, T1, and T2, and WDT). For I2CM, the interrupt flag is located in the EXIF register bit I2CMIF. This needs to be cleared by software. INT2 to INT8 are used to connect to the external peripherals. INT2F to INT8F are direct equivalents of the interrupt flags from the corresponding peripherals. These peripherals include Timer 3, Timer 4, Timer 5, Buzzer, SPI, I2CS, PWM, TCC, QE, TKC2, TKC3 and etc. WKMASK (0x9F) R/W (0xFF) Wake Up Mask Register TB Protected 7 6 5 4 3 2 1 0 RD WEINT8 WEINT7 WEINT6 WEINT4 WEINT3 WEINT2 WEPINT1 WEPINT0 WR WEINT8 WEINT7 WEINT6 WEINT4 WEINT3 WEINT2 WEPINT1 WEPINT0 WEINT8 Set this bit to allow INT8 to trigger the wake up of CPU from STOP modes. WEINT7 Set this bit to allow INT7 to trigger the wake up of CPU from STOP modes. WEINT6 Set this bit to allow INT6 to trigger the wake up of CPU from STOP modes. WEINT4 Set this bit to allow INT4 to trigger the wake up of CPU from STOP modes. WEINT3 Set this bit to allow INT3 to trigger the wake up of CPU from STOP modes. WEINT2 Set this bit to allow INT2 to trigger the wake up of CPU from STOP modes. WEPINT1 Set this bit to allow INT1 to trigger the wake up of CPU from STOP modes. WEPINT0 Set this bit to allow INT0 to trigger the wake up of CPU from STOP modes. WKMASK register defines the wake up control of the interrupt signals from the STOP/SLEEP mode. The wake-up is performed by these interrupts and if enabled the internal oscillator is turned on and SYSCLK resumes. The interrupt can be set as a level trigger or an edge trigger and the wake-up always runs in accordance with the edge. Please note the wake-up control is wired separately from the interrupt logic, therefore, after waking up, the CPU does not necessarily enter the interrupt service routine if the corresponding interrupt is not enabled. In this case, the CPU continues onto the next instruction, which initiates the STOP/SLEEP mode. Extra attention should be exerted as designing the exit and re-entry of modes to ensure proper operation. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 15 IS31CS8974 Please note that all clocks are stopped in STOP/SLEEP mode, therefore peripherals require clock such as Timer 3, Timer 4, Buzzer, SPI, PWM, UART0, and LVD cannot perform wake-up function. Only external pins and peripherals that do not require a clock (or can use SIOSC clock) can be used for wake up purposes. Such peripherals for examples are I2CS1, LIN, WDT2, Timer 5, and TK3. PINT0 and PINT1 are used for external GPIO pin Interrupts. All GPIO pin can be enabled to generate the PINT0 or PINT1 depending on its MFCFG register setting. Each GPIO pin also contains the rising/falling edge detections and either or both edges can be used for interrupt triggering. The same signaling can be used for generating wake-up. TCON (0x88) R/W (0x00) 7 6 5 4 3 2 1 0 RD TF1 TR1 TF0 TR0 PINT1F - PINT0F - WR - TR1 - TR0 PINT1F - PINT0F - TF1 TR1 TF0 TR0 PINT1F PINT0F 1.6 Timer 1 Interrupt Flag bit. TF1 is cleared by hardware when entering the interrupt routine. Timer 1 Run Control bit. Set to enable Timer 1. Timer 0 Interrupt Flag. TF0 is cleared by hardware when entering the interrupt routine. Timer 0 Run Control bit. Set to enable Timer 0. Pin INT1 Interrupt Flag bit. Pin INT0 Interrupt Flag bit. Register Access Control One important aspect of the embedded MCU is its reliable operations under a harsh environment. Many system failures result from the accidental loss of data or changes of critical registers that may lead to catastrophic effects. The CPU provides several protection mechanisms, which are described in this section. TA (0xC7) Time Access A Control Register2 WO xxxxxxx0 RD 7 6 5 4 3 2 1 0 - - - - - - - TASTAT WR TA Register TA access control emulates a ticket that must be purchased before modifying a critical register. To modify or write into a TA protected register, TA must be accessed in a predefined sequence to obtain the ticket. The ticket is used when an intended modification operation is done to the TA protected register. To obtain the next access a new ticket must be obtained again by performing the same predefined sequence on TA. TA does not limit the read access of the TA protect registers. The TA protected register includes WDCON (0xD8), MCON (0xC6), and ACON (0x9D) registers. The following predefined sequence is required to modify the content of MCON. MOV TA, #0xAA; MOV TA, #0x55; MOV MCON, #0x01; Once the access is granted, there is no time limitation of the access. The access is voided if any operation is performed in TA address. When read, TASTAT indicates whether TA is locked or not (1 indicates “unlock” and 0 indicates “lock”). TB (0xC9) Time Access B Control Register2 RW (0x00) RD 7 6 5 4 3 2 1 0 - - - - - - - TBSTAT WR TB Register TB access control functions are similar to TA control, except the ticket is for multiple uses with a time limit. Once access is granted, the access is open for 256 clock periods and then expires. The software can also read TB address to obtain the current TB status. The TB protected registers include two SFR registers, CKSEL (0x8F) and WKMASK (0x9F), and several XFR registers, such as FLSHCMD (0xA025), ISPCLKF (0xA026), FLSHPRTC (0xA027), FLSHPRT0 (0xA030), BPINTE (0xA0E1), and SI2C_DebugID (0xA09F) etc. To modify registers with TB protection, the following procedure must be performed. MOV TB, #0xAA MOV TB, #0x55 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 16 IS31CS8974 This action creates a timed window of 256 SYSCLK periods to allow write access of these TB protected registers. If any above-mentioned sequences are repeated before the 128 cycles expires, a new 128 cycles is extended. The current 256 cycles can be terminated immediately by writing #0x00 to TB registers, such as MOV TB, #0x00 It is recommended to terminate the TB access window once the user program finishes the modifications of TB protected registers. Because TA and TB are critical reassurance of the reliable operation of the MCU that prevents accidental hazardous uncontrollable modifications of critical registers, the operation of these two registers should bear extreme cautions. It is strongly advised that these two registers should be turned on only when needed. Both registers use synchronous CPU clock, therefore it is imperative that any running tasks of TA and TB should be terminated before entering IDLE mode or STOP mode. Both modes turn off the CPU clock and if TA and TB are enabled, they stay enabled until the CPU clock resumes thus may create vulnerabilities for critical registers. Another reliability concern of embedded Flash MCU is that the important content on the Flash can be accidentally erased. This concern is addressed by the content protection in the Flash controller. 1.7 Clock Control and Power Management Modes This section describes the clock control and power saving modes of the CPU and its integrated peripherals. The settings are controlled by PCON (0x87) and PMR (0xC4) registers. The register description is defined as following. PCON (0x87) R/W (0x00) 7 6 5 4 3 2 1 0 RD SMOD0 - - - - - - - WR SMOD0 - - - - SLEEP STOP IDLE SMOD0 SLEEP STOP IDLE UART 0 Baud Rate Control. This is used to select double baud rate in mode 1, 2 or 3 for UART0 using Timer 1 overflow. This definition is the same as standard 8051. Sleep Mode Control Bit. When this bit and the Stop bit are set to 1, the clock of the CPU and all peripherals is disabled and enters SLEEP mode. The SLEEP mode exits when non-clocked interrupts or resets occur. Upon exiting SLEEP mode, Sleep bit and Stop bit in PCON is automatically cleared. In terms of power consumption, the following relationship applies: IDLE mode > STOP mode > SLEEP mode. SLEEP mode is the same as STOP mode, except it also turns off the band gap and the regulator. It uses a very low power back-up regulator (< 5uA). When waking up from SLEEP mode, it takes longer time (< 64 IOSC clock cycles, compared with STOP mode) because the regulator requires more time to stabilize. Stop Mode Control Bit. The clock of the CPU and all peripherals is disabled and enters STOP mode if the Sleep bit is in the reset state. The STOP mode can only be terminated by non-clocked interrupts or resets. Upon exiting STOP mode, Stop bit in PCON is automatically cleared. Idle Bit. If the IDLE bit is set, the system goes into IDLE mode. In Idle mode, CPU clock becomes inactive and the CPU and its integrated peripherals such as WDT, T0/T1/T2, and UART0 are reset. But the clocks of external peripherals and CPU like PCA, ADC, LIN-capable16550-like UART2, SPI, T3, I2C slave and the others are still active. This allows the interrupts generated by these peripherals and external interrupts to wake the CPU. The exit mechanism of IDLE mode is the same as STOP mode. Idle bit is automatically cleared at the exit of the IDLE mode. PMR (0xC4) R/W (010xxxxx) 7 6 5 4 3 2 1 0 RD CD1=0 CD0 SWB - - - - - WR - CD0 SWB - - - - - CD1, CD0 NOTE: Clock Divider Control. These two bits control the entry of PMM mode. When CD0=1, and CD1=0, full speed operation is in effect. When CD0=1, and CD1=1, the CPU enters PMM mode where CPU and its integrated peripherals operate at a clock rate divided by 257. Note that in PMM mode, all integrated peripherals such as UART0, LIN-capable 16550-like UART2, WDT, and T0/T1/T2 run at this reduced rate, thus may not function properly. All external peripherals to CPU still operate at full speed in PMM mode. CD1 is internally hardwired to 0. This implementation does not support PMM mode. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 17 IS31CS8974 SWB NOTE: Switch Back Control bit. Setting this bit allows the actions to occur in integrated peripherals to automatically switch back to normal operation mode. PMM mode is not supported. CKSEL (0x8F) R/W (0x0C) System Clock Selection Register TB Protected 7 6 5 4 3 2 1 0 RD IOSCDIV[3-0] - - CLKSEL[1] CLKSEL[0] WR IOSCDIV[3-0] REGRDY[1] REGRDY[0] CLKSEL[1] CLKSEL[0] IOSCDIV[3-0] REGRDY[1-0] CLKSEL[1-0] IOSC Pre-Divider. Default is IOSC. IOSCDIV[3-0] SYSCLK 0 IOSC 1 IOSC/2 2 IOSC/4 3 IOSC/6 4 IOSC/8 5 IOSC/10 6 IOSC/12 7 IOSC/14 8 IOSC/16 9 IOSC/32 10 IOSC/64 11 IOSC/128 12 IOSC/256 13 IOSC/256 14 IOSC/256 15 IOSC/256 Wake up delay time for main regulator stable time from reset or from sleep mode wakeup. Default is longest delay at 256 SIOSC. REGRDY[1] REGRDY[0] Delay time 0 0 4 SIOSC cycle 0 1 16 SIOSC cycle 1 0 64 SIOSC cycle 1 1 256 SIOSC cycle Clock Source Selection These two bits define the clock source of the system clock SYSCLK. The selections are shown in the following table. The default setting after reset is IOSC. CLKSEL[1] CLKSEL[0] SYSCLK 0 0 IOSC (through divider) 0 1 SIOSC (32KHz) 1 0 IOSC (through divider) 1 1 XCLKIN Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 18 IS31CS8974 WKMASK (0x9F) R/W (0xFF) Wake-Up Mask Register TB Protected 7 6 5 4 3 2 1 0 RD WEINT8 WEINT7 WEINT6 WEINT4 WEINT3 WEINT2 WEPINT1 WEPINT0 WR WEINT8 WEINT7 WEINT6 WEINT4 WEINT3 WEINT2 WEPINT1 WEPINT0 WEINT8 Set this bit to allow INT8 to trigger the wake up of CPU from STOP modes. WEINT7 Set this bit to allow INT7 to trigger the wake up of CPU from STOP modes. WEINT6 Set this bit to allow INT6 to trigger the wake up of CPU from STOP modes. WEINT4 Set this bit to allow INT4 to trigger the wake up of CPU from STOP modes. WEINT3 Set this bit to allow INT3 to trigger the wake up of CPU from STOP modes. WEINT2 Set this bit to allow INT2 to trigger the wake up of CPU from STOP modes. WEPINT1 Set this bit to allow INT1 to trigger the wake up of CPU from STOP modes. WEPINT0 Set this bit to allow INT0 to trigger the wake up of CPU from STOP modes. WKMASK register defines the wake up control of the interrupt signals from the STOP/SLEEP mode. The wake-up is performed by these interrupts and if enabled the internal oscillator is turned on and SYSCLK resumes. The interrupt can be set as a level trigger or an edge trigger and the wake-up always runs in accordance with the edge. Please note the wake-up control is wired separately from the interrupt logic, therefore, after waking up, the CPU does not necessarily enter the interrupt service routine if the corresponding interrupt is not enabled. In this case, the CPU continues onto the next instruction, which initiates the STOP/SLEEP mode. Extra attention should be exercised as designing the exit and re-entry of modes to ensure proper operation. Please note that all clocks are stopped in STOP/SLEEP mode, therefore peripherals require clock such as I2C slave, UARTx, ADC, LVD, and T3/T4 cannot perform wake-up function. Only external pins and peripherals that do not require a clock can be used for wake up purposes. Such peripherals are LIN Wakeup and Timer5 with SIOSC. IDLE Mode IDLE mode provides power saving by stopping SYSCLK to CPU and its integrated peripherals while other peripherals are still in operation with SYSCLK. Thus other peripherals still function normally and can generate interrupts that wake up the CPU from IDLE mode. The IDLE mode is enabled by setting IDLE bit to 1. When the CPU is in idle mode, no processing is possible. All integrated internal peripherals such as T0/T1/T2, UART0, LIN-capable 16550-likeUART2and I2C Master are inaccessible during idling. The IDLE mode can be excited by hardware reset through RSTN pin (no such pin) or by external interrupts as well as the interrupts from external peripherals that are OR-ed with the external interrupts. The triggering external interrupts need be enabled properly. Upon exiting from IDLE mode, the CPU resumes operation as the clock is being turned on. CPU immediately vectors to the interrupt service routine of the corresponding interrupt sources that wake up the CPU. When the interrupt service routine completes, RETI returns to the program and immediately follows the one that invokes the IDLE mode. Upon returning from IDLE mode to normal mode, idle bit in PCON is automatically cleared. STOP Mode STOP mode provides further power reduction by stopping SYSCLK to all circuits. In STOP mode, IOSC oscillator is disabled. STOP mode is entered by setting STOP=1. To achieve minimum power consumption, it is essential to turn off all peripherals with DC current consumption. It is also important that the software switches to the IOSC clock and disables all other clock generator before entering STOP mode. This is critical to ensure a smooth transition when resuming its normal operations. Upon entering STOP mode, the system uses the last edge of IOSC clock to shut down the IOSC clock generator. Valid interrupt/wakeup event or reset will result the exit of STOP mode. Upon exit, STOP bit is cleared by hardware and IOSC is resumed. The triggering interrupt source must be enabled and its Wake-up bit is set in the WKMASK register. As CPU resumes the normal operation using previous clock settings. When an interrupt occurs, the CPU immediately vectors to the interrupting service routine of the corresponding interrupt source. When the interrupt service routine completes, RETI returns to the program immediately to execute the instruction that invokes the STOP mode. The on-chip 1.5V regulator for core circuits is still enabled along with its reference voltage. As the result, the power consumption due to the regulator and its reference circuit is still around 100uA to 200uA. The advantage of STOP mode is its immediate resumption of the CPU. SLEEP Mode SLEEP mode achieves very low standby consumption by putting the on-chip 1.5V regulator in disabled state. An ultra low power 1.3V backup regulator supplies the internal core circuit and maintains the logic state and Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 19 IS31CS8974 SRAM data. The total current drain in SLEEP mode is less than 1uA. Only the backup regulator and the SIOSC circuit are still in operation in SLEEP mode. The exit of SLEEP mode is the same interrupt/wakeup event as in STOP node, and in addition the onchip regulator is enabled, then after a delay set by REGRDY (clocked by SIOSC), SYSCLK is resumed. REGRDY delay is necessary to ensure stable operation of the regulator. The larger the decoupling capacitance longer delay should be set. Clock Control The clock selection is defined by CKSEL register (0x8F). There are two selections either from divided IOSC or SIOSC. The default selection is divided IOSC. Typical power consumption of CPU is 0.150mA/MHZ. 1.8 Watchdog Timer The Watchdog Timer is a 30-bit timer that can be used by a system supervisor or as an event timer. The Watchdog timer can be used to generate an interrupt or to issue a system reset depending on the control settings. This section describes the register related to the operation of Watchdog Timer and its functions. The following diagram shows the structure of the Watchdog Timer. Note WDT shares the same clock with the CPU, thus WDT is disabled in IDLE mode or STOP mode however it runs at a reduced rate in PMM mode. SYS CLOCK 30-BIT TIMER WTRF RESET WD1 131072 1048576 000 001 8388608 010 67108864 134217728 268435456 536870912 1073741824 100 010 101 110 111 TIMEOUT SELECT WD1 WD2 DELAY 512 EWDI EWT WATCHDOG INT RESET WDCON (0xD8) R/W (0x02) 7 6 5 4 3 2 1 0 RD - - - - WDIF WTRF EWT - WR - - - - WDIF WTRF EWT RWT WDIF WDT Interrupt Flag bit. This bit is set when the session expires regardless of a WDT interrupt is enabled or not. Note the WDT interrupt enable control is located in EIE (0xE8). 4 EWDI bit. It must be cleared by software WDT Reset Flag bit. WDRF is cleared by hardware reset including RSTN, POR etc. WTRF is set to 1 after a WDT reset occurs. It can be cleared by software. WTRF can be used by software to determine if a WDT reset has occurred. Watchdog Timer Reset Enable bit. Set this bit to enable the watchdog reset function. The default WDT reset is enabled and WDT timeout is set to maximum. Reset the Watchdog timer. Writing 1 to RWT resets the WDT timer. RWT bit is not a register and does not hold any value. The clearing action of Watchdog timer is protected by TA access. In another word, to clear Watchdog timer, TA must be unlocked then and then followed by writing RWT bit to 1. If TA is still locked, the program can write 1 into RWT bit, but it does not reset the Watchdog timer. WTRF EWT RWT CKCON (0x8E) R/W (0xC4) 7 6 5 4 3 2 1 0 RD WD1 WD0 T2CKDCTL T1CKDCTL T0CKDCTL WD2 - - WR WD1 WD0 T2CKDCTL T1CKDCTL T0CKDCTL WD2 - - Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 20 IS31CS8974 T2CKDCTL T1CKDCTL T0CKDCTL WD[2:0] Timer 2 Clock Source Division Factor Control Flag. Setting this bit to 1 sets the Timer 2 division factor to 4, the Timer 2 clock frequency equals CPU clock frequency divided by 4. Setting this bit to 0 (the default power on value) sets the Timer 2 division factor to 12, the Timer 2 clock frequency equals CPU clock frequency divided by 12. Timer 1 Clock Source Division Factor Control Flag. Setting this bit to 1 sets the Timer 1 division factor to 4, the Timer 1 clock frequency equals CPU clock frequency divided by 4. Setting this bit to 0 (the default power on value) sets the Timer 1 division factor to 12, the Timer 1 clock frequency equals CPU clock frequency divided by 12. Timer 0 Clock Source Division Factor Control Flag. Setting this bit to 1 sets the Timer 0 division factor to 4, the Timer 0 clock frequency equals CPU clock frequency divided by 4. Setting this bit to 0 (the default power on value) sets the Timer 0 division factor equals 12, the Timer 0 clock frequency equals CPU clock frequency divided by 12. This register controls the time out value of WDT as the following table. The time out value is shown as follows and the default is set to maximum: WD2 WD1 WD0 Time Out Value 0 0 0 131072 0 0 1 1048576 0 1 0 8388608 0 1 1 67108864 1 0 0 134217728 1 0 1 268435456 1 1 0 536870912 1 1 1 1073741824 A second 16-bit Watchdog Timer (WDT2) clocked by the independent nonstop SIOSC (32KHz) is included. WDT2 can be used to generate interrupt/wakeup timing from STOP/SLEEP mode, or generate software reset. WDT2CF (0xA0D8h) WatchDog Timer 2 Configure Registers R/W (0xA7) TB Protected 7 6 5 4 RD - WDT2REN WDT2RF WDT2IEN WDT2CS[2-0] WDT2IF WR WDT2CLR WDT2REN WDT2RF WDT2IEN WDT2CS[2-0] WDT2IF WDT2CLR WDT2REN WDT2RF WDT2IEN WDT2CS[2-0] 3 2 1 0 WDT2 Counter Clear Writing “1” to WDT2CLR clears the WDT2 count to 0. It is self-cleared by hardware. WDT2 Reset Enable WDT2REN=1 configures WDT2 to perform software reset. WDT2 Reset Flag WDT2RF is set to “1” after a WDT2 reset occurs. This must be cleared by software by writing “0”. WDT2 Interrupt Enable WDT2IEN=1 enables WDT2 interrupt. WDT2 Clock Scaling WDT2CS[2-0] Clock SIOSC Divider WDT2Period (SIOSC=32K) 000 2^8 8 msec 001 2^8 8 msec 010 2^8 8 msec 011 2^8 8 msec 100 2^12 128 msec 101 2^13 256 msec 110 2^14 512 msec 111 2^15 1024 msec WDT2IF WDT2 Interrupt Flag WDT2IF is set to “1” after a WDT2 interrupt. This must be cleared by software by writing “0”. Please note the longest effective time WDT2 can be set is approximately 18 hours. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 21 IS31CS8974 WDT2L (0xA0D9h) Watchdog Timer 2 Time Out Value Low Byte RW (0xFF) TB Protected 7 6 5 4 3 RD WDT2CNT[7-0] WR WDT2[7-0] 2 1 0 1 0 WDT2H (0xA0DAh) Watchdog Timer 2 Time Out Value High Byte RW (0x0F) TB Protected 7 6 5 4 3 RD WDT2CNT[15-8] WR WDT2[15-8] 2 WDT2L and WDT2H hold the time out value for watchdog timer 2. When the counter reaches WDT2 time out value, an interrupt or reset is generated. Reading this register returns the current count value. A third Watchdog Timer (WDT3) is also included for further enhancement of fault recovery. WDT3 cannot be disabled in normal mode. The clock scaling of WDT3 is the same as WDT2. WDT2CS[2-0] 000 001 010 011 100 101 110 111 Clock SIOSC Divider 2^8 2^8 2^8 2^8 2^12 2^13 2^14 2^15 WDT3 Period (SIOSC=32K) 8 msec 8 msec 8 msec 8 msec 128 msec 256 msec 512 msec 1024 msec Therefore the longest time of WDT3 is about 1 second time 2^16 approximately 18 hours. In default setting, the time of WDT3 is 8 msec time 2^8 approximately 2 seconds. WDT3CF (0xA0DBh) WatchDog Timer 3 Configure Registers R/W (0xD1) TB Protected 7 6 5 4 3 2 1 0 RD - - - WDT3RF WR WDT3CLR - - WDT3RF WDT3CLR WDT3RF WDT3 Counter Clear Writing “1” to WDT3CLR clears the WDT3 count to 0. It is self-cleared by hardware. WDT3 Reset Flag WDT3RF is set to “1” after a WDT3 reset occurs. This must be cleared by software by writing “0”. WDT3L (0xA0DCh) Watchdog Timer 3 Time Out Value Low Byte RO (0xFF) TB Protected 7 6 5 4 3 RD WDT3CNT[7-0] WR WDT3[7-0] 2 1 0 1 0 WDT3H (0xA0DDh) Watchdog Timer 3 Time Out Value High Byte RO (0x00) TB Protected 7 6 5 4 3 RD WDT3CNT[15-8] WR WDT3[15-8] 2 WDT3L and WDT3H hold the time out value for watchdog timer 3. When the counter reaches WDT2 time out value, a reset is generated. Reading this register returns the current count value. 1.9 System Timers – T0 and T1 The CPU contains three 16-bit timers/counters, Timer 0, Timer 1 and Timer 2. In timer mode, Timer 0, Timer 1 registers are incremented every 12 SYSCLK period when the appropriate timer is enabled. In the timer mode, Timer 2 registers are incremented every 12 or 2 SYSCLK period (depending on the operating mode). In the counter mode, Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 22 IS31CS8974 the timer registers are incremented every falling edge on their corresponding inputs: T0, T1, and T2. These inputs are read every SYSCLK period. Timer 0 and Timer 1 are fully compatible with the standard 8051. Timer 0 and 1 are controlled by TCON (0x88) and TMOD (0x89) registers while each timer consists of two 8-bit registers TH0 (0x8C), TL0 (0x8A), TH1 (0x8D), TL1 (0x8B). TCON (0x88h) Timer 0 and 1 Configuration Register 7 6 5 4 3 2 1 0 RD TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 WR TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TF1 TR1 TF0 TR0 IE1,IT1,IE0,IT0 Timer 1 Overflow Interrupt Flag bit. TF1 is cleared by hardware when entering ISR. Timer 1 Run Control bit. Set to enable Timer 1, and clear to disable Timer 1. Timer 0 Overflow Interrupt Flag bit. TF0 is cleared by hardware when entering ISR. Timer 0 Run Control bit. Set to enable Timer 0, and clear to disable Timer 0. These bits are related to configurations of expanded interrupt INT1 and INT0. These are described in the Interrupt System section. TMOD (0x89h) Timer 0 and 1 Mode Control Register 7 6 5 4 3 2 1 0 RD GATE1 CT1 T1M1 T1M0 GATE0 CT0 T0M1 T0M0 WR GATE1 CT1 T1M1 T1M0 GATE0 CT0 T0M1 T0M0 GATE1 CT1 T1M1 T1M0 GATE0 CT0 T0M1 T0M0 Timer 1 Gate Control bit. Set to enable external T1 to function as gating control of the counter. Counter or Timer Mode Select bit. Set CT1 to access external T1 as the clock source. Clear CT1 to use internal clock. Timer 1 Mode Select bit. Timer 1 Mode Select bit. Timer 0 Gate Control bit. Set to enable external T0 to function as gating control of the counter. Counter or Timer Mode Select bit. Set CT0 to use external T0 as the clock source. Clear CT0 to use internal clock. Timer 0 Mode Select bit. Timer 0 Mode Select bit. M1 M0 Mode 0 0 0 0 1 1 1 0 2 1 1 3 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 Mode Descriptions TL serves as a 5-bit pre-scaler and TH functions as an 8-bit counter/timer. They form a 13-bit operation. TH and TL are cascaded to form a 16-bit counter/timer. TL functions as an 8-bit counter/timer and auto-reloads from TH. TL functions as an 8-bit counter/timer. TH functions as an 8bit timer, which is controlled by GATE1. Only Timer 0 can be configured in Mode 3. When this happens, Timer 1 can only be used where its interrupt is not required. 23 IS31CS8974 Mode 0 In this mode, TL serves as a 5-bit pre-scaler and TH functions as an 8-bit counter/timer, together working as a 13bit counter/timer. The Mode 0 operation is shown in the following diagram. CKCON [TxCKDCTL] DIV 4 Or 12 CPUCLK CT 0 MUX External T0 or T1 TL 5-Bit 1 TH 8-Bit OV INT FLAG TF0/TF1 TR GATE Mode 1 Mode 1 operates the same way Mode 0 does, except TL is configured as 8-bit and thus forming a 16-bit counter/timer. This is shown as the following diagram. CT CKCON [TxCKDCTL] DIV 4 or 12 CPUCLK 0 MUX External T0 or T1 TL 8-Bit 1 TH 8-Bit OV INT FLAG TF0/TF1 TR GATE Mode 2 Mode 2 configures the timer as an 8-bit re-loadable counter. The counter is TL while TH stores the reload data. The reload occurs when TL overflows. The operation is shown in the following diagram: CT CKCON [TxCKDCTL] DIV 4 or 12 CPUCLK 0 MUX External T0 or T1 1 TR GATE TL 8-Bit OV INT FLAG TF0/TF1 RELOAD TH 8-Bit Mode 3 Mode 3 is a special mode for Timer 0 only. In this mode, Timer 0 is configured as two separate 8-bit counters. TL0 uses control and interrupt flags of Timer 0whereas TH0 uses control and interrupt flag of Timer 1. Since Timer 1’s control and flag are occupied, Timer 2 can only be used for counting purposes such as Baud rate generating while Timer 0 is in Mode 3. The operation flow of Mode 3 is shown in the following diagram. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 24 IS31CS8974 TR1 CKCON [TxCKDCTL] TH0 8-Bit OV INT FLAG TF1 TL0 8-Bit OV INT FLAG TF0 CT0 DIV 4 or 12 CPUCLK 0 MUX 1 T0 TR0 GATE0 1.10 System Timer – T2 Timer 2 is fully compatible with the standard 8052 timer 2. Timer 2 can be used as the re-loadable counter, capture timer, or baud rate generator. Timer 2 uses five SFR as counter registers, capture registers and a control register. T2CON (0xC8h) Timer 2 Control and Configuration Register 7 6 5 4 3 2 1 0 RD TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 WR TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 TF2 Timer 2 Interrupt Flag bit. TF2 must be cleared by software. TF2 is not set when RCLK or TCLK is set (that means Timer 2 is used as an UART0 Baud rate generator). EXF2 T2EX Falling Edge Flag bit. This bit is set when T2EX has a falling edge when EXEN2=1. EXF2 must be cleared by software. RCLK Receive Clock Enable bit 1 – UART0 receiver is clocked by Timer 2 overflow pulses 0 – UART0 receiver is clocked by Timer 1 overflow pulses TCLK Transmit Clock Enable bit 1 – UART0 transmitter is clocked by Timer 2 overflow pulses 0 – UART0 transmitter is clocked by Timer 1 overflow pulses EXEN2 T2EX Function Enable bit. 1 – Allows capture or reload as T2EX falling edge appears 0 – Ignore T2EX events TR2 Start/Stop Timer 2 Control bit 1 – Start 0 – Stop CT2 Timer 2 Timer/Counter Mode Select bit 1 – External event counter uses T2 pin as the clock source 0 – Internal clock timer mode CPRL2 Capture/Reload Select bit 1 – Use T2EX pin falling edge for capture 0 – Automatic reload on Timer 2 overflow or falling edge of T2EX (when EXEN2=1). If RCLK or TCLK is set (Timer 2 is used as a baud rate generator), this bit is ignored and an automatic reload is forced on Timer 2 overflows. Timer 2 can be configured in three modes of operations –Auto-reload Counter, Capture Timer, or Baud Rate Generator. These modes are defined by RCLK, TCLK, CPRL2 and TR2 bits of T2CON registers. The definition is illustrated in the following table: RCLK or TCLK CPRL2 TR2 0 0 1 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 Mode Descriptions 16-bit Auto-reload Counter mode. Timer 2 overflow sets the TF2 interrupt flag and TH2/TL2 is reloaded with RLDH/RLHL register. 25 IS31CS8974 0 1 1 1 X 1 X X 0 16-bit Capture Timer mode. Timer 2’s overflow sets TF2 interrupt flag. When EXEN2=1, TH2/TL2 content is captured into RLDH/RLDL when T2EX falling edge occurs. Baud Rate Generator mode. Timer 2’s overflow is used for configuring UART0. Timer 2 is stopped. The block diagram of the Timer 2 operating in Auto-reload Counter and Capture Timer modes are shown in the following diagram: External T2 and External T2EX are tied together in this product. CT2 CPUCLK DIV 12 MUX External T2 TR2 RELOAD External T2EX FALLING DET T2EXF T2OV TL2:TH2 16-Bit T2EXF INT FLAG TF2 CPRL2 CAPTURE RLDL:RLDH 16-Bit EXEN2 The block diagram of the Timer 2 operating in Baud Rate Generator is shown in the following diagram: DIV 2 MUX CPUCLK External T2 DIV 2 T2OV TL2:TH2 16-Bit TR2 MUX T1OV MUX PCON.SMOD0 DIV 16 RXC DIV 16 TXC RCLK External T2EX FALLING DET INT FLAG TF2 EXEN 2 MUX RELOAD RLDL:RLDH 16-Bit TCLK System Timer – T3 and T4 1.11 Both Timer 3 and Timer 4 are simple 16-Bit reload timers or free-run counters and are clocked by the system clock. The block diagram is shown as below. TM=1 AUTO RELOAD CPU CPU TM=0 FREE-RUN T[15-0] RELOAD TIEN TR TIEN INTERRUPT COUNTER[15-0] OV TF SYSCLK Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 TR SYSCLK TL[15-0] OV = COUNTER[15-0] INTERRUPT TF 26 IS31CS8974 T34CON (0xCFh) Timer 3 and Timer 4 Control and Status Register 7 6 5 4 3 2 1 0 RD TF4 TM4 TR4 T4IEN TF3 TM3 TR3 T3IEN WR TF4 TM4 TR4 T4IEN TF3 TM3 TR3 T3IEN TF4 Timer 4 Overflow Interrupt Flag bit. TF4 is set by hardware when overflow condition occurs. TF4 must be cleared by software. Timer 4 Mode Control bit. TM4 = 1 set timer 4 as auto reload, and TM4=0 set timer 4 as free-run. Timer 4 Run Control bit. Set to enable Timer 4, and clear to stop Timer 4. Timer 4 Interrupt Enable bit. T4IEN=0 disable the Timer 4 overflow interrupt T4IEN=1 enable the Timer 4 overflow interrupt Timer 3 Overflow Interrupt Flag bit. TF3 is set by hardware when overflow condition occurs. TF3 must be cleared by software. Timer 3 Mode Control bit. TM3 = 1 set timer 3 as auto reload, and TM3=0 set timer 3 as free-run. Timer 3 Run Control bit. Set to enable Timer 3, and clear to stop Timer 3. Timer 3 Interrupt Enable bit. T3IEN=0 disable the Timer 3 overflow interrupt T3IEN=1 enable the Timer 3 overflow interrupt TM4 TR4 T4IEN TF3 TM3 TR3 T3IEN TL3 (0xAEh) Timer 3 Low Byte Register 0 R/W 00000000 7 6 5 4 RD T3[7-0] WR T3[7-0] 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 TH3 (0xAFh) Timer 3 High Byte Register 0 R/W 00000000 7 6 5 4 RD T3[15-8] WR T3[15-8] TL4 (0xACh) Timer 4 Low Byte Register 0 R/W 00000000 7 6 5 4 RD T4[7-0] WR T4[7-0] TH4 (0xADh) Timer 4 High Byte Register 0 R/W 00000000 7 6 5 4 RD T4[15-8] WR T4[15-8] T3[15-0] and T4[15-0] function differently when been read or written. When written in auto-reload mode, its reload value register is written, and in free-run mode, the counter value is written immediately. When been read, the return value is always the present counter value. There is no snapshot buffer in the read operation, so software should always read the high byte then the low byte. 1.12 System Timer – T5 T5 is a 24-Bit simple timer. It can select four different clock sources and can be used for extended sleep mode wake up. The clock sources include IOSC and SIOSC. T5 can be configured either as free-run mode or auto-reload mode. Timer 5 does not depend on the SYSCLK, therefore it continues to count under STOP or SLEEP mode if the clock source is present. The following diagram shows the block diagram of Timer 5. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 27 IS31CS8974 TM=1 AUTO RELOAD CPU IOSC XOSC RTC SOSC T5[23-0] TM=0 FREE-RUN CPU 00 01 T5CLK 10 MUX 11 RELOAD T5CLK T5SEL[1-0] TIEN TIEN TR INTERRUPT COUNTER[23-0] OV TR TF T5CLK T5CLK T5[23-0] OV = COUNTER[23-0] INTERRUPT TF T5CON (0xA068h) Timer 5 Control and Status Register 7 6 5 4 3 2 1 0 RD TF5 T5SEL[1] T5SEL[0] TM5 TR5 - - T5IEN WR TF5 T5SEL[1] T5SEL[0] TM5 TR5 - - T5IEN TF5 T5SEL[1-0] TM5 TR5 T5IEN Timer 5 Overflow Interrupt Flag bit. TF5 is set by hardware when overflow condition occurs. TF5 must be cleared by software. Timer 5 Clock Selection bits. T5SEL[1-0] = 00, IOSC T5SEL[1-0] = 01, IOSC T5SEL[1-0] = 10, SIOSC T5SEL[1-0] = 11, SIOSC Timer 5 Mode Control bit. TM5=1 set timer 5 as auto reload, and TM5=0 set timer 5 as free-run. Timer 5 Run Control bit. Set to enable Timer 5, and clear to stop Timer 5. Timer 5 Interrupt Enable bit. T5IEN=0 disable the Timer 5 overflow interrupt T5IEN=1 enable the Timer 5 overflow interrupt TL5 (0xA069) Timer5 Low Byte Register 0 R/W 00000000 7 6 5 4 RD T5[7-0] WR T5[7-0] 3 2 1 0 3 2 1 0 3 2 1 0 TH5 (0xA06A) Timer5 Medium Byte Register 0 R/W 00000000 7 6 5 4 RD T5[15-8] WR T5[15-8]] TT5 (0xA063) Timer5 High Byte Register 0 R/W 00000000 7 6 5 4 RD T5[23-16] WR T5[23-16] T5[23-0] functions differently when been read or written. When written in auto-reload mode, its reload value register is written, and in free-run mode, the counter value is written immediately. When been read, the return value is always the present counter value. There is no snapshot buffer in the read operation, so software should always read the high byte then the low byte. 1.13 Multiplication and Division Unit (MDU) MDU provides acceleration on unsigned integer operations of 16-bit multiplications, 32-bit division, and shifting and normalizing operations. The following table shows the execution characteristics of these operations. The MDU does not contain the operation completion status flag. Therefore the most efficient utilization of MDU uses NOP delay for the required clock time of the MDU operation types. The number of the clock cycles required for each operation is shown in the following table and it is counted from the last write of the writing sequence. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 28 IS31CS8974 Operations Result Reminder # of Clock Cycle 32-bit division by 16-bit 32-bit 16-bit 17 16-bit division by 16-bit 16-bit 16-bit 9 16-bit multiplication by 16-bit 32-bit - 10 32-bit normalization - - 3 – 20 32-bit shift left/right - - 3 – 18 The MDU is accessed through MD0 to MD5 that contains the operands and the results, and the operation is controlled by ARCON register. ARCON (0xFF) MDU Control R/W 00000000 7 6 5 4 3 2 1 0 RD MDEF MDOV SLR SC4 SC3 SC2 SC1 SC0 WR MDEF MDOV SLR SC4 SC3 SC2 SC1 SC0 MDEF MDU Error Flag bit. Set by hardware to indicate MDx being written before the previous operation completes. MDEF is automatically cleared after reading ARCON. MDU Overflow Flag bit. MDOV is set by hardware if dividend is zero or the result of multiplication is greater than 0x0000FFFFh Shift Direction Control bit. SLR = 1 indicates a shift to the right and SLR =0 indicates a shift to the left. Shift Count Control and Result bit. If SC0-4 is written with 00000, the normalization operation performed by MDU. When the normalization is completed, SC4-0 contains the number of shift performed in the normalization. If SC4-0 is written with a non-zero value, then the shift operation is performed by MDU with the number of shift specified by SC40 value. MDOV SLR SC4-0 MD0 (0xF9) MDU Data Register 0 R/W 00000000 7 6 5 4 RD MD0[7-0] WR MD0[7-0] 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 MD1 (0xFA) MDU Data Register 1 R/W 00000000 7 6 5 4 RD MD1[7-0] WR MD1[7-0] MD2 (0xFB) MDU Data Register 2 R/W 00000000 7 6 5 4 RD MD2[7-0] WR MD2[7-0] MD3 (0xFC) MDU Data Register 3 R/W 00000000 7 6 5 4 RD MD3[7-0] WR MD3[7-0] MD4 (0xFD) MDU Data Register 4 R/W 00000000 7 6 5 4 RD MD4[7-0] WR MD4[7-0] Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 29 IS31CS8974 MD5 (0xFE) MDU Data Register 5 R/W 00000000 7 6 5 4 3 RD MD5[7-0] WR MD5[7-0] 2 1 0 MDU operation consists of three phases. 1. Loading MD0 to MD5 data registers in an appropriate order depending on the operation. 2. Execution of the operations. 3. Reading result from MD0 to MD5 registers. The following list shows the MDU read and write sequences. Each operation has its unique writing sequence and reading sequence of MD0 to MD5 registers therefore a precise access sequence is required. Division – 32-bit divide by 16-bit or 16-bit divide by 16-bit Follow the following write-sequence. The first write of MD0 resets the MDU and initiates the MDU error flag mechanism. The last write incites calculation of MDU. Write MD0 with Dividend LSB byte Write MD1 with Dividend LSB+1 byte Write MD2 with Dividend LSB+2 byte (ignore this step for 16-bit divide by 16-bit) Write MD3 with Dividend MSB byte (ignore this step for 16-bit divide by 16-bit) Write MD4 with Divisor LSB byte Write MD5 with Divisor MSB byte Then follow the following read-sequence. The last read prompts MDU for the next operations. Read MD0 with Quotient LSB byte Read MD1 with Quotient LSB+1 byte Read MD2 with Quotient LSB+2 byte (ignore this step for 16-bit divide by 16-bit) Read MD3 with Quotient MSB byte (ignore this step for 16-bit divide by 16-bit) Read MD4 with Remainder LSB byte Read MD5 with Remainder MSB byte Read ARCON to determine error or overflow condition Please note if the sequence is violated, the calculation may be interrupted and result in errors. Multiplication – 16-bit multiply by 16-bit Follow the following write sequence. Write MD0 with Multiplicand LSB byte Write MD4 with Multiplier LSB byte Write MD1 with Multiplicand MSB byte Write MD5 with Multiplier MSB byte Then follow the following read sequence. Read MD0 with Product LSB byte Read MD1 with Product LSB+1 byte Read MD2 with Product LSB+2 byte Read MD3 with Product MSB byte Read ARCON to determine error or overflow condition Normalization – 32-bit Normalization is obtained with integer variables stored in MD0 to MD3. After normalization, all leading zeroes are removed by shift left operations. To start the normalization operation, SC4-0 in ARCON is first written with 00000. After completion of the normalization, SC4-0 is updated with the number of leading zeroes and the normalized result is restored on MD0 to MD3. The number of the shift of the normalization can be used as exponents. The following write sequence should be followed. The last write to ARCON initiates the normalization operations by MDU. Write MD0 with Operand LSB byte Write MD1 with Operand LSB+1 byte Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 30 IS31CS8974 Write MD2 with Operand LSB+2 byte Write MD3 with Operand MSB byte Write ARCON with SC4-0 = 00000 Then follow the following read sequence. Read MD0 with Result LSB byte Read MD1 with Result LSB+1 byte Read MD2 with Result LSB+2 byte Read MD3 with Result MSB byte Read SC[4-0] from ARCON for normalization count or error flag Shift – 32-bit Shift is done with integer variables stored in MD0 to MD3. To start the shift operation, SC4-0 in ARCON is first written with shift count and SLR with shift direction. After completion of the Shift, the result is stored back to MD0 to MD3.The following write sequence should be followed. The last write to ARCON initiates the normalization operations by MDU. Write MD0 with Operand LSB byte Write MD1 with Operand LSB+1 byte Write MD2 with Operand LSB+2 byte Write MD3 with Operand MSB byte Write ARCON with SC4-0 = Shift count and SLR with shift direction Then follow the following read sequence. Read MD0 with Result LSB byte Read MD1 with Result LSB+1 byte Read MD2 with Result LSB+2 byte Read MD3 with Result MSB byte Read ARCON’s for error flag MDU Flag The error flag (MDEF) of MDU indicates improperly performed operations. The error mechanism starts at the first MD0 write and finishes with the last read of MD result register. MDEF is set if current operation is interrupted or restarted by improper write of MD register before the operation completes. MDEF is cleared if the operations and proper write/read sequences successfully complete. The overflow flag (MDOV) of MDU indicates an error of operations. MDOV is set if The divisor is zero Multiplication overflows Normalization operation is performed on already normalized variables (MD3.7 =1) 1.14 Serial Port – UART0 UART0 is full duplex and fully compatible with the standard 8052 UART. The receive path of the UART0 is double-buffered that can commence reception of second byte before previously received byte is read from the receive register. Writing to SBUF0 loads the transmit register while reading SBUF0, reads a physically separate receive register. The UART0 can operate in four modes: one synchronous (Mode 0) and three asynchronous modes (Mode 1, 2, and 3). Mode 2 and Mode 3 share a special provision for multi-processor communications. This feature is enabled by setting SM2 in SCON0 register. The master processor first sends out an address byte, which identifies the slave. An address byte differs from a data byte in the 9 th bit: 1 defines an address byte whereas 0 defines a data byte. When SM2 is set to 1, no slave can be interrupted by a data byte. The addressed slave clears its SM2 bit and prepares to receive the following incoming data bytes. The slaves that are not addressed leave their SM2 set and ignore the incoming data. The UART0-related registers are SBUF0, SCON0, PCON, IE, and IP. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 31 IS31CS8974 SCON0 (0x98h) UART0 Configuration Register 7 6 5 4 3 2 1 0 RD SM0 SM1 SM2 REN TB8 RB8 TIF RIF WR SM0 SM1 SM2 REN TB8 RB8 TIF RIF SM0, SM1 SM2 REN UART Operation Mode MODE SM0 SM1 0 0 0 1 0 1 2 1 0 3 1 1 Description Synchronous Shift Register Mode Baud rate = SYSCLK/12 8-Bit UART Mode Baud rate = Timer 1 or Timer 2 overflow rate. This is selected in T2CON registers. 9-Bit UART Mode, fix baud rate Baud rate = SYSCLK/64 (PCON.SMOD0 = 0) or SYSCLK/32 (PCON.SMOD0 = 1) 9-Bit UART Mode, variable baud rate Baud rate = Timer 1 or Timer 2 overflow rate. This is selected in TCON registers. Set to enable a multiprocessor communication as a slave device. Set REN=1 to enable UART PMM switch back function. REN=0 disables this function. In PMM mode, if REN=1, then any transition on RX of UART triggers the exit of PMM mode into normal mode. The transmit-value of 9th bit in 9-bit UART mode (mode 2 and mode 3). Set or cleared by CPU depending on the function of the 9th bit as a parity check bit or a multiprocessor. The receive-value of 9th bit in 9-bit UART mode (mode 2 and mode 3). Set or cleared by hardware. Transmit Interrupt Flag bit. Set by hardware after completion of a serial transmission and must be cleared by software. The interrupt enable bit is located in IE (0xA8) and the interrupt priority is located in IP (0xB8). Receive Interrupt Flag bit. Set by hardware after completion of a serial reception and must be cleared by software. The interrupt enable bit is located in IE (0xA8) and the interrupt priority is located in IP (0xB8). TB8 RB8 TIF RIF SBUF0 (0x99h) UART0 Data Buffer Register 7 6 5 4 3 RD RB[7-0] WR TB[7-0] 2 1 0 SBUF0 is used for both transmission and reception. Writing a data byte into SBUF0 puts this data in UART0’s transmit buffer and starts a transmission. Reading a byte from SBUF means data being read from the UART0’s receive buffer. Mode 0 Mode 0 is a simple synchronous shift register mode. TXD0 outputs the shift clock, which is fixed at CPUCLK/12. RXD0 is a bidirectional I/O port that serves as a data-shifting port. To utilize this mode, TXD0 pin must be enabled as an output pin, while RXD0 needs to be configured as an open-drain type of I/O port. The shift data changes at the rising edge of the shift clock and is valid at the falling edge of the shift clock. The transmission starts when anew byte is written in SBUF0 as TI is cleared to 0. When the byte is transmitted, TI is set and the UART0 waits for the next byte to be transmitted. The reception is initiated by setting REN=1 and RI cleared to 0. When a byte is received, RI is set by UART0. Mode 1 8-bit UART mode. RXD0 is the serial input and TXD0 is the serial output. To utilize this mode, the corresponding RXD0 and TXD0 pin configuration should also be set correctly. 10-bit data (including a Start bit, 8 data bit, and a Stop bit) are transferred. For UART0, the baud rate is set by Timer 1 or Timer 2 overflow rate. The control is determined by SMOD0.PCON, and RCLK.T2CON, TCLK.T2CON. When SMOD0.PCON is 1, Timer 1 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 32 IS31CS8974 overflow is selected, and SMOD0.PCON is 0, Timer 1 overflow rate divided by 2 is selected. And if RCLK.T2CON, or TCLK.T2CON is set, the Timer 2 overflow rate is selected and overwrites the SMOD0 setting. Mode 2 9-bit UART mode. RXD0 is the serial input and TXD0 is the serial output. To utilize this mode, the corresponding RXD0 and TXD0 pins should be configured correctly. 11-bit data including a Start bit (always 0), 8 data bits, a programmable 9th bit, and a Stop bit (always 1) are transferred. The 9 th bit can be configured as a parity bit configured by software through TB8 in SCON0. The received 9th bit can be read from TB8. The software determines the correctness of the parity check. The baud rate in Mode 2 is fixed at 1/32 or 1/64 of CPU clock. This is controlled by SMOD0 in PCON register. Mode 3 Similar to Mode 2 (9-bit UART mode). RXD0 is the serial input and TXD0 is the serial output. To utilize this mode, the corresponding RXD0 and TXD0 pins should also be configured properly. 11-bit data including a Start bit (always 0), 8 data bits, a programmable 9th bit, and a Stop bit (always 1) are transferred. The 9th bit can serve as a parity bit configured by software through TB8 in SCON0. The received 9th bit can be read from TB8. The software determines the correctness of the parity check. The mechanism of the baud rate control in Mode 3 is similar to that in Mode 1,which is determined by Timer 1 or Timer 2 overflow and is set by SMOD0, and T2CON. 1.15 I2C Master The I2C master controller provides the interface to I2C slave devices. It can be programmed to operate with arbitration and clock synchronization to allow it to operate in multi-master configurations. The master uses SCL and SDA pins. The controller contains a built-in 8-bit timer to allow various I2C bus speed. The maximum I2C master bus speed is limited to SYSCLK/12. I2CMTP (0xF7h) I2C Master Time Period R/W 00000000 7 6 5 4 3 RD I2CMTP[7-0] WR I2CMTP[7-0] 2 1 0 This register set the frequency of I2C bus clock. If I2CMTP[7-0] is equal to or larger than 0x01, SCL_FREQ = SYSCLK_FREQ/8/(1 + I2CMTP). If I2CMTP[7-0] = 0x00, SCL_FREQ = SYSCLK_FREQ /12. I2CMSA (0xF4) I2C Master Slave Address R/W 00000000 7 6 5 4 3 RD SA[6-0] WR SA[6-0] 2 1 0 RS RS I2C SA[6-0] RS Slave Address. SA[6-0] defines the slave address the master uses to communicate. Receive/Send Bit. RS determines if the following operation is to RECEIVE (RS=1) or SEND (RS=0). I2CMBUF (0xF6) I2C Master Data Buffer Register R/W 00000000 7 6 5 4 3 RD RD[7-0] WR TD[7-0] 2 1 0 I2CMBUF functions as a transmit-data register when written and as a receive-data register when read. When written, TDis sent to the bus by the next SEND or BURST SEND operations. TD[7] is sent first. When read, RD contains the 8-bit data received from the bus upon the last RECEIVE or BURST RECEIVE operation. I2CMCR (0xF5) I2C Master Control and Status Register R/W 00000000 RD WR 7 6 5 4 3 2 1 0 CLEAR BUSBUSY INFILEN IDLE - ARBLOST HS DATAACK ACK ADDRACK STOP ERROR START BUSY RUN The I2CMCR register is used for setting control when it is written, and as a status signal when read. CLEAR Reset I2C Master State Machine Set CLEAR=1 will reset the state machine. CLEAR is self-cleared when reset is completed. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 33 IS31CS8974 INFILEN Input Noise Filter Enable. When IFILEN is set, pulses shorter than 50 nsec on inputs of SDA and SCL are filtered out. IDLE This bit indicates that I2C master is in the IDLE mode. BUSY This bit indicates that I2C master is receiving or transmitting data, and other status bits are not valid. BUSBUSY This bit indicates that the external I2C bus is busy and access to the bus is not possible. This bit is set/reset by START and STOP conditions. ERROR This bit indicates that an error occurs in the last operation. The errors include slave address was not acknowledged, or transmitted data is not acknowledged, or the master controller loses arbitration. ADDRERR This bit is automatically set when the last operation slave address transmitted is not acknowledged. DATAERR This bit is automatically set when the last operation transmitted data is not acknowledged. ARBLOST This bit is automatically set when the last operation I2C master controller loses the bus arbitration. START, STOP, RUN and HS, RS, ACK bits are used to driveI2C Master to initiate and terminate a transaction. The Start bit generates START, or REPEAT START protocol. The Stop bit determines if the cycle stops at the end of the data cycle or continues to a burst. To generate a single read cycle, the designated address is written in SA, RS is set to 1, ACK=0, STOP=1, START=1, RUN=1 are set in I2CMCR to perform the operation and then STOP. When the operation is completed (or aborted due to errors), I2C master generates an interrupt. The ACK bit must be set to 1. This causes the controller to send an ACK automatically after each byte transaction. The ACK bit must be reset when set to 0 when the master operates in receive mode and not to receive further data from the slave devices. The following table lists the permitted control bits combinations in master IDLE mode. HS RS ACK STOP START RUN 0 0 - 0 1 1 0 0 - 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 OPERATIONS START condition followed by SEND. Master remains in TRANSMITTER mode START condition followed by SEND and STOP START condition followed by RECEIVE operation with negative ACK. Master remains in RECEIVER mode START condition followed by RECEIVE and STOP START condition followed by RECEIVE. Master remains in RECEIVER mode Illegal command Master Code sending and switching to HS mode The following table lists the permitted control bits combinations in master TRANSMITTER mode. HS RS ACK STOP START RUN 0 - - 0 0 1 0 0 - - 1 1 0 0 0 1 0 0 - 0 1 1 0 1 - 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 OPERATIONS SEND operation. Master remains in TRANSMITTER mode STOP condition SEND followed by STOP condition REPEAT START condition followed by SEND. Master remains in TRANSMITTER mode REPEAT START condition followed by SEND and STOP condition REPEAT START condition followed by RECEIVE operation with negative ACK. Master remains in TRANSMITTER mode REPEAT START condition followed by SEND and STOP condition. REPEAT START condition followed by RECEIVE. Master remains in RECEIVER mode. Illegal command 34 IS31CS8974 The following table lists the permitted control bits combinations in master RECEIVER mode. HS RS ACK STOP START RUN 0 - 0 0 0 1 0 0 - 0 1 1 0 0 0 1 0 - 1 0 0 1 0 - 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 - 0 1 1 0 0 - 1 1 1 OPERATIONS RECEIVE operation with negative ACK. Master remains in RECEIVE mode STOP condition RECEIVE followed by STOP condition RECEIVE operation. Master remains in RECEIVER mode Illegal command REPEAT START condition followed by RECEIVE operation with negative ACK. Master remains in RECEIVER mode REPEAT START condition followed by RECEIVE and STOP conditions REPEAT START condition followed by RECEIVE. Master remains in RECEIVER mode REPEAT START condition followed by SEND. Master remains in TRANSMITTER mode. REPEAT START condition followed by SEND and STOP conditions. All other control-bit combinations not included in three tables above are NOP. In Master RECEIVER mode, STOP should be generated only after data negative ACK executed by Master or address negative ACK executed by slave. Negative ACK means SDA is pulled low when the acknowledge clock pulse is generated. I2CMTO (0xC3) I2CTime Out Control Register R/W 00000000 7 RD WR 5 4 I2CMTOF I2CMTOEN I2CMTOEN I2CMTOF I2CMTO[6-0] 1.16 6 3 2 1 0 I2CMTO[6-0] I2CMTO[6-0] I2CM Time Out Enable I2CM Time Out Flag This bit is set when a time out occurs. It is cleared when I2CM CLEAR command is issued. I2CM Time Out Setting The TO time is set to (I2CMTO[6-0]+1)*8*BT. When time out occurs, an I2CM interrupt will be generated. Checksum/CRC Accelerator To enhance the performance, a hardware Checksum/CRC Accelerator is included and closely coupled with CPU. This provides most commonly used checksum and CRC operation for 8/16/24/32-bit data width. For 8-bit data, one SYSCLK cycle is used, and for 16-bit data two cycles is used, and 32-bit takes four cycles. CCCFG (0xA078h) Checksum/CRC Accelerator Configuration Register R/W ( 0x00) 7 6 5 4 3 2 1 0 - - BUSY RD DWIDTH[1-0] REVERSE NOCARRY SEED WR DWIDTH[1-0] REVERSE NOCARRY SEED DWIDTH[1-0] REVERSE Data Input Width 00 – set input as 8-bit wide 01 – set input as 16-bit wide 10 – set the input as 24-bit wide 11 – set the input as 32-bit wide Reverse Input MSB/LSB Sequence REVERSE=0 is for LSB first operations. REVERSE=1 is for MSB first operation. The reverse order is based on the data width. For example, if the data width is 32-bit, and REVERSE=1, then CCDATA[0] holds MSB, and CCDATA[31] holds LSB. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 CRCMODE[2-0] 35 IS31CS8974 REVERSE dose not affect output result and SEED ordering i.e. CCDATA[31] always holds MSB, CCDATA[0] always holds MSB. The following table shows the MSB/LSB relationship DWIDTH REVERSE=0 REVERSE=1 0 CRCIN[7-0] = CCDATA[7-0] CRCIN[7-0] = CCDATA[0-7] 1 CRCIN[15-0] = CCDATA[15-0] CRCIN[15-0] = CCDATA[0-15] 2 CRCIN[23-0] = CCDATA[23-0] CRCIN[23-0] = CCDATA[0-23] 3 CRCIN[31-0] = CCDATA[31-0] CRCIN[31-0] = CCDATA[0-31] NOCARRY Carry Setting for Checksum NOCARRY=0 uses previous carry result for new result NOCARRY=1 discard previous carry result. SEED Seed Entry SEED=1 results writing into CCDATA to become SEED value SEED=0 for normal data inputs. Please note, the MSB/LSB ordering of SEED entry from CCDATA is not affected by REVERSE. CRCMODE[2-0] Defines CRC/Checksum Mode 000 – Accelerator is disabled and clock gated off 001 – 8-bit Checksum 010 – 32-bit Checksum 011 – CRC-16 (IBM 0x8005) X16+X15+X2+1 100 – CRC-16 (CCITT 0x1021) X16+X12+X5+1 101 – CRC-32 (ANSI 802.3 0x104C11DB7) X32+X26+C23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1 110 – Reserved 111 – CRC and Checksum Clear Writing “111” to CRCMODE[1-0] resets the CS/CRC states and restore default seed value (for checksum, seed value=0x00 or 0x00000000, for CRC seed value = 0xFFFF or 0xFFFFFFF). Writing “111” does not affect the previously set mode selection. BUSY CRC Status BUSY=1 indicates the results is not yet completed. Since only up to two cycles are used to calculate the Checksum or CRC, there is no need to check BUSY status before next data entry and reading the results. CCDATA registers are the data I/O port for Checksum/CRC Accelerator. For 8-bit data width only CCDATA[7-0] should be used. For data width wider than 8-bit, high byte should always be written first, writing the low byte (CCDATA0) completes the data entry and starts the calculations. When SEED=1, the data been written goes to CS or CRC seed value. The SEED value entry bit ordering is not affected by REVERSE setting. The result of accelerator can be directly read out from CCDATA registers also not affected by REVERSE setting. CCDATA0 (0xA07Ch) Chceksum/CRC Data Register 0 R/W 00000000 7 6 5 4 3 RD CCDATA[7-0] WR CCDATA[7-0] 2 1 0 2 1 0 CCDATA1 (0xA07Dh) Chceksum/CRC Data Register 1 R/W 00000000 7 6 5 4 3 RD CCDATA[15-0] WR CCDATA[15-0] Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 36 IS31CS8974 CCDATA2 (0xA07Eh) Chceksum/CRC Data Register 2 R/W 00000000 7 6 5 4 3 RD CCDATA[23-16] WR CCDATA[23-16] 2 1 0 2 1 0 CCDATA3 (0xA07Fh) Chceksum/CRC Data Register 3 R/W 00000000 7 6 5 4 3 RD CCDATA[31-24] WR CCDATA[31-24] 1.17 Break Point and Debug Controller The CPU core also includes a Break Point Controller for software debugging purposes and handling exceptions. Program Counter break point triggers at PC address matching, and there are seven PC matching settings available. Single Step break point triggers at interaction return from an interrupt routine. Upon the matching of break point conditions, the Break Point Controller issues BKP Interrupt for handling the break points. The BKP Interrupt vector is located at 0x7080. Upon entering the BKP ISR (Break Point Interrupt Service Routine), all interrupts and counters (WDT, T0, T1, and T2) are disabled. To allow further interrupts and continuing counting, the BKP ISR must be enabled. At exiting, the BKP ISR setting must be restored to resume normal operations. BPINTF (A0E0h) Break Point Interrupt Flag Register R/W (0x00) 7 6 5 4 3 2 1 0 RD STEP_IF - - - - - PC2IF PC1IF WR STEP_IF - - - - - PC2IF PC1IF This register is for reading the Break Points interrupt flags. STEP_IF This bit is set when the Break Point conditions are met by a new instruction fetching from an interrupt routine. This bit must be cleared by software. PC2IF – PC1IF These bits are set when Break Point conditions are met by PC2 – PC1 address. These bits must be cleared by software. BPINTE (A0E1h) Break Point Interrupt Enable Register R/W (0x00) TB Protected 7 6 5 4 3 2 1 0 RD STEP_IE - - - - - PC2IE PC1IE WR STEP_IE - - - - - PC2IE PC1IE This register controls the enabling of individual Break Points interrupt. STEP_IE Set this bit to enable Single Step event break point interrupt. PC2IE – PC1IE Set these bits to enable PC2 to PC1 address match break point interrupts. BPINTC (A0E2h) Break Point Interrupt Control Register R/W (0x00) 7 6 5 4 3 2 1 0 RD - - - - - - - - WR - - - - - - - - This register is reserved for other applications. BPCTRL (A0E3h) DBG and BKP ISR Control and Status Register R/W (0xFC) 7 6 5 4 3 2 1 0 RD DBGINTEN DBGWDTEN DBGT2EN DBGT1EN DBGT0EN - - DBGGST WR DBGINTEN DBGWDTEN DBGT2EN DBGT1EN DBGT0EN - - DBGGST When entering the DBG or BKP ISR (Interrupt Service Routine), all interrupts and timers are disabled. The enabled bits are cleared by hardware reset in this register. As the interrupts and timers are disabled, the ISR can process debugging requirement in a suspended state. If a specific timer should be kept active, it must be enabled by ISR after ISR entry. Before exit of DBG and BKP ISR, the control bits should be enabled to allow the timers to resume operating. This register should be modified only in Debug ISR. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 37 IS31CS8974 DBGINTEN DBGWDEN DBGT2EN DBGT1EN DBGT0EN DBGST Set this bit to enable all interrupts (except WDT interrupt). This bit is cleared automatically at the entry of DBG and BKP ISR. Set this bit to allow ISR to be further interrupted by other interrupts. This is sometimes necessary if DBG or BKP ISR needs to use UART or I2C, for example. Set this bit to allow WDT counting during the DBG and BKP ISR. This bit should always be set before exiting the ISR. Set this bit to allow T2 counting during the DBG and BKP ISR. This bit should always be set before exiting the ISR. This bit only controls the counting but not T2 interrupt. Set this bit to allow T1 counting during the DBG and BKP ISR. This bit should always be set before exiting the ISR. This bit only controls the counting but not T1 interrupt. Set this bit to allow T0 counting during the DBG and BKP ISR. This bit should always be set before exiting the ISR. This bit only controls the counting but not T0 interrupt. This bit indicates the DBG and BKP ISR status. It is set to 1 when entering DBG and BKP ISR. It should be cleared when exiting the DBG and BKP ISR. Checking this bit allows other interrupt routine to determine whether it is a sub-service of the DBG and BKP ISR. PC1AL (A0F0h) Program Counter Break Point 1 Low Address Register R/W (0x00) 7 6 5 4 3 RD PC1AL[7-0] WR PC1AL[7-0] 2 1 0 This register defines the PC low address for PC match break point 1. PC1AH (A0F1h) Program Counter Break Point 1 High Address Register R/W (0x00) 7 6 5 4 3 RD PC1AH[7-0] WR PC1AH[7-0] 2 1 0 This register defines the PC high address for PC match break point 1. PC1AT (A0F2h) Program Counter Break Point 1 Top Address Register R/W (0x00) 7 6 5 4 3 RD PC1AT[7-0] WR PC1AT[7-0] 2 1 0 This register defines the PC top address for PC match break point 1. PC1AT:PC1HT:PC1LT together form a 24 bit compare value of break point 1 for Program Counter. PC2AL (A0F4h) Program Counter Break Point 2 Low Address Register R/W (0x00) 7 6 5 4 3 RD PC2AL[7-0] WR PC2AL[7-0] 2 1 0 1 0 This register defines the PC low address for PC match break point 2. PC2AH (A0F5h) Program Counter Break Point 2 High Address Register R/W (0x00) 7 6 5 4 3 RD PC2AH[7-0] WR PC2AH[7-0] 2 This register defines the PC high address for PC match break point 2. PC2AT (A0F6h) Program Counter Break Point 2 Top Address Register R/W (0x00) 7 6 5 4 3 RD PC2AT[7-0] WR PC2AT[7-0] 2 1 0 This register defines the PC top address for PC match break point 2. PC2AT:PC2HT:PC2LT together form a 24bit compare value of PC break point 2 for Program Counter. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 38 IS31CS8974 Host or program can obtain the status of the break point controller through the current break point address and next PC address register. DBPCID[23-0] contains the PC address of just executed instruction when the break point occurs. DBNXPC[23-0] contains the next PC address to be executed when the break point occurs, therefore, it is usually exactly the same value of the break pointer setting. DBPCIDL (A098h) Debug Program Counter AddressLow Register RO (0x00) 7 6 5 4 3 RD DBPCID[7-0] WR - 2 1 0 2 1 0 2 1 0 1 0 1 0 1 0 DBPCIDH (A099h) Debug Program Counter Address High Register RO (0x00) 7 6 5 4 3 RD DBPCID[15-8] WR - DBPCIDT (A09Ah) Debug Program Counter Address Top Register RO (0x00) 7 6 5 4 3 RD DBPCID[23-16] WR - DBPCNXL (A09Bh) Debug Program Counter Next Address Low Register RO (0x00) 7 6 5 4 3 RD DBPCNX[7-0] WR - 2 DBPCNXH (A09Ch) Debug Program Counter Next Address High Register RO (0x00) 7 6 5 4 3 RD DBPCNX[15-8] WR - 2 DBPCNXT (A09Dh) Debug Program Counter Next Address Top Register RO (0x00) 7 6 5 4 3 RD DBPCNX[23-16] WR - 2 STEPCTRL (A09Eh) Single Step Control Enable Register R/W (0x00) 7 6 5 4 3 RD STEPCTRL[7-0] WR STEPCTRL[7-0] 2 1 0 To enable single-step debugging, STEPCTRL must be written with value 0x96. 1.18 Debug I2C Port The I2C Slave 2 (I2CS2) can be configured as the debug and ISP port. This is achieved by assigning a predefined debug ID for the I2CSlave address. When a host issues an I2C access to this special address, a DBG interrupt is generated. DBG Interrupt has the highest priority. The DBG interrupt vector is located at 0x70C0. DBG ISR is used to communicate with the host and is usually closely associated with BKP ISR. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 39 IS31CS8974 SI2CDBGID (A09Fh) Slave I2C Debug ID Register R/W (0x36) TB Protected 7 6 5 4 3 RD DBGSI2C2EN SI2CDBGID[6:0] WR DBGSI2C2EN SI2CDBGID[6:0] 2 1 0 DBGSI2C2EN=1 enables I2CS2 as debug port. When I2CS2 receives an access of I 2C address matching SI2CDBGID[6:0], a debug interrupt is generated. SI2CDBGID[6:0] Slave I2C ID address for debug function. DBGSI2C2EN 1.19 Data SRAM ECC Handling The data SRAM (IRAM and XRAM) is configured as 2048 x 13-bit. An 8:5 ECC encoder and decoder are implemented to check the SRAM data. ECC check in data access path is in hardware and performed automatically. It can correct 1-bit error in each byte and detect 2-bit error in each byte. All generation and checking are done in hardware. It is strongly recommended all SRAM data should be initialized at power on or after reset if ECC is enabled to avoid initial ECC error. If ECC encounters either an uncorrectable error, hardware will latch the address and triggers an interrupt. Software needs to examine the severity of data corruption and determine appropriate actions. Please also note, switching between ECC and non-ECC mode, all the data in SRAM will be corrupted thus require re-initialization. It is strongly suggested keeping ECC enabled for best reliability as well as noise immunity. DECCCFG (0xA02Dh) Data ECC Configuration Register R/W (0x80) TB Protected 7 6 5 4 RD DECCEN - DECCIEN2 WR DECCEN - DECCIEN2 3 2 1 0 DECCIEN1 - DECCIF2 DECCIF1 DECCIEN1 - DECCIF2 DECCIF1 DECCEN DECCIEN2 DECCIEN1 DECCIF2 Data ECC Enable Data ECC Uncorrectable Error Interrupt Enable Data ECC Correctable Error Interrupt Enable Data ECC Uncorrectable Error Interrupt Flag DECCIF2 is set to 1 by hardware when reading SRAM encounters uncorrectable error. DECCIF2 is set independent of DECCIEN2. DECCIF2 needs to be cleared by software. DECCIF1 Data ECC Correctable Error Interrupt Flag DECCIF1 is set to 1 by hardware when reading SRAM encounters correctable error. DECCIF1 is set independent of DECCIEN2. DECCIF2 needs to be cleared by software. Please note if a correctable error is encountered, the data will be automatically corrected. To prevent further corruption, software upon DECIF1 interrupt should rewrite the data into the SRAM. DECCADL (0xA02Eh) Data ECC Configuration and Address Register Low RO (0x00) 7 6 5 4 3 RD DECCAD[7-0] WR - 2 1 0 1 0 DECCADH (0xA02Fh) Data ECC Configuration and Address Register High R/W (0x00) 7 6 5 4 3 RD DECCAD[15-8] WR - 2 DECCAD[15-0] records the address of ECC fault when data SRAM ECC error occurs. It is read-only and reflects the error address that causes DECCIF to be set. If DECCIF is set and not cleared, DECCAD will not be updated if further error is detected. 1.20 Program ECC Handling The program code stored in e-Flash has built-in ECC checking. The e-Flash is in 16-bit width, and when read by CPU program space accesses, the lower LSB 8-bit is read for instruction and the upper MSB 8-bit contains the ECC value of the LSB 8-bit. The ECC is nibble based, [15-12] is ECC for [7-4], and [11-8] is ECC for [3-0]. Four bits ECC for four bits data allows one bit error correction and two bits error detection. This means for Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 40 IS31CS8974 an 8-bit code stored, 2-bit error corrects is possible, and this greatly increases the reliability of the overall program robustness. During program fetch and execution, ECC is performed simultaneously by hardware. If any ECC correctable error is detected, the value fetched is corrected, and optionally a PECCIEN1 interrupt can be generated. If any ECC non-correctable error is detected, two options can be configured, either a PECCIEN2 interrupt can be generated or software reset can be generated. In both PECCIEN interrupt, the address of the error encountered is latched in PECCADL[15-0]. PECCCFG (0xA00Dh) Program ECC Configuration Register R/W (0x80) TB Protected 7 6 5 4 RD - - PECCIEN2 WR - - PECCIEN2 PECCIEN2 PECCIEN1 PECCIF2 PECCIF1 3 2 1 0 PECCIEN1 - PECCIF2 PECCIF1 PECCIEN1 - PECCIF2 PECCIF1 Program ECC Uncorrectable Error Interrupt Enable Program ECC Correctable Error Interrupt Enable Program ECC Uncorrectable Error Interrupt Flag PECCIF2 is set to 1 by hardware when program fetching from e-Flash encounters uncorrectable error. PECCIF2 is set independent of PECCIEN2. PECCIF2 needs to be cleared by software. Program ECC Correctable Error Interrupt Flag PECCIF1 is set to 1 by hardware when program fetching from e-Flash encounters correctable error. PECCIF1 is set independent of PECCIEN2. PECCIF2 needs to be cleared by software. PECCADL (0xA00Eh) Program ECC Fault Address Register Low RO (0x00) 7 6 5 4 3 RD PECCAD[7-0] WR - 2 1 0 2 1 0 PECCADLH(0xA00Fh) Program ECC Fault Address Register High R/W (0x00) 7 6 5 4 3 RD PECCAD[15-8] WR - PECCAD[15-0] records the address of ECC fault when Flash ECC error occurs. It is read-only and reflects the last error address. 1.21 Memory and Logic BIST Test BSTCMD (0xA016h) SRAM Built-In and Logic Self Test R/W (0x00) TB Protected 7 6 5 RD MODE[3-0] WR MODE[3-0] MODE[3-0] 3 2 1 0 BST - FAIL FINISH BSTCMD[3-0] BIST Mode Selection 0000 – Normal Mode 0001 – SRAM MBIST 0010 – Reserved 0011 – Reserved 0100 – Register LBIST 0101 – Reserved 0110 – Reserved 0111 – Reserved 1000 – Normal Mode 1001 – SRAM MBIST and monitor on pins 1010 – Reserved 1011 – Reserved 1100 – Register LBIST and monitor on pins Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 4 41 IS31CS8974 1101 – Reserved 1110 – Reserved 1111 – Reserved Please note MODE[3-0] is cleared only by POR and RSTN. Software can read this setting along with the Pass/Fail status to determine which BIST was performed and its result even after a software reset. BST BIST Status BST is set to 1 by hardware when BIST in ongoing. FAIL BIST Test Fail Flag FAIL is set to 1 by hardware when BIST error has occurred. FAIL is cleared to 0 by hardware when a new BIST command is issued. FINISH BIST Completion Flag FINISH is set to 1 by hardware when BIST controller finishes the test. FINISH is cleared to 0 by hardware when a new BIST command is issued. BSTCMD[3-0] Memory BIST Command Writing BSTCMD[3-0] with value 4b’0101 causes the BIST controller to perform BIST. Writing BSTCMD[3-0] with value 4b’1010 causes the BIST controller to perform BIST, and after BIST is completed, it automatically generates a software reset. Writing BSTCMD[3-0] with value 4b’0000 causes FAIL and FINISH bits to be cleared to 0. Any other value will either have no effect or abort any ongoing BIST. Please note after the BSTCMD is issued, CPU is paused until BIST is completed. And any BIST operations will results the state of CPU in undefined states, and the content of the SRAM undefined. Therefore it is highly recommended that a software reset or initiation should be performed after any BIST operation. Please also note MODE[3-0], FINISH, FAIL bits are not cleared by software resets. TSTMON (0xA014h) Test Monitor Flag R/W (0x00) TB Protected 7 6 5 4 3 RD TSTMON[7-0] WR TSTMON[7-0] 2 1 0 TSTMON register stores temporary status and is initialized by power-on reset only. 1.22 System Clock Monitoring SYSCLK in normal running mode is monitored by SIOSC (32K). If SYSCLK is not present in normal mode for four SIOSC cycles, a hardware reset is triggered. R D F/F R Q D F/F R Q D F/F R Q D F/F Q CLKFAULT SYSCLK R NORMAL MODE D F/F R Q D F/F R Q D F/F R Q D F/F Q SIOSC32K The clock monitoring is default turned off after reset. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 42 IS31CS8974 1.23 Reset There are several reset sources and includes both software resets and hardware resets. Software resets include command reset, WDT reset and ECC error reset. Hardware resets include power-on reset (low voltage detect on VDDC), LVD reset (low voltage detect on VDD), SYSCLK monitor reset, and external RSTN reset. Software reset only restores some registers to default values, and hardware reset restore all registers to its default values. RSTN reset is filtered that ignores any low going glitch on RSTN with less than 4msec. All hardware reset condition once being met will be extended by 4 msec when exiting reset. Internal hardware resets also has feedback to RSTN pin and extend the reset duration by external RSTN R/C time. The reset scheme is shown in the following diagram. LVDTH VDD 2.0V – 5.5V LVR LVREN SCHOTTKY VDDC 1.5V VDDC 1.5V REGULATOR CMDRST VDDC 1.3V BACKUP REGULATOR ECCRST CKMONRST PORRST VDD < 1.6V VDDC < 1.2V VDD SOFTWARE RESET WDTRST VTH=0.35*VDD RSTN ASSERT FILTER 4msec XRST RSTN SYSTEM RESET ASSERTION EXTENSION 4msec HARDWARE RESET ASSERTION EXTENSION 1msec RSTCMD (0xA017h) Reset Command Register R/W 0x00 TB Protected 7 6 5 4 3 2 1 0 RD RSTCKM RSTECC - - CKMRF ECCRF WDTRF CMDRF WR RSTCKM RSTECC - CLRF RSTCKM RSTECC CKMRF ECCRF WDTRF CLRF RSTCMD[3-0] Reset Enable for Clock Monitor Fault RENCKM=1 enables reset after clock fault detection. RSTCKM is cleared to 0 after any reset. Default RSTCKM is 0. Reset Enable for Uncorrectable Code Fetch ECC Error RSTECC=1 enables reset at e-Flash code fetch ECC error. Default RSTECC is 0. Clock Monitor Fault Reset Flag CKMRF is set to 1 by hardware when a clock fault reset has occurred. CKMRF is not cleared by reset except power-on reset. ECC Error Reset Flag ECCRF is set to 1 by hardware when an ECC error reset has occurred. ECCRF is cleared to 0 when writing CLRF=0. ECCRF is not cleared by reset except power-on reset. WDT Reset Flag WDTRF is set to 1 by hardware when WTRF, WT1RF or WT2RF is set. Clear Reset Flag Writing 1 to CLRF will clear CKMRF, ECCRF, WDTRF, and CMDRF. It is self-cleared. Software Reset Command Writing RSTCMD[3-0] with consecutive 4b’0101, 4b’1010 sequences will cause a software reset. Any other value will clear the sequence state. These bits are write-only and self-cleared. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 RSTCMD[3-0] 43 IS31CS8974 2. Flash Controller The flash controller connects the CPU to the on-chip embedded FLASH memory. The FLASH memory functions as the program storage as well as non-volatile data storage. The program access of the FLASH does not require any special attention. When an ECC error during program fetch occurs, this cause ECC interrupt or reset. When the FLASH is used as data storage, the software issues commands to the FLASH controller through the XFR registers. And when the FLASH controller processes these commands, CPU is held idle until the command is completed. There is a time-out mechanism for holding CPU in idle to prevent hanged operations. From FLASH controller point of view, the embedded Flash is always in 16-bit width with no distinction between ECC and data information. For code storage through FLASH controller, ECC byte (upper MSB 8-bit) must be calculated by software. During read command, ECC is detected but not corrected, the raw content is loaded into FLSHDAT[15-0]. If ECC error is detected, FAIL status is set after the read command execution. The e-Flash contains 64 pages (also referred as Sector), and each page is 512x16. It also contains two IFB (Information Blocks) pages. In Flash operation, the erase command only operates on page. FLSHCMD (A025h) Flash Controller Command Register R/W (0x80) TB Protected RD WR 7 WRVFY WRVFY BUSY FAIL CYC[2-0] CMD4 – CMD0 6 BUSY CYC[2-0] 5 FAIL 3 CMD3 CMD3 2 CMD2 CMD2 1 CMD1 CMD1 0 CMD0 CMD0 Write Result Verify. At the end of a write cycle, hardware reads back the data and compares it with which should be written to the flash. If there is a mismatch, this bit represents 0. It is reset to 1 by hardware when another ISP command is executed. Flash command is in processing. This bit indicates that Flash Controller is executing the Flash Read, Write, or Sector Erase and other commands are not valid. Command Execution Result. It is set if the previous command execution fails due to any reasons. It is recommended that the program should verify the command execution after issuing a command to the Flash controller. It is not cleared by reading but when a new command is issued. Possible causes of FAIL include address over range, or address falls into protected region, and also include ECC error for read. Flash Command Time Out CYC[2-0] defines command time out cycle count. Cycle period is defined by ISPCLK, which is SYSCLK/256/(ISPCLKF[7-0]+1). The number of cycles is tabulated as following. CYC[2-0] WRITE ERASE 0 0 0 55 5435 0 0 1 60 5953 0 1 0 65 6452 0 1 1 69 6897 1 0 0 75 7408 1 0 1 80 7906 1 1 0 85 8404 1 0 0 89 8889 For normal operations, CYC[2-0] should be set to 111. Flash Command These bits define commands for the Flash controller. The valid commands are listed in the following table. Any invalid commands do not get executed but return with a Fail bit. CMD4 CMD3 CMD2 CMD1 CMD0 COMMAND 1 0 0 0 0 Main Memory Read 0 1 0 0 0 Main Memory Sector Erase 0 0 1 0 0 Main Memory Write 0 0 0 1 0 IFB Read 0 0 0 0 1 IFB Write 0 0 0 1 1 IFB Sector Erase 1 0 0 1 0 - Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 4 CMD4 CMD4 44 IS31CS8974 IFB1 contains manufacture data and user OTP, therefore IFB write command are limited to IFB1 (0x0040-0x01FF) and IFB2. IFB Sector Erase is limited to IFB2. For READ operations, FLSHDATH is the raw data, which is ECC code and FLSHDATL is ECC corrected data. If there is ECC error, the FAIL status will be set, and corresponding ECC flags, PECCIF1 or PECCIF2 will be set according to the error condition. FLSHDATL (A020h) Flash Controller Data Register R/W (0x00) 7 6 5 RD WR 4 3 2 1 0 2 1 0 2 1 0 1 0 1 0 Flash Read Data Register DATA[7-0] Flash Write Data Register DATA[7-0] FLSHDATH (A021h) Flash Controller Data Register R/W (0x00) 7 6 5 RD WR 4 3 Flash Read Data Register DATA[15-8] Flash Write Data Register DATA[15-8] FLSHADL (A022h) Flash Controller Low Address Data Register R/W (0x00) 7 6 5 4 3 RD Flash Address Low Byte Register ADDR[7-0] WR Flash Address Low Byte Register ADDR[7-0] FLSHADH (A023h) Flash Controller High Address Data Register R/W (0x00) 7 6 5 4 3 2 RD Flash Address High Byte Register ADDR[15-8] WR Flash Address High Byte Register ADDR[15-8] FLSHECC (A024h) Flash ECC Acclerator Register R/W (0x00) 7 6 5 4 3 RD ECC[7-0] WR DATA[7-0] 2 FLSHECC aids the calculation of ECC value of an arbitrary 8-bit data. The data is written to FLSHECC, and its corresponding ECC value can be read out from ECC. ISPCLKF (A026h) Flash Command Clock Scaler R/W (0x25) 7 6 5 RD WR 4 3 2 1 0 ISPCLKF[7-0] ISPCLKF[7-0] ISPCLKF[7-0] configures the clock time base for generation of Flash erase and write timing. ISPCLK = SYSCLK * (ISPCLKF[7-0]+1)/256. For correct timing, ISPCLK should be set to approximately at 2MHz. FLSHPRT0 (A030h) Flash Controller Zone Protection Register 0 R/W (0xFF) 7 6 5 RD WR 4 3 2 1 0 2 1 0 FLSHPRT[7-0] FLSHPRT[7-0] FLSHPRT1 (A031h) Flash Controller Zone Protection Register 1 R/W (0xFF) 7 6 RD WR Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 5 4 3 FLSHPRT[15-8] FLSHPRT[15-8] 45 IS31CS8974 FLSHPRT2 (A032h) Flash Controller Zone Protection Register 2 R/W (0xFF) 7 6 5 RD WR 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 FLSHPRT[23-16] FLSHPRT[23-16] FLSHPRT3 (A033h) Flash Controller Zone Protection Register 3 R/W (0xFF) 7 6 5 RD WR 4 3 FLSHPRT[31-24] FLSHPRT[31-24] FLSHPRT4 (A034h) Flash Controller Zone Protection Register 4 R/W (0xFF) 7 6 5 RD WR 4 3 FLSHPRT[39-32] FLSHPRT[39-32] FLSHPRT5 (A035h) Flash Controller Zone Protection Register 5 R/W (0xFF) 7 6 5 RD WR 4 3 FLSHPRT[47-40] FLSHPRT[47-40] FLSHPRT6 (A036h) Flash Controller Zone Protection Register 6 R/W (0xFF) 7 6 5 RD WR 4 3 FLSHPRT[55-48] FLSHPRT[55-48] FLSHPRT7 (A037h) Flash Controller Zone Protection Register 7 R/W (0xFF) 7 6 RD WR 5 4 3 FLSHPRT[63-56] FLSHPRT[63-56] FLSHPRT partitions the total code space of 64K into 64 uniform 1K zones foe protection. If the corresponding bit in the FLSHPRT is 0, the zone protection is on. All bits in FLSHPRT are set to 1 by any reset. A “1” state corresponds to unprotected state. A bit can only be written to “0” by software and cannot be set to “1”. When a bit is “0”, the protection is on and disallowed erasure or modifications. For contents reliability, the user program should turn off the corresponding access after initialization as soon as possible. FLSHPRT[63] Flash Zone Protect 63 This bit protect area 0xFC00 – 0xFFFF FLSHPRT[30] Flash Zone Protect 62 This bit protect area 0xF800 – 0xFBFF … … FLSHPRT[4] Flash Protect 4 This bit protect area 0x1000 – 0x13FF FLSHPRT[3] Flash Protect 3 This bit protect area 0x0C00 – 0x0FFF FLSHPRT[2] Flash Protect 2 This bit protect area 0x0800 – 0x0BFF FLSHPRT[1] Flash Protect 1 This bit protect area 0x0400 – 0x07FF FLSHPRT[0] Flash Protect 0 This bit protect area 0x0000 – 0x03FF Please note since there is only 32K code Flash, therefore only FLSHPRT[31-0] is used. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 46 IS31CS8974 FLSHPRTC (A027h) Flash Controller Code Protection Register R/W 0x(00) TB Protected 7 6 RD WR 5 4 3 FLSHPRTC[7-0] 2 1 0 STAT This register further protects the code space (0x0000 – 0xFFFF). The protection is on after any reset. Software write “55” into this register turns off protection. However, protection is maintained on until a wait time (approximately 300msec) has expired. The 300msec delay prevents any false action due to power or interface transient. Any write other than “55” will turn on the protection immediately. STAT indicates the protection, STAT=1 indicates the protection is off, and STAT=0 indicates the protection is on. Please note, in order to modify or erase the flash (not including IFB) both FLSHPRT and FLSHPRTC conditions needs to be satisfied at the same time. IFB1’s manufacturing data is always protected while user data can only be written “0”. IFB2 are user application data and thus not protected. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 47 IS31CS8974 I2C Slave Controller 1 (I2CS1) 3. The I2C Slave Controller 1 is a regular I2C Slave controller with enhanced functions such as clockstretching and programmable hold time. These enhancements provide significant improvement on compatibilities. I2CS1 shares the SCL/SDA pins with the I2CM1. I2CS1 also can be configured to respond to two I 2C addresses – I2CADR1 and I2CADR3. These two addresses can be enabled separately. In receive mode, the controller detects a valid matching address and issues an ADDRMI interrupt. At the same time, the data bit on SDA line is shifted into receive buffer. The RCBI interrupt is generated whenever a complete byte is received and is ready to be read from I2CSDAT. If for any reason, the software does not respond to RCBI interrupt in time (i.e. RCBI is not cleared), and a new byte is received, the controller either forces an NACK response on I2C (if CLKSTREN bit is not set) or by pulling and holding SDA low (if CLKSTREN bit is set) to stretch the SCL low duration to force the master into a wait state. In clock stretching mode, SCL is released when the software responds to RCBI interrupt and cleared RCBI flag. In transmit mode, the controller detects a valid matching address and issue an ADDRMI interrupt. At the same time, the data preloaded in the transmit data register through I2CSDAT is transferred to the transmit shift register and is serially shifted out onto SDA line. When this occurs, the controller generates a TXBI interrupt to inform the software that a new byte can be written into I2CSDAT. When the shift register is empty and ready for the next transmit, the slave controller checks if the new byte is written to the I2CSDAT. If TXBI is not cleared, it indicates lack of new data and the slave controller holds SCL line low to stretch the current clock cycle if CLKSTREN is set. If the clock stretching is not enabled, the slave controller takes the old byte into the shift register and replies with NACK, thus causing data corruption. On the other hand, if the master returns the NACK after the byte transfer, this indicates the end of data to the I2C slave. In this case, the I2C slave releases the data line to allow the master to generate a STOP or REPEAT START. The I2C slave controller also implements the input noise spike filter, and this is enabled by INFILEN bit in the I2CSCON register. The filter is implemented using digital circuit. When INFILEN is set, the spikes less than 1/2 SYSCLK period on the input of SDA and SCL lines are filtered out. If INFILEN is low, no input filtering is done. The following registers are related to I2C Slave Controller. Also please note the I2C slave controller uses SYSCLK to sample the SCL and SDA signals, therefore, the maximum allowable I2C bus speed is limited to SYSCLK/8 with conforming data setup and hold times. If setup and hold time cannot be guaranteed, then it is recommended the bus speed is limited to 1/40 SYSCLK. I2CSCON1A (0xEB) I2CS1 Configuration Register A R/W (0x00) 7 6 5 4 3 2 1 0 RD EADRWK EADDRMI ESTOPI ERPSTARTI ETXBI ERCBI CLKSTREN EACKWK WR EADRWK EADDRMI ESTOPI ERPSTARTI ETXBI ERCBI CLKSTREN EACKWK EADRWK EADDRMI ESTOPI ERPSTARTI ETXBI ERCBI CLKSTREN INFILEN START Enable Address matched wakeup from SLEEP mode, ADDRMI Interrupt Enable bit. Set this bit to set ADDRMI interrupt as the I2C slave interrupt. This interrupt is generated when I2C slave received a matching address. STOPI Interrupt Enable bit. Set this bit to set STOPI interrupt as the I2C slave interrupt. RPTSTARTI Interrupt Enable Bit. S et this bit to set RPTSTARTI interrupt as the I2C slave interrupt. TXBI Interrupt Enable bit Set this bit to allow TXBI interrupt as the I2C slave interrupt. RCBI Interrupt Enable bit. Set this bit to allow RCBI interrupt as the I2C slave interrupt. Clock Stretching Enable bit. Set to enable the clock stretching function of the slave controller. Clock stretching is an optional feature defined in I2C specification. If the clock stretching option is enabled (for slave I2C), the data written into transmit buffer is shifted out only after the occurrence of clock stretching, and the data cannot be loaded to transmit shift register. The programmer must write the same data again to the transmit buffer. Input Noise Filter Enable bit. Set this bit to enable the input noise filter of SDA and SCL lines. When the filter is enabled, it filters out the spike of less than 50nsec. Start Condition. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 48 IS31CS8974 EACKWK This bit is set when the slave controller detects a START condition on the SCL and SDA lines. This bit is not very useful as the start of transaction can be indicated by address match interrupt. This read-only bit is cleared when STOP condition is detected. 1: Enable clock stretching during system wakeup from sleep and wait until system wakeup completed and asks controller send ACK to master. 0: controller send NACK when address matched I2CSCON1B (0xAB) I2CS1 Configuration Register B R/W (0x00) 7 6 5 4 RD - SADR3M XMT START SDAFLT[1-0] GDFLT[1-0] WR I2CSRST - - - SDAFLT[1-0] GDFLT[1-0] I2CSRST SDAFLT[1-0] GDFLT [1:0] SARD3M XMT START 3 2 1 0 I2C Slave Reset bit. Set this bit causes the Slave Controller to reset all internal state machine. It is selfcleared by hardware. Delay for SDA input to satisfy SDA to SCL hold time 00 - 20ns RC filter delay 01 - 15ns RC filter delay 10 - 10ns RC filter delay 11 - 5ns RC filter delay Glitch filter for SCL and SDA input 00 - 20ns RC filter delay 01 - 15ns RC filter delay 10 - 10ns RC filter delay 11 - 5ns RC filter delay Slave Address Match Flag bit. This bit is meaningful only when ADDRMI is set. SARD3M=0 indicates the received I2C address matches with I2CSADR1. SARD3M=1 indicates the received I2C address matches with I2CSADR3. This bit is cleared when ADDRMI is cleared. This bit is set by the controller when the I2C slave is in transmit operation; is clear when the I2C slave controller is in receive operation. Start Condition. This bit is set when the slave controller detects a START condition on the SCL and SDA lines. This bit is not very useful as the start of transaction can be indicated by address match interrupt. This read-only bit is cleared when STOP condition is detected. I2CSST1 (0xEC) I2CSA1 Status Register R/W (0x00) 7 6 5 4 3 2 1 0 RD ADRWKF ADDRMI STOPI RPSTARTI TXBI RCBI FIRSTBT NACK WR CLRWKF CLRADMI CLRSTOPI CLRRPSTI CLRWKF ADRWKF ADDRMI STOPI RPTSARTI TXBI RCBI Clear Address Matched Wakeup Flag (ADRWKF) Address Matched Wakeup Flag Slave Address Match Interrupt Flag bit. This bit is set when the received address matches the address defined in I2CSADR1. If EADDMI is set, this generates an interrupt. This bit must be cleared by software. Stop Condition Interrupt Flag bit. This bit is set when the slave controller detects a STOP condition on the SCL and SDA lines. This bit must be cleared by software. Repeat Start Condition Interrupt Flag bit. This bit is set when the slave controller detects a REPEAT START condition on the SCL and SDA lines. This bit must be cleared by software. Transmit Buffer Interrupt Flag. This bit is set when the slave controller is ready to accept a new byte for transmit. This bit is cleared when new data is written into I2CSDAT register. Receiver Buffer Interrupt Flag bit. This bit is set when the slave controller puts new data in the I2CSDAT and ready for software-reading. This bit is cleared after the software reads I2CSDAT. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 CLRNACK 49 IS31CS8974 FIRSTBT NACK This bit is set to indicate the data in the data register as the first byte received after address match. This bit is cleared after the second byte received. The bit is read only and generated by the slave controller. NACK Condition bit. This bit is set when the host responds with NACK in the byte transaction. This bit is only meaningful for slave-transmit operation. Please note if the master returns with NACK on the byte transaction, the slave does not upload new data into the shift register. And the slave transmits the old data again as the next transfer, and this re-transmission continues if NACK is repeated until the transmission is successful and returned with ACK. This bit is cleared when a new ACK is detected or it can be cleared by software. I2CSADR1 (0xED) I2CS1 Slave Address Register R/W (0x00) 7 RD I2CSEN1 WR I2CSEN1 I2CSEN1 ADDR1[6-0] I2CADDR[6-0] 6 5 4 3 2 1 0 I2CADDR[6-0] ADDR1[6-0] I2C Set this bit to enable the slave controller and ADDR1[6-0] for address matching 7-bit slave address 1. Received slave I2C address I2CSDAT1 (0xEE) I2CS1 Data Register R/W (0x00) 7 6 5 4 3 RD I2C Slave Receive Data Register WR I2C Slave Transmit Data Register 2 1 0 2 1 0 I2CSADR3 (0x9E) I2CS1 2nd Slave Address Register R/W (0x00) 7 RD I2CSEN2 WR I2CSEN I2CSEN2 ADDR2[6-0] 6 4 3 ADDR2[6-0] ADDR2[6-0] I2 C Set this bit to enable the slave controller and ADDR2[6-0] for address matching. Please note this can coexist with ADDR1. 7-bit slave address 2. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 5 50 IS31CS8974 I2C Slave Controller 2 (I2CS2) 4. The I2C Slave Controller 2 has dual functions – as a debug port for communication with host or as a regular I2C slave port. Please note both functions can coexist. I2C Slave 2 controller also supports the clock stretching functions. The debug accessed by the host is through I2C slave address defined by SI2CSDBGID register and enabled by DBGSI2C2EN=1. When I2CS2 received this address match, a DBG interrupt is generated. This is described in the Debug and ISP sections. If DBGSI2C2EN=0, then I2CS2 functions as a regular I 2C slave. The address of the slave is set by I2CSADR2 register. The MSB in I2CSADDR2 is the enable bit for the I2C slave controller and I2CSADR2[6-0] specifies the actual slave address. In receive mode, the controller detects a valid matching address and issues an ADDRMI interrupt. At the same time, the data bit on SDA line is shifted into receive buffer. The RCBI interrupt is generated whenever a complete byte is received and is ready to be read from I2CSDAT. If for any reason, the software does not respond to RCBI interrupt in time (i.e. RCBI is not cleared), and a new byte is received, the controller either forces an NACK response on I2C (if CLKSTREN bit is not set) or by pulling and holding SDA low (if CLKSTREN bit is set) to stretch the SCL low duration to force the master into a wait state. In clock stretching mode, SCL is released when the software responds to RCBI interrupt and cleared RCBI flag. In transmit mode, the controller detects a valid matching address and issue an ADDRMI interrupt. At the same time, the data preloaded in the transmit data register through I2CSDAT is transferred to the transmit shift register and is serially shifted out onto SDA line. When this occurs, the controller generates a TXBI interrupt to inform the software that a new byte can be written into I2CSDAT. When the shift register is empty and ready for the next transmit, the slave controller checks if the new byte is written to the I2CSDAT. If TXBI is not cleared, it indicates lack of new data and the slave controller holds SCL line low to stretch the current clock cycle if CLKSTREN is set. If the clock stretching is not enabled, the slave controller takes the old byte into the shift register and replies with NACK, thus causing data corruption. On the other hand, if the master returns the NACK after the byte transfer, this indicates the end of data to the I2C slave. In this case, the I2C slave releases the data line to allow the master to generate a STOP or REPEAT START. The I2C slave controller also implements the input noise spike filter, and this is enabled by INFILEN bit in the I2CSCON register. The filter is implemented using digital circuit. When INFILEN is set, the spikes less than 1/2 SYSCLK period on the input of SDA and SCL lines are filtered out. If INFILEN is low, no input filtering is done. The following registers are related to I2C Slave Controller. Also please note the I2C slave controller uses SYSCLK to sample the SCL and SDA signals, therefore, the maximum allowable I2C bus speed is limited to SYSCLK/8 with conforming data setup and hold times. If setup and hold time cannot be guaranteed, then it is recommended the bus speed is limited to 1/40 SYSCLK. I2CSCON2 (0xDB) I2CS2 Configuration Register R/W (0x00) 7 6 5 4 3 2 1 0 RD - - - START - - - XMT WR I2CSRST EADDRMI ESTOPI ERPSTARTI ETXBI ERCBI CLKSTREN INFILEN I2CSRST EADDRMI ESTOPI ERPSTARTI ETXBI ERCBI CLKSTREN INFILEN I2C Slave Reset bit. Set this bit causes the Slave Controller to reset all internal state machine. Clear this bit for normal operations. Setting this bit clears the I2CSADR2 (I2C slave address x). ADDRMI Interrupt Enable bit. Set this bit to set ADDRMI interrupt as the I2C slave interrupt. This interrupt is generated when I2C slave received a matching address. STOPI Interrupt Enable bit. Set this bit to set STOPI interrupt as the I2C slave interrupt. RPTSTARTI Interrupt Enable Bit. Set this bit to set RPTSTARTI interrupt as the I2C slave interrupt. TXBI Interrupt Enable bit Set this bit to allow TXBI interrupt as the I2C slave interrupt. RCBI Interrupt Enable bit. Set this bit to allow RCBI interrupt as the I2C slave interrupt. Clock Stretching Enable bit. Set to enable the clock stretching function of the slave controller. Clock stretching is an optional feature defined in I2C specification. If the clock stretching option is enabled (for slave I2C), the data written into transmit buffer is shifted out only after the occurrence of clock stretching, and the data cannot be loaded to transmit shift register. The programmer must write the same data again to the transmit buffer. Input Noise Filter Enable bit. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 51 IS31CS8974 Set this bit to enable the input noise filter of SDA and SCL lines. When the filter is enabled, it filters out the spike of less than 50nsec. This bit is set by the controller when the I2C slave is in transmit operation; is clear when the I2C slave controller is in receive operation. XMT I2CSST2 (0xDC) I2CS2 Status Register R/W (0x00) 7 6 5 4 3 2 1 0 RD FIRSTBT ADDRMI STOPI RPSTARTI TXBI RCBI START NACK WR - ADDRMI STOPI RPSTARTI HOLDT[3] HOLDT[2] HOLDT[1] HOLDT[0] FIRSTBT ADDRMI STOPI RPTSARTI TXBI RCBI START NACK HOLDT[3-0] This bit is set to indicate the data in the data register as the first byte received after address match. This bit is cleared after the first byte of the transaction is read. The bit is read only and generated by the slave controller. Slave Address Match Interrupt Flag bit. This bit is set when the received address matches the address defined in I2CSADR2. If EADDMI is set, this generates an interrupt. This bit must be cleared by software. Stop Condition Interrupt Flag bit. This bit is set when the slave controller detects a STOP condition on the SCL and SDA lines. This bit must be cleared by software. Repeat Start Condition Interrupt Flag bit. This bit is set when the slave controller detects a REPEAT START condition on the SCL and SDA lines. This bit must be cleared by software. Transmit Buffer Interrupt Flag. This bit is set when the slave controller is ready to accept a new byte for transmit. This bit is cleared when new data is written into I2CSDAT register. Receiver Buffer Interrupt Flag bit. This bit is set when the slave controller puts new data in the I2CSDAT and ready for software-reading. This bit is cleared after the software reads I2CSDAT. Start Condition. This bit is set when the slave controller detects a START condition on the SCL and SDA lines. This bit is not very useful as the start of transaction can be indicated by address match interrupt. This read-only bit is cleared when STOP condition is detected. NACK Condition. This bit is set when the host responds with NACK in the byte transaction. This bit is only meaningful for slave-transmit operation. Please note if the master returns with NACK on the byte transaction, the slave does not upload new data into the shift register. And the slave transmits the old data again as the next transfer, and this re-transmission continues if NACK is repeated until the transmission is successful and returned with ACK. This bit is cleared when a new ACK is detected or it can be cleared by software. These four bits define the hold time of the peripheral clock (EPPCLK) cycles between SDA to SCL. The I2C specification requires for minimum of 300nsec hold time, so the condition of “TEPPCLK*(HOLDT[3:0]+3) ≧ 300nsec hold time” equation must be met. For example, if the peripheral clock cycle (EPPCLK) is 20MHz, then HOLD[3-0] should be set to ≧ 3. I2CSADR2 (0xDD) I2CS2 Slave Address Register R/W (0x00) 7 6 5 4 3 RD I2CSEN ADDR[6-0] WR I2CSEN ADDR[6-0] I2CSENT ADDR[6-0] 2 1 0 2 1 0 Set this bit to enable the I2C slave controller. 7-bit slave address. I2CSDAT2 (0xDE) I2CS2 Data Register R/W (0x00) 7 6 5 4 3 RD I2C Slave Receive Data Register WR I2C Slave Transmit Data Register Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 52 IS31CS8974 5. EUART2 with LIN Controller (EUART2) LIN-capable 16550-like EUART2 is an enhanced UART controller (EUART) with separate transmit and receive FIFO. Both transmit and receive FIFO are 15-bytes deep and can be parameterized for interrupt triggering. The addition of FIFO significantly reduces the CPU load to handle high-speed serial interface. Transmit FIFO and receive FIFO have respective interrupt trigger levels that can be set based on optimal CPU performance adjustment. The EUART2 also has dedicated 16-bit Baud Rate generator and thus provides accurate baud rate under wide range of system clock frequency. The EUART2 also provides LIN extensions that incorporate message handling and baud-rate synchronization. The block diagram of EUART2 is shown in the following. EUART_LIN ephclk rsto EUART_RCV divisor[15:0] divisor[15:0] sfroe euart_into EUART_REGS ramsfrdatao[7:0] ramsfraddr[6:0] sfrdatai[7:0] euart_txd BR[15:0] sfr_active Load (start or rx_baud_out) ephsfrwe 16-bit down counter baudrate_cntr[15:0] euart_rxd EUART_TX xaddr[15:0] xdin[7:0] xwr lin_int sync_timeout lin_xdout[7:0] lin_en rx_sync_byte rx_rise lin_xfr_active xrd euart_si inh_rx_fifo rx_fall rx_baud_out = send_break_o (baudrate_cntr == 16'h00) lin_controller LCTRL (A090H) 16-bit Counter LCNTRH (A091h) LCNTRL (A092h) SBRH (A093H) SBRL (A094H) LINT (A095H) FSM LINTEN (A090H) The following registers are used for configurations of and interface with EUART2. SCON2 (0xC2) UART2 Configuration Register 00000000, R/W 7 EUARTEN EUARTEN RD WR EUARTEN SB 6 SB SB 5 WLS[1] WLS[1] 3 BREAK BREAK 2 OP OP 1 PERR PE 0 SP SP Transmit and Receive Enable bit Set to enable EUART2 transmit and receive functions: To transmit messages in the TX FIFO and to store received messages in the RX FIFO. Stop Bit Control Set to enable 2 Stop bits, and clear to enable 1 Stop bit. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 4 WLS[0] WLS[0] 53 IS31CS8974 WLS[1-0] BREAK OP PE/PERR SP The number of bits of a data byte. This does not include the parity bit when parity is enabled. 00 - 5 bits 01 - 6 bits 10 - 7 bits 11 - 8 bits Break Condition Control Bit. Set to initiate a break condition on the UART interface by holding UART output at low until BREAK bit is cleared. Odd/Even Parity Control Bit Parity Enable / Parity Error status Set to enable parity and clear to disable parity checking functions. If read, PERR=1 indicates a parity error in the current data of RX FIFO. Parity Set Control Bit When SP is set, the parity bit is always transmitted as 1. SFIFO2 (0xA5) UART2 FIFO Status/Control Register 00000000 R/W 7 RD WR 6 5 RFL[3-0] RFLT[3-0] RFL[3-0] RFLT[3-0] TFL[3-0] TFLT[3-0] 3 2 1 0 TFL[3-0] TFLT[3-0] Current Receive FIFO level. This is read only and indicate the current receive FIFO byte count. Receive FIFO trigger threshold. This is write-only. RDA interrupt will be generated when RFL[3-0] is greater than RFLT[3-0]. RFLT[3-0] Description 0000 RX FIFO trigger level = 0 0001 RX FIFO trigger level = 1 0010 RX FIFO trigger level = 2 0011 RX FIFO trigger level = 3 0100 RX FIFO trigger level = 4 0101 RX FIFO trigger level = 5 0110 RX FIFO trigger level = 6 0111 RX FIFO trigger level = 7 1000 RX FIFO trigger level = 8 1001 RX FIFO trigger level = 9 1010 RX FIFO trigger level = 10 1011 RX FIFO trigger level = 11 1100 RX FIFO trigger level = 12 1101 RX FIFO trigger level = 13 1110 RX FIFO trigger level = 14 1111 Reset Receive State Machine and Clear RX FIFO Current Transmit FIFO level. This is read only and indicate the current transmit FIFO byte count. Transmit FIFO trigger threshold. This is write-only. TRA interrupt will be generated when TFL[3-0] is less than TFLT[3-0]. TFLT[3-0] Description 0000 Reset Transmit State Machine and Clear TX FIFO 0001 TX FIFO trigger level = 1 0010 TX FIFO trigger level = 2 0011 TX FIFO trigger level = 3 0100 TX FIFO trigger level = 4 0101 TX FIFO trigger level = 5 0110 TX FIFO trigger level = 6 Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 4 54 IS31CS8974 0111 1000 1001 1010 1011 1100 1101 1110 1111 TX FIFO trigger level = 7 TX FIFO trigger level = 8 TX FIFO trigger level = 9 TX FIFO trigger level = 10 TX FIFO trigger level = 11 TX FIFO trigger level = 12 TX FIFO trigger level = 13 TX FIFO trigger level = 14 TX FIFO trigger level = 15 Receive and transmit FIFO can be reset by clear FIFO operation. This is done by setting BR[11-0]=0 and EUARTEN=0. This also clears RFO, RFU and TFO interrupt flags without writing the interrupt register. The LIN counter LCNTR is also cleared. SINT2 (0xA7) UART2 Interrupt Status/Enable Register 00000000 R/W RD WR 7 INTEN INTEN 6 TRA TRAEN 5 RDA RDAEN 4 RFO RFOEN 3 RFU RFUEN 2 TFO TFOEN 1 FERR FERREN 0 TI TIEN INTEN Interrupt Enable bit. Write only Set to enable UART2 interrupt. Clear to disable interrupt. Default is 0. TRA/TRAEN Transmit FIFO is ready to be filled. This bit is set when transmit FIFO has been emptied below FIFO threshold. Write “1” to enable interrupt. The flag is automatically cleared when the condition is absent. RDA/RDAEN Receive FIFO is ready to be read. This bit is set by hardware when receive FIFO exceeds the FIFO threshold. Write “1” to enable interrupt. RDA will also be set when RFL < RFLT for bus idle duration longer than RFLT * 16 * Baud Rate. This is to inform software that there are still remaining unread received bytes in the FIFO. The flag is cleared when RFL < RFLT and writing “0” on the bit (the interrupts is disabled simultaneously) RFO/RFOEN Receive FIFO Overflow Enable bit This bit is set when overflow condition of receive FIFO occurs. Write “1” to enable interrupt. The flag can be cleared by software by writing “0” on the bit (the interrupt is disabled simultaneously), or by FIFO reset action. RFU/RFUEN Receive FIFO Underflow Enable bit This bit is set when underflow condition of receive FIFO occurs. Write “1” to enable interrupt. The flag can be cleared by software by writing “0” on the bit (the interrupt is disabled simultaneously), or by FIFO reset action. TFO/TFOEN Transmit FIFO Overflow Interrupt Enable bit This bit is set when overflow condition of transmit FIFO occurs. Write “1” to enable interrupt. The flag can be cleared by software by writing “0” on the bit (the interrupt is disabled simultaneously), or by FIFO reset action. FERR/FERREN Framing Error Enable bit This bit is set when framing error occurs as the byte is received. Write “1” to enable interrupt. The flag must be cleared by software, writing “0” on the bit (the interrupt is disabled simultaneously). TI/TIEN Transmit Message Completion Interrupt Enable bit This bit is set when all messages in the TX FIFO are transmitted and thus the TX FIFO becomes empty. Write “1” to enable interrupt. The flag must be cleared by software, writing “0” on the bit (the interrupt is disabled simultaneously). SBUF2 (0xA6) UART2 Data Buffer Register 0x00 R/W 7 6 5 RD WR 4 3 EUART2 Receive Data Register EUART2 Transmit Data Register 2 1 0 This register is the virtual data buffer register for both receive and transmit FIFO. When being read, it reads out the top byte of the RX FIFO; when being written, it writes into the top byte of the TX FIFO. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 55 IS31CS8974 EUART2 can be configured to add LIN capability. The major enhancement of LIN includes master/slave configurations, auto baud-rate synchronization, and frame-based protocol with header. Under LIN extension mode, all EUART2 registers and functions are still effective and operational. LIN is a single-wire bus and it requires external components to combine RX and TX signals externally. LIN is frame based and consists of message protocols with master/slave configurations. The following diagram shows the basic composition of a header message sent by the master. It starts with BREAK, the SYNC byte, ID bytes, DATA bytes, and CRC bytes. 11 bit times Break delimiter Break IDLE BREAK BREAK_OK BREAK_DEL Byte field Start bit BREAK_DEL SYNC_S MSB (bit 7) LSB (bit 0) SYNC_0 SYNC_1 SYNC_2 SYNC_3 SYNC_4 Stop bit IDLE A LIN frame structure is shown and the frame time matches the number of bits sent and has a fixed timing. LIN bus protocol is based on frame. Each frame is partitioned into several parts as shown above. For master to initiate a frame, the software follows the following procedure. Initiate a SBK command. (SW needs to check if the bus is in idle state, and there is no pending transmit data). Write “55” into TFIFO. Write “PID” into TFIFO. Wait for SBK to complete interrupts and then write the following transmit data if applicable. (This is optional). The following diagram shows Finite State Machine (FSM) of the LIN extension and is followed by registers within EUART2. Lumissil Microsystems – www.lumissil.com Rev. A, 04/09/2021 56 IS31CS8974 reset or ~LINEN rx_fall & ~mas_en IDLE send_break & mas_en rx_rise BREAK TX_BREAK lcntr[3:0] == 4'hB lcntr[4:0] == bk_len[2:0] + 4'hD sync_timeout lcntr[5] SYNC_0 Clear LIN Counter (count in sysclk) BREAK_OK rx_fall TX_BREAK_DEL rx_baud_out rx_rise sync_timeout lcntr[5] SYNC_1 Clear LIN Counter (count in sysclk) BREAK_DEL rx_rise rx_fall rx_rise sync_timeout SYNC_2 Clear LIN Counter (count in sysclk) send_break