ASNT1123-PQB

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT1123-PQB DC-32Gbps Broadband Digital DDR 4:1 Multiplexer  Quarter-rate clock output  Single +3.3V or -3.3V power supply  Power consumption: 1.15W   Fabricated in SiGe for high performance, yield, and reliability Standard 40-pin QFN package with a thermal pad vee vcc vcc n/c d1p vcc vcc qp d1n vcc ASNT1123 vcc qn 1 vcc cen vee vcc vcc cep vcc vcc d2n d3n n/c vcc vcc d3p vcc vcc d2p vee Rev. 1.2.2 vee Half-rate clock input (DDR mode) vcc  c4op Differential CML I/O data and clock buffers vcc  c4on Ideal for high speed proof-of-concept prototyping vcc  d0p Exhibits low jitter and limited temperature variation over industrial temperature range vcc  d0n High speed broadband 4:1 Multiplexer (MUX) vcc  May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION vcc d0p d0n d1p d1n vcc qp qn d2p d2n d3p d3n vcc cep cen DIV c4op c4on Fig. 1. Functional Block Diagram The ASNT1123-PQB SiGe IC is a low power and high-speed digital 4 to 1 serializer-multiplexer (MUX) that functions seamlessly over data rates (fbit) ranging from DC to its maximum frequency. The main function of the part shown in Fig. 1 is to multiplex 4 parallel differential CML data signals d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n running at a bit rate of fbit/4 into a high speed serial bit stream qp/qn running at a bit rate of fbit. Differential or single-ended half-rate clock cep/cen (DDR mode) must be provided by an external source for the part to function properly. The serialized data words qp/qn and the clock divided-by-4 signal c4op/c4on are transmitted through CML output interfaces. The clock and data outputs are phase-matched to each other resulting in very little relative skew over the operating temperature range of the device. The input data streams should be phase-aligned to the output c4 clock as shown in Fig. 2 and Table 1. thold thold c4op tsetup tsetup d0p, d1p, d2p, d3p Fig. 2. Input Data Alignment to Output c4 Clock Rev. 1.2.2 2 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Table 1. Input Data to Output c4 Clock Phase Requirements Maximum required tsetup, ps 25 Maximum required thold, ps -16 The output data is then delayed in relation to the input half-rate clock as shown in Fig. 3 and Table 2. tD cep qp tD Fig. 3. Output Data to Input Clock Delay Table 2. Output Data to Input Clock Delay Values (DDR Mode) Minimum tD, ps Maximum tD, ps 60 118 The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance. POWER SUPPLY CONFIGURATION The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need AC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply combination. All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V. Rev. 1.2.2 3 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vcc). Table 3. Absolute Maximum Ratings Parameter Supply Voltage (vee) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min -40 10 10 Max -3.6 1.3 1.4 +90 +100 98 98 Units V W V ºC ºC % % TERMINAL FUNCTIONS TERMINAL Name No. Type d0p d0n d1p d1n d2p d2n d3p d3n c4op c4on cep cen qp qn Name vcc vee n/c Rev. 1.2.2 DESCRIPTION Low-Speed I/Os Differential quarter-rate data inputs with internal SE 50Ohm termination to vcc Differential quarter-rate data inputs with internal SE 50Ohm termination to vcc Differential quarter-rate data inputs with internal SE 50Ohm termination to vcc Differential quarter-rate data inputs with internal SE 50Ohm termination to vcc Differential quater-rate clock outputs with internal SE 50Ohm termination to vcc. Require external SE 50Ohm termination to vcc High-Speed I/Os 7 CML Differential half-rate clock input signals with internal 50Ohm input termination to vcc 9 17 CML Differential full-rate data outputs with internal SE 50Ohm output termination to vcc. Require external SE 50Ohm termination to vcc 15 Supply and Termination Voltages Description Pin Number Positive power supply 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, (+3.3V or 0) 34, 36, 38, 40 Negative power supply 1, 11, 21, 31 (0V or -3.3V) Not connected pins 13, 19 27 29 33 35 37 39 3 5 23 25 CML input CML input CML input CML input CML output 4 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX UNIT COMMENTS General Parameters -3.1 -3.3 -3.5 V ±6% vee 0.0 V External ground vcc Ivee 347 mA Power consumption 1.15 W Junction temperature -40 25 125 °C LS Input Data (d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n) Data Rate DC 8 Gb/s Swing 0.2 0.8 V Differential or SE, p-p CM Voltage Level vcc-0.8 vcc V Must match for both inputs HS Input Clock (cep/cen) Frequency DC 16 GHz Swing 0.2 0.8 V Differential or SE, p-p CM Voltage Level vcc-0.8 vcc V Must match for both inputs Duty Cycle 40 50 60 % HS Output Data (qp/qn) Data Rate DC 32 Gb/s Logic “1” level V vcc Logic “0” level vcc-0.4 V With external 50Ohm DC termination Output Jitter 2 ps Peak-to-peak at 32Gb/s LS Output Clock (c4op/c4on) Frequency DC 4 GHz Logic “1” level V vcc Logic “0” level vcc-0.4 V With external 50Ohm DC termination Duty Cycle 50 % Output Jitter 1 ps Peak-to-peak at 4GHz PACKAGE INFORMATION The chip is packaged in a standard 40-pin QFN package shown Fig. 4. The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive supply. The part’s identification label is ASNT1123-PQB. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. Rev. 1.2.2 5 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT1123 Fig. 4. QFN 40-Pin Package Drawing (All Dimensions in mm) REVISION HISTORY Revision 1.2.2 1.1.2 1.1.1 1.0.1 Rev. 1.2.2 Date 05-2020 07-2019 05-2019 08-2015 Changes Updated Package Information Updated Letterhead Added timing diagrams First release 6 May 2020