iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
1.0 Features
2.0 Description
●● Primary-side feedback eliminates opto-isolators and
simplifies design
●● Quasi-resonant operation for highest overall efficiency
●● EZ-EMI ® design to easily meet global EMI standards
●● Up to 130 kHz switching frequency enables small
adapter size
●● Very tight LED constant current regulation
●● No external compensation components required
●● Built-in output constant-current control with primary-side
feedback for LED driver.
●● Low start-up current (10 µA typical)
●● Built-in soft start
The iW3620 is a high performance AC/DC offline LED driver
which uses digital control technology to build peak current
mode PWM flyback power supplies. The device operates in
quasi-resonant mode at heavy load to provide high efficiency
along with a number of key built-in protection features while
minimizing the external component count, simplifying EMI
design and lowering the total bill of material cost. The
iW3620 removes the need for secondary feedback circuitry
while achieving excellent line and load regulation. It also
eliminates the need for loop compensation components while
maintaining stability over all operating conditions. Pulse-bypulse waveform analysis allows for a loop response that is
much faster than traditional solutions, resulting in improved
dynamic load response. The built-in current limit function
enables optimized transformer design in universal off-line
applications over a wide input voltage range.
●● Built-in short circuit protection and output overvoltage
protection
3.0 Applications
●● Current sense resistor short protection
●● LED lighting
●● Overtemperature Protection
●● Open circuit protection
●● Universal input range from 85 Vac to 264 Vac
●● Single-fault protection
●● Small input bulk capacitor
●● Long MTBF
●● High efficiency
L
VOUT
+
N
+
+
RTN
Optional
NTC
Thermistor
1
NC
VCC 8
2
VSENSE
3
VIN
4
SD
OUTPUT 7
ISENSE 6
GND 5
U1
iW3620
Figure 3.1 : Typical Application Circuit
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
4.0 Pinout Description
iW3620
1
NC
2
VSENSE
3
4
VCC
8
OUTPUT
7
VIN
ISENSE
6
SD
GND
5
Pin #
Name
Type
Pin Description
1
NC
-
2
VSENSE
3
VIN
Analog Input Rectified AC line average voltage sense.
4
SD
Analog Input
5
GND
Ground
6
ISENSE
7
OUTPUT
Output
8
VCC
Power Input
No connection.
Analog Input Auxiliary voltage sense (used for primary side regulation).
External shutdown control. Connect to ground through a resistor if not used.
(see Section 10.16)
Ground.
Analog Input Primary current sense (used for cycle-by-cycle peak current control and limit).
Gate drive for external MOSFET switch.
Power supply for control logic and voltage sense for power-on reset circuitry.
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
5.0 Absolute Maximum Ratings
Absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. For
maximum safe operating conditions, refer to Electrical Characteristics in Section 6.0.
Parameter
Symbol
Value
Units
DC supply voltage range (pin 8, ICC = 20mA max)
VCC
-0.3 to 18
V
DC supply current at VCC pin
ICC
20
mA
Output (pin 7)
-0.3 to 18
V
VSENSE input (pin 2, IVsense ≤ 10 mA)
-0.7 to 4.0
V
VIN input (pin 3)
-0.3 to 18
V
ISENSE input (pin 6)
-0.3 to 4.0
V
SD input (pin 4)
-0.3 to 18
V
Power dissipation at TA ≤ 25°C
PD
526
mW
Maximum junction temperature
TJ MAX
125
°C
Storage temperature
TSTG
–65 to 150
°C
Lead temperature during IR reflow for ≤ 15 seconds
TLEAD
260
°C
ψJB (Note 1)
70
°C/W
ESD rating per JEDEC JESD22-A114
2,000
V
Latch-Up test per JEDEC 78
±100
mA
Thermal Resistance Junction-to-PCB Board Surface Temperature
Notes:
Note 1. ψJB [Psi Junction to Board] provides an estimation of the die junction temperature relative to the PCB [Board]
surface temperature. This data is measured at the ground pin (pin 5) without using any thermal adhesives. See
Section 9.14 for more information.
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
6.0 Electrical Characteristics
VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VIN_A(STLOW)
TA= 25°C, positive edge
335
369
406
mV
363
413
477
mV
15
µA
VIN SECTION (Pin 3)
Start-up low voltage threshold (VIN_A)
at internal ADC input (see Figure 8.1)
(Note 2)
Start-up low voltage threshold (VIN)
VIN(STLOW)
Start-up current
IINST
VIN = 10 V, CVCC = 10 µF
10
Input impedance
ZIN
After start-up
5
IBVS
VSENSE = 2 V
kW
VSENSE SECTION (Pin 2)
Input leakage current
1
μA
Nominal voltage threshold
VSENSE(NOM)
TA=25°C, negative edge
1.523
1.538
1.553
V
Output OVP threshold (Note 2)
VSENSE(MAX)
TA=25°C, negative edge
1.790
1.846
1.900
V
OUTPUT SECTION (Pin 7)
Output low level ON-resistance
RDS(ON)LO
ISINK = 5 mA
40
W
Output high level ON-resistance
RDS(ON)-HP
ISOURCE = 5 mA
75
W
Rise time (Note 2)
tR
TA = 25°C, CL = 330 pF
10% to 90%
200
300
ns
Fall time (Note 2)
tF
TA = 25°C, CL = 330 pF
90% to 10%
40
60
ns
Any combination of
line and load
130
140
kHz
16
V
Maximum switching frequency
fSW(MAX)
VCC SECTION (Pin 8)
Maximum operating voltage (Note 2)
VCC(MAX)
Start-up threshold
VCC(ST)
VCC rising
10.8
12
13.2
V
Undervoltage lockout threshold
VCC(UVL)
VCC falling
5.5
6.0
6.6
V
3.5
5
mA
Operating current
ICCQ
CL = 330 pF,
VSENSE = 1.5 V
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
6.0 Electrical Characteristics (cont.)
VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ISENSE SECTION (Pin 6)
Peak limit threshold
VPEAK
1.045
1.1
1.155
V
Isense short protection reference
VRSNS
0.127
0.15
0.173
V
CC regulation threshold limit (Note 2)
VREG-TH
1.0
V
SD SECTION (Pin 4)
Shutdown threshold
Shutdown threshold in Startup
(Note 2)
VSD-TH
TA = 25°C
0.95
VSD-TH(ST)
1.0
1.05
1.2
Input leakage current
IBVSD
VSD = 1.0 V
Pull down resistance
RSD
TA = 25°C
7916
Pull up current source
ISD
TA = 25°C
96
V
V
1
µA
8333
8750
W
107
118
µA
Notes:
Note 1. Adjust VCC above the start-up threshold before setting at 12 V.
Note 2. These parameters are not 100% tested, guaranteed by design and characterization.
Note 3. Operating frequency varies based on the line and load conditions, see Theory of Operation for more details.
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
VCC Start-up Threshold (V)
VCC Supply Start-up Current (µA)
7.0 Typical Performance Characteristics
9.0
6.0
3.0
0.0
0.0
2.0
4.0
8.0
6.0
VCC (V)
10.0
12.0
14.0
12.2
12.0
11.8
11.6
-50
25
50
75
100
125
Internal Reference Voltage (V)
% Deviation of Switching Frequency from Ideal
0
Ambient Temperature (°C)
Figure 7.2 : Start-Up Threshold vs. Temperature
Figure 7.1 : VCC Supply Current vs. VCC
0.3 %
1.548
-0.3 %
1.538
-0.9 %
-1.5 %
-50
-25
1.528
-25
0
25
50
75
Ambient Temperature (°C)
100
Figure 7.3 : Switching Frequency % Change vs.
Temperature
125
1.518
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
Figure 7.4 : Internal Reference vs. Temperature
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
8.0 Functional Block Diagram
VIN
3
ENABLE
VSENSE
2
ISD
VIN_A
0.2 V ~ 2.0 V
Signal
Conditioning
VVMS
Gate
Driver
Digital
Logic
Control
VFB
Detection Switch
–
IPEAK
VIPK
5
1.1 V
6
ISENSE
DAC
RSD
GND
–
VSD-TH
OUTPUT
60 kΩ
VOCP
+
4
7
ADC
+
SD
VCC
Start-up
ENABLE
ZVin
5 kΩ
8
0V~1V
+
– –
Figure 8.1 : iW3620 Functional Block Diagram
9.0 Theory of Operation
The iW3620 is a digital controller which uses a proprietary
primary-side control technology to eliminate the opto-isolated
feedback and secondary regulation circuits required in
traditional designs. This results in a low-cost solution for
AC/DC adapters. The iW3620 uses Critical Discontinuous
Conduction Mode (CDCM) or Pulse Width Modulation
(PWM) mode at high output power levels and switches to
Pulse Frequency Modulation (PFM) mode at light load to
minimize power dissipation to meet EPA 2.0 specification.
Furthermore, iWatt’s digital control technology enables fast
dynamic response, tight output regulation, and full featured
circuit protection with primary-side control.
control algorithm to reduce system design time and improve
reliability.
Referring to the block diagram in Figure 8.1, the digital logic
control block generates the switching on-time and off-time
information based on the line voltage and the output voltage
feedback signal and provides commands to dynamically
control the external MOSFET current. The system loop is
compensated internally by a digital error amplifier. Adequate
system phase and gain margin are guaranteed by design
and no external analog components are required for loop
compensation. The iW3620 uses an advanced digital
iWatt’s digital control scheme is specifically designed to
address the challenges and trade-offs of power conversion
design. This innovative technology is ideal for balancing new
regulatory requirements for green mode operation with more
practical design considerations such as lowest possible cost,
smallest size and highest performance output control.
Furthermore, accurate secondary constant-current operation
is achieved without the need for any secondary-side sense
and control circuits.
The built-in protection features include overvoltage protection
(OVP), output short circuit protection (SCP) and soft-start,
AC line brown out, overcurrent protection, and Isense fault
protection. Also the iW3620 automatically shuts down if it
detects any of its sense pins to be either open or short.
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
9.1 Pin Detail
Pin 2 – VSENSE
turns off so that the VCC capacitor can be charged up again
towards the start-up threshold. Figure 9.1 shows the startup sequence of the iW3620.
Sense signal input from auxiliary winding. This provides the
secondary voltage feedback used for output regulation.
Start-up
Sequencing
Pin 3 – VIN
VIN
Sense signal input from the rectified line voltage. VIN is used
for line regulation. The input line voltage is scaled down
using a resistor network. It is used for input undervoltage
and overvoltage protection. This pin also provides the supply
current to the IC during start-up.
VCC(ST)
VCC
Pin 4 – SD
External shutdown control. If the shutdown control is not
used, this pin should be connected to GND via a resistor.
ENABLE
Pin 5 – GND
Figure 9.1 : Start-up Sequencing Diagram
Ground.
9.3 Understanding Primary Feedback
Pin 6 – ISENSE
Figure 9.2 illustrates a simplified flyback converter. When the
switch Q1 conducts during tON(t), the current ig(t) is directly
drawn from rectified sinusoid vg(t). The energy Eg(t) is stored
in the magnetizing inductance LM. The rectifying diode D1 is
reverse biased and the load current IO is supplied by the
secondary capacitor CO. When Q1 turns off, D1 conducts
and the stored energy Eg(t) is delivered to the output.
Primary current sense. Used for cycle by cycle peak current
control.
Pin 7 – OUTPUT
Gate drive for the external MOSFET switch.
iin(t)
Pin 8 – VCC
Power supply for the controller during normal operation. The
controller will start up when VCC reaches 12 V (typical) and
will shut-down when the VCC voltage is below 6 V (typical). A
decoupling capacitor should be connected between the VCC
pin and GND.
+
When VCC is fully charged to a voltage higher than the startup threshold VCC(ST), the ENABLE signal becomes active and
enables the control logic; the VIN switch turns on, and the
analog-to-digital converter begins to sense the input voltage.
Once the voltage on the VIN pin is above VINSTLOW, the iW3620
commences soft start function. An adaptive soft-start control
algorithm is applied at startup state, during which the initial
output pulses will be small and gradually get larger until the
full pulse width is achieved. The peak current is limited cycle
by cycle by IPEAK comparator.
If at any time the VCC voltage drops below VCC(UVL) threshold
then all the digital logic is reset. At this time VIN switch
id(t)
N:1
vg(t)
vin(t)
VO
+
D1
CO
IO
VAUX
–
VAUX
TS(t)
9.2 Start-up
Prior to start-up the VIN pin charges up the VCC capacitor
through the diode between VIN and VCC (see Figure 8.1).
ig(t)
Q1
Figure 9.2 : Simplified Flyback Converter
In order to tightly regulate the output voltage, the information
about the output voltage and load current needs to be
accurately sensed. In the DCM flyback converter, this
information can be read via the auxiliary winding. During the
Q1 on-time, the load current is supplied from the output filter
capacitor CO. The voltage across LM is vg(t), assuming the
voltage dropped across Q1 is zero. The current in Q1 ramps
up linearly at a rate of:
dig (t )
dt
=
vg (t )
LM
(9.1)
At the end of on-time, the current has ramped up to:
Rev. 1.8
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February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
ig _ peak (tON ) =
vg (t ) × tON
LM
(9.2)
9.4 Dynamic Load Transient
This current represents a stored energy of:
LM
E
=
× ig _ peak (tON ) 2
g
2
(9.3)
When Q1 turns off, ig(t) in LM forces a reversal of polarities on
all windings. Ignoring the communication-time caused by the
leakage inductance LK at the instant of turn-off, the primary
current transfers to the secondary at a peak amplitude of:
NP
id =
× ig _ peak (tON )
(t )
NS
represents the output voltage and is used to regulate the
output voltage.
There are two components that compose the voltage drop
during a load transient event.
VDROP(sense) is the drop in voltage before the VSENSE signal is
able to show a significant drop in output voltage. This is
determined by Vmin or the reference voltage at which a load
transient is detected. The smaller the Vmin means the smaller
this drop in voltage is.
(
(9.4)
Assuming the secondary winding is master and the auxiliary
winding is slave.
VAUX = VO x
NAUX
NS
(9.7)
The final drop in voltage is due to the time from when VSENSE
drops Vmin to when the next VSENSE signal appears. In the
worst case condition this is how much voltage drops during
the longest switching period.
I OUT × TP (No load)
COUT
(9.8)
9.5 Valley Mode Switching
NAUX
NP
Figure 9.3 : Auxiliary Voltage Waveforms
The auxiliary voltage is given by:
=
VAUX
A larger output capacitance in this case greatly reduces the
VDROP(IC).
0V
VAUX = -VIN x
VOUT
VSENSE ( nom )
Keep in mind that a smaller Vmin is less tolerant of noise and
distortions in VSENSE than a larger one.
VDROP ( IC ) =
VAUX
)
VDROP ( sense ) = VSENSE ( nom ) − VSENSE (min) ×
N AUX
(VO + ∆V )
NS
(9.5)
and reflects the output voltage as shown in Figure 9.3.
The voltage at the load differs from the secondary voltage by
a diode drop and IR losses. The diode drop is a function of
current, as are IR losses. Thus, if the secondary voltage is
always read at a constant secondary current, the difference
between the output voltage and the secondary voltage will
be a fixed ΔV. Furthermore, if the voltage can be read when
the secondary current is small; for example, at the knee of
the auxiliary waveform (see Figure 9.3), then ΔV will also be
small. With the iW3620, ΔV can be ignored.
The real-time waveform analyzer in the iW3620 reads the
auxiliary waveform information cycle by cycle. The part then
generates a feedback voltage VFB. The VFB signal precisely
In order to reduce switching losses in the MOSFET and
EMI, the iW3620 employs valley mode switching when
IOUT is above 50%. In valley mode switching, the MOSFET
switch is turned on at the point where the resonant voltage
across the drain and source of the MOSFET is at its lowest
point (see Figure 9.4). By switching at the lowest VDS, the
switching loss will be minimized.
Gate
VDS
Figure 9.4 : Valley Mode Switching
Turning on at the lowest VDS generates lowest dV/dt, thus
valley mode switching can also reduce EMI. To limit the
switching frequency range, the iW3620 can skips valleys
Rev. 1.8
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
(seen in the first cycle in Figure 9.4) when the switching
frequency becomes too high.
iW3620 provides valley mode switching during constant
current (CC) output operation. So, the EMI and switching
losses are still minimized during CC mode. This feature is
superior to other quasi-resonant technologies which only
support valley mode switching during constant voltage
operation. This is beneficial to LED driver applications where
the IC mainly operates in CC mode.
9.6 Constant Voltage Operation
After soft-start has been completed, the digital control block
measures the output conditions. It determines output power
levels and adjusts the control system according to a light
load or a heavy load. If this is in the normal range, the device
operates in the Constant Voltage (CV) mode, and changes
the pulse width (TON), and off time (TOFF) in order to meet the
output voltage regulation requirements. During this mode
the PWM switching frequency is between 30 kHz and 130
kHz, depending on the line and load conditions.
If less than 0.2 V is detected on VSENSE it is assumed that the
auxiliary winding of the transformer is either open or shorted
and the iW3620 shuts down.
9.7 Constant Current Operation
The constant current mode (CC mode) maintains a constant
current output. During this mode of operation the iW3620
will regulate the output current at a constant level regardless
of the output voltage, while avoiding continuous conduction
mode. Figure 9.5 shows the operation modes of the
iW3620.
To achieve this regulation the iW3620 senses the load
current indirectly through the primary current. The primary
current is detected by the ISENSE pin through a resistor from
the MOSFET source to ground.
CC mode
Output Current
Figure 9.5 : Power Envelope
The iW3620 normally operates in a fixed frequency PWM or
critical discontinuous conduction mode when IOUT is greater
than approximately 10% of the specified maximum load
current. As the output load IOUT is reduced, the on-time tON
is decreased. At the moment that the load current drops
below 10% of nominal, the controller transitions to Pulse
Frequency Modulation (PFM) mode. Thereafter, the ontime will be modulated by the line voltage and the off-time
is modulated by the load current. The device automatically
returns to PWM mode when the load current increases.
9.9 Variable Frequency Operation
At each of the switching cycles, the falling edge of VSENSE
will be checked. If the falling edge of VSENSE is not detected,
the off-time will be extended until the falling edge of VSENSE
is detected. The maximum allowed transformer reset time is
75 µs for iW3620.
9.10 Internal Loop Compensation
The iW3620 incorporates an internal Digital Error Amplifier
with no requirement for external loop compensation. For a
typical power supply design, the loop stability is guaranteed
to provide at least 45 degrees of phase margin and –20dB
of gain margin.
9.11 Voltage Protection Functions
The iW3620 includes a function that protects against an
output overvoltage (OVP).
The output voltage is monitored by the VSENSE pin. If the
voltage at this pin exceed its overvoltage threshold the
iW3620 shuts down immediately. However, the IC remains
biased which discharges the VCC supply. Once VCC drops
below the UVLO threshold, the controller resets itself and
then initiates a new soft-start cycle. The controller continues
attempting start-up until the fault condition is removed.
9.12 PCL, OC and SRS Protection
CV mode
Output Voltage
VNOM
9.8 PFM Mode at Light Load
IOUT(CC)
Peak-current limit (PCL), over-current protection (OCP) and
sense-resistor short protection (SRSP) are features built-into
the iW3620. With the ISENSE pin the iW3620 is able to monitor
the primary peak current. This allows for cycle by cycle peak
current control and limit. When the primary peak current
multiplied by the ISENSE sense resistor is greater than 1.1 V
over current is detected and the IC will immediately turn
off the gate drive until the next cycle. The output driver will
send out switching pulse in the next cycle, and the switching
pulse will continue if the OCP threshold is not reached; or,
the switching pulse will turn off again if the OCP threshold is
still reached.
Rev. 1.8
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February 1, 2012
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Digital PWM Current-Mode Controller for AC/DC LED Driver
If the ISENSE sense resistor is shorted there is a potential
danger of the over current condition not being detected.
Thus the IC is designed to detect this sense-resistor-short
fault after start-up, and shutdown immediately. The VCC will
be discharged since the IC remains biased. Once VCC drops
below the UVLO threshold, the controller resets itself and
then initiates a new soft-start cycle. The controller continues
attempting start-up, but does not fully start-up until the fault
condition is removed.
9.13 Shutdown
The shutdown (SD) pin in the iW3620 provides protection
against overtemperature (OTP) and additional overvoltage
(OVP) for the power supply.
The iW3620 switches between monitoring overtemperature
fault and overvoltage fault. In order to detect the resistance in
the NTC for an overtemperature fault, the iW3620 connects
a current source to the SD pin and checks the voltage on the
pin. To ensure that the current source is settled before the
voltage is checked both OTP and OVP are detected on the
last cycle, as depicted in Figure 9.6.
OTP
Detection
OVP
Detection
9.14 Thermal Design
The iW3620 is typically installed inside a small enclosure,
where space and air volumes are constrained. Under these
circumstances θJA (thermal resistance, junction to ambient)
measurements do not provide useful information for this
type of application. Instead we have provided ψJB which
estimates the increase in die junction temperature relative
to the PCB surface temperature. Figure 9.8 shows the PCB
surface temperature is measured at the IC’s GND pin pad.
ψJB
J
B
Exposed
Die Pad
Thermal Epoxy
Artic Silver
Copper Thermal Pad
Under Package
PCB Top Copper Trace
IC Die
Printed Circuit Board
GND pin
Printed Circuit Board
Thermal Vias
Connect top thermal pad
to bottom copper
PCB Bottom Copper Trace
Figure 9.8 : Ways to Improve Thermal Resistance
Using ψJB, the junction temperature (TJ) of the IC can be
found using the equation below.
T=
TB + PH ⋅ ψ JB (9.9)
J
Vgate
where, TB is the PCB surface temperature and PH is the
power applied to the chip or the product of VCC and ICCQ.
Detection Switch
Detection Switch:
When switch is low SD pin is connected to R SD
When switch is high SD pin is connected to a current source ISD
Figure 9.6 : SD Pin Detection Cycles
During an overvoltage monitor cycle the SD pin is connected
to a resistance internal to the chip, RSD, to ground and the
voltage on the SD pin is observed. Figure 9.7 shows how
the SD pin is configured inside the chip.
Ways to Improve Thermal Resistance
●● Increase PCB area and associated amount of copper
interconnect.
iW3620
ISD
Detection
Switch
SD pin
The iW3620 uses an exposed pad package to reduce the
thermal resistance of the package. Although just by using
an exposed package can provide some thermal resistance
improvement, more significant improvements can be
obtained with simple PCB layout and design. Figure 9.8
demonstrates some recommended techniques to improve
thermal resistance, which are also highlighted below.
OTP / OVP
Fault Detect
●● Use thermal adhesive to attach the package to a thermal
pad on PCB.
●● Connect PCB thermal pad to additional copper on PCB.
Environment
ψJB
No Attachment to PCB
70 °C/W
Attach Package to PCB with Thermal Adhesive
63 °C/W
Use Thermal Adhesive and Thermal Vias
49 °C/W
VSD-TH
R SD
Figure 9.7 : Internal Function of SD Pin
Table 9.1 : Improvements in ψJB Based on Limited
Experimentation
Rev. 1.8
iW3620
February 1, 2012
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iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
Effect of Thermal Resistance Improvements
85
10.1 Design Procedure
75
ΨJB (˚C/Watt)
10.0 Design Example
This design example gives the procedure for a flyback
converter using iW3620. Refer to Figure 12.1 for the
application circuit. The design objectives for this adapter
are given in Table 10.1. It meets UL, IEC, and CEC
requirements.
A
~ 30%
65
55
B
45
Determine the Design Specifications
(Vout, Iout_max, Vin_max, Vin_min, ƒline, Ripple specification)
35
Determine Rvin Resistors
25
5
10
15
20
25
30
PCB Area (cm2)
Determine Turns Ratio
A: without thermal adhesive and thermal vias
B: with thermal adhesive and thermal vias
Determine Operating VinTon Limit
Figure 9.9 : Effect of Thermal Resistance Improvements
Determine Magnetizing Inductance
Figure 9.9 shows improvement of approximately 30% in
thermal resistance across different PCB sizes when the
exposed pad is attached to PCB using a thermal adhesive
and thermal vias connect the pad to a larger plate on the
opposing side of the PCB.
Determine Primary Turns
Determine Secondary Turns
Determine Bias Turns and Vcc Capacitance
No
Determine Vsense Resistors
Can you wind this transformer ?
Yes
Determine Current Sensing Resistor
Determine Input Bulk Capacitance
Determine Output Capacitance
Determine Snubber Network
Determine Ton Delay Compensation
Determine SD Pin Components
Finish
Figure 10.1 : Design Procedure
Rev. 1.8
iW3620
February 1, 2012
Page 12
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
10.2 Determine Design Specifications
Parameter
Symbol
VIN
90 - 264 VRMS
fIN
47 - 64 Hz
Maximum
Output Voltage
VOUT(max)
24.0 V
Nominal
Output Voltage
VOUT(nom)
21.0 V
Maximum
Output Current
IOUT(max)
0.87 A
Nominal
Output Current
IOUT(nom)
0.5 A
Output Ripple
VRIPPLE
< 100 mV
Power Out
POUT
20 W
EPA 2.0
Efficiency
h
84%
Input Voltage
Frequency
Range
Table 10.1 : iW3620 Design Specification Table
Use equation 10.1 and 10.2 to determine VOUT in the following
calculations, where VFD is the forward voltage of the output
diode.
VOUT (=
110% × VOUT ( nom )
PCB )
=
VOUT VOUT ( PCB ) + VFD
(10.1)
(10.2)
For this example the nominal VOUT(nom) is 21 V, assuming VFD
is 0.5, VOUT is:
VOUT ( PCB ) = 110% × 21V = 23.1
VIN resistors are chosen primarily to scale down the input
voltage for the IC. The default scale factor for the input
voltage in the IC is 0.0043 and the internal impedance of this
pin is ZIN (5 kW). Therefore, the VIN resistors should equate
to:
Z IN
− Z IN
0.0043
(10.3)
From equation 10.3, ideally RVin should be 1.16 MW. A lower
value of RVin can decrease the startup time of the power
supply. The value of RVin affects the (VINTON) limits of the IC.
720V ⋅ ms
IN
( RVin + Z IN )
( RVin + Z IN )
(10.5)
(VIN ⋅ TON )=
limit
0.0043 ×
(VIN ⋅ TON )=
limit
0.0043 ×
5k W
720V ⋅ms
= 697V ⋅ms
(1.12M W + 5k W )
135V ⋅ms
= 131V ⋅ms
5k W
(1.12 + 5k W )
Keep in mind, by changing RVin to be something other than
1.16 MW the minimum and maximum input voltage for startup also changes.
Since the iW3620 uses the exact scaled value of VIN for its
calculations, there should be a filter capacitor on the input
pin to filter out any noise that may appear on the VIN signal.
This is especially important for line in surge conditions.
10.4 Turns Ratio
The maximum allowable turns ratio between the primary
and secondary winding is determined by the minimum
detectable reset time of the transformer during PFM mode.
NTR (max) =
(VIN ⋅ TON )PFM
TRESET (min) × VOUT
(10.6)
Setting TRESET(min) at 1.5 μs,
131V ⋅ms
= 3.70
1.5ms × 23.6V
For this example a turns ratio of 2.5 is chosen.
10.3 Input Selection
(VIN ⋅ TON )limit =0.0043 × Z
135V ⋅ms
IN
For this example RVin is chosen to be 1.12 MΩ therefore,
=
NTR (max)
VOUT = 23.1V + 0.5V = 23.6V
=
RVin
(VIN ⋅ TON )limit =0.0043 × Z
Keep in mind in valley mode switching the higher the turns
ratio the lower the VDS turn-on voltage, which means less
switch turn-on power loss. Also consider the voltage stress
on the MOSFET (VDS) is higher with an increase in turns
ratio. The voltage stress on the output diode is lower with
an increase in turns ratio respectively.
10.5 Operating Maximum (VINTON)
Maximum operating VINTON or (VINTON)MAX for valley mode
switching is traditionally designed at full load and lowest
input voltage. For the iW3620, two constraints (equation
10.7 and 10.8) need to be satisfied so that indeed (VINTON)MAX
occurs at full load and lowest input voltage.
(10.4)
Rev. 1.8
iW3620
February 1, 2012
Page 13
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
TP (QR min) >
TP' (QR min) >
1
100kHz
(10.7)
1
+ TRES
110kHz
(10.8)
TRES is the VDS resonant period as shown in Figure 10.2. TRES
can be estimated to be approximately 2 μs as a starting point
and then adjusted after the power supply is tested.
Gate
Since we calculated 399 V·μs as our VIN·TON we have enough
margin.
10.6 Magnetizing Inductance
A feature of the iW3620 is the lack of dependence on the
magnetizing inductance for the CC curve.
Although the constant current limit does not depend on the
magnetizing inductance, there are still restrictions on the
magnetizing inductance. The maximum LM is limited by the
amount of power that needs to come out of the transformer
in order for the power supply to regulate. This is given by:
(VIN ⋅ TON )2max × f sw(max op)
LM (max) =
2 × PXFMR (max)
V
×I
= OUT OUT
hX
PXFMR (max)
VDS
Where ηX is the efficiency of the transformer, for this example
we assume it’s 87 %.
TRES
TRESET
TON
TPERIOD
PXFMR (max)
=
Figure 10.2 : VDS Timing
LM (max)
=
When both criterion are met then (VINTON)MAX can be
determined by equation 10.9.
(VIN
1
1
⋅ TON )max
= f SW (max op) ×
+
VINDC (min) NTR × VOUT
where, f SW (max op) =
−1
1
TP (QRmin)
(10.9)
Where VINDC(min) is the minimum input voltage across the bulk
capacitor.
Assuming TRES is 2 μs then:
1
>
+ 2ms= 11.1ms
110kHz
f SW (max=
85kHz , and=
TP 11.76ms
op)
−1
1
1
399V ⋅ms
+
85kHz ×
=
80
V
2.5
23.6
×
Also, to provide enough margin for component values,
usually:
(VIN ⋅ TON )max < (VIN ⋅ TON )limit × 0.85
=
(VIN ⋅ TON )max < 697V ⋅ ms × 0.85
( 399V ⋅ms )2 × 85kHz
= 0.497 mH
2 × 13.6W
LM (min) =
2 × PXFMR ( max )
V
f SW (max op) × REG −TH
RIsense
2
(10.12)
2 × 13.6W
=
0.387 mH
2
85kHz × 1.0V
1.1W
(
)
For this example, we choose LM to be 0.438 mH.
Using 80 V for VINDC(min),
(VIN ⋅ TON )=
max
23.6V × 0.5 A
= 13.6W
0.87
The minimum LM is limited by the maximum allowable peak
primary current. VREG-TH corresponds to the maximum ISENSE
voltage (see Section 10.11 to calculate RIsense). Therefore LM
is limited by:
=
LM (min)
TP (QR min) > 10ms
TP' (QR min)
(10.11)
592V ⋅ms
(10.10)
If these limits do not give enough tolerance for LM, increasing
(VINTON)max can raise the maximum limit on LM. Take care not
to go above (VINTON)limit. Also, keep in mind that if equation
10.7 and 10.8 are not met then (VINTON)max does not occur at
full load and lowest input voltage, thus some of the equations
here would be invalid.
10.7 Primary Winding
In order to keep the transformer from saturation, the
maximum flux density must not be exceeded. Therefore the
minimum primary winding must meet:
Rev. 1.8
iW3620
February 1, 2012
Page 14
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
N PRI ≥
(VIN ⋅ TON )max
Bmax × Ae
=
VSENSE VOUT _ PCB × K SENSE
(10.13)
(10.17)
Where:
Where BMAX is maximum allowed flux density and Ae is the
RBVsns
N
K SENSE
× Vsense
core area. From the transformer core datasheet we find that=
RBVsns + RTVsns ) N SEC
(
(10.18)
for this example BMAX is 320 mT. For an RM6 core, Ae is 35
2
mm .
Internally, VSENSE is compared to a reference voltage
399V ⋅ ms
VSENSE(nom). Where, VSENSE(nom) is 1.538 V.
N
36
≥
=
PRI
320mT × 35mm 2
For this example, we choose 75 primary turns.
10.8 Secondary Winding
From the primary winding turns, we obtain the secondary
winding.
N PRI
NTR
N SEC =
(10.14)
N SEC
=
10.9 Bias Winding and VCC Capacitance
VCC is the supply to the iW3620 and should be below 16 V.
The bias winding needs to ensure than VCC does not exceed
16 V during normal operation.
N SEC (VCC + VFD )
VOUT
(10.15)
30 (11V + 0.5 )
= 15
23.6
Choose a value for NBIAS to be close to this number, for this
example we choose 15 turns.
The VCC capacitor (CVcc) stores the VCC charge during IC
operation and the controller checks this voltage and makes
sure it is within range before starting and operating. The
startup time is a function of how quickly this capacitor can
charge up.
tSTART −UP =
CVCC × VCC ( ST )
VINAC × 2
RVin
From here we can find the ratio necessary for RBVsns and
RTVsns. For this example we set RTVsns to be 20 kΩ. Assuming
we use the same winding for both VSENSE and VCC:
RBVsns
( RBVsns + 20k W )
×
15
30
− I INST
At this point the transformer design is complete. This would
be a good time to confirm that this transformer is feasible to
build.
10.11 Current Sense Resistor
The ISENSE resistor determines the maximum current output
of the power supply. The output current of the power supply
is determined by:
I OUT =
Set VCC at around 11 V
=
N BIAS
(10.19)
∴ RBVsns =
3.0k W
75
= 30
2.5
N BIAS =
VOUT _ PCB
1.538V
= 0.065
23.6V
K=
SENSE
=
0.065
Thus, in our example:
VSENSE ( nom )
K SENSE =
(10.16)
10.10 VSENSE Resistors and Winding
1
2
× NTR × I PRI ( pk ) ×
TRESET
× hX
TPERIOD
(10.20)
When the maximum current output is achieved the voltage
seen on the ISENSE pin (VIsense) should reach its maximum.
Thus, at constant current limit:
I PRI ( pk ) =
VIsense (CC )
RIsense
(10.21)
Substituting this into equation 10.20 we get:
VIsense
=
(CC )
TPERIOD
× KC
TRESET
(10.22)
For iW3620 KC is 0.5 V, therefore RIsense depends on the
maximum output current by;
=
RIsense
The output voltage regulation is mainly determined by the
feedback signal VSENSE.
Rev. 1.8
iW3620
February 1, 2012
NTR × KC
× hX
2 × I OUT ( nom )
(10.23)
Page 15
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
From Table 10.1 IOUT(nom) is given to be 0.5 A, therefore RIsense
is:
RIsense
=
I SEC
( pk )
2.5 × 0.5V
=
× 0.87 =1.08W
2 × 0.5 A
10.12 Input Bulk Capacitor
The input bulk capacitor, CBULK is chosen to maintain enough
input power to sustain constant output power even as the
input voltage is dropping. In order for this to be true CBULK
must be:
PIN =
V
2 × PIN × 0.25 + 21π × arcsin INDC (min)
2 ×VINAC (min)
=
2
2
2 × VINAC
(min) − VINDC (min) × f line
(
)
(10.24)
VOUT (Cable ) × I OUT
hpower supply
VINAC(min) is the minimum input voltage (rms) to be inputted
into the power supply and fline is the lowest line frequency for
the power supply (in this case 47 Hz). VINDC(min) is determined
in Section 10.5 to be 80 V.
23.6V × 0.5 A
= 13.88W
0.85
2 × 13.88W × 0.25 + 21π × arcsin
CBULK=
2 × 852 − 802 × 47
=
PIN
(
)
(
80V
2 ×85VAC
)=
10.13 Output Capacitance
22mF
)
LM
× NTR × h X
I OUT ( HIGH ) × TP (No load)
VDROP ( IC )
(10.28)
Then solving for VDROP(IC), where VDynamic(DROP) is the maximum
allowable drop in voltage for the design during dynamic
response, and VDROP(sense) is the drop in voltage before VSENSE
signal is low enough to register a dynamic transient.
I OUT ( HIGH ) × TP (No load)
VDynamic ( Drop ) − VDROP ( sense )
(10.29)
RPreload × (VIN ⋅ TON ) PFM
2
2 × LM × VOUT
× hNo load
(10.30)
Assume that we want no more than 2.0 V drop on VOUT(PCB)
during load transient from no load to 100% load and the
efficiency of the power supply at no load (ηNo load) is 50% ,
then COUT(Dynamic) is:
20k W × (131V ⋅ms )
2
2 × 0.438mH × 23.6V 2
VDROP ( sense ) =
(1.538V − 1.48V ) ×
× 0.5 = 352ms
23.6V
= 0.890V
1.538V
Plug everything into equation 10.29:
2
(10.26)
The ISEC(pk) is:
I SEC ( pk )
=
COUT ( Dynamic ) =
(10.25)
2
2 × NTR
× h X × VOUT
(VIN ⋅ TON )MAX
Assume that the load transient goes from no load to IOUT(HIGH).
Then from Section 9.4, equation 9.8 we find that the
relationship between output capacitance (COUT(Dynamic)) and
VDROP(IC) is :
TP ( No load ) =
The output capacitor supplies the load current when the
secondary current is below the output current.
QOUT =
The actual ripple is higher than the above calculations
suggest, because the calculations do not include ESR.
2
QOUT
VOUT ( ripple)
3.74mC
= 37mF
100mV
COUT (Steady State)=
=
TP ( No load )
Assuming an ideal capacitor where ESR (equivalent series
resistance) and ESL (equivalent series inductance) are
negligible then:
(
0.438mH × (1.98 A − 0.5 A )
= 3.74mC
2 × 2.52 × 0.87 × 23.6V
Where TP(No load) is the maximum period under no load
condition, given by equation 10.30:
The output capacitance affects both the steady state ripple
and the dynamic response of the power supply.
LM × I SEC ( pk ) − I OUT ( nom )
QOUT
=
COUT ( Dynamic ) =
For this example CBULK is chosen to be 47 µF.
COUT (Steady State) =
399V ⋅ms
0.87 1.98 A
× 2.5 ×=
0.438mH
2
We recommend using ±1% tolerance resistors for RIsense.
CBULK
So to keep VOUT(ripple) to be 100 mV,
COUT ( Dynamic=
)
0.5 A × 352ms
= 159mF
( 2V − 0.890V )
Pick the larger capacitance value between COUT(Dynamic) and
COUT(Steady State). In this case COUT is chosen to be 470 μF.
(10.27)
Rev. 1.8
iW3620
February 1, 2012
Page 16
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
10.14 Snubber Network
The snubber network is implemented to reduce the voltage
stress on the MOSFET immediately following the turn off of
the gate drive. The goal is to dissipate the energy from the
leakage inductance of the transformer. For simplicity and
a more conservative design first assume the energy of the
leakage inductance is only dissipated through the snubber.
Thus:
1
2
2
2
1
2
× Llk × I PRI
( pk ) =2 × CSNUB × VSnub ( pk ) − VSnub ( val )
(10.31)
Llk can be measured from the transformer. VSnub(pk) and
VSnub(val) refer to the voltage measured across the snubber
capacitor. Choose a CSNUB, keeping in mind that the larger
the value of CSNUB the lower the voltage stress is on the
MOSFET. However, capacitors are more expensive the
larger their capacitance. Choose CSNUB based on these two
criteria and select VSnub(pk) and VSnub(val). Now a resistor needs
to be selected to dissipate VSnub(pk) to VSnub(val) during the ontime of the gate driver. The dissipation of this resistor is
given by:
VSnub (val )
VSnub ( pk )
1. Measure the difference between high line and low line
constant current limit without filter components.
2. Find the curve that best matches this difference from
Figure 11.1.
3. Find the LM that matches the power supply, and find the
tRC.
4. Find RDly and CDly from equation 10.33
t RC = RDly × CDly
(10.33)
10.16 SD Protection
The SD pin can be configured to provide three different
types of protection: OTP protection, OVP protection and
both OVP and OTP Protection. Figure 10.3 shows the three
configurations plus the configuration for no OTP and OVP
protection.
RSD1(ext)
SD pin
=e
− TP ( min op)
RNTC
RSNUB ⋅CSNUB
Using equation 10.32 solve for RSNUB. This gives a
conservative estimate of what CSNUB and RSNUB should be.
Included in the snubber network is also a resistor in series with
a diode. The diode directs current to the snubber capacitor
when the MOSFET is turned off; however there is some
reverse current that goes through the diode immediately
after the MOSFET is turned back on. This reverse current
occurs because there is a short period of time when the
diode still conducts after switching from forward biased to
reverse biased. This conduction distorts the falling edge of
the VSENSE signal and affects the operation of the IC. So,
the resistor in series with the diode is there to diminish the
reverse current that goes through the diode immediately
after the MOSFET is turned on.
10.15 TON Delay Filter
iW3620 also contains a feature that allows for adjustment
to match high line and low line constant current curves.
The mismatch in high line and low line is due to the delay
from the IC propagation delay, driver turn-on delay, and the
MOSFET turn-on delay. The driver turn-on delay maybe
further increased by a gate resistor to the MOSFET. To
adjust for these delays the iW3620 factors these delays into
its calculations and slightly over compensates for them to
provide flexibility. RDly and CDly provide extra delay in the
circuit to tweak the compensation. To determine values RDly
and CDly follow these steps:
SD pin
RSD2(ext)
RSD(ext)
(optional)
(10.32)
RNTC
OUTPUT
a) Overtemperature Protection only
b) Overtemperature Protection
and Overvoltage Protection
SD pin
RSD(ext)
RSD(ext)
SD pin
c) Overvoltage Protection only
d) No Overtemperature Protection
and no overvoltage protection
Figure 10.3 : SD Pin Application Configurations
OTP Only
To detect an overtemperature protection the iW3620 sends
a 107 mA current (ISD) to the SD pin every four cycles (see
Section 9.13). On the last cycle the iW3620 observes the
voltage on the SD pin and detects an OTP fault if the voltage
is lower than VSD-TH, 1.0 V during normal operation and 1.2 V
during startup. So RSD(ext) in series with NTC must meet
( RNTC +RSD(ext ) ) × I SD > VSD−TH (10.34)
in order not to trigger OTP fault during normal operation.
OVP Only
For the other four cycles, the iW3620 connects the SD pin
to RSD to ground (see Section 9.13). At the last cycle the
iW3620 observes the voltage on the SD pin and detects an
Rev. 1.8
iW3620
February 1, 2012
Page 17
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
OVP fault if the voltage is higher than VSD-TH, 1 V. In order to
not trigger OVP fault, assuming 0 V drop across the series
diode, RSD(ext) must meet:
3. VCC winding and rectifier diode loop.
L
VOUT
+
VOUT _ PCB
N SEC
× N AUX ×
RSD
RSD
< VSD −TH
+ RSD (ext )
N
3)
Both OTP and OVP
Optional
NTC
Thermistor
To find RSD1(ext) so that OVP can be detected, use equation
10.35. To find RSD2(ext) in series with the NTC use equation
10.34.
No OTP and OVP
If OTP and OVP from the SD pin are not needed, simply
place a resistor, RSD(ext) to ground from the SD pin. Make
sure RSD(ext) meets equation 10.36 so OTP protection does
not trip.
(10.36)
Note that this means OVP is not detected through the SD pin;
however, OVP from VSENSE pin is still active and the iW3620
still shuts down if overvoltage condition is detected.
+
+
(10.35)
where, RSD = 8.333 kΩ
RSD (ext ) × I SD > VSD −TH
2)
1)
1
NC
2
VSENSE
3
VIN
4
SD
RTN
VCC 8
OUTPUT 7
ISENSE 6
GND 5
U1
iW3620
Figure 10.4 : Switching Loops
To improve ESD performance provide a low impedance path
from the ground pin of the transformer to the ac power source
and make sure this path does not go through the IC ground
pin. A discharge spark gap helps to transfer ESD and EOS
energy from the secondary side of the power supply directly
to the external ac power source.
In a switch-mode power supply there are several ground
signals, namely: the power ground, the switching ground
and the control logic ground. These ground signals should
be connected by a star connection. Ground traces should
be kept as short as possible. A thick trace on the switching
ground helps to lessen switching losses.
Since for this example OTP and OVP are not necessary we
place a resistor from SD pin to ground and calculate its value
from equation 10.36.
RNTC > 1.2V
100mA
=
12k W
10.17 PCB Layout
In the iW3620, there are two signals that are important to
control the output performance; these are the ISENSE signal
and the VSENSE signal. The ISENSE resistor should be close to
the source of the MOSFET to avoid any trace resistance from
contaminating the ISENSE signal. Also, the ISENSE signal should
be placed close to the ISENSE pin. The VSENSE signal should
be placed close to the transformer to improve the quality of
the sensing signal. Also for better output performance all
bypass capacitors should be placed close to their respective
pins.
To reduce EMI, switching loops need to be minimized. These
loops include (see Figure 10.4):
1. The input bulk capacitor, primary winding, MOSFET and
RIsense loop.
2. The output diode, output capacitor and secondary
winding loop.
Rev. 1.8
iW3620
February 1, 2012
Page 18
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
11.0 Performance Characteristics
120
∆IOUT (Note1)
50 mA
40 mA
30 mA
20 mA
10 mA
(RDly x CDly), τRC (ns)
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
Magnetizing Inductance LM (mH)
3.0
Figure 10.5 : TON Compensation Chart
12.0 Application Circuit
L
2 A / 250 V
470 µH
VOUT
10 kΩ
+
Cbulk
0.1 µF
N
Cbulk
47 µF
+
Rvin
560 kΩ
Rvin
560 kΩ
470 pF
Csnub
10 nF
Rsnub
120 kΩ
+
Cvcc
4.7 µF
Cout +
470 µF
0Ω
Rpreload
20 kΩ
10 Ω
RTN
Rtvsns
20 kΩ
Rbvsns
3.0 kΩ
68 pF
Rntc
20 kΩ
VCC 8
1
NC
2
VSENSE
3
VIN
ISENSE 6
4
SD
GND 5
OUTPUT 7
U1
iW3620
Rgate
10 Ω
Rdly
1 kΩ
Cdly
270 pF
Risense
1.1 Ω
Figure 12.1 : Typical Application Circuit
Note 1: ΔIOUT refers to the difference in constant current limit between 264 Vac and 90 Vac when no RDLY and CDLY are applied.
Rev. 1.8
iW3620
February 1, 2012
Page 19
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
13.0 Physical Dimensions
8-Lead Small Outline (SOIC) Package
E
M
8
5
1
4
8
5
N
H
4
e
TOP VIEW
1
EXPOSED
PAD
BOTTOM VIEW
Inches
Symbol
D
MIN
MAX
MIN
A
0.051
0.067
1.30
1.70
A1
0.0020
0.0060
0.05
0.150
A
COPLANARITY
0.10 (0.004)
B
SEATING
PLANE
L
α
C
SIDE VIEWS
MAX
B
0.014
0.019
0.36
0.48
C
0.007
0.010
0.18
0.25
D
0.189
0.197
4.80
5.00
E
0.150
0.157
3.81
3.99
e
A1
Millimeters
0.050 BSC
1.27 BSC
H
0.228
0.244
5.79
6.20
N
0.086
0.118
2.18
3.00
2.39
M
0.094
0.126
L
0.016
0.050
0.41
1.27
α
0°
8°
3.20
Figure 13.1 : Physical dimensions, 8-lead SOIC package
Compliant to JEDEC Standard MS12F
Controlling dimensions are in inches; millimeter dimensions are for reference only
This product is RoHS compliant and Halide free.
Soldering Temperature Resistance:
[a] Package is IPC/JEDEC Std 020D Moisture Sensitivity Level 3
Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 mm per end. Dimension E does not include interlead flash or protrusion. Interlead flash or
protrusion shall not exceed 0.25 mm per side.
The package top may be smaller than the package bottom. Dimensions D and E are determined at the
outermost extremes of the plastic bocy exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
14.0 Ordering Information
Part Number
Package
Description
iW3620-00
SOIC-8
Tape & Reel1
Note 1: Tape & Reel packing quantity is 2,500/reel.
Rev. 1.8
iW3620
February 1, 2012
Page 20
iW3620
Digital PWM Current-Mode Controller for AC/DC LED Driver
About iWatt
iWatt Inc. is a fabless semiconductor company that develops intelligent power management ICs for computer, communication,
and consumer markets. The company’s patented pulseTrain™ technology, the industry’s first truly digital approach to power
system regulation, is revolutionizing power supply design.
Trademark Information
© 2012 iWatt, Inc. All rights reserved. iWatt, EZ-EMI and pulseTrain are trademarks of iWatt, Inc. All other trademarks and
registered trademarks are the property of their respective companies.
Contact Information
Web: http://www.iwatt.com
E-mail: info@iwatt.com
Phone: 408-374-4200
Fax: 408-341-0455
iWatt Inc.
675 Campbell Technology Parkway, Suite 150
Campbell, CA 95008
Disclaimer
iWatt reserves the right to make changes to its products and to discontinue products without notice. The applications
information, schematic diagrams, and other reference information included herein is provided as a design aid only and are
therefore provided as-is. iWatt makes no warranties with respect to this information and disclaims any implied warranties of
merchantability or non-infringement of third-party intellectual property rights.
iWatt cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an iWatt product. No
circuit patent licenses are implied.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property
or environmental damage (“Critical Applications”).
IWATT SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO
BE SUITABLE FOR USE IN LIFE‑SUPPORT APPLICATIONS, DEVICES OR SYSTEMS, OR OTHER CRITICAL
APPLICATIONS.
Inclusion of iWatt products in critical applications is understood to be fully at the risk of the customer. Questions concerning
potential risk applications should be directed to iWatt, Inc.
iWatt semiconductors are typically used in power supplies in which high voltages are present during operation. High-voltage
safety precautions should be observed in design and operation to minimize the chance of injury.
Rev. 1.8
iW3620
February 1, 2012
Page 21
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