HI3-0546-5

HI-546, HI-547, HI-548, HI-549 ® Data Sheet September 21, 2005 Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1kΩ of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521. FN3150.5 Features • Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P • No Channel Interaction During Overvoltage • Guaranteed rON Matching • Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V • Break-Before-Make Switching • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns • Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Data Acquisition • Industrial Controls • Telemetry For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-546, HI-547, HI-548, HI-549 Ordering Information (Continued) Ordering Information PART NUMBER PART MARKING TEMP. RANGE (oC) HI1-0546-5 HI1-546-5 HI1-0546-2 HI1-546-2 HI3-0546-5 HI3-546-5 0 to 75 28 Ld PDIP E28.6 HI4P0546-5 HI4P546-5 0 to 75 28 Ld PLCC N28.45 HI4P0546-5Z (Note) HI4P546-5Z 0 to 75 28 Ld PLCC (Pb-free) N28.45 HI9P0546-9** HI9P546-9 -40 to 85 28 Ld SOIC M28.3 -40 to 85 28 Ld SOIC (Pb-free) M28.3 HI9P0546-9Z** HI9P546-9Z (Note) 0 to 75 PACKAGE PKG. DWG. # 28 Ld CERDIP F28.6 -55 to 125 28 Ld CERDIP F28.6 HI1-0547-5 HI1-547-5 0 to 75 28 Ld CERDIP F28.6 HI3-0547-5 HI3-547-5 0 to 75 28 Ld PDIP E28.6 HI3-0547-5Z (Note) HI3-0547-5Z 0 to 75 28 Ld PDIP* (Pb-free) E28.6 HI4P0547-5 HI4P547-5 0 to 75 28 Ld PLCC N28.45 HI4P0547-5Z (Note) HI4P547-5Z 0 to 75 28 Ld PLCC (Pb-free) N28.45 HI9P0547-9 HI9P547-9 -40 to 85 28 Ld SOIC M28.3 HI9P0547-9Z (Note) HI9P547-9Z -40 to 85 28 Ld SOIC (Pb-free) M28.3 HI1-0548-2 HI1-548-2 HI1-0548-5 HI1-548-5 0 to 75 16 Ld CERDIP F16.3 HI3-0548-5 HI3-548-5 0 to 75 16 Ld PDIP E16.3 HI4P0548-5 HI4P548-5 0 to 75 20 Ld PLCC N20.35 -55 to 125 16 Ld CERDIP F16.3 PART NUMBER HI9P0548-5** PART MARKING HI9P548-5 HI9P0548-5Z** HI9P548-5Z (Note) TEMP. RANGE (oC) PACKAGE 0 to 75 16 Ld SOIC M16.15 0 to 75 16 Ld SOIC (Pb-free) M16.15 HI9P0548-9 HI9P548-9 -40 to 85 16 Ld SOIC M16.15 HI9P0548-9Z (Note) HI9P548-9Z -40 to 85 16 Ld SOIC (Pb-free) M16.15 HI1-0549-2 HI1-549-2 -55 to 125 16 Ld CERDIP F16.3 HI3-0549-5 HI3-549-5 0 to 75 16 Ld PDIP E16.3 HI4P0549-5 HI4P549-5 0 to 75 20 Ld PLCC N20.35 HI4P0549-5Z (Note) HI4P549-5Z 0 to 75 20 Ld PLCC (Pb-free) N20.35 HI9P0549-9 HI9P549-9 -40 to 85 16 Ld SOIC M16.15 HI9P0549-9Z (Note) HI9P549-9Z -40 to 85 16 Ld SOIC (Pb-free) M16.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. **Add “96” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts HI-546 (CERDIP, PDIP, SOIC) TOP VIEW +VSUPPLY 28 OUT 1 HI-547 (CERDIP, PDIP, SOIC) TOP VIEW +VSUPPLY 1 OUT B 2 28 OUT A 27 -VSUPPLY NC 2 27 -VSUPPLY NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 VREF 13 16 ADDRESS A1 VREF 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 2 PKG. DWG. # HI-546, HI-547, HI-548, HI-549 Pinouts (Continued) NC NC +VSUPPLY OUT -VSUPPLY IN 8 IN 8B NC OUT B +VSUPPLY OUT A -VSUPPLY IN 8A HI-547 (PLCC) TOP VIEW IN 16 HI-546 (PLCC) TOP VIEW 4 3 2 1 28 27 26 4 3 2 1 28 27 26 IN 4B 8 22 IN 4A IN 11 9 21 IN 3 IN 3B 9 21 IN 3A IN 10 10 20 IN 2 IN 2B 10 20 IN 2A IN 9 11 19 IN 1 IN 1B 11 19 IN 1A 12 13 14 15 16 17 18 HI-548 (CERDIP, PDIP, SOIC) TOP VIEW 12 13 14 15 16 A0 1 16 A1 A0 1 15 A2 ENABLE 2 14 GND 3 18 HI-549 (CERDIP, PDIP, SOIC) TOP VIEW ENABLE 2 -VSUPPLY 17 ENABLE 22 IN 4 A0 IN 12 8 A1 23 IN 5A A2 IN 5B 7 NC 23 IN 5 VREF IN 13 7 GND 24 IN 6A ENABLE IN 6B 6 A0 24 IN 6 A1 IN 14 6 A2 25 IN 7A A3 IN 7B 5 GND 25 IN 7 VREF IN 15 5 -VSUPPLY 16 A1 15 GND 14 +VSUPPLY 3 IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 IN 1 5 17 +V SUPPLY 14 IN 6 9 10 11 12 13 IN 7 IN 3 8 IN 8 15 IN 5 NC IN 2 7 OUT 16 NC IN 4 NC 6 3 A1 GND 2 1 20 19 18 +VSUPPLY -VSUPPLY 4 17 IN 1B IN 1A 5 16 NC NC 6 IN 2A 7 15 IN 2B IN 3A 8 14 IN 3B 9 10 11 12 13 IN 4B 18 GND 3 OUT B -VSUPPLY 4 NC 19 NC 20 A0 A2 1 OUT A A1 2 ENABLE NC 3 IN 4A A0 HI-549 (PLCC) TOP VIEW ENABLE HI-548 (PLCC) TOP VIEW 9 OUT B HI-546, HI-547, HI-548, HI-549 TRUTH TABLE HI-547 (Continued) TRUTH TABLE HI-546 A3 A2 A1 A0 EN “ON” CHANNEL A2 A1 A0 EN “ON” CHANNEL PAIR X X X X L None H L L H 5 L L L L H 1 H L H H 6 L L L H H 2 H H L H 7 L L H L H 3 H H H H 8 L L H H H 4 L H L L H 5 L H L H H 6 A2 A1 A0 EN “ON” CHANNEL L H H L H 7 X X X L None L H H H H 8 L L L H 1 H L L L H 9 L L H H 2 H L L H H 10 L H L H 3 H L H L H 11 L H H H 4 H L H H H 12 H L L H 5 H H L L H 13 H L H H 6 H H L H H 14 H H L H 7 H H H L H 15 H H H H 8 H H H H H 16 TRUTH TABLE HI-548 TRUTH TABLE HI-549 TRUTH TABLE HI-547 A1 A0 EN “ON” CHANNEL PAIR A2 A1 A0 EN “ON” CHANNEL PAIR X X L None X X X L None L L H 1 L L L H 1 L H H 2 L L H H 2 H L H 3 L H L H 3 H H H 4 L H H H 4 Functional Diagrams HI-546 HI-547 OUT 1K OUT A 1K IN 1A IN 1 1K 1K OUT B IN 8A IN 2 DECODER/ DRIVER 1K IN 1B 1K 1K DECODER/ DRIVER IN 8B IN 16 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT † DIGITAL INPUT † † † † † OVERVOLTAGE CLAMP AND SIGNAL ISOLATION † DIGITAL INPUT 5V REF LEVEL SHIFT † † † † VREF A0 A1 A2 EN PROTECTION PROTECTION VREF A0 A1 A2 A3 EN 4 HI-546, HI-547, HI-548, HI-549 Functional Diagrams (Continued) HI-548 HI-549 OUT 1K OUT A 1K IN 1A IN 1 1K 1K OUT B IN 4A IN 2 1K DECODER/ DRIVER IN 1B 1K 1K DECODER/ DRIVER IN 4B IN 8 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT † DIGITAL INPUT † † † 5V REF † DIGITAL INPUT † LEVEL SHIFT † † † A0 A1 EN PROTECTION PROTECTION A0 A1 A2 EN Schematic Diagrams ADDRESS DECODER V+ P P P P A0 OR A0 A1 OR A1 A2 OR A2 A3 OR A3 P P P N N N N N TO N-CHANNEL DEVICE OF THE SWITCH N N ENABLE DELETE A3 OR A3 INPUT FOR HI-547, HI-548, HI-549 DELETE A2 OR A2 INPUT FOR HI-549 5 TO P-CHANNEL DEVICE OF THE SWITCH V- HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) MULTIPLEX SWITCH FROM DECODE OVERVOLTAGE PROTECTION N V+ P R11 1K D6 Q5 D7 D4 D5 N IN N Q6 V- P FROM DECODE 6 OUT HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 Q1 VREF Q4 D3 GND LEVEL SHIFTER V+ OVERVOLTAGE PROTECTION P P P N R2 P P P P R5 V+ R3 D1 LEVEL SHIFTED ADDRESS TO DECODE N N N N R8 N N N V- GND ADD IN 7 P R7 R6 N P R4 D2 R1 200 Ω P V- N HI-546, HI-547, HI-548, HI-549 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V or 20mA, Whichever Occurs First Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) 16 Ld CERDIP Package . . . . . . . . . . . 85 32 28 Ld CERDIP Package . . . . . . . . . . . 55 18 28 Ld PDIP Package*. . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A 28 Ld PLCC Package . . . . . . . . . . . . . 70 N/A 20 Ld PLCC Package . . . . . . . . . . . . . 80 N/A 28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A 16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC, SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Ranges HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.5 - - 0.5 - µs Full - - 1.0 - - 1.0 µs Break-Before Make Delay, tOPEN 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns To 0.1% 25 - 1.2 - - 1.2 - µs To 0.01% 25 - 3.5 - - 3.5 - µs Note 6 25 50 68 - 50 68 - dB 25 - 10 - - 10 - pF HI-546 25 - 52 - - 52 - pF HI-547 25 - 30 - - 30 - pF HI-548 25 - 25 - - 25 - pF HI-549 25 - 12 - - 12 - pF 25 - 0.1 - - 0.1 - pF Input Low Threshold, TTL Drive, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH (Note 8) Full 4.0 - - 4.0 - - V 25 - - 0.8 - - 0.8 V PARAMETER SWITCHING CHARACTERISTICS Access Time, tA Enable Delay (OFF), tOFF(EN) Settling Time Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance CD(OFF) Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS MOS Drive, VAL (HI-546/547 Only) 8 VREF = 10V HI-546, HI-547, HI-548, HI-549 Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST CONDITIONS PARAMETER TEMP (oC) -2 -5, -9 MIN TYP MAX MIN TYP MAX UNITS MOS Drive, VAH (HI-546/547 Only) VREF = 10V 25 6.0 - - 6.0 - - V Input Leakage Current (High or Low), IA Note 5 Full - - 1.0 - - 1.0 µA Full -15 - +15 -15 - +15 V 25 - 1.2 1.5 - 1.5 1.8 kΩ Full - 1.5 1.8 - 1.8 2.0 kΩ 25 - - 7.0 - - 7.0 % ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON Note 2 ∆rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA 25 - 4.0 - - 4.0 - nA Full - - 2.0 - - - µA 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA Full - - 50 - - 50 nA Full - 7.5 - - 7.5 - mW Off Output Leakage Current, ID(OFF) Note 3 Note 3 ID(OFF) With Input Overvoltage Applied Note 4 On Channel Leakage Current, ID(ON) Note 3 Differential Off Output Leakage Current IDIFF (HI-547, HI-549 Only) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Note 7 Full - 0.5 2.0 - 0.5 2.0 mA Current, I- Note 7 Full - 0.02 1.0 - 0.02 1.0 mA NOTES: ± 2. VOUT = ±10V, IOUT = 100µA. 3. 10nA is the practical lower limit for high speed measurement in the production test environments. 4. Analog Overvoltage = ±33V. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 7. VEN , VA = 0V or 4V. 8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended. 9 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified 100µA V2 IN OUT VIN rON = V2 100µA FIGURE 1A. ON RESISTANCE TEST CIRCUIT 1.4 1.2 1.1 25oC 1.0 -55oC 0.9 0.8 0.7 0.6 -10 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -8 -6 -4 -2 0 2 4 6 8 10 5 ANALOG INPUT (V) 6 7 8 9 10 11 12 13 14 SUPPLY VOLTAGE (±V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA LEAKAGE CURRENT 10nA ON LEAKAGE CURRENT ID(ON) OFF OUTPUT CURRENT ID(OFF) +0.8V EN OUT 1nA A ±10V ID(OFF) ± ON RESISTANCE (kΩ) NORMALIZED ON RESISTANCE (REFERRED TO VALUE AT ±15V) 125oC 1.3 10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 10pA 25 50 75 100 TEMPERATURE (oC) 125 FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE 10 FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 9) 15 HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A +0.8V A EN ± ±10V ID(ON) EN 10V ±10V 10V ± 4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 9) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 9) NOTE: 10V. (Two measurements per device for ID(OFF): ±10V and ± 9. Two measurements per channel: ±10V and 10V.) ± FIGURE 2. LEAKAGE CURRENTS ANALOG INPUT CURRENT (IIN) 15 5 12 4 9 3 6 2 OUTPUT OFF LEAKAGE CURRENT ID(OFF) 3 1 0 0 15 18 21 24 27 30 33 ANALOG INPUT OVERVOLTAGE (±V) OUTPUT OFF LEAKAGE CURRENT (nA) ANALOG INPUT CURRENT (mA) 18 A IIN A ID(OFF) ±VIN 36 FIGURE 3B. TEST CIRCUIT FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF LEAKAGE CURRENT vs ANALOG INPUT OVER-VOLTAGE FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS ±14 -55oC 25oC SWITCH CURRENT (mA) ±12 ±10 125oC ±8 ±6 ±VIN ±4 A ±2 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (±V) 14 FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4. ON CHANNEL CURRENT 11 FIGURE 4B. TEST CIRCUIT HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) 8 6 V+ IN 1 A3 VSUPPLY = ± 10V 2 A1 IN 2 THRU IN 15 A0 IN 16 EN +4V GND ± 50Ω VA ±10V/±5V HI-546 † A2 VSUPPLY = ± 15V 4 +15V/+10V +ISUPPLY 10V/ 5V OUT V10MΩ A 0 1K 10K 100K 1M ± SUPPLY CURRENT (mA) A 10M 14pF -ISUPPLY -15V/-10V TOGGLE FREQUENCY (Hz) † Similar connection for HI-547/HI-548/HI-549. FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT FIGURE 5. DYNAMIC SUPPLY CURRENT +15V VA INPUT 2V/DIV. VREF = OPEN FOR LOGIC HIGH LEVEL < 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V ACCESS TIME (ns) 800 VREF S1 ON A3 S16 ON 700 A2 50Ω VA OUTPUT 0.5V/DIV. 600 A1 V+ IN 1 ±10V IN 2 THRU IN 15 HI-546 † A0 ± 900 10V IN 16 500 EN +4V GND OUT V- 400 10kΩ 100ns/DIV. 300 3 4 5 6 8 7 9 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 -15V 15 † Similar connection for HI-547/HI-548/HI-549. FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) VAH = 4.0V FIGURE 6B. TEST CIRCUIT VA INPUT 2V/DIV. ADDRESS DRIVE (VA) 50% 0V S1 ON +10V OUTPUT 10% OUTPUT 5V/DIV. -10V S16 ON tA 200ns/DIV. FIGURE 6C. MEASUREMENT POINTS FIGURE 6D. WAVEFORMS FIGURE 6. ACCESS TIME 12 50pF HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms A3 TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) HI-546 † A2 +5V VAH = 4V IN 1 IN 2 THRU 50Ω VA +4V A1 IN 15 A0 IN 16 EN OUT GND ADDRESS DRIVE (VA) 0V VOUT OUTPUT 50pF 1kΩ 50% 50% tOPEN † Similar connection for HI-547/HI-548/HI-549 FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY A3 HI-546 † A2 A1 IN 1 +10V IN 2 THRU IN16 ENABLE DRIVE (VA) 0V VOUT 90% OUT EN 50Ω 50% 50% A0 VA VAH = 4V GND 1kΩ OUTPUT 50pF 10% 0V t ON(EN) † Similar connection for HI-547/HI-548/HI-549 FIGURE 8A. TEST CIRCUIT 13 t OFF(EN) FIGURE 8B. MEASUREMENT POINTS HI-546, HI-547, HI-548, HI-549 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) ENABLE DRIVE 2V/DIV. DISABLED OUTPUT 2V/DIV. ENABLED (S1 ON) 100ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8. ENABLE DELAYS 14 HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: PASSIVATION: 83.9 mils x 159 mils Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 485 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-546 EN (18) A0 (17) A1 A2 (16) (15) HI-547 A3 VREF (14) (13) GND (12) EN (18) A0 (17) A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1 (19) IN 9 (11) IN 1A (19) IN 2 (20) IN 10 (10) IN 2A (20) IN 3 (21) IN 11 (9) IN 3A (21) IN 3B (9) IN 4 (22) IN 12 (8) IN 4A (22) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 15 (5) IN 7A (25) IN 7B (5) IN 8 (26) IN 16 (4) IN 8A (26) IN 8B (4) V- (27) OUT (28) +V (1) 15 NC (2) V- (27) IN 1B (11) IN 2B (10) OUT A (28) +V (1) OUT B(2) HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: PASSIVATION: 83 mils x 108 mils Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm SUBSTRATE POTENTIAL (NOTE): TRANSISTOR COUNT: -VSUPPLY 253 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-548 IN 6 (11) IN 7 IN 8 (10) (9) HI-549 OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) IN 2 (5) IN 2B (12) IN 2A (5) +V (13) GND (14) IN 1 (4) IN 1B (13) +V (14) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) 16 EN (2) -V (3) GND (15) A1 (16) A0 (1) EN (2) HI-546, HI-547, HI-548, HI-549 17 HI-546, HI-547, HI-548, HI-549 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.232 - 5.92 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 15.49 5 eA ccc M C A-B S e eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 12.70 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 18 N 28 28 8 Rev. 0 4/94 HI-546, HI-547, HI-548, HI-549 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -BD A2 SEATING PLANE e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - 0.13 A L D1 MIN A E -C- MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 35.1 39.7 5 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 19 28 28 9 Rev. 1 12/00 HI-546, HI-547, HI-548, HI-549 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N28.45 (JEDEC MS-018AB ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 20 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE HI-546, HI-547, HI-548, HI-549 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 21 MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS MAX A1 e α MIN 28 0o 28 7 8o Rev. 0 12/93 HI-546, HI-547, HI-548, HI-549 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 eA ccc M C A-B S e eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 22 N 16 16 8 Rev. 0 4/94 HI-546, HI-547, HI-548, HI-549 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 N 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 23 5 E 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 0.355 19.68 D1 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 0.204 16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 16 6 7 4 9 Rev. 0 12/93 HI-546, HI-547, HI-548, HI-549 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N20.35 (JEDEC MS-018AA ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N 20 20 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24