IS32FL3238
18-CHANNEL LED DRIVER
March 2020
GENERAL DESCRIPTION
FEATURES
IS32FL3238 is an LED driver with 18 constant current
channels. Each channel can be pulse width modulated
(PWM) by 16 bits for smooth LED brightness control.
In addition, each channel has an 8-bit output current
control register which allows fine tuning the current for
rich RGB color mixing, e.g., a pure white color LED
application. The maximum output current of each
channel is designed to be 78mA, which can be
adjusted by one 8-bit global control register.
Proprietary programmable algorithms are used in
IS32FL3238 to minimize audible noise caused by the
MLCC decoupling capacitor. All registers can be
programmed via a high speed I2C (1MHz).
IS32FL3238 can be turned off with minimum current
consumption by either pulling the SDB pin low or by
using the software shutdown feature.
IS32FL3238 is available in eTSSOP-28 package. It
operates from 2.7V to 5.5V over the temperature range
of -40°C to +125°C
2.7V to 5.5V VCC supply
1MHz I2C interface, automatic address increment
function with readout function
Four selectable I2C addresses
Accurate color rendition
- Selectable 8-bit/10-bit/12-bit/16-bit PWM
- 8-bit dot correction
- 8-bit global current adjust
Open/short detect function
62kHz PWM frequency(8-bit PWM)
Temperature detect function
EMI/Noise reduction technology
- Spread spectrum
- Selectable phase delay
- Selectable 180 degree clock phase
-40°C to +125°C temperature range
eTSSOP-28 package
AEC-Q100 Qualified
APPLICATIONS
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Rev. A, 01/02/2020
Ambient lighting
Roof lighting
Display backlight
Functional lighting
1
IS32FL3238
TYPICAL APPLICATION CIRCUIT
*Note 1
*Note 1
VCC = VBattery
27
VCC
26
OUT1
AD
1 F
0.1 F
OUT2
5
VLED+ = VBattery
6
*Note 2
VIH
2k
OUT3
7
2k
3
SDA
4
Micro
Controller
100k
IS32FL3238
SCL
25
SDB
0.1 F
OUT16
2
RISET
6.8k
ISET
1,14
OUT17
OUT18
GND
15,28
Figure 1
22
23
24
Typical Application Circuit
*Note 1
*Note 3
VCC = 5V
27
26
1 F
VCC
OUT1
AD
0.1 F
OUT2
5
33
6
91
7
33
22
33
23
91
24
33
*Note 2
VIH
2k
OUT3
*Note 1
VLED+ = 5V
2k
3
4
Micro
Controller
25
SDA
SCL
IS32FL3238
SDB
100k
0.1 F
OUT16
2
RISET
6.8k
1,14
15,28
ISET
GND
Figure 2
OUT17
OUT18
Typical Application Circuit (VCC = 5V)
Note 1: VLED+ should be same as VCC voltage.
Note 2: VIH is the high level voltage for IS32FL3238, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V,
VIH=3.3V. If VCC=5V and VIH is lower than 2.8V, recommend to add a level shift circuit.
2
Note 3: These optional resistors are for offloading the thermal dissipation (P=I R) away from the IS32FL3238.
Note 4: The output current is set up to 78mA when RISET= 2kΩ. The maximum global output current can be set by external resistor, RISET. Please
refer to the detail application information in RISET section.
Note 5: The IC and LED should be placed far away from the antenna in order to prevent the EMI.
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2
IS32FL3238
PIN CONFIGURATION
Package
Pin Configuration (Top View)
eTSSOP-28
GND
1
28
GND
ISET
2
27
VCC
SDA
3
26
AD
SCL
4
25
SDB
OUT1
5
24
OUT18
OUT2
6
23
OUT17
OUT3
7
22
OUT16
OUT4
8
21
OUT15
OUT5
9
20
OUT14
OUT6
10
19
OUT13
OUT7
11
18
OUT12
OUT8
12
17
OUT11
OUT9
13
16
OUT10
GND
14
15
GND
PIN DESCRIPTION
No.
Pin
Description
1,14,15,28
GND
Ground.
2
ISET
Input terminal used to connect an external
resistor. This regulates the global output current.
When RISET= 6.8kΩ, IOUT= 23mA.
3
SDA
I2C serial data.
4
SCL
I2C serial clock.
5~7
OUT1~OUT3
Output channel 1~3 for LEDs.
8~13
OUT4~OUT9
Output channel 4~9 for LEDs.
16~21
OUT10~OUT15
Output channel 10~15 for LEDs.
22~24
OUT16~OUT18
Output channel 16~18 for LEDs.
25
SDB
Shutdown the chip when pulled low.
26
AD
I2C address setting.
27
VCC
Power supply.
Thermal Pad
Connect to GND.
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3
IS32FL3238
ORDERING INFORMATION
Automotive Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS32FL3238-ZLA3-TR
eTSSOP-28, Lead-free
2500
Copyright © 2020 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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4
IS32FL3238
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at SCL, SDA, SDB, AD, OUT1 to OUT18
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4 layer
standard test PCB based on JESD 51-2A), θJA
Package thermal resistance, junction to thermal PAD (4
layer standard test PCB based on JEDEC standard), θJP
ESD (HBM)
ESD (CDM)
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~ +150°C
-40°C ~ +150°C
32.3°C/W
11.08°C/W
±2kV
±750V
Note 6: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Typical values are TA = 25°C, VCC = 5V.
Symbol
VCC
Parameter
Condition
Supply voltage
Min.
Typ.
2.7
Max.
Unit
5.5
V
Maximum output current
VCC= 5V, VOUT= 0.8V, RISET= 2kΩ,
GCC= 0xFF, Scaling= 0xFF (Note 7)
78
mA
Output current
VCC= 5V, VOUT= 0.4V, RISET= 6.8kΩ,
GCC= 0xFF, Scaling= 0xFF
23
mA
∆IMAT
IOUT mismatch in chip
RISET= 6.8kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA
-8
8
%
∆IOUT
IOUT mismatch between chip
RISET= 6.8kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA
-8
8
%
Headroom voltage
RISET= 6.8kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA
0.2
0.35
V
VCC= 5V, RISET= 6.8kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA, PWM=
0x00
5
10
mA
VCC= 3.6V, RISET= 6.8kΩ, GCC=
0xFF, Scaling= 0xFF, IOUT= 23mA,
PWM= 0x00
4
7
mA
VCC= 5V, RISET= 6.8kΩ, VSDB= 0V or
software shutdown
2
3
μA
VCC= 3.6V, RISET= 6.8kΩ, VSDB= 0V or
software shutdown
1
2
μA
0.1
μA
34
kHz
IOUT
VHR
ICC
ISD
Quiescent power supply
current
Shutdown current
IOZ
Output leakage current
VSDB= 0V or software shutdown,
VOUT= 5.5V
fOUT
PWM frequency of output
OSC= 8MHz, PWM Resolution= 8bit
Thermal shutdown
(Note 8)
165
°C
(Note 8)
20
°C
TSHDN
TSHDNHYST Hysteresis
29
31.5
VOD
OUTx pin open detect
threshold
RISET=6.8kΩ, IOUT≥0.1mA, measured
at OUTx
0.08
0.18
0.26
V
VSD
LED short detect threshold
RISET=6.8kΩ, IOUT≥0.1mA, measured
at (VCC-VOUTx)
0.7
1.3
1.5
V
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5
IS32FL3238
ELECTRICAL CHARACTERISTICS (CONTINUE)
Typical values are TA = 25°C, VCC = 5V.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
0.4
V
Logic Electrical Characteristics (SDA, SCL, SDB, AD)
VIL
Logic “0” input voltage
VCC= 2.7V~5.5V
VIH
Logic “1” input voltage
VCC= 2.7V~5.5V
IIL
Logic “0” input current
VINPUT= 0V (Note 8)
5
nA
IIH
Logic “1” input current
VINPUT= VCC (Note 8)
5
nA
1.4
V
DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 8)
Symbol
Parameter
Fast Mode
Min.
Typ.
Fast Mode Plus
Typ.
Max.
Units
Max.
Min.
-
400
-
1000
kHz
fSCL
Serial-clock frequency
tBUF
Bus free time between a STOP and a
START condition
1.3
-
0.5
-
μs
tHD, STA
Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA
Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO
STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT
Data hold time
-
-
-
-
μs
tSU, DAT
Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving
-
300
-
120
ns
Note 7: The recommended minimum value of RISET is 2kΩ.
Note 8: Guaranteed by design.
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6
IS32FL3238
FUNCTIONAL BLOCK DIAGRAM
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7
IS32FL3238
DETAILED DESCRIPTION
Then the master sends an SCL pulse. If the
IS32FL3238 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
I2C INTERFACE
The IS32FL3238 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS32FL3238 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0. Set
A0 to “0” for a write command and set A0 to “1” for a
read command. The value of bits A1 and A2 are
decided by the connection of the AD pin. The complete
slave address is:
Following acknowledge of IS32FL3238, the register
address byte is sent, most significant bit first.
IS32FL3238 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS32FL3238 must generate another acknowledge to
indicate that the data was received.
Table 1 Slave Address
Bit
A7:A3
A2:A1
A0
Value
01101
AD
0/1
AD connected to GND, AD = 00;
AD connected to VCC, AD = 11;
AD connected to SCL, AD = 01;
AD connected to SDA, AD = 10;
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
The SCL line is uni-directional. The SDA line is
bi-directional (open-drain) with a pull-up resistor
(typically 2kΩ). The maximum clock frequency
specified by the I2C standard is 1MHz. In this
discussion, the master is the microcontroller and the
slave is the IS32FL3238.
To write multiple bytes of data into IS32FL3238, load
the address of the data register that the first data byte
is intended for. During the IS32FL3238 acknowledge
of receiving the data byte, the internal address pointer
will increment by one. The next data byte sent to
IS32FL3238 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS32FL3238
(Figure 6).
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
READING OPERATION
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS32FL3238’s acknowledge. The master
releases the SDA line high (through a pull-up resistor).
Figure 3
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Rev. A, 01/02/2020
Most of the registers can be read.
To read the register, after I2C start condition, the bus
master must send the IS32FL3238 device address
____
with the R/W bit set to “0”, followed by the register
address which determines which register is accessed.
Then restart I2C, the bus master should send the
____
IS32FL3238 device address with the R/W bit set to
“1”. Data from the register defined by the command
byte is then sent from the IS32FL3238 to the master
(Figure 7).
Interface Timing
8
IS32FL3238
Figure 4
Figure 5
Figure 6
Bit Transfer
Writing to IS32FL3238 (Typical)
Writing to IS32FL3238 (Automatic Address Increment)
Figure 7
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Reading from IS32FL3238
9
IS32FL3238
REGISTER DEFINITIONS
Table 2 Register Function
Address
Name
Function
R/W
Table
Control Register
Power control register
R/W
3
PWM Register
Channel [18:1] PWM register byte
R/W
5
Update Register
Update the PWM and scaling data
W
-
LED Scaling Register
Control each channel’s DC current
R/W
7
6Eh
Global Current Control Register
Control global DC current/SSD
R/W
8
70h
Phase Delay and Clock Phase
Register
Phase delay and clock phase
R/W
9
71h
Open Short Detect Enable Register
Open short detect enable
R/W
10
LED Open/Short Register
Open short information
R/W
11
77h
Temperature Sensor Register
Temperature information
R/W
12
78h
Spread Spectrum Register
Spread spectrum control register
R/W
13
7Fh
Reset Register
Reset all registers
W
-
00h
01h~48h
49h
4Ah~6Dh
72h~76h
Table 3 00h Control Register
Default
0000
0000
Table 4 PWM Frequency
PWM
16M
Resolution
Bit
D7
D6:D4
D3
D2:D1
D0
Name
-
OSC
-
PMS
SSD
8-bit
Default
0
000
0
00
0
The Control Register sets software shutdown mode,
internal oscillator clock frequency and PWM resolution.
The internal oscillator clock frequency and the PWM
resolution will decide the output PWM frequency.
Recommend using lower than 500Hz option or higher
than 20kHz options to avoid the MLCC’s audible noise
as shown in Table 4.
SSD
0
1
Software Shutdown Enable
Software shutdown mode
Normal operation
PMS
00
01
10
11
PWM Resolution
N=256, 8-bit
N=1024, 10-bit
N=4096, 12-bit
N=65536, 16-bit
OSC
000
001
010
011
100
101
110
111
Oscillator Clock Frequency Selection
16MHz
8MHz
1MHz
500kHz
250kHz
125kHz
62kHz
31kHz
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Rev. A, 01/02/2020
8M
1M 500k 250k 125k 62k
31k
62k
32k
4k
0.5k 244
122
10-bit
16k
8k
1k
0.5k 244
122
NA
NA
12-bit
4k
2k
244
122
NA
NA
NA
NA
16-bit
244
122
NA
NA
NA
NA
NA
NA
2k
1k
Table 5 01h~48h PWM Register
Reg
02h (04h, 06h…)
01h (03h, 05h…)
Bit
D7:D0
D7:D0
Name
PWMX_H
PWMX_L
Default
0000 0000
0000 0000
X=A or B, Each output has 2 bytes × 2, total 4 registers
to modulate the PWM duty in 256/1024/4096/65536
steps. For example, OUT1 use 04h/03h (PWMB),
02h/01 (PWMA) to modulate the PWM, OUT2 use
08h/07h (PWMB), 06h/05 (PWMA) to modulate the
PWM, etc., If using the 8 bit PWM resolution, only the
PWM_L needs to be set.
The value of the SL (LED Scaling Register) decides
the peak current of each LED noted as IOUT.
IOUT and the value of the PWM Registers decide the
average current of each LED noted as ILED.
IOUT computed by Formula (1):
I OUT I OUT ( MAX )
GCC SLB SLA
256
512
(1)
ILED computed by Formula (2):
10
IS32FL3238
I LED
PWMB PWMA
I OUT
2N
PWMA
PWMB
(2)
15
D[ n ] 2
n
(3)
n0
15
D[ n ] 2 n
1
(4)
n0
2
Where IOUT(MAX) is the maximum output current decided
by RISET (check RISET section for more information),
GCC is the global current setting (6Eh), and SLB, SLA
are the scaling of each output (4Ah~6Dh),
N=256/1024/4096/65536(8/10/12/16
bits
PWM
resolution)
For example: RISET=6.8kΩ, GCC=0xFF, SL=0xFF,
PMS= “11” (16 bits PWM resolution), PWMA_H=0xFF,
PWMA_L=0xFF, PWMB_H=0xFF, PWMB_L=0xFF,
IOUT(MAX) = 23mA
I OUT
255 255 255
I OUT ( MAX )
23 mA (1)
256
512
PWMA
Table 6 PWM and Scaling Register Map
PWM
OUT
PWM_H
PWM_L
15
D[ n ] 2 n 65535
3
4
5
6
7
(3)
n0
PWMB
15
D[ n ] 2
n
65535
8
(3)
n0
N= 65536
I LED
9
65535 65535
23 mA 23 mA
2 65536
(2)
Where IOUT(MAX) is the maximum output current decided
by RISET (check RISET section for more information)
The IOUT of each channel is set by the SL bits of LED
Scaling Register (4Ah~6Dh). Please refer to the detail
information in Table 7.
If RISET=6.8kΩ, GCC=0xFF, SL=0xFF, PMS= “00” (8-bit
PWM resolution, only use the PWM_L, the PWM_H
will be ignored), PWMA_H=0x77, PWMA_L=0xAA,
PWMB_H=0x77, PWMB_L=0xAA, IOUT(MAX) = 23mA
I OUT
255 255 255
I OUT ( MAX )
23 mA (1)
256
256 2
PWMA
PWMB
7
D[ n ] 2
n
D[n ] 2
n
n0
7
170
(3)
170
10
11
12
13
14
15
(4)
16
n0
N=256
I LED
170 170
23 mA
256 2
(2)
17
18
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Rev. A, 01/02/2020
SL
02h
01h
4Ah
04h
03h
4Bh
06h
05h
4Ch
08h
07h
4Dh
0Ah
09h
4Eh
0Ch
0Bh
4Fh
0Eh
0Dh
50h
10h
0Fh
51h
12h
11h
52h
14h
13h
53h
16h
15h
54h
18h
17h
55h
1Ah
19h
56h
1Ch
1Bh
57h
1Eh
1Dh
58h
20h
1Fh
59h
22h
21h
5Ah
24h
23h
5Bh
26h
25h
5Ch
28h
27h
5Dh
2Ah
29h
5Eh
2Ch
2Bh
5Fh
2Eh
2Dh
60h
30h
2Fh
61h
32h
31h
62h
34h
33h
63h
36h
35h
64h
38h
37h
65h
3Ah
39h
66h
3Ch
3Bh
67h
3Eh
3Dh
68h
40h
3Fh
69h
42h
41h
6Ah
44h
43h
6Bh
46h
45h
6Ch
48h
47h
6Dh
11
IS32FL3238
49h
Update Register
When SDB = “H” and SSD = “1”, a write of “0000 0000”
to 49h will update the PWM Registers (01h~48h)
values.
Table 7 4Ah~6Dh LED Scaling Register
Bit
D7:D0
Name
SLx
Default
0000 0000
GCC SLA SLB
256
256 2
n
(5)
D[ n ] 2
(5)
n0
SLB
7
n
n0
Where IOUT(MAX) is the maximum output current decided
by RISET, GCC is the global current setting (6Eh)
4Ah~6Dh don’t need to be update by writing to 49h,
each register will be updated immediately when it is
written.
Table 8 6Eh Global Current Control Register
Bit
D7:D0
Name
GCC
Default
0000 0000
GCC and SL control the IOUT as shown in Formula (1).
GCC
7
D[ n ] 2
n
D7
Name
PDE
-
Default
0
0
D6 D5
D4
D3
D2
D1
D0
PS
PS
PS
PS
PS
PS
0
0
0
0
0
0
PDE
0
1
Phase Delay Enable
Phase delay disable
Phase delay enable
PS[n]
0
1
Clock Phase Select
All outputs work as scheme of Clock Phase 1
Outputs OUT[2+(n-1)*6], OUT[4+(n-1)*6],
OUT[6+(n-1)*6] work as scheme of Clock
Phase 2
(1)
7
D[ n ] 2
SLA
Bit
The PDE bit is for enabling channel group delay to
minimize peak load current draw from the LED power
supply rail.
X=A or B, each output has 8 bits × 2 to modulate DC
current in 256 steps, for example, OUT1 use 4Bh and
4Ah to set the DC output current, OUT2 use 4Dh and
4Ch to set the DC output current, etc..
The value of the SLB+SLA Registers decides the DC
peak current of each LED noted by IOUT.
IOUT computed by Formula (1):
I OUT I OUT ( MAX )
Table 9 70h Phase Delay and Clock Phase
Register
(5)
Phase Delay separates 18 outputs as 6 groups,
OUT1~OUT3 as group 1, OUT4~OUT7 as group
2…OUT15~OUT18 as group 6. When the is enabled,
group 2 will have a 1/(6*fOUT) time delay than group 1,
group 3 will also have a 1/(6*fOUT) time delay than
group 2, and so on.
For each group of 6 outputs there is a Clock Phase
option PS[n](n=1~6), when PSn is set to “1”, half
current of each output(current decided by SLA) will
keep the phase, phase 1, the turning on edge of the
PWM pulse is fixed from starting of PWM cycle, but
another half current of each output(current decided by
SLB) will change to phase 2, the turning off edge of the
PWM pulse is fixed from ending of PWM cycle as
below, the rising and falling edges will cancel the
power ripple.
Phase Delay feature and Clock Phase options can
work together to minimize the voltage ripple of LED
power supply(check PHASE DELAY and CLOCK
PHASE section for phase 1, phase 2 definition and
more information).
n0
If GCC=0xFF, SLA=0xFF, SLB=0xFF, IOUT=IOUT(MAX)
If GCC=0x01, SLA=0xFF, SLB=0x00,
I OUT I OUT ( MAX )
1
255 0
256 256 2
Where IOUT(MAX) is the maximum output current decided
by RISET (check RISET section for more information).
Table 10 71h Open Short Detect Enable Register
Bit
D7:D2
D1:D0
Name
-
OSDE
Default
0000 00
00
OSDE enables the open and/or short LED channel
detection with the result stored in 72h~76h, note either
open or short information is saved not both.
OSDE
00
01
10
11
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Open/Short Detect Enable
Detect disable
Detect disable
Short detect enable
Open detect enable
12
IS32FL3238
Table 11-1 72h~75h LED Open/Short Register
Table 13 78h Spread Spectrum Register
72h
D7:D0
Bit
D7:D5
D4
D3:D2
D1:D0
Name
OP/ST[8:1]
Name
DCPWM
SSP
RNG
CLT
Default
x0x0 x0x0
Default
000
0
00
00
Table 11-2 76h LED Open/Short Register
Bit
D7:D4
D3:D0
Name
-
OP/ST[18:17]
Default
0000
x0x0
Open or short status are stored in 72h to 76h.
OP[18:1]
0
1
Open Information of OUT18:OUT1
No open happens
The output opens
ST[18:1]
0
1
Short Information of OUT18:OUT1
No short happens
The output shorts
Table 12 77h Temperature Sensor Register
Bit
D7:D6
D5
D4
D3:D2
D1:D0
Name
TROF
-
T_Flag
-
TS
Default
00
0
0
00
00
TS stores the temperature/thermal roll-off point. TROF
stores percentage of output current of the thermal
roll-off function.
Read T_Flag=1 indicates die temperature exceeds the
setting point (TS). Before each reading of 77h register,
TROF and TS need to be re-written.
TROF
current
00
01
10
11
Thermal roll off percentage of output
100%
75%
55%
30%
Temperature Point, Thermal roll off start
TS
point
00
01
10
11
140°C
120°C
100°C
90°C
T_Flag
0
1
Temperature Flag
Temperature point not exceeded
Temperature point exceeded
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When DCPWM is set to “0”, the PWM outputs are
decided by 01h~48h, and the PWM range is
0/256~255/256(8-bit PWM, 0/1024~1023/1024 for 10
bit PWM, 0/4096~4095/4096 for 12 bit PWM,
0/65536~65535/65536 for 16 bit PWM), still the
1/256(8-bit PWM, 1/1024 for 10 bit PWM, 1/4096 for
12 bit PWM, 1/65536 for 16 bit PWM), can’t be
turned on. When the DCPWM is set to “1”, PWM
dimming is disabled and dimming will be done by
current adjust GCC and SLX registers.
Spread spectrum register enable the spread spectrum
function, adjust the cycle time and range.
DCPWM
xx0
xx1
x0x
x1x
0xx
1xx
Setting the output to work in DC mode
Output 1~6 PWM data set by registers
01h~18h
Output 1~6 set to turn on (PWM is
disabled)
Output 7~12 PWM data set by registers
19h~30h
Output 7~12 set to turn on (PWM is
disabled)
Output 13~18 PWM data set by
registers 31h~48h
Output 13~18 set to turn on (PWM is
disabled)
SSP
0
1
Spread Spectrum Enable
Disable
Enable
CLT
00
01
10
11
Spread Spectrum Cycle Time
1980μs
1200μs
820μs
660μs
RNG
00
01
10
11
Spread Spectrum Range
±5%
±15%
±24%
±34%
7Fh Reset Register
When power on, all registers values are reset to 0x00
(default). A write of “0000 0000” to 7Fh will also reset
all registers to their default values.
13
IS32FL3238
APPLICATION INFORMATION
RISET
The
maximum
output
current
IOUT(MAX)
for
OUT1~OUT18 can be adjusted by the external resistor,
RISET, as described in Formula (6).
I OUT ( MAX ) 2 x
V ISET R ISET k 283
R ISET k 283
(6)
x = 81.28, VOUT = 0.8V, VISET = 0.945V.
The recommended minimum value of RISET is 2kΩ.
When RISET=6.8kΩ, IOUT(MAX)=23mA
When RISET=3.3kΩ, IOUT(MAX)=47mA
When RISET=2kΩ, IOUT(MAX)=78mA
RISET should be close to the chip and the ground side
should well connect to the GND plane.
CURRENT SETTING
The maximum output current is set by the external
resistor RISET. The Global Current Control register GCC
can be used to set a lower current than set by RISET.
The 8-bit SL registers (4Ah~6Dh) control the individual
currents for each of the outputs.
Some applications may require the IOUT of each
channel to be adjusted independently. For example, if
OUT1 drives 1 LED and OUT2 drives 2 parallel LEDs,
and they should have the same average current like
18mA, we can set the IOUT(MAX) to 36mA, and
GCC=0xFF,
4Ah=0x80,
4Bh=0x80,
4Ch=0xFF,
4Dh=0xFF, the OUT1 sinks about 18mA and OUT2
sinks 36mA which can have two LEDs in parallel.
all the OUTx channels are synchronized, the DC
power supply will experience large instantaneous
current surges when the OUTx channels turn ON.
These current surges will generate an AC ripple on the
power supply which cause stress to the decoupling
capacitors. When the AC ripple is applied to a
monolithic ceramic capacitor chip (MLCC) it will
expand and contract causing the PCB to flex and
generate audible hum in the range of between 20Hz to
20kHz. To avoid this hum, there are many
countermeasures, such as selecting the capacitor type
and value which will not cause the PCB to flex and
contract.
An additional option for avoiding audible hum is to set
the
IS32FL3238’s
output
PWM
frequency
above/below the audible range. The Control Register
(00h) can be used to set the switching frequency to
122Hz~62kHz as shown in Table 4, some combine
setting of the OSC and PMS bits will get different
output PWM frequency, and higher than 20kHz is out
of the audible range.
PHASE DELAY and CLOCK PHASE
To reduce audible noise due to PWM switching, the
IS32FL3238 features Phase Delay and Clock Phase
schemes. When Phase Delay and Clock Phase are
disabled (default) all of the outputs turn on
simultaneously causing large current draw from the
ceramic capacitors and pausible audible noise.
Another example, OUT1, OUT2 and OUT3 drive an
RGB LED, OUT1 is Red LED, OUT2 is Green LED and
OUT 3 is Blue LED. If GCC and SL bits are the same,
then the RGB LED may appear a pinkish, or not so
white. The SL bits can be used to adjust the IOUTx
current so the RGB LED appears closer to a pure white
color. We call this SL bit adjustment by another name:
white balance registers.
PWM CONTROL
The PWM Registers (01h~48h) can modulate LED
brightness of 18 channels with 256/1024/4096/65536
steps. For example, if the data in PWM_H Register is
“0000 0000” and in PWMA_L Register is “0000 0100”,
then the PWM is the fourth step (total is 512 steps).
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
PWM FREQUENCY SELECT
The IS32FL3238 output channels operate with a
default 8 bits PWM resolution and the PWM frequency
of 62kHz (the oscillator frequency is 16MHz). Because
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Figure 8
Phase Delay and Clock Phase Disable
The PDE bit of register 70h will enable the Phase
Delay function so at power-on the OUTx channel will
not all turn on at the same time to minimize peak load
current, resulting in reduced voltage ripple on the LED
power supply rail. Phase Delay separates the 18
outputs as 6 groups, OUT1~OUT3 as group 1,
OUT4~OUT6 as group 2…OUT15~OUT18 as group 6,
when Phase Delay is enabled, group 2 will have a
1/(6×fOUT) time delay than group 1, group 3 will also
have a 1/(6×fOUT) time delay than group 2, and so on.
14
IS32FL3238
VCC
Clock Phase 1
OUT[1+(n-1)×3] SLA Ton
OUT[1+(n-1)×3] SLB
OUT[2+(n-1)×3] SLA Ton
OUT[2+(n-1)×3] SLB
OUT[3+(n-1)×3] SLA Ton
OUT[3+(n-1)×3] SLB
Figure 11
Figure 9
PDE= “1” Phase Delay Enable
Also in each group of outputs, there is a Clock Phase
option PS[n](n=1~6), when PSn of 71h register is set to
“0” (default), all outputs in group n keep the phase 1.
Figure 10
Toff
Clock Phase 2
Toff
Clock Phase 1
Ton
Toff
Clock Phase 2
Toff
Clock Phase 1
Ton
Toff
Clock Phase 2
Toff
Ton
1/fOUT
Rising & Falling edges canceled the power ripple
PSn= “1” Clock Phase Enable
Phase Delay feature and Clock Phase options can
work together to minimize the voltage ripple of LED
power supply.
PSn= “0” Clock Phase Disable
When PSn is set to “1”, OUT[1+(n-1)×6],
OUT[2+(n-1)×6], OUT[3+(n-1)×6], half of the current
(current decide by SLA) will keep the phase 1, the
turning on edge of the PWM pulse is fixed from starting
of PWM cycle as below, but OUT[1+(n-1)×6],
OUT[2+(n-1)×6], OUT[3+(n-1)×6] another half of the
current (current decide by SLB) will change to phase 2,
the turning off edge of the PWM pulse is fixed from
ending of PWM cycle as below, the rising and falling
edges will cancel the power ripple.
Figure 12
PDE= “1” Phase Delay Enable, PSn= “1” (n=1~6) Clock
Phase Enable
OPEN/SHORT DETECT FUNCTION
IS32FL3238 has open and short detect bit for each
LED. See Open (VOD) and Short (VSD) detection
thresholds in the Electrical Characteristics table.
By setting the OSDE bit of Open Short Detect Enable
Register (71h) from “00” to “10” (store short
information) or “11” (store open information), the LED
Open/Short Register will store the open/short
information immediately the MCU can get the
open/short information by reading the 72h~76h.
SPREAD SPECTRUM FUNCTION
A switch mode controller can be particularly
troublesome for application when the EMI is
concerned. To optimize the EMI performance, the
IS32FL3238 includes a spread spectrum function. By
setting the RNG bit of Spread Spectrum Register (78h),
Spread Spectrum range can be choose from ±5%
/±15% /±24% /±34%. The spread spectrum can
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15
IS32FL3238
spread the total electromagnetic emitting energy into a
wider range that significantly degrades the peak
energy of EMI. With the spread spectrum, the EMI test
can be easy to be passed with smaller size and lower
cost filter circuit.
Hardware Shutdown
OPERATING MODE
The chip releases hardware shutdown when the SDB
pin is pulled high. The rising edge of SDB pin will reset
the I2C module, but the register information is retained.
During hardware shutdown the registers are
accessible.
IS32FL3238 can operate in PWM Mode. The
brightness of each LED can be modulated with
256/1024/4096/65536 steps by PWM registers. For
example, if N=256, the data in PWMA Register are
“0000 0100”, PWMB Register are “0000 0000”, then
the PWM is the fourth step (total is 256+256=512
steps).
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
SHUTDOWN MODE
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
Software Shutdown
By setting the SSD bit of the Control Register (00h) to
“0”, the IS32FL3238 will operate in software shutdown
mode. When the IS32FL3238 is in software shutdown,
all current sources are switched off, so the LEDs are
OFF but all registers remain accessible. Typical current
consumption is 1μA (VCC=3.6V).
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The IS32FL3238 enters hardware shutdown when the
SDB pin is pulled low. All analog circuits are disabled
during
hardware
shutdown,
typical
current
consumption is 1μA (VCC=3.6V).
If the VCC supply drops below 1.75V but remains
above 0.1V while SDB is pulled low, please re-initialize
all Function Registers before SDB pulled high.
LAYOUT
As described in external resistor (RISET), the chip
consumes lots of power. Please consider below
factors when layout the PCB.
1. The VCC capacitors need to close to the chip and
the ground side should well connect to the GND of the
chip.
2. RISET should be close to the chip and the ground
side should well connect to the GND of the chip.
3. The thermal pad should connect to ground pins and
the PCB should have the thermal pad too, usually this
pad should have 16 or 25 via thru the PCB to other
side’s ground area to help radiate the heat. About the
thermal pad size, please refer to the land pattern of
each package.
16
IS32FL3238
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 13
Classification Profile
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17
IS32FL3238
PACKAGE INFORMATION
eTSSOP-28
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18
IS32FL3238
RECOMMENDED LAND PATTERN
eTSSOP-28
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use.
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19
IS32FL3238
REVISION HISTORY
Revision
Detail Information
Date
0A
Initial release.
2018.01.11
0B
1. Update typical application figure 1, RJA value and correct mistakes
2. Update Equation (6)
3. Add ESD (HBM) and RJP value
2019.03.08
0C
1. Add 62kHz PWM frequency in Feature
2. Update applications in page 1
3. Update EC condition to VCC=5V
2019.06.12
A
1. Add figure 1
2. Update note 4
3. Update eTSSOP-28 land pattern
4. Update to final version
2020.01.02
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