MCF5480CZP166

Advance Information MCF5485EC/D Rev. 1.2, 3/2004 MCF548x Integrated Microprocessor Hardware Specifications The MCF548x is a highly-integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MCF548x family: the MCF5480, MCF5481, MCF5482, MCF5483, MCF5484, and MCF5485. This document contains the following topics: Topic Section 1.1, “MCF548x Family Overview” Section 1.2, “MCF548x Block Diagram” Section 1.3, “MCF548x Family Products” Section 1.4, “MCF548x Family Features” Section 1.5, “Signal Description” Section 1.6, “Chip Configuration” Section 1.7, “Design Recommendations” Section 1.8, “MCF5485/5484 Pinout” Section 1.9, “MCF5483/5482 Pinout” Section 1.10, “MCF5481/5480 Pinout” Section 1.11, “Mechanicals” Section 1.12, “Ordering Information” Section 1.13, “Device/Family Documentation List” Section 1.14, “Document Revision History” Appendix A, “Preliminary Electrical Characteristics” Page 1 3 4 5 14 43 45 54 58 62 67 68 68 68 69 To locate any published errata or updates for this document, refer to the web site at http://motorola.com/semiconductors. 1.1 MCF548x Family Overview The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4 central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit (MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers for caches and local data memories. The MCF548x family is capable of performing at an operating frequency of up to 200 MHz or 308 MIPS (Dhrystone 2.1). PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE MCF548x Family Overview To maximize throughput, the MCF548x family incorporates three independent external bus interfaces: 1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals and has up to six chip selects. 2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate (DDR) bus that can run at up to one half of the CPU core frequency. The glueless DDR SDRAM controller handles all address multiplexing, input and output strobe timing, and memory bus clock generation. 3. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency of 33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for bus mastership, and access to internal MCF548x memory resources. The MCF548x family provides substantial communications functionality by integrating the following connectivity peripherals: • Up to two 10/100 Mbps fast Ethernet controllers (FECs) • An optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver • Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs) • A DMA serial peripheral interface (DSPI) • An inter-integrated circuit (I2C™) bus controller • Two controller area network 2.0B (FlexCAN) interfaces with 16 message buffers each Additionally, the MCF548x provides hardware support for a range of Internet security standards with an optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and random number generation. Hardware acceleration of these functions is critical to avoiding the throughput bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and other security standards. The incorporation of cryptography acceleration makes the MCF548x family a compelling solution for a wide range of office automation, industrial control, and SOHO networking devices that must have the ability to securely transmit critical equipment control information across typically insecure Ethernet data networks. Additional features of MCF548x products include a watchdog timer, two 32-bit slice timers for RTOS scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL) to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple general-purpose I/O ports. To manage current consumption, MCF548x products provide chip-wide internal clock gating control on a per module basis under software control. With on-chip support for multiple common communications interfaces, MCF548x products require only the addition of memories and certain physical layer transceivers to be cost-effective system solutions for many applications, such as industrial routers, high-end POS terminals, building automation systems, and process control equipment. MCF548x products require four supply voltages: 1.5V for the high-performance, low power, internal core logic, 2.5V for the DDR SDRAM bus interface, 1.25V for the DDR SDRAM VREF, and 3.3V for all other I/O functionality, including the PCI and FlexBus interfaces. 2 MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA MCF548x Block Diagram 1.2 MCF548x Block Diagram Figure 1 shows a top-level block diagram of the MCF548x products. ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-cache PLL DDR SDRAM Interface FlexBus Interface XL Bus Arbiter Memory Controller FlexBus Controller Cryptography Accelerator*** XL Bus Read/Write Write DMA DMA Bus Read 32K System SRAM GP Timers x 4 PCI 2.2 Controller Multi-Channel DMA Master Bus Interface and FIFOs FlexCAN x2 PCI Interface & FIFOs CommBus DSPI I2 C PSC x 4 FEC1 FEC2** USB 2.0 DEVICE* Perpheral Communications I/O Interface & Ports Communications I/O Subsystem Slice Timers x 2 PCI I/O Interface and Ports Watchdog Timer R/W Master/Slave Interface Crypto Interrupt Controller Slave Perpheral I/O Interface & Ports System Integration Unit XL Bus USB 2.0 PHY* *Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices. **Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices. ***Available in MCF5485, MCF5483, and MCF5481 devices. Figure 1. MCF548x Block Diagram MOTOROLA MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3 MCF548x Family Products 1.3 MCF548x Family Products Table 1 summarizes the products available within the MCF548x product family. All products are available in pin-compatible, 388 pin PBGA packaging allowing for ease of mirgration between products within the family. A printed circuit board designed using the MCF5485/4 footprint is compatible with any of the MCF548x family devices. Table 1. MCF548x Family Products 4 Product Performance Features Temperature Range MCF5485 308 MIPS 200 MHz Two 10/100 Ethernet Controllers Two CAN Controllers USB 2.0 Device with Integrated PHY v2.2 PCI Controller DDR Memory Controller Encryption Accelerator -40 to 85 ° C MCF5484 308 MIPS 200 MHz Two 10/100 Ethernet Controllers Two CAN Controllers USB 2.0 Device with Integrated PHY v2.2 PCI Controller DDR Memory Controller -40 to 85 ° C MCF5483 255 MIPS 166 MHz One 10/100 Ethernet Controller Two CAN Controllers USB 2.0 Device with Integrated PHY v2.2 PCI Controller DDR Memory Controller Encryption Accelerator -40 to 85 ° C MCF5482 255 MIPS 166 MHz One 10/100 Ethernet Controller Two CAN Controllers USB 2.0 Device with Integrated PHY v2.2 PCI Controller DDR Memory Controller -40 to 85 ° C MCF5481 255 MIPS 166 MHz Two 10/100 Ethernet Controllers Two CAN Controllers v2.2 PCI Controller DDR Memory Controller Encryption Accelerator -40 to 85 ° C MCF5480 255 MIPS 166 MHz Two 10/100 Ethernet Controllers Two CAN Controllers v2.2 PCI Controller DDR Memory Controller -40 to 85 ° C MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA MCF548x Family Features 1.4 • MCF548x Family Features ColdFire V4e core — Limited superscalar V4 ColdFire processor core — Up to 200 MHz peak internal core frequency (308 Dhrystone 2.1 MIPS) — Harvard architecture – 32-Kbyte instruction cache – 32-Kbyte data cache — Memory management unit (MMU) – Separate, 32-entry, fully-associative instruction and data translation lookahead buffers — Floating point unit (FPU) – Double-precision support that conforms to IEEE-754 standard – Eight floating point registers • Internal master bus (XLB) arbiter — High performance split address and data transactions — Support for various parking modes • 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller — 66–133 MHz operation — Supports both DDR and SDR DRAM — Built-in initialization and refresh — Up to four chip selects enabling up to 1 GB of external memory • Version 2.2 peripheral component interconnect (PCI) bus — 32-bit target and initiator operation — Support for up to five external PCI masters — 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4 • Flexible multifunction external bus (FlexBus) — Supports operation with the following: – Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over PCI bus–PCI not usable) – Multiplexed 32-bit address and 32-bit data (PCI usable) – Multiplexed 32-bit address and 16-bit data – Multiplexed 32-bit address and 8-bit data — Provides a glueless interface to boot Flash/ROM, SRAM, and peripheral devices — Up to six chip selects — 33–66 MHz operation • Communications I/O subsystem — Intelligent 16-channel DMA controller — Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces MOTOROLA MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 5 MCF548x Family Features — Up to two 10/100 Mbps fast Ethernet controllers (FECs), each with separate 2-Kbyte receive and transmit FIFOs — Universal serial bus (USB) version 2.0 device controller – Support for one control and six programmable endpoints — interrupt, bulk, or isochronous – 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM – Integrated physical layer interface — Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces — I2C peripheral interface — Two FlexCAN controller area network 2.0B controllers each with 16 message buffers — DMA serial peripheral interface (DSPI) • Optional security encryption controller (SEC) module — Execution units for the following: – – – – – DES/3DES block cipher AES block cipher RC4 stream cipher MD5/SHA-1/SHA-256/HMAC hashing Random number generator compliant with FIPS 140-1 standards for randomness and non-determinism — Dual-channel architecture permits single-pass encryption and authentication • 32-Kbyte system SRAM — Arbitration mechanism shares bandwidth between internal bus masters (CPU, cryptography accelerator, PCI, and DMA) • System integration unit (SIU) — Interrupt controller — Watchdog timer — Two 32-bit slice timers for periodic alarm and interrupt generation — Up to four 32-bit general-purpose timers with capture, compare, and PWM capability — General-purpose I/O ports multiplexed with peripheral pins • Debug and test features — Core debug support via ColdFire background debug mode (BDM) port — Chip debug support via JTAG/ IEEE 1149.1 test access port • PLL and clock generator — 30–66.67 MHz input frequency range • Operating Voltages — 1.5V internal logic — 2.5V DDR SDRAM bus I/O (1.25V VREF) — 3.3V PCI, FlexBus, and all other I/O • Estimated power consumption — DQ) Relative to DQS (DDR Write Mode) (tQH) 1.0 DD9 Input Data Skew Relative to DQS (Input Setup) (tIS) DD10 Input Data Hold Relative to DQS (tIH) DD11 5 6 — ns 7 1 ns 8 0.25*SDCLK +0.5ns — ns 9 DQS falling edge to SDCLK rising (output setup time) (tDSS) 0.5 — ns DD12 DQS falling edge from SDCLK rising (output hold time) (tDSH) 0.5 — ns DD13 DQS input read preamble width (tRPRE) 0.9 1.1 SDCLK DD14 DQS input read postamble width (tRPST) 0.4 0.6 SDCLK DD15 DQS output write preamble width (tWPRE) 0.25 — SDCLK DD16 DQS output write postamble width (tWPST) 0.4 0.6 SDCLK 1 2 3 4 5 82 The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter for more information on setting the SDRAM clock rate. SDCLK is one memory clock in (ns). Pulse width high plus pulse width low cannot exceed max clock period. Pulse width high plus pulse width low cannot exceed max clock period. This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Document Revision History 6 The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats will be valid for each subsequent SDDQS edge. 7 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 8 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 9 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS CMD DD4 SDADDR, SDBA[1:0] DD6 ROW COL DD7 SDDM DD8 SDDQS DD7 SDDATA WD1 WD2 WD3 WD4 DD8 Figure 33. DDR Write Timing MOTOROLA MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 83 Document Revision History DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 CL=2 DD5 SDCSn,SDWE, RAS, CAS CMD CL=2.5 DD4 SDADDR, SDBA[1:0] ROW COL DQS Read Preamble SDDQS DD9 DQS Read Postamble DD10 SDDATA WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble SDDQS WD1 WD2 WD3 WD4 SDDATA Figure 34. DDR Read Timing A.10 PCI Bus The PCI bus on the MCF548X is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Table 32. PCI Timing Specifications Num Characteristic Frequency of Operation 84 Min Max Unit Notes 30 66 Mhz 1 15.15 33.33 ns 2 P1 Clock Period (tCK) P2 Address, Data, and Command (33< PCI