HI3-0201HS-5

DATASHEET HI-201HS FN3123 Rev 4.00 September 2004 High Speed, Quad SPST, CMOS Analog Switch The HI-201HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI-201 switch. Features Fabricated using silicon-gate technology and the Intersil Dielectric Isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches. Featuring maximum switching times of 50ns, low ON resistance of 50 maximum, and a wide analog signal range, the HI-201HS is designed for any application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-201HS can be found in Application Note AN543.) • Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . 30 • Fast Switching Times - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns • Pin Compatible with Standard HI-201 • Wide Analog Voltage Range (15V Supplies) . . . . . . . 15V • Low Charge Injection (15V Supplies) . . . . . . . . . . 10pC • TTL Compatible • Symmetrical Switching Analog Current Range . . . . . 80mA Applications Ordering Information PART NUMBER TEMP. RANGE (oC) • High Speed Multiplexing PACKAGE PKG. NO. HI1-0201HS-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0201HS-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0201HS-5 0 to 75 16 Ld CERDIP F16.3 HI3-0201HS-5 0 to 75 16 Ld PDIP E16.3 HI9P0201HS-5 0 to 75 16 Ld SOIC M16.3 HI9P0201HS-9 -40 to 85 16 Ld SOIC M16.3 FN3123 Rev 4.00 September 2004 • High Frequency Analog Switching • Sample and Hold Circuits • Digital Filters • Operational Amplifier Gain Switching Networks • Integrator Reset Circuits Pinout (Switches Shown For Logic “1” Input) HI-201HS (CERDIP, PDIP, SOIC) TOP VIEW A1 1 16 A2 OUT1 2 15 OUT2 IN1 3 14 IN2 V- 4 13 V+ GND 5 12 NC IN4 6 11 IN3 OUT4 7 10 OUT3 A4 8 9 A3 Page 1 of 12 HI-201HS Functional Diagram TRUTH TABLE V+ SOURCE LEVEL SHIFTER AND DRIVER TTL LOGIC INPUT SWITCH CELL GATE INPUT GATE LOGIC SWITCH 0 1 ON OFF DRAIN OUTPUT V- Schematic Diagrams TTL/CMOS REFERENCE CIRCUIT V+ SWITCH CELL MP42 MP43 P41 MP44 MP45 V+ Q MN31 QN41 QN43 QN42 C48 R42 QN44 D41 5V ANALOG IN QN45 QP44 MN32 MP32 VR1 ANALOG OUT MP33 MN33 R41 C49 D42 5.6V MP31 QP41 Q QP42 V- MN42 MN44 MN45 V- FN3123 Rev 4.00 September 2004 Page 2 of 12 HI-201HS Schematic Diagrams (Continued) DIGITAL INPUT BUFFER AND LEVEL SHIFTER MN46 MP51 MP52 QN6 IX4 IX3 IQ MP4 QN8 QN9 QN7 MP3 MP7 VR1 IX2 IX1 MP8 MP5 MP6 MP9 MP10 MP11 MP12 QN1 IQ C1 VA MN11 R1 QN4 QP1 QN5 QN2 QP4 QP5 VCC R3 R2 C2 Q MP13 MP14 QP2 IX3 MN5 CFF QP7 IX2 Q VEE VR1 IX1 MN12 QP9 QP6 MN3 MN4 MN9 MN6 MN10 MN13 MN7 MN14 MN8 QP8 MN51 MN52 REPEAT FOR EACH LEVEL SHIFTER FN3123 Rev 4.00 September 2004 Page 3 of 12 HI-201HS Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage (One Switch) . . . . . . . (V+) +2.0V to (V-) -2.0V Peak Current, S or D (Pulse 1ms, 10% Duty Cycle Max) . . . . 50mA Continuous Current Any Terminal (Except S or D) . . . . . . . . . 25mA Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 20 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Ranges HI-201HS-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-201HS-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC HI-201HS-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-201HS-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = +0.8V, GND = 0V, Unless Otherwise Specified TEST CONDITIONS PARAMETER -2 -4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Switch ON Time, tON (Note 3) 25 - 30 50 - 30 50 ns Switch OFF Time, tOFF1 (Note 3) 25 - 40 50 - 40 50 ns Switch OFF Time, tOFF2 (Note 3) 25 - 150 - - 150 - ns Output Settling Time To 0.1% 25 - 180 - - 180 - ns Charge Injection, Q (Note 6) 25 - 10 - - 10 - pC OFF Isolation (Note 4) 25 - 72 - - 72 - dB Crosstalk (Note 5) 25 - 86 - - 86 - dB 25 - 10 - - 10 - pF CD(OFF) 25 - 10 - - 10 - pF CD(ON) 25 - 30 - - 30 - pF Digital Input Capacitance, CA 25 - 18 - - 18 - pF Drain-To-Source Capacitance, CDS(OFF) 25 - 0.5 - - 0.5 - pF Input Low Threshold, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH 25 2.0 - - 2.0 - - V Full 2.4 - - 2.4 - - V 25 - 200 - - 200 - A Full - - 500 - - 500 A 25 - 20 - - 20 - A Full - - 40 - - 40 A Full -15 - +15 -15 - +15 V 25 - 30 50 - 30 50  Full - - 75 - - 75  Input Switch Capacitance, CS(OFF) Output Switch Capacitance DIGITAL INPUT CHARACTERISTICS Input Leakage Current (Low), IAL Input Leakage Current (High), IAH VAH = 4.0V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VS ON Resistance, rON FN3123 Rev 4.00 September 2004 (Note 2) Page 4 of 12 HI-201HS Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = +0.8V, GND = 0V, Unless Otherwise Specified (Continued) TEST CONDITIONS -2 -4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS rON Match 25 - 3 - - 3 - % OFF Input Leakage Current, IS(OFF) 25 - 0.3 10 - 0.3 10 nA Full - - 100 - - 50 nA 25 - 0.3 10 - 0.3 10 nA Full - - 100 - - 50 nA 25 - 0.1 10 - 0.1 10 nA Full - - 100 - - 50 nA 25 - 120 - - 120 - mW Full - - 240 - - 240 mW 25 - 4.5 - - 4.5 - mA Full - - 10.0 - - 10.0 mA 25 - 3.5 - - 3.5 - mA Full - - 6 - - 6 mA PARAMETER OFF Output Leakage Current, ID(OFF) ON Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS (Note 7) Power Dissipation, PD Current, I+ (Pin 13) Current, I- (Pin 4) NOTES: 2. VOUT = 10V, IOUT = 1mA. 3. RL = 1k , CL = 35pF, VIN = +10V, VA = +3V. (See Figure 1). 4. VA = 3V, RL = 1k , CL = 10pF, VIN = 3VRMS , f = 100kHz. 5. VA = 3V, RL = 1k , VIN = 3VRMS , f = 100kHz. 6. CL = 1nF, VIN = 0V, Q = CL x VO . 7. VA = 3V or VA = 0 for all switches. Test Circuits and Waveforms = 3.0V V DIGITAL AH INPUT 50% 50% VAL = 0V tOFF1 tON 90% SWITCH OUTPUT 0V 90% tOFF2 10% TOP: Logic Input (2V/Div.) BOTTOM: Output (5V/Div.) HORIZONTAL: 100ns/Div. FIGURE 1A. MEASUREMENT POINTS FN3123 Rev 4.00 September 2004 FIGURE 1B. WAVEFORMS Page 5 of 12 HI-201HS Test Circuits and Waveforms (Continued) V+ = +15V 13 SWITCH INPUT 3 VIN = +10V VA SWITCH OUTPUT VO 2 RL 1k 1 LOGIC INPUT 5 CL 35pF 4 VO = VIN V- = -15V GND RL RL + rON CL INCLUDES CFIXTURE + CPROBE FIGURE 1C. TEST CIRCUIT LOGIC INPUT (V) FIGURE 1. SWITCH tON AND tOFF 3 2 +10 1 +5 0 0 tO tO FIGURE 2A. LOGIC INPUT WAVEFORM +5 FIGURE 2B. VIN = +10V +5 0 0 +5 tO tO FIGURE 2C. VIN = +5V FN3123 Rev 4.00 September 2004 FIGURE 2D. VIN = 0V Page 6 of 12 HI-201HS Test Circuits and Waveforms (Continued) 0 0 -5 -5 -10 tO tO FIGURE 2E. VIN = -5V FIGURE 2F. VIN = -10V FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES Application Information Logic Compatibility The HI-201HS is TTL compatible. Its logic inputs (pins 1, 8, 9, and 16) are designed to react to digital inputs which exceed a fixed, internally generated TTL switching threshold. The HI-201HS can also be driven with CMOS logic (0V-15V), although the switch performance with CMOS logic will be inferior to that with TTL logic (0V-5V). The logic input design of the HI-201HS is largely responsible for its fast switching speed. It is a design which features a unique input stage consisting of complementary vertical PNP and NPN bipolar transistors. This design differs from that of the standard HI-201 product where the logic inputs are MOS transistors. Although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. Therefore, the HI-201HS will exhibit larger digital input leakage currents in comparison to the standard HI-201 product. Charge Injection Charge injection is the charge transferred, through the internal gate-to-channel capacitances, from the digital logic input to the analog output. To optimize charge injection performance for the HI-201HS, it is advisable to provide a TTL logic input with fast rise and fall times. If the power supplies are reduced from 15V, charge injection will become increasingly dependent upon the digital input frequency. Increased logic input frequency will result in larger output error due to charge injection. FN3123 Rev 4.00 September 2004 Power Supply Considerations The electrical characteristics specified in this data sheet are guaranteed for power supplies VS = 15V. Power supply voltages less than 15V will result in reduced switch performance. The following information is intended as a design aid only. POWER SUPPLY VOLTAGES 12  VS 15V SWITCH PERFORMANCE Minimal Variation VS < 12V Parametric variation becomes increasingly large (increased ON resistance, longer switching times). VS < 10V Not Recommended. VS > 16V Not Recommended. Single Supply The switch operation of the HI-201HS is dependent upon an internally generated switching threshold voltage optimized for 15V power supplies. The HI-201HS does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI-300 series of switches is recommended. The HI-300 series will remain operational to a minimum +5V single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels (15V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For further information see Application Notes AN520, AN521, AN531, AN532, AN543 and AN557. Page 7 of 12 HI-201HS Typical Performance Curves 80 80 V+ = +15V, V- = -15V TA = 25oC 70 60 ON RESISTANCE () ON RESISTANCE () 70 50 125oC 40 25oC 30 -55oC 20 10 60 50 40 30 20 V+ = +12V, V- = -12V V+ = +15V, V- = -15V 10 0 -15 -10 -5 0 5 10 0 -15 15 ANALOG INPUT (V) -10 -5 0 5 10 15 ANALOG INPUT (V) 100.0 100.0 LEAKAGE CURRENT (nA) FIGURE 4. ON RESISTANCE vs ANALOG SIGNAL LEVEL LEAKAGE CURRENT (nA) FIGURE 3. ON RESISTANCE vs ANALOG SIGNAL LEVEL 10.0 1.0 0.10 0.01 25 75 10.0 1.0 0.10 0.01 25 125 TEMPERATURE (oC) 75 125 TEMPERATURE (oC) FIGURE 6. ID(ON) vs TEMPERATURE † o Theoretically, leakage current will continue to decrease below 25 C. But due to environmental conditions, leakage measurements below this temperature FIGURE 5. IS(OFF) OR ID(OFF) vs TEMPERATURE † V+ = +8V, V- = -8V V+ = +10V, V- = -10V † are not representative of actual switch performance. 7 V+ = +15V, V- = -15V LEAKAGE CURRENT (pA) SUPPLY CURRENT (mA) 6 5 I+ 4 I3 2 1 0 -55 -35 -15 5 25 45 65 85 105 TEMPERATURE (oC) FIGURE 7. SUPPLY CURRENT vs TEMPERATURE FN3123 Rev 4.00 September 2004 125 100 80 V+ = +15V, V- = -15V 60 IS(OFF)  VD = 0V 40 ID(OFF)  VS = 0V 20 IDON 0 -20 -40 -60 IS(OFF) /ID(OFF) -80 -100 -120 -140 -160 -180 -200 -14 -12 -10 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 12 14 FIGURE 8. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE Page 8 of 12 HI-201HS 60 40 VAL = 0V, VAH2 = 3V, VAH1 = 5V 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 -240 -260 -280 35 25 45 55 65 75 85 (Continued) IAH1 LEAKAGE CURRENT (nA) LEAKAGE CURRENT (A) Typical Performance Curves IAH2 IAL 95 105 115 125 10 9 V+ = +15V, V- = -15V, TA = 25oC 8 I S(OFF)  VD = 0V 7 6 ID(OFF)  VS = 0V 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -16.0 -15.5 -15.0 -14.5 -14.0 14.0 TEMPERATURE (oC) 14.5 15.0 15.5 16.0 ANALOG INPUT (V) FIGURE 9. DIGITAL INPUT LEAKAGE CURRENT vs TEMPERATURE † FIGURE 10. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE † Theoretically, leakage current will continue to decrease below 25oC. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. 180 350 tOFF2 160 RL = 1k, CL = 35pF, TA = 25oC 300 120 SWITCHING TIME (ns) SWITCHING TIME (ns) 140 V+ = +15V V- = -15V RL = 1k CL = 35pF 100 80 60 tOFF1 40 250 tOFF2 200 150 100 20 tON 0 -55 -35 -15 5 25 45 65 85 105 0 125 5 6 7 TEMPERATURE (oC) 350 tOFF2 150 100 tOFF1 50 6 7 8 9 10 11 12 13 14 15 POSITIVE SUPPLY (V) FIGURE 13. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FN3123 Rev 4.00 September 2004 11 12 13 14 15 250 200 tOFF2 150 100 tOFF1 tON 50 tON 5 10 V+ = +15V, RL = 1k CL = 35pF, TA = 25oC 300 SWITCHING TIME (ns) SWITCHING TIME (ns) 350 250 200 9 FIGURE 12. SWITCHING TIME vs SUPPLY VOLTAGE V- = -15V, RL = 1k CL = 35pF, TA = 25oC 300 8 SUPPLY VOLTAGE (V) FIGURE 11. SWITCHING TIME vs TEMPERATURE 0 tOFF1 tON 50 0 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 NEGATIVE SUPPLY (V) FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE Page 9 of 12 HI-201HS Typical Performance Curves (Continued) 3.0 350 V + = +15V, V- = -15V, RL = 1k SWITCHING TIME (ns) INPUT LOGIC THRESHOLD (V) CL = 35pF, VAL = 0V, TA = 25oC 300 250 200 tOFF2 150 100 tOFF1 50 0 2.5 2.0 1.8 1.5 1.0 0.5 tON 0 0 1 2 3 DIGITAL INPUT VOLTAGE (V) 4 5 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) FIGURE 15. SWITCHING TIME vs INPUT LOGIC VOLTAGE FIGURE 16. INPUT SWITCHING THRESHOLD vs SUPPLY  VOLTAGE 40 VO OUT IN CHARGE INJECTION (pC) 40 30 20 CL VA 10 0 Q Q = CL x VO -10 -20 30 25 20 15 CD(OFF) OR CS(OFF) 10 -30 V+ = +15V, V- = -15V CL = 1nF -40 -50 -10 -5 0 ANALOG INPUT (V) 5 5 140 120 10 20 CROSSTALK (dB) RL = 100 VIN 40 VO RL OFF ISOLATION = 20 Log 0 10K 100K RL = 1k V+ = +15V, V- = -15V VIN = 3VRMS , VA = 3V 100 IN 80 60 VIN 40 OUT VO1 RL = 1k VO2 20 VO CROSSTALK = 20 Log 1M FIGURE 19. OFF ISOLATION vs FREQUENCY 15 10 RL = 1k VIN FREQUENCY (Hz) FN3123 Rev 4.00 September 2004 0 5 ANALOG INPUT (V) 120 80 OUT -5 140 100 IN -10 FIGURE 18. CAPACITANCE vs ANALOG VOLTAGE V+ = +15V, V- = -15V VIN = 3VRMS , VA = 3V 60 CDS(OFF) 0 -15 FIGURE 17. CHARGE INJECTION vs ANALOG VOLTAGE OFF ISOLATION (dB) CD(ON) 35 CAPACITANCE (pF) 50 10M 0 10K VO2 VO1 100K 1M FREQUENCY (Hz) 10M FIGURE 20. CROSSTALK vs FREQUENCY Page 10 of 12 HI-201HS Die Characteristics DIE DIMENSIONS 2440m x 2860m x 485m METALLIZATION Type: CuAl Thickness: 16kÅ 2kÅ PASSIVATION Type: Nitride Over Silox Nitride Thickness: 3.5kÅ 1kÅ Silox Thickness: 12kÅ 2kÅ WORST CASE CURRENT DENSITY 9.5 x 104 A/cm2 © Copyright Intersil Americas LLC 2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3123 Rev 4.00 September 2004 Page 11 of 12 HI-201HS Metallization Mask Layout HI-201HS A1 A2 OUT2 OUT1 IN2 IN1 V+ V- GND IN4 IN3 OUT4 OUT3 A4 FN3123 Rev 4.00 September 2004 A3 Page 12 of 12