IS31FL3235A-QFLS2-TR

IS31FL3235A 28 CHANNELS LED DRIVER August 2020 GENERAL DESCRIPTION FEATURES IS31FL3235A is comprised of 28 constant current channels each with independent PWM control, designed for driving LEDs, PWM frequency can be 3kHz or 22kHz. The output current of each channel can be set at up to 38mA (Max.) by an external resistor and independently scaled by a factor of 1, 1/2, 1/3 and 1/4. The average LED current of each channel can be changed in 256 steps by changing the PWM duty cycle through an I2C interface.   The chip can be turned off by pulling the SDB pin low or by using the software shutdown feature to reduce power consumption. IS31FL3235A is available in QFN-36 (4mm × 4mm) package. It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C.         2.7V to 5.5V supply I2C interface, automatic address increment function Internal reset register Modulate LED brightness with 256 steps PWM Each channel can be controlled independently Each channel can be scaled independently by 1, 1/2, 1/3 and 1/4 PWM frequency selectable - 3kHz (Default) - 22kHz -40°C to +85°C temperature range ESD HBM 8kV QFN-36 (4mm × 4mm) package APPLICATIONS   Mobile phones and other hand-held devices for LED display LED in home appliances TYPICAL APPLICATION CIRCUIT Figure 1 Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 Typical Application Circuit 1 IS31FL3235A *Note 1 5V *Note 3 31 30 1 F VCC OUT1 AD 0.1 F OUT2 36 33 1 91 2 33 26 33 27 91 28 33 *Note 2 VIH 4.7k OUT3 *Note 1 5V 4.7k 34 35 Micro Controller 29 SDA SCL IS31FL3235A SDB 100k 33 REXT 3.3k 14 32 OUT26 R_EXT GND Figure 2 OUT27 OUT28 Typical Application Circuit (VCC=5V) Note 1: VLED+ should be same as VCC voltage. Note 2: VIH is the high level voltage for IS31FL3235A, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V, VIH=3.3V. If VCC=5V and VIH is lower than 2.8V, recommend to add a level shift circuit. Note 3: These resistors are optional to help reduce the power of IS31FL3235A only (values are for VLED+=5V). Note 4: The maximum global output current is set up to 23mA when REXT = 3.3kΩ. The maximum global output current can be set by external resistor, REXT. Please refer to the detail information in Page 11. Note 5: The IC should be placed far away from the mobile antenna in order to prevent the EMI. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 2 IS31FL3235A PIN CONFIGURATION Package Pin Configuration (Top View) QFN-36 PIN DESCRIPTION No. Pin Description 1 ~ 13 OUT2 ~ OUT14 Output channel 2~14 for LEDs. 14, 32 GND Ground. 15 ~ 28 OUT15 ~ OUT28 Output channel 15~28 for LEDs. 29 SDB Shutdown the chip when pulled low. 30 AD I2C address setting. 31 VCC Power supply. 33 R_EXT Input terminal used to connect an external resistor. This regulates the global output current. 34 SDA I2C serial data. 35 SCL I2C serial clock. 36 OUT1 Output channel 1 for LEDs. Thermal Pad Connect to GND. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 3 IS31FL3235A ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3235A-QFLS2-TR QFN-36, Lead-free 2500 Copyright  ©  2020  Lumissil  Microsystems.  All  rights  reserved.  Lumissil Microsystems reserves  the  right  to  make  changes  to  this  specification  and  its  products  at  any  time  without  notice.  Lumissil  Microsystems  assumes  no  liability  arising  out  of  the  application  or  use  of  any  information,  products  or  services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and  before placing orders for products.  Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in  such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:  a.) the risk of injury or damage has been minimized;  b.) the user assume all such risks; and  c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 4 IS31FL3235A ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at SCL, SDA, SDB, OUT1 to OUT28 Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA=TJ Package thermal resistance, junction to ambient (4 layer standard test PCB based on JESD 51-2A), θJA ESD (HBM) ESD (CDM) -0.3V ~ +6.0V -0.3V ~ VCC+0.3V +150°C -65°C ~ +150°C -40°C ~ +85°C 53°C/W ±8kV ±1kV Note 6: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Typical values are TA = 25°C, VCC = 3.6V. Symbol Parameter Condition Min. Typ. 2.7 Max. Unit 5.5 V VCC Supply voltage IMAX Maximum global output current VCC= 4.2V, VOUT= 0.8V REXT= 2kΩ, SL= “00” (Note 7) 38 mA IOUT Output current VOUT= 0.6V REXT= 3.3kΩ, SL= “00” 23 mA ICC Quiescent power supply current REXT= 3.3kΩ 9 mA ISD Shutdown current fOUT PWM frequency of output IOZ Output leakage current VSDB= 0V or software shutdown, VOUT= 5.5V TSD Thermal shutdown (Note 8) 160 °C TSD_HYS Thermal shutdown hysteresis (Note 8) 20 °C VEXT Output voltage of R_EXT pin 1.3 V VSDB= 0V or software shutdown TA= 25°C, VCC= 3.6V 3 5 μA 0x4B= 0x00 2.9 kHz 0x4B= 0x01 21.6 kHz 0.2 μA Logic Electrical Characteristics (SDA, SCL, SDB) VIL Logic “0” input voltage VCC= 2.7V~5.5V VIH Logic “1” input voltage VCC= 2.7V~5.5V IIL Logic “0” input current VINPUT= 0V (Note 8) 5 nA IIH Logic “1” input current VINPUT= VCC (Note 8) 5 nA Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 0.4 1.4 V V 5 IS31FL3235A DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 8) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-Clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs tR tF Rise time of both SDA and SCL signals, receiving Fall time of both SDA and SCL signals, receiving 0.9 μs (Note 9) 20+0.1Cb 300 ns (Note 9) 20+0.1Cb 300 ns Note 7: The recommended minimum value of REXT is 2kΩ, or it may cause a large current. Note 8: Guaranteed by design. Note 9: Cb= total capacitance of one bus line in pF. ISINK ≤ 6mA. TR and tF measured between 0.3×VCC and 0.7×VCC. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 6 IS31FL3235A DETAILED DESCRIPTION The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. I2C INTERFACE The IS31FL3235A uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3235A has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Since IS31FL3235A only supports write operations, A0 must always be “0”. The value of bits A1 and A2 are decided by the connection of the AD pin. After the last bit of the chip address is sent, the master checks for the IS31FL3235A’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3235A has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. The complete slave address is: Table 1 Slave Address (Write only): Bit A7:A3 A2:A1 A0 Value 01111 AD 0 Following acknowledge of IS31FL3235A, the register address byte is sent, most significant bit first. IS31FL3235A must generate another acknowledge indicating that the register address has been received. AD connected to GND, AD = 00; AD connected to VCC, AD = 11; AD connected to SCL, AD = 01; AD connected to SDA, AD = 10; Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3235A must generate another acknowledge to indicate that the data was received. The SCL line is uni-directional. The SDA line is bi-directional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3235A. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. ADDRESS AUTO INCREMENT The timing diagram for the I2C is shown in Figure 3. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. Figure 3 Interface Timing Figure 4 Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 To write multiple bytes of data into IS31FL3235A, load the address of the data register that the first data byte is intended for. During the IS31FL3235A acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3235A will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS31FL3235A (Figure 6). Bit Transfer 7 IS31FL3235A Figure 5 Figure 6 Writing to IS31FL3235A (Typical) Writing to IS31FL3235A (Automatic Address Increment) REGISTERS DEFINITIONS Table 2 Register Function Address 00h Name Function Table Default Shutdown Register Set software shutdown mode 3 PWM Register 28 channels PWM duty cycle data register 4 25h PWM Update Register Load PWM Register and LED Control Register’s data - 2Ah~45h LED Control Register Channel 1 to 28 enable bit and current setting 5 4Ah Global Control Register Set all channels enable 6 4Bh Output Frequency Setting Register Set all channels operating frequency 7 0000 0000 4Fh Reset Register Reset all registers into default value - xxxx xxxx 05h~20h xxxx xxxx 0000 0000 Table 4 05h~20h PWM Register (OUT1~OUT28) Table 3 00h Shutdown Register Bit D7:D1 D0 Bit D7:D0 Name - SSD Name PWM Default 0000 000 0 Default 0000 0000 The Shutdown Register sets software shutdown mode of IS31FL3235A. SSD 0 1 0000 0000 Software Shutdown Enable Software shutdown mode Normal operation The PWM Registers adjusts LED luminous intensity in 256 steps. The value of a channel’s PWM Register decides the average output current for each output, OUT1~OUT28. The average output current may be computed using the Formula (1): I PWM  I OUT 7   D[n]  2 n 256 n0 (1) Where “n” indicates the bit location in the respective PWM register. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 8 IS31FL3235A For example: D7:D0 = 10110101, IOUT = IMAX (20+22+24+25+27)/256 The IOUT of each channel is setting by the SL bit of LED Control Register (2Ah~45h). Please refer to the detail information in Page 11. 25h PWM Update Register The data sent to the PWM Registers and the LED Control Registers will be stored in temporary registers. A write operation of “0000 0000” value to the Update Register is required to update the registers (05h~20h, 2Ah~45h). Table 6 4Ah Global Control Register Bit D7:D1 D0 Name - G_EN Default 0000 000 0 The Global Control Register set all channels enable. G_EN 0 1 Global LED Enable Normal operation Shutdown all LEDs Table 7 4Bh Output Frequency Setting Register Table 5 2Ah~45h LED Control Register (OUT1~OUT28) Bit D7:D3 D2:D1 D0 Name - SL OUT Default 0000 0 00 0 The LED Control Registers store the on or off state of each LED and set the output current. SL 00 01 10 11 Output Current Setting (IOUT) IMAX IMAX/2 IMAX/3 IMAX/4 OUT 0 1 LED State LED off LED on Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 Bit D7:D1 D0 Name - OFS Default 0000 000 0 The Output Frequency Setting Register selects a fixed PWM operating frequency for all output channels. OFS 0 1 Output Frequency Setting 3kHz 22kHz 4Fh Reset Register Once user writes “0000 0000” data to the Reset Register, IS31FL3235A will reset all registers to default value. On initial power-up, the IS31FL3235A registers are reset to their default values for a blank display. 9 IS31FL3235A FUNCTIONAL BLOCK DIAGRAM VCC Scaling Data SDA SCL I2C Interface EN Data Registers PWM&EN &Scaling Logic AD PWM Data CMP OSC Current Control R_EXT Output OUT1~OUT28 Counter Bias SD_Chip SDB GND Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 10 IS31FL3235A TYPICAL APPLICATION INFORMATION PWM CONTROL Table 8 32 Gamma Steps With 256 PWM Steps The PWM Registers (05h~2Ah) can modulate LED brightness of 28 channels with 256 steps. For example, if the data in PWM Register is “0000 0100”, then the PWM is the fourth step. C(0) C(1) C(2) C(3) C(4) C(5) C(6) C(7) 0 1 2 4 6 10 13 18 C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) 22 28 33 39 46 53 61 69 Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23) 78 86 96 106 116 126 138 149 C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31) 161 173 186 199 212 226 240 255 REXT The maximum output current of OUT1~OUT28 can be adjusted by the external resistor, REXT, as described in Formula (2). 256 224 192 (2) PWM Data I MAX V  x  EXT REXT x = 58.5, VOUT = 0.8V, VEXT = 1.3V. 160 128 96 The recommended minimum value of REXT is 2kΩ. 64 CURRENT SETTING 32 The current of each LED can be set independently by the SL bit of LED Control Register (2Ah~45h). The maximum global current is set by the external register REXT. When channels drive different quantity of LEDs, adjust maximum output current according to quantity of LEDs to ensure average current of each LED is the same. For example, set REXT= 3.3kΩ then IMAX= 23mA. If OUT1 drives two LEDs and OUT2 drives four LEDs, set the SL bit of LED Control Register (2Ah) to “01” and SL bit of LED Control Register (2Bh) to “00”. So the current of OUT1 is IOUT1= IMAX/2= 11.5mA and the current of OUT2 is IOUT2= IMAX= 23mA. The average current of each LED is the same. GAMMA CORRECTION In order to perform a better visual LED breathing effect we recommend using a gamma corrected PWM value to set the LED intensity. This results in a reduced number of steps for the LED intensity setting, but causes the change in intensity to appear more linear to the human eye. Gamma correction, also known as gamma compression or encoding, is used to encode linear luminance to match the non-linear characteristics of display. Since the IS31FL3235A can modulate the brightness of the LEDs with 256 steps, a gamma correction function can be applied when computing each subsequent LED intensity setting such that the changes in brightness matches the human eye’s brightness curve. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 0 0 4 8 12 16 20 24 28 32 Intensity Steps Figure 7 Gamma Correction (32 Steps) Choosing more gamma steps provides for a more continuous looking breathing effect. This is useful for very long breathing cycles. The recommended configuration is defined by the breath cycle T. When T=1s, choose 32 gamma steps, when T=2s, choose 64 gamma steps. The user must decide the final number of gamma steps not only by the LED itself, but also based on the visual performance of the finished product. Table 9 64 Gamma Steps With 256 PWM Steps C(0) C(1) C(2) C(3) C(4) C(5) C(6) C(7) 0 1 2 3 4 5 6 7 C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) 8 10 12 14 16 18 20 22 C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23) 24 26 29 32 35 38 41 44 C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31) 47 50 53 57 61 65 69 73 C(32) C(33) C(34) C(35) C(36) C(37) C(38) C(39) 77 81 85 89 94 99 104 109 C(40) C(41) C(42) C(43) C(44) C(45) C(46) C(47) 114 119 124 129 134 140 146 152 C(48) C(49) C(50) C(51) C(52) C(53) C(54) C(55) 158 164 170 176 182 188 195 202 C(56) C(57) C(58) C(59) C(60) C(61) C(62) C(63) 209 216 223 230 237 244 251 255 11 IS31FL3235A generate an AC ripple on the power supply which cause stress to the decoupling capacitors. 256 224 When the AC ripple is applied to a monolithic ceramic capacitor chip (MLCC) it will expand and contract causing the PCB to flex and generate audible hum in the range of between 20Hz to 20kHz, To avoid this hum, there are many countermeasures, such as selecting the capacitor type and value which will not cause the PCB to flex and contract. 160 128 96 64 32 0 0 8 16 24 32 40 48 56 64 Intensity Steps Figure 8 Gamma Correction (64 Steps) Note, the data of 32 gamma steps is the standard value and the data of 64 gamma steps is the recommended value. SHUTDOWN MODE Shutdown mode can be used as a means of reducing power consumption. During shutdown mode all registers retain their data. Software Shutdown By setting SSD bit of the Shutdown Register (00h) to “0”, the IS31FL3235A will operate in software shutdown mode. When the IS31FL3235A is in software shutdown mode, all current sources are switched off. An additional option for avoiding audible hum is to set the IS31FL3235A’s output PWM frequency above the audible range. The Output Frequency Setting Register 4Bh bit D0 can be used to set the switching frequency to 22kHz, which is beyond the audible range. Figure 9 below shows the variation of output PWM frequency across supply voltage and temperature. 30 Output PWM Frequency (kHz) PWM Data 192 25 85°C 20 25°C 15 -40°C 10 5 Hardware Shutdown The chip enters hardware shutdown mode when the SDB pin is pulled low. 0 2.7 3.1 Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 3.9 4.3 4.7 5.1 5.5 VCC (V) PWM FREQUENCY SELECT The IS31FL3235A output channels operate with a default PWM frequency of 3kHz. Because all the OUTx channels are synchronized, the DC supply will experience large instantaneous current surges when the OUTx channels turn ON. These current surges will 3.5 Figure 9 VCC vs. Output PWM Frequency 12 IS31FL3235A CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 10 Classification Profile Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 13 IS31FL3235A PACKAGE INFORMATION QFN-36 Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 14 IS31FL3235A RECOMMENDED LAND PATTERN QFN-36 Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use. Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 15 IS31FL3235A REVISION HISTORY Revision Detail Information Date A Initial release 2016.12.22 B Correct wrong package information 2017.01.22 C Update land pattern 2017.06.16 D Update functional block’s pin name 2017.12.12 E 1. Update θJA value 2. Revise VIL, VIH test condition to VCC = 2.7V~5.5V 3. Update Figure 1 and add Figure 2 for RGB application 2018.08.03 F Update logo to LUMISSIL 2019.09.20 G Update to new Lumissil logo 2019.12.26 H Update land pattern 2020.08.20 Lumissil Microsystems – www.lumissil.com Rev. H, 08/20/2020 16