T4 Data Sheet
DST4-v3.0
November 2021
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Copyright © 2021. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.
Contents
Introduction..................................................................................................................................... 3
Features............................................................................................................................................3
Available Package Options...................................................................................................................... 4
Device Core Functional Description................................................................................................5
XLR Cell.......................................................................................................................................................5
Logic Cell....................................................................................................................................................5
Embedded Memory..................................................................................................................................6
Multipliers................................................................................................................................................... 7
Global Clock Network.............................................................................................................................. 7
Clock and Control Distribution Network....................................................................................7
Device Interface Functional Description......................................................................................... 8
Interface Block Connectivity.................................................................................................................... 8
General-Purpose I/O Logic and Buffer...................................................................................................9
Simple I/O Buffer......................................................................................................................... 10
I/O Banks.................................................................................................................................................. 11
PLL............................................................................................................................................................. 12
Oscillator...................................................................................................................................................13
Power Up Sequence...................................................................................................................... 14
Power Supply Current Transient............................................................................................................14
Configuration.................................................................................................................................15
Supported Configuration Modes..........................................................................................................16
Mask-Programmable Memory Option..................................................................................................16
DC and Switching Characteristics................................................................................................. 17
ESD Performance........................................................................................................................... 19
Configuration Timing.................................................................................................................... 20
Maximum tUSER for SPI Active and Passive Modes............................................................................. 22
PLL Timing and AC Characteristics............................................................................................... 22
Internal Oscillator..........................................................................................................................23
Pinout Description.........................................................................................................................23
Efinity Software Support............................................................................................................... 26
T4 Interface Floorplan...................................................................................................................26
Ordering Codes............................................................................................................................. 26
Revision History.............................................................................................................................27
T4 Data Sheet
Introduction
The T4 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped
with an I/O interface in a small footprint package for easy integration. T4 FPGAs support
mobile, consumer, and IoT edge markets that need low power, low cost, and a small form
factor. With ultra-low power T4 FPGAs, designers can build products that are always on,
providing enhanced capabilities for applications such as embedded vision, voice and gesture
recognition, intelligent sensor hubs, and power management.
Features
•
•
•
•
•
•
•
•
•
High-density, low-power Quantum™ architecture
Built on SMIC 40 nm process
Less than 150 μA typical core leakage current at 1.1 V
Ultra-small footprint package options
FPGA interface blocks
— GPIO
— PLL
— Oscillator
Programmable high-performance I/O
— Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
Flexible on-chip clocking
— 12 low-skew global clock signals can be driven from off-chip external clock signals or
PLL synthesized clock signals
— PLL support
Flexible device configuration
— Standard SPI interface (active, passive, and daisy chain)
— JTAG interface
— Optional Mask Programmable Memory (MPM) capability
Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1: T4 FPGA Resources
(1)
LEs(1)
Global Clock
Networks
Global Control
Networks
Embedded
Memory (kbits)
Embedded
Memory Blocks
(5 Kbits)
Embedded
Multipliers
3,888
Up to 16
Up to 8
76.8
15
4
Logic capacity in equivalent LE counts.
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T4 Data Sheet
Table 2: T4 FPGA Package-Dependent Resources
Resource
BGA49
BGA81
Available GPIO
33
55
Global clocks from GPIO pins
4
8
Global controls from GPIO
pins
5
8
PLL (simple)
1
1
Oscillator
1
1
1 (optional)
1 (optional)
MPM
Learn more: Refer to the Trion Packaging User Guide for the package outlines and markings.
Available Package Options
Table 3: Available Packages
Package
(2)
Dimensions (mm x mm)
Pitch (mm)
49-ball FBGA(2)
3x3
0.4
81-ball FBGA
5x5
0.5
This package does not have dedicated JTAG pins (TDI, TDO, TCK, TMS).
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T4 Data Sheet
Device Core Functional Description
T4 FPGAs feature an eXchangeable Logic and Routing (XLR) cell that Efinix has optimized
for a variety of applications. Trion® FPGAs contain three building blocks constructed from
XLR cells: logic elements, embedded memory blocks, and multipliers. Each FPGA in the
Trion® family has a custom number of building blocks to fit specific application needs. As
shown in the following figure, the FPGA includes I/O ports on all four sides, as well as
columns of XLR cells, memory, and multipliers. A control block within the FPGA handles
configuration.
Figure 1: T4 FPGA Block Diagram
Quantum Fabric
Device Interface
XLR Cells and Routing
Multiplier
Embedded Memory
Device Interface
I/O Ports from Core to Device Interface
Each Device Contains Unique
Interface Blocks such as GPIO
and PLL
Note: The number and locations of rows and
columns are shown for illustration purposes
only. The actual number and position depends
on the core.
XLR Cell
The eXchangeable Logic and Routing (XLR) cell is the basic building block of the Quantum™
architecture. The Efinix XLR cell combines logic and routing and supports both functions
interchangeably. This unique innovation greatly enhances the transistor flexibility and
utilization rate, thereby reducing transistor counts and silicon area significantly.
Logic Cell
The logic cell comprises a 4-input LUT or a full adder plus a register (flipflop). You can
program each LUT as any combinational logic function with four inputs. You can configure
multiple logic cells to implement arithmetic functions such as adders, subtractors, and
counters.
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T4 Data Sheet
Figure 2: Logic Cell Block Diagram
I[3:0]
Clock
4-Input LUT
LUT Out
Flipflop
Clock Enable
Preset/Reset
Register Out
Adder
Carry Out
Carry In
Embedded Memory
The core has 5-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory
blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, FIFOs,
or ROM. You can initialize the memory content during configuration. The Efinity® software
includes a memory cascading feature to connect multiple blocks automatically to form a
larger array. This feature enables you to instantiate deeper or wider memory modules.
The memory read and write ports have the following modes for addressing the memory
(depth x width):
256 x 16
1024 x 4
4096 x 1
512 x 10
512 x 8
2048 x 2
256 x 20
1024 x 5
The read and write ports support independently configured data widths.
Figure 3: Embedded Memory Block Diagram (True Dual-Port Mode)
Write Data A [9:0]
Address A [11:0]
Write Enable A
Clock A
Clock Enable A
Read Data A [9:0]
Embedded
Memory
Write Data B [9:0]
Address B [11:0]
Write Enable B
Clock B
Clock Enable B
Read Data B [9:0]
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T4 Data Sheet
Multipliers
The FPGA has high-performance multipliers that support 18 x 18 fixed-point multiplication.
Each multiplier takes two signed 18-bit input operands and generates a signed 36-bit output
product. The multiplier has optional registers on the input and output ports.
Figure 4: Multiplier Block Diagram
Operand A [17:0]
Multiplier
Operand B [17:0]
Clock
Multiplier Output [35:0]
Clock Enable Output
Set/Reset Output
Clock Enable A
Set/Reset A
Clock Enable B
Set/Reset B
Global Clock Network
The Quantum™ core fabric supports up to 16 global clock (GCLK) signals feeding 16 prebuilt global clock networks. Global clock pins (GPIO), PLL outputs, oscillator output, and
core-generated clocks can drive the global clock network.
The global clock networks are balanced clock trees that feed all FPGA modules. Each
network has dedicated clock-enable logic to save power by disabling the clock tree at the
root. The logic dynamically enables/disables the network and guarantees no glitches at the
output.
Figure 5: Global Clock Network
Binary Clock Tree
Distribution
GCLK [0:7]
GCLK [8:15]
Clock and Control Distribution Network
The global clock network is distributed through the device to provide clocking for the core's
LEs, memory, multipliers, and I/O blocks. Designers can access the T4 global clock network
using the global clock GPIO pins, PLL outputs, oscillator output, and core-generated clocks.
Similarly, the T4 has GPIO pins (the number varies by package) that the designer can
configure as control inputs to access the high-fanout network connected to the LE's set, reset,
and clock enable signals.
Learn more: Refer to the T4 pinout for information on the location and names of these pins.
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T4 Data Sheet
Device Interface Functional Description
The device interface wraps the core and routes signals between the core and the device
I/O pads through a signal interface. Because they use the flexible Quantum™ architecture,
devices in the Trion® family support a variety of interfaces to meet the needs of different
applications.
Learn more: The following sections describe the available device interface features in T4 FPGAs. Refer to
the Trion® Interfaces User Guide for details on the Efinity® Interface Designer settings.
Interface Block Connectivity
The FPGA core fabric connects to the interface blocks through a signal interface. The
interface blocks then connect to the package pins. The core connects to the interface blocks
using three types of signals:
• Input—Input data or clock to the FPGA core
• Output—Output from the FPGA core
• Clock output—Clock signal from the core clock tree
Figure 6: Interface Block and Core Connectivity
FPGA
Interface
Block
Interface
Block
Signal
Interface
Input
Output
Core
Input
Output
Clock Output
Clock Output
Input
Output
Input
Output
Clock Output
Clock Output
Interface
Block
Interface
Block
GPIO
GPIO blocks are a special case because they can operate in several modes. For example, in
alternate mode the GPIO signal can bypass the signal interface and directly feed another
interface block. So a GPIO configured as an alternate input can be used as a PLL reference
clock without going through the signal interface to the core.
When designing for Trion® FPGAs, you create an RTL design for the core and also configure
the interface blocks. From the perspective of the core, outputs from the core are inputs to the
interface block and inputs to the core are outputs from the interface block.
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T4 Data Sheet
The Efinity netlist always shows signals from the perspective of the core, so some signals do
not appear in the netlist:
• GPIO used as reference clocks are not present in the RTL design, they are only visible in
the interface block configuration of the Efinity® Interface Designer.
• The FPGA clock tree is connected to the interface blocks directly. Therefore, clock
outputs from the core to the interface are not present in the RTL design, they are only
part of the interface configuration (this includes GPIO configured as output clocks).
The following sections describe the different types of interface blocks in the T4. Signals and
block diagrams are shown from the perspective of the interface, not the core.
General-Purpose I/O Logic and Buffer
The GPIO support the 3.3 V LVTTL and 1.8 V, 2.5 V, and 3.3 V LVCMOS I/O standards.
The GPIOs are grouped into banks. Each bank has its own VCCIO that sets the bank voltage
for the I/O standard.
Each GPIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the
I/O buffers. I/O buffers are located at the periphery of the device.
The I/O logic comprises three register types:
• Input—Capture interface signals from the I/O before being transferred to the core logic
• Output—Register signals from the core logic before being transferred to the I/O buffers
• Output enable—Enable and disable the I/O buffers when I/O used as output
Table 4: GPIO Modes
GPIO Mode
Input
Description
Only the input path is enabled; optionally registered. If registered, the input path uses the input
clock to control the registers (positively or negatively triggered).
Select the alternate input path to drive the alternate function of the GPIO. The alternate path
cannot be registered.
Output
Only the output path is enabled; optionally registered. If registered, the output path uses the
output clock to control the registers (positively or negatively triggered).
The output register can be inverted.
Bidirectional
The input, output, and OE paths are enabled; optionally registered. If registered, the input clock
controls the input register, the output clock controls the output and OE registers. All registers can
be positively or negatively triggered. Additionally, the input and output paths can be registered
independently.
The output register can be inverted.
Clock output
Clock output path is enabled.
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T4 Data Sheet
Table 5: Supported Features for GPIO
Package
BGA49
BGA81
GPIO
Schmitt Trigger
Variable Drive Strength
LVDS as GPIO
–
Pull-up
Pull-down
Slew Rate
During configuration, all GPIO pins are configured in weak pull-up mode.
During user mode, unused GPIO pins are tri-stated and configured in weak pull-up mode.
You can change the default mode to weak pull-down in the Interface Designer.
Note: Refer to Table 19: Single-Ended I/O Buffer Drive Strength Characteristics on page 18 for more
information.
Simple I/O Buffer
Figure 7: I/O Interface Block
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T4 Data Sheet
Table 6: GPIO Signals
Signal
Direction
Description
IN
Output
Input data from the GPIO pad to the core fabric.
ALT
Output
Alternative input connection (in the Interface Designer, the input
Register Option is none). Alternative connections are GCLK, GCTRL, and
PLL_CLKIN.
OUT
Input
Output data to GPIO pad from the core fabric.
OE
Input
Output enable from core fabric to the I/O block. Can be registered.
OUTCLK
Input
Core clock that controls the output and OE register. This clock is not
visible in the user netlist.
INCLK
Input
Core clock that controls the input register. This clock is not visible in the
user netlist.
Table 7: GPIO Pads
Signal
IO
Direction
Bidirectional
Description
GPIO pad.
I/O Banks
Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has
independent power pins. The number and voltages supported vary by FPGA and package.
Table 8: I/O Banks by Package
Package
I/O Banks
Voltage (V)
Banks with
DDIO Support
Merged Banks
BGA49, BGA81
1A - 1C, 2A, 2B
1.8, 2.5, 3.3
–
–
Learn more: Refer to the T4 pinout for information on the I/O bank assignments.
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T4 Data Sheet
PLL
The T4 has 1 PLL to synthesize clock frequencies. The PLL's reference clock input comes
from a dedicated GPIO's alternate input pin. The PLL consists of a pre-divider counter (N
counter), a feedback multiplier counter (M counter), post-divider counter (O counter), and an
output divider per clock output.
Figure 8: T4 PLL Block Diagram
PLL
CLKIN
FIN
N
Counter
FPFD
Phase
Frequency
Detector
Charge
Pump
Voltage
Control
Oscillator
Loop
Filter
FVCO
M
Counter
RSTN
FOUT
O
Counter
Output
Divider
The counter settings define the PLL output frequency:
LOCKED
CLKOUT0
CLKOUT1
CLKOUT2
where:
FPFD = FIN / N
FVCO is the voltage control oscillator frequency
FOUT = FVCO / (O x Output divider)
FIN is the reference clock frequency
FVCO = FPFD x M
FOUT is the output clock frequency
FPFD is the phase frequency detector input frequency
Note: The reference clock must be between 10 and 50 MHz.
The PFD input must be between 10 and 50 MHz.
The VCO frequency must be between 500 and 1,500 MHz.
Unlike other Trion® FPGAs, the T4 PLL output locks on the negative clock edge (not the
positive edge). When you are using two or more clock outputs, they are aligned on the falling
edge. If the core register receiving the clock is positive edge triggered, Efinix recommends
inverting the clock outputs so they are correctly edge aligned.
Figure 9: PLL Output Aligned with Negative Edge
PLL Output (Negative Edge)
Inverted PLL Output (Positive Edge)
CLKOUT0
CLKOUT0
CLKOUT1
CLKOUT1
CLKOUT2
CLKOUT2
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T4 Data Sheet
Table 9: PLL Pins
Port
Direction
Description
CLKIN
Input
Reference clock. This port is also a GPIO pin; the GPIO pins' alternate
function is configured as a reference clock.
RSTN
Input
Active-low PLL reset signal. When asserted, this signal resets the PLL;
when de-asserted, it enables the PLL. Connect this signal in your design to
power up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10
ns to reset the PLL.
CLKOUT0
CLKOUT1
Output
PLL output. The designer can route these signals as input clocks to the
core's GCLK network.
Output
Goes high when PLL achieves lock; goes low when a loss of lock is
detected. Connect this signal in your design to monitor the lock status.
This signal is analog asynchronous.
CLKOUT2
LOCKED
Table 10: PLL Settings
Configure these settings in the Efinity® Interface Designer.
Setting
Allowed Values
Notes
N counter
1 - 15 (integer)
Pre-divider
M counter
1 - 255 (integer)
Multiplier
O counter
1, 2, 4, 8
Post-divider
Output divider
2, 4, 8, 16, 32, 64, 128, 256
Output divider per output
Oscillator
The T4 has 1 low-frequency oscillator tailored for low-power operation. The oscillator runs
at nominal frequency of 10 kHz. Designers can use the oscillator to perform always-on
functions with the lowest power possible. Its output clock is available to the GCLK network.
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T4 Data Sheet
Power Up Sequence
Efinix® recommends the following power up sequence when powering Trion® FPGAs:
1. Power up VCC and VCCA_xx first.
2. When VCC and VCCA_xx are stable, power up all VCCIO pins. There is no specific
timing delay between the VCCIO pins.
3. After all power supplies are stable, hold CRESET_N low for a duration of tCRESET_N
before asserting CRESET_N from low to high to trigger active SPI programming (the
FPGA loads the configuration data from an external flash device).
When you are not using the GPIO or PLL resources, connect the pins as shown in the
following table.
Table 11: Connection Requirements for Unused Resources
Unused Resource
Pin
Note
GPIO Bank
VCCIOxx
Connect to either 1.8 V, 2.5 V, or 3.3 V.
PLL
VCCA_PLL
Connect to VCC.
Note: Refer to Configuration Timing on page 20 for timing information.
Figure 10: Trion® FPGAs Power Up Sequence
VCC
VCCA_xx
All VCCIO
CRESET_N
tCRESET_vN
Power Supply Current Transient
You may observe an inrush current on the dedicated power rail during power-up. You must
ensure that the power supplies selected in your board meets the current requirement during
power-up and the estimated current during user mode. Use the Power Estimator to calculate
the estimated current during user mode.
Table 12: Maximum Power Supply Current Transient
Power Supply
VCC
(3)
(4)
Maximum Power Supply
Current Transient(3)(4)
Unit
18
mA
Inrush current for other power rails are not significant in Trion® FPGAs.
Measured at room temperature.
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T4 Data Sheet
Configuration
The T4 FPGA contains volatile Configuration RAM (CRAM). The user must configure the
CRAM for the desired logic function upon power-up and before the FPGA enters normal
operation. The FPGA's control block manages the configuration process and uses a bitstream
to program the CRAM. The Efinity® software generates the bitstream, which is design
dependent. You can configure the T4 FPGA(s) in active, passive, or JTAG mode.
Learn more: Refer to AN 006: Configuring Trion FPGAs for details on the dedicated configuration pins
and how to configure FPGA(s).
Figure 11: High-Level Configuration Options
Board
JTAG
Interface
SPI Flash
Processor
Microcontroller
Trion FPGA
JTAG
SPI Data
JTAG Mode
Controller
SPI Active Mode
Controller
Control Block
Configuration
Manager
User
Logic
SPI Passive Mode
Controller
In active mode, the FPGA controls the configuration process. An oscillator circuit within the
FPGA provides the configuration clock. The bitstream is typically stored in an external serial
flash device, which provides the bitstream when the FPGA requests it.
The control block sends out the instruction and address to read the configuration data. First,
it issues a release from power-down instruction to wake up the external SPI flash. Then, it
waits for at least 30 μs before issuing a fast read command to read the content of SPI flash
from address 24h’000000.
In passive mode, the FPGA is the slave and relies on an external master to provide the
control, bitstream, and clock for configuration. Typically the master is a microcontroller or
another FPGA in active mode.
In JTAG mode, you configure the FPGA via the JTAG interface.
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T4 Data Sheet
Supported Configuration Modes
Table 13: T4 Configuration Modes by Package
Configuration Mode
Active
Width
BGA49
BGA81
X1
X2
X4
Passive
X1
X2
X4
X8
JTAG
X1
Mask-Programmable Memory Option
The T4 FPGA is equipped with one-time programmable MPM. With this feature, you use
on-chip MPM instead of an external serial flash device to configure the FPGA. This option
is for systems that require an ultra-small factor and the lowest cost structure such that an
external serial flash device is undesirable and/or not required at volume production. MPM is
a one-time factory programmable option that requires a Non-Recurring Engineering (NRE)
payment. To enable MPM, submit your design to our factory; our Applications Engineers
(AEs) convert your design into a single configuration mask to be specially fabricated.
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T4 Data Sheet
DC and Switching Characteristics
Table 14: Absolute Maximum Ratings (5)
Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute
maximum ratings for extended periods of time has adverse effects on the device.
Symbol
Description
Min
Max
Units
VCC
Core power supply
-0.5
1.42
V
VCCIO
I/O bank power supply
-0.5
4.6
V
VCCA_PLL
PLL analog power supply
-0.5
1.42
V
VIN
I/O input voltage
-0.5
4.6
V
TJ
Operating junction temperature
-40
125
°C
TSTG
Storage temperature, ambient
-55
150
°C
Table 15: Recommended Operating Conditions (5)
Symbol
Description
Min
Typ
Max
Units
VCC
Core power supply
1.05
1.1
1.15
V
VCCIO
1.8 V I/O bank power supply
1.71
1.8
1.89
V
2.5 V I/O bank power supply
2.38
2.5
2.63
V
3.3 V I/O bank power supply
3.14
3.3
3.47
V
PLL analog power supply
1.05
1.1
1.15
V
-0.3
–
VCCIO
+ 0.3
V
0
–
85
°C
-40
–
100
°C
VCCA_PLL
VIN
I/O input voltage
TJCOM
Operating junction temperature, commercial
TJIND
Operating junction temperature, industrial
(6)
Table 16: Power Supply Ramp Rates
Symbol
tRAMP
Description
Power supply ramp rate for all supplies.
Min
Max
Units
VCCIO/0.01
10
V/ms
VOL (V)
VOH (V)
Table 17: Single-Ended I/O DC Electrical Characteristics
I/O Standard
VIL (V)
VIH (V)
Min
Max
Min
Max
Max
Min
3.3 V LVCMOS
-0.3
0.8
2
VCCIO + 0.3
0.2
VCCIO - 0.2
3.3 V LVTTL
-0.3
0.8
2
VCCIO + 0.3
0.4
2.4
2.5 V LVCMOS
-0.3
0.7
1.7
VCCIO + 0.3
0.5
1.8
1.8 V LVCMOS
-0.3
VCCIO + 0.3
0.45
VCCIO - 0.45
(5)
(6)
0.35 * VCCIO 0.65 * VCCIO
Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply.
Values applicable to both input and tri-stated output configuration.
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T4 Data Sheet
Table 18: Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic
Voltage
VT+ (V) Schmitt
Trigger Low-toHigh Threshold
VT- (V) Schmitt
Trigger High-toLow Threshold
Input Leakage
Current (μA)
Tristate Output
Leakage
Current (μA)
3.3
1.73
1.32
±10
±10
2.5
1.37
1.01
±10
±10
1.8
1.05
0.71
±10
±10
Table 19: Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage, device in nominal process (TT).
CDONE and CRESET_N have a drive strength of 1.
I/O Standard
3.3 V
2.5 V
1.8 V
Drive Strength
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
1
14.4
8.0
9.1
8.0
4.4
5.1
2
19.1
10.5
12.2
10.5
5.8
6.8
3
23.9
13.3
15.2
13.4
7.3
8.6
4
28.7
15.8
18.2
15.9
8.6
10.3
Table 20: Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance
CDONE and CRESET_N also have an internal weak pull-up with these values.
I/O Standard
Internal Pull-Up
Internal Pull-Down
Units
Min
Typ
Max
Min
Typ
Max
3.3 V LVTTL/LVCMOS
27
40
65
30
47
83
kΩ
2.5 V LVCMOS
35
55
95
37
62
118
kΩ
1.8 V LVCMOS
53
90
167
54
99
202
kΩ
Table 21: Single-Ended I/O Rise and Fall Time
Data are based on the following IBIS simulation setup:
• Weakest drive strength model
• Typical simulation corner setting
• RLC circuit with 6.6 pF capacitance, 16.6 nH inductance, 0.095 ohm resistance, and 25 °C temperature
Note: For a more accurate data, you need to perform the simulation with your own circuit.
I/O Standard
Rise Time (TR)
Fall Time (TF)
Units
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
3.3 V LVTTL/LVCMOS
1.13
1.02
1.24
1.17
ns
2.5 V LVCMOS
1.4
1.3
1.44
1.31
ns
1.8 V LVCMOS
2.14
2.01
2.05
1.85
ns
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T4 Data Sheet
Table 22: Maximum Toggle Rate
I/O Standard
Test Condition Load (pF)
Max Toggle Rate (Mbps)
3.3 V LVTTL/LVCMOS
10
400
2.5 V LVCMOS
10
400
1.8 V LVCMOS
10
400
Table 23: Block RAM Characteristics
Symbol
fMAX
Description
Block RAM maximum frequency.
C2, I2 Speed Grade
Units
275
MHz
C2, I2 Speed Grade
Units
275
MHz
Table 24: Multiplier Block Characteristics
Symbol
fMAX
Description
Multiplier block maximum frequency.
ESD Performance
Refer to the Trion Reliability Report for ESD performance data.
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T4 Data Sheet
Configuration Timing
The T4 FPGA has the following configuration timing specifications. Refer to AN 006:
Configuring Trion FPGAs for detailed configuration information.
Timing Waveforms
Figure 12: SPI Active Mode (x1) Timing Sequence
CCK
tCRESET_N
CRESET_N
SS_N
VCC
CDI0
Read
24 bit Start Address
Dummy Byte
tH
CDI1
Data
tSU
Figure 13: SPI Passive Mode (x1) Timing Sequence
CCK
tCRESET_N
CRESET_N
SS_N
tDMIN
tCLK
GND
tCLKL
tH
CDI
Header and Data
tSU
CDONE
tUSER
The FPGA enters user mode; configuration
I/O pins are released for user functions
Figure 14: Boundary-Scan Timing Waveform
TMS
TDI
tTMSSU
tTDISU
tTMSH
TCK
tTDIH
TDO
tTCKTDO
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T4 Data Sheet
Timing Parameters
Table 25: All Modes
Symbol
Parameter
Min
Typ
Max
Units
tCRESET_N
Minimum creset_n low pulse width required to
trigger re-configuration.
320
–
–
ns
tUSER
Minimum configuration duration after CDONE
goes high before entering user mode.(7)(8)
12
–
(9)
μs
Test condition at 10 kΩ pull-up resistance and
10 pF output loading on CDONE pin.
Table 26: Active Mode
Symbol
Parameter
Frequency
Min
Typ
Max
Units
DIV4
14
20
26
MHz
DIV8
7
10
13
MHz
Min
Typ
Max
Units
Passive mode X1 configuration clock frequency.
–
–
25
MHz
Passive mode X2, X4 or X8 configuration clock frequency.
–
–
50
MHz
fMAX_M
Active mode configuration clock
frequency(10).
Table 27: Passive Mode
Symbol
fMAX_S
Parameter
tCLKH
Configuration clock pulse width high.
0.48*1/
fMAX_S
–
–
ns
tCLKL
Configuration clock pulse width low.
0.48*1/
fMAX_S
–
–
ns
tSU
Setup time.
4
–
–
ns
tH
Hold time.
1
–
–
ns
tDMIN
Minimum time between deassertion of CRESET_N to first
valid configuration data.
1.2
–
–
μs
Table 28: JTAG Mode
Symbol
Parameter
Min
Typ
Max
Units
fTCK
TCK frequency.
–
–
25
MHz
tTDISU
TDI setup time.
3.5
–
–
ns
tTDIH
TDI hold time.
1
–
–
ns
tTMSSU
TMS setup time.
3
–
–
ns
tTMSH
TMS hold time.
1
–
–
ns
tTCKTDO
TCK falling edge to TDO output.
–
–
10.5(11)
ns
(7)
(8)
(9)
(10)
(11)
The FPGA may go into user mode before tUSER has elapsed. However, Efinix recommends that you keep the system
interface to the FPGA in reset until tUSER has elapsed.
For JTAG programming, the min tUSER configuration time is required after CDONE goes high and FPGA receives the
ENTERUSER instruction from JTAG host (TAP controller in UPDATE_IR state).
See Maximum tUSER for SPI Active and Passive Modes on page 22
For parallel daisy chain x2 and x4, the active configuration clock frequency, fMAX_M, is required to set to DIV4.
0 pf output loading.
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21
T4 Data Sheet
Maximum tUSER for SPI Active and Passive
Modes
The following waveform illustrates the minimum and maximum values for tUSER.
B
CDONE
A
FPGA
Configuration
Mode
User
Mode
tUSER_MIN
tUSER
• Point A—User-defined trigger point to start counter on tUSER
• Point B—VIH (with Schmitt Trigger) of Trion I/Os
The maximum tUSER value can be derived based on the following formula:
Table 29: tUSER Maximum
Configuration Setup
tUSER Maximum
Single Trion FPGA
tUSER = t(from A to B) + tUSER_MIN
Slave FPGA in a dual-Trion FPGA SPI chain
Master FPGA in a dual-Trion FPGA SPI chain tUSER = (1344 / SPI_WIDTH) * CCK period + tUSER_MIN + t(from A to B)
PLL Timing and AC Characteristics
The following tables describe the PLL timing and AC characteristics.
Table 30: PLL Timing
Symbol
Parameter
Min
Typ
Max
Units
10
–
50
MHz
FPFD
Phase frequency detector input frequency.
FOUT
Output clock frequency.
0.25
–
400
MHz
FVCO
PLL VCO frequency.
500
–
1500
MHz
Min
Typ
Max
Units
40
50
60
%
tOPJIT (PK - PK) Output clock period jitter (PK-PK).
–
100
–
ps
tILJIT (PK - PK)
Input clock long-term jitter (PK-PK)
–
–
800
ps
tLOCK
PLL pull in plus lock-in time.
–
–
0.5
ms
Table 31: PLL AC Characteristics
Symbol
tDT
Parameter
Output clock duty cycle.
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T4 Data Sheet
Internal Oscillator
The internal oscillator has the following specifications.
Table 32: Internal Oscillator Specifications
Symbol
Parameter
FCLKOSC
Oscillator clock frequency.
DCHOSC
Duty cycle.
Min
Typ
Max
Units
–
10
–
kHz
45
50
55
%
Pinout Description
The following tables describe the pinouts for power, ground, configuration, and interfaces.
Table 33: General Pinouts
Function
Group
Direction
Description
VCC
Power
–
Core power supply.
VCCIO
Power
–
I/O pin power supply.
VCCA_PLL
Power
–
PLL analog power supply.
GND
Ground
–
Ground.
GNDA_PLL
Ground
–
PLL ground pin.
CLKn
Alternate
Input
Global clock network input. n is the number. The number of
inputs is package dependent.
CTRLn
Alternate
Input
Global network input used for high fanout and global reset. n is
the number. The number of inputs is package dependent.
PLLIN
Alternate
Input
PLL reference clock.
MREFCLK
Alternate
Input
MIPI PLL reference clock source.
GPIOx_n
GPIO
I/O
General-purpose I/O for user function. User I/O pins are singleended.
x: Indicates the bank (L or R)
n: Indicates the GPIO number.
GPIOx_n_yyy
GPIOx_n_yyy_zzz
GPIOx_zzzn
GPIO
MultiFunction
I/O
Multi-function, general-purpose I/O. These pins are single
ended. If these pins are not used for their alternate function, you
can use them as user I/O pins.
x: Indicates the bank; left (L) or right (R).
n: Indicates the GPIO number.
yyy, yyy_zzz: Indicates the alternate function.
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T4 Data Sheet
Table 34: Dedicated Configuration Pins
These pins cannot be used as general-purpose I/O after configuration.
Pins
Direction
Description
Output
Configuration done status pin. CDONE is an open drain output;
connect it to an external pull-up resistor to VCCIO. When CDONE
= 1, configuration is complete. If you hold CDONE low, the device
will not enter user mode.
CRESET_N
Input
Initiates FPGA re-configuration (active low). Pulse CRESET_N low
for a duration of tcreset_N before asserting CRESET_N from low to
high to initiate FPGA re-configuration. This pin does not perform a
system reset.
TCK
Input
JTAG test clock input (TCK). The rising edge loads signals applied
at the TAP input pins (TMS and TDI). The falling edge clocks out
signals through the TAP TDO pin.
TMS
Input
JTAG test mode select input (TMS). The I/O sequence on this
input controls the test logic operation . The signal value typically
changes on the falling edge of TCK. TMS is typically a weak pullup; when it is not driven by an external source, the test logic
perceives a logic 1.
TDI
Input
JTAG test data input (TDI). Data applied at this serial input is fed
into the instruction register or into a test data register depending
on the sequence previously applied at TMS. Typically, the signal
applied at TDI changes state following the falling edge of TCK
while the registers shift in the value received on the rising edge.
Like TMS, TDI is typically a weak pull-up; when it is not driven from
an external source, the test logic perceives a logic 1.
TDO
Output
JTAG test data output (TDO). This serial output from the test logic
is fed from the instruction register or from a test data register
depending on the sequence previously applied at TMS. During
shifting, data applied at TDI appears at TDO after a number of
cycles of TCK determined by the length of the register included
in the serial path. The signal driven through TDO changes state
following the falling edge of TCK. When data is not being shifted
through the device, TDO is set to an inactive drive state (e.g., highimpedance).
CDONE
Use External
Weak Pull-Up
Note: All dedicated configuration pins have Schmitt Trigger buffer. See Table 18: Single-Ended I/O and
Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic on page 18 for the Schmitt Trigger
buffer specifications.
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T4 Data Sheet
Table 35: Dual-Purpose Configuration Pins
In user mode (after configuration), you can use these dual-purpose pins as general I/O.
Pins
Direction
Description
Use External
Weak Pull-Up
CBUS[2:0]
Input
Configuration bus width select. Connect to weak pull-up
resistors if using default mode (x1).
CBSEL[1:0]
Input
Optional multi-image selection input (if external multi-image
configuration mode is enabled).
N/A
CCK
I/O
Passive SPI input configuration clock or active SPI output
configuration clock (active low). Includes an internal weak
pull-up.
N/A
CDIn
I/O
n is a number from 0 to 31 depending on the SPI
configuration.
N/A
0: Passive serial data input or active serial output.
1: Passive serial data output or active serial input.
n: Parallel I/O.
In multi-bit daisy chain connection, the CDIn (31:0) connects
to the data bus in parallel.
CSI
Input
Chip select.
0: The FPGA is not selected or enabled and will not be
configured.
1: Selects the FPGA for configuration (SPI and JTAG
configuration).
CSO
Output
Chip select output. Selects the next device for cascading
configuration.
N/A
NSTATUS
Output
Status (active low). Indicates a configuration error. When the
FPGA drives this pin low, it indicates an ID mismatch.
N/A
Input
SPI slave select (active low). Includes an internal weak
pull-up resistor to VCCIO during configuration. During
configuration, the logic level samples on this pin determine
the configuration mode. This pin is an input when sampled
at the start of configuration (SS is low); an output in active SPI
flash configuration mode.
SS_N
The FPGA senses the value of SS_N when it comes out of
reset (pulse CRESET_N low to high).
0: Passive mode
1: Active mode
TEST_N
Input
Active-low test mode enable signal. Set to 1 to disable test
mode.
During configuration, rely on the external weak pull-up or
drive this pin high.
RESERVED_OUT
Output
Reserved pin during user configuration. This pin drives high
during user configuration.
N/A
BGA49 and BGA81 packages only.
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T4 Data Sheet
Efinity Software Support
The Efinity® software provides a complete tool flow from RTL design to bitstream
generation, including synthesis, place-and-route, and timing analysis. The software has a
graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow,
and view results. The software also has a command-line flow and Tcl command console. The
Efinity® software supports simulation flows using the ModelSim, NCSim, or free iVerilog
simulators. An integrated hardware Debugger with Logic Analyzer and Virtual I/O debug
cores helps you probe signals in your design. The software-generated bitstream file configures
the T4 FPGA. The software supports the Verilog HDL and VHDL languages.
T4 Interface Floorplan
Note: The numbers in the floorplan figures indicate the GPIO number ranges. Some packages may not
have all GPIO pins in the range bonded out. Refer to the T4 pinout for information on which pins are
available in each package.
Figure 15: Floorplan Diagram for BGA49 and BGA81 Packages
Ordering Codes
Refer to the Trion Selector Guide for the full listing of T4 ordering codes.
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T4 Data Sheet
Revision History
Table 36: Revision History
Date
November 2021
Version
3.0
Description
Added storage temperature, TSTG spec. (DOC-560)
Updated maximum JTAG mode TCK frequency, fTCK.
(DOC-574)
Updated CSI pin description. (DOC-546)
Updated tCLKH and tCLKL, and corrected SPI Passive Mode (x1)
Timing Sequence waveform. (DOC-590)
Updated minimum Power Supply Ramp Rates. (DOC-631)
Updated Maximum Toggle Rate table. (DOC-630)
September 2021
2.10
Added Single-Ended I/O Rise and Fall Time specs. (DOC-522)
Added note to Active mode configuration clock frequency
stating that for parallel daisy chain x2 and x4 configuration,
fMAX_M, must be set to DIV4. (DOC-528)
Added Maximum tUSER for SPI Active and Passive Modes
topic. (DOC-535)
August 2021
2.9
Removed Static Supply Current parameter. (DOC-456)
Added internal weak pull-up and pull-down resistor specs.
(DOC-485)
Added note in Pinout Description stating all dedicated
configuration pins have Schmitt Trigger buffer. (DOC-507)
Updated table title for Single-Ended I/O Schmitt Trigger
Buffer Characteristic. (DOC-507)
June 2021
2.8
Updated CRESET_N pin description. (DOC-450)
April 2021
2.7
Updated PLL specs; tILJIT (PK - PK) and tDT. (DOC-403)
March 2021
2.6
The simple PLL output is negative edge aligned. (DOC-400)
February 2021
2.5
Added I/O input voltage, VIN specification. (DOC-389)
December 2020
2.4
Updated NSTATUS pin description. (DOC-335)
Added a table to Power Up Sequence topic describing pin
connection when PLL or GPIO is not used. (DOC-325)
Updated fMAX_S for passive configuration modes. (DOC-350)
September 2020
2.3
Updated pinout links.
August 2020
2.2
Removed typical standby (low power [LP] option) from static
supply current table and updated typical standby value.
Updated tUSER timing parameter values and added a note
about the conditions for the values.
Updated description for GPIO pins state during
configuration.
Added operating junction temperature for industrial speed
grade.
Updated block RAM and multiplier block maximum
frequencies to include I2 speed grade.
Added maximum power supply current transient during
power-up.
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T4 Data Sheet
Date
July 2020
Version
2.1
Description
Updated the term DSP to multiplier.
Updated timing parameter symbols in boundary scan timing
waveform to reflect JTAG mode parameter symbols.
Added supported GPIO features.
Updated power up sequence description about holding
CRESET_N low.
Updated PLLCLK pin name to PLL_CLKIN.
February 2020
2.0
Added fMAX for DSP blocks and RAM blocks.
Added Trion power-up sequence.
Updated number of global clocks and controls that can come
from GPIO pins in package resources table.
December 2019
1.9
Removed DIV1 and DIV2 active mode configuration
frequencies; they are not supported.
October 2019
1.8
Added waveforms for configuration timing.
August 2019
1.7
Removed ESD table and added link to Trion Reliability Report.
February 2019
1.6
Removed incorrect footnote about LVDS under Available
Package Options.
November 2018
1.5
Updated PLL interface description.
Minor formatting changes.
Added floorplan information.
Updated configuraiton timing and PLL timing information.
August 2018
1.4
Updated configuration pin table.
August 2018
1.3
Updated standby current specifications.
July 2018
1.2
•
•
May 2018
1.1
Added ordering code information.
April 2018
1.0
Initial release.
Renamed RST PLL pin as RSTN.
Updated ordering codes.
Updated the PLL timing specification to add FPFD.
Clarified the slew rate description.
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