Advance Information
MC9328MX1/D
Rev. 3.0, 12/2003
MC9328MX1
(i.MX1) Integrated
Portable System
Processor
Contents
1 Introduction . . . . . . . . . . . 1
2 Signals and
Connections . . . . . . . . . . 5
3 Specifications . . . . . . . . 13
4 Pin-Out and Package
Information . . . . . . . . . . 91
Contact Information
. . . . . . . . . . . . . .Last Page
1 Introduction
Motorola’s i.MX family of microprocessors has demonstrated leadership in the portable
handheld market. Continuing this legacy, the i.MX series provides a leap in performance
with an ARM9™ microprocessor core and highly integrated system functions. The i.MX
products specifically address the requirements of the personal, portable product market by
providing intelligent integrated peripherals, an advanced processor core, and power
management capabilities.
The new MC9328MX1 features the advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller,
static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD
host controller, support a suite of peripherals to enhance any product seeking to provide a
rich multimedia experience. In addition, the MC9328MX1 is the first Bluetooth™
technology-ready applications processor. It is packaged in a 256-pin Mold Array ProcessBall Grid Array (MAPBGA). Figure 1 on page 1 shows the functional block diagram of the
MC9328MX1.
System Control
JTAG/ICE
Bootstrap
Power
Control
CGM
(DPLLx2)
Standard
System I/O
GPIO
Connectivity
PWM
MC9328MX1
MMC/SD
RTC
ARM9TDMI™
SPI 1 and
SPI 2
UART 1
Timer 1 & 2
CPU Complex
Memory Stick®
Host Controller
Watchdog
D Cache
I Cache
UART 2 & 3
SSI/I2S 1 & 2
AIPI 1
Interrupt
Controller
VMMU
Multimedia
Multimedia
Accelerator
Video Port
I2C
USB Device
AIPI 2
DMAC
(11 Chnl)
Bus
Control
SmartCard I/F
Bluetooth
Accelerator
EIM &
SDRAMC
eSRAM
(128K)
Human Interface
Analog Signal
Processor
LCD Controller
Figure 1. MC9328MX1 Functional Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change
without notice. © Motorola, Inc., 2003. All rights reserved.
Introduction
1.1 Conventions
This document uses the following conventions:
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•
Logic level one is a voltage that corresponds to Boolean true (1) state.
•
Logic level zero is a voltage that corresponds to Boolean false (0) state.
•
To set a bit or bits means to establish logic level one.
•
To clear a bit or bits means to establish logic level zero.
•
A signal is an electronic construct whose state conveys or changes in state convey information.
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
•
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
•
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
•
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
1.2 Features
To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including
the following:
2
•
ARM920T Microprocessor Core
•
AHB to IP Bus Interfaces (AIPIs)
•
External Interface Module (EIM)
•
SDRAM Controller (SDRAMC)
•
DPLL Clock and Power Control Module
•
Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3)
•
Two Serial Peripheral Interfaces (SPI)
•
Two General-Purpose 32-bit Counters/Timers
•
Watchdog Timer
•
Real-Time Clock/Sampling Timer (RTC)
•
LCD Controller (LCDC)
•
Pulse-Width Modulation (PWM) Module
•
Universal Serial Bus (USB) Device
•
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
•
Memory Stick® Host Controller (MSHC)
MC9328MX1 Advance Information
MOTOROLA
Introduction
•
SmartCard Interface Module (SIM)
•
Direct Memory Access Controller (DMAC)
•
Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I2S) Module
•
Inter-IC (I2C) Bus Module
•
Video Port
•
General-Purpose I/O (GPIO) Ports
•
Bootstrap Mode
•
Analog Signal Processing (ASP) Module
•
Bluetooth Accelerator (BTA)
•
Multimedia Accelerator (MMA)
•
256-pin MAPBGA Package
1.3 Target Applications
The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital
MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging
applications such as Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS
interactive communicator.
1.4 Document Revision History
The following table provides revision history for this release. This history includes technical content
revisions only and not stylistic or grammatical changes.
Table 1. MC9328MX1 Data Sheet Revision History Rev. 3.0
Revision Location
Revision
Throughout data sheet
Changed all references to USB from self-powered only to self-powered
and bus-powered.
Changed all references to DragonBall to i.MX.
SDRAM timing in
Section 3.17, “SDRAM Memory
Controller,” on page 71
SDRAM clock cycle time changed from 11.4 ns to 10.4 ns at 1.8V in all
three tables.
Maximum ratings Table 4 on page 13
Change to maximum operation temperature range from 70°C to 85°C in
table and throughout data sheet.
32 k/16 MHz Osc signal timing.
Table 8 on page 15
Changed EXTAL32k input jitter (peak to peak) data/
Section Section 3.8.2, “DTACK Signal
Timing,” on page 23
Updated DTACK waveform and timing tables and figures.
Signals Table 3
Corrected MS_CLKI and MS_CLKO pin descriptions.
Removed descriptions of SVDD and SGND.
Section 3.8.3, “EIM External Bus
Timing,” on page 28
Clarified signal naming on all waveform diagrams
Specification updates
Max temperature ratings and part numbers were updated.
MOTOROLA
MC9328MX1 Advance Information
3
Introduction
1.5 Product Documentation
The following documents are required for a complete description of the MC9328MX1 and are necessary to
design properly with the device. Especially for those not familiar with the ARM920T processor or
previous DragonBall products, the following documents are helpful when used in conjunction with this
manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MX1 Product Brief (order number MC9328MX1P/D)
MC9328MX1S Reference Manual (order number MC9328MX1SRM/D)
MC68VZ328 Product Brief (order number MC68VZ328P/D)
MC68VZ328 User’s Manual (order number MC68VZ328UM/D)
MC68VZ328 User’s Manual Addendum (order number MC68VZ328UMAD/D)
MC68SZ328 Product Brief (order number MC68SZ328P/D)
MC68SZ328 User’s Manual (order number MC68SZ328UM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at http://
www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola
Web site, or printed versions may be ordered. The ARM documentation is available from
http://www.arm.com.
1.6 Ordering Information
Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA)
package.
Table 2. MC9328MX1 Ordering Information
4
Package Type
Frequency
Temperature
Solderball Type
Order Number
256-lead MAPBGA
200 MHz
0°C to 70°C
Standard
MC9328MX1VH20(R2)
256-lead MAPBGA
200 MHz
0°C to 70°C
Pb-free
MC9328MX1VM20(R2)
256-lead MAPBGA
200 MHz
-30°C to 70°C
Standard
MC9328MX1DVH20(R2)
256-lead MAPBGA
200 MHz
-30°C to 70°C
Pb-free
MC9328MX1DVM20(R2)
256-lead MAPBGA
150 MHz
-40°C to 85°C
Standard
MC9328MX1CVH15(R2)
256-lead MAPBGA
150 MHz
-40°C to 85°C
Pb-free
MC9328MX1CVM15(R2)
MC9328MX1 Advance Information
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Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [24:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE
Memory Output Enable—Active low output enables external data bus
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are
selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is
selected.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must
terminate an on-going burst sequence and initiate a new (long first access) burst
sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting
burst address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst
mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used
as a WE input signal by external DRAM.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon
system reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A
[15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/
SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address
signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in
SDRAM/SyncFlash cycles.
MA [11:10]
SDRAM address signals
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MC9328MX1 Advance Information
5
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
MA [9:0]
SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are
selected on SDRAM/SyncFlash cycles.
DQM [3:0]
SDRAM data enable
CSD0
SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two
signals are selectable by programming the system control register.
CSD1
SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two
signals are selectable by programming the system control register. By default, CSD1 is
selected, so it can be used as SyncFlash boot chip select by properly configuring BOOT
[3:0] input pins.
RAS
SDRAM/SyncFlash Row Address Select signal
CAS
SDRAM/SyncFlash Column Address Select signal
SDWE
SDRAM/SyncFlash Write Enable signal
SDCKE0
SDRAM/SyncFlash Clock Enable 0
SDCKE1
SDRAM/SyncFlash Clock Enable 1
SDCLK
SDRAM/SyncFlash Clock
RESET_SF
SyncFlash Reset
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit
is shut down.
XTAL16M
Crystal output
EXTAL32K
32 kHz crystal input
XTAL32K
32 kHz crystal output
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for
internal clock selection.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes
active, all modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is
asserted from the following sources: Power-on reset, External reset (RESET_IN), and
Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is
normally generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG
controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
6
MC9328MX1 Advance Information
MOTOROLA
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the
rising edge of TCK.
System
BIG_ENDIAN
BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is
a static pin to inner module. If the pin is driven logic-high the memory system is configured
into big endian. If it is driven logic-low the memory system is configured into little endian.
The pin is not supposed to be changed on the fly.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM
mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM
mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in
ETM mode.
ETMTRACEPKT [7:0]
ETM packet signals which are multiplex with ECB, LBA, BCLK, PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for gate.
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line Pulse or H Sync
LSCLK
Shift Clock
ACD/OE
Alternate Crystal Direction/Output Enable
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
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MC9328MX1 Advance Information
7
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
PS
Control signal output for source driver (Sharp panel dedicated signal).
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel
dedicated signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SIM
SIM_CLK
SIM Clock
SIM_RST
SIM Reset
SIM_RX
Receive Data
SIM_TX
Transmit Data
SIM_PD
Presence Detect Schmitt trigger input
SIM_SVEN
SIM Vdd Enable
SPI
SPI1_MOSI
Master Out/Slave In
SPI1_MISO
Slave In/Master Out
SPI1_SS
Slave Select (Selectable polarity)
SPI1_SCLK
Serial Clock
SPI1_SPI_RDY
Serial Data Ready
SPI2_TXD
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin however it does
show up as a primary or alternative signal in the signal multiplex scheme table. Refer to
Chapter 16, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29,
“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to
the assigned pin.
SPI2_RXD
SPI2 master RxData input—This signal is multiplexed with a GPI/O pin however it does
show up as a primary or alternative signal in the signal multiplex scheme table. Refer to
Chapter 16, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29,
“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to
the assigned pin.
SPI2_SS
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin, however it does show up
as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16,
“Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module
and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned
pin.
SPI2_SCLK
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin however it does show up as
a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16,
“Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module
and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned
pin.
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MOTOROLA
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USB Minus Output
USBD_VPO
USB Plus Output
USBD_VM
USB Minus Input
USBD_VP
USB Plus Input
USBD_SUSPND
USB Suspend Output
USBD_RCV
USB RxD
USBD_OE
USB OE
USBD_AFE
USB Analog Front End Enable
Secure Digital Interface
SD_CMD
SD Command—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK
MMC Output Clock
SD_DAT [3:0]
Data—If the system designer does not want to make use of the internal pull-up, via the
Pull-up enable register, a 50 K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
MS_SDIO
Memory Stick Serial Data (Input/Output)
MS_SCLKO
Memory Stick Serial Clock (Output)—Serial Protocol clock output
MS_SCLKI
Memory Stick External Clock (Input)—Test clock input pin for SCLK divider. This pin is
only for test purposes, not for use in application mode.
MS_PI0
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
MS_PI1
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD
Receive Data
UART1_TXD
Transmit Data
MOTOROLA
MC9328MX1 Advance Information
9
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
UART1_RTS
Request to Send
UART1_CTS
Clear to Send
UART2_RXD
Receive Data
UART2_TXD
Transmit Data
UART2_RTS
Request to Send
UART2_CTS
Clear to Send
UART2_DSR
Data Set Ready
UART2_RI
Ring Indicator
UART2_DCD
Data Carrier Detect
UART2_DTR
Data Terminal Ready
UART3_RXD
Receive Data
UART3_TXD
Transmit Data
UART3_RTS
Request to Send
UART3_CTS
Clear to Send
UART3_DSR
Data Set Ready
UART3_RI
Ring Indicator
UART3_DCD
Data Carrier Detect
UART3_DTR
Data Terminal Ready
Serial Audio Ports – SSI (configurable to I2S protocol)
SSI1_TXDAT
TxD
SSI1_RXDAT
RxD
SSI1_TXCLK
Transmit Serial Clock
SSI1_RXCLK
Receive Serial Clock
SSI1_TXFS
Transmit Frame Sync
SSI1_RXFS
Receive Frame Sync
SSI2_TXDAT
TxD
SSI2_RXDAT
RxD
SSI2_TXCLK
Transmit Serial Clock
SSI2_RXCLK
Receive Serial Clock
10
MC9328MX1 Advance Information
MOTOROLA
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
SSI2_TXFS
Transmit Frame Sync
SSI2_RXFS
Receive Frame Sync
I2C
I2C_SCL
I2C Clock
I2C_SDA
I2C Data
PWM
PWMO
PWM Output
ASP
UIN
Positive U analog input (for low voltage, temperature measurement)
UIP
Negative U analog input (for low voltage, temperature measurement)
PX1
Positive pen-X analog input
PY1
Positive pen-Y analog input
PX2
Negative pen-X analog input
PY2
Negative pen-Y analog input
R1A
Positive resistance input (a)
R1B
Positive resistance input (b)
R2A
Negative resistance input (a)
R2B
Negative resistance input (b)
RVP
Positive reference for pen ADC
RVM
Negative reference for pen ADC
AVDD
Analog power supply
AGND
Analog ground
BlueTooth
BT1
I/O clock signal
BT2
Output
BT3
Input
BT4
Input
BT5
Output
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MC9328MX1 Advance Information
11
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
BT6
Output
BT7
Output
BT8
Output
BT9
Output
BT10
Output
BT11
Output
BT12
Output
BT13
Output
TRISTATE
Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal
operations.
BTRF VDD
Power supply from external BT RFIC
BTRF GND
Ground from external BT RFIC
Noisy Supply Pins
NVDD
Noisy Supply for the I/O pins
NVSS
Noisy Ground for the I/O pins
Supply Pins – Analog Modules
AVDD
Supply for analog blocks
AVSS
Quiet GND for analog blocks
Internal Power Supply
QVDD
Power supply pins for silicon internal circuitry
QVSS
GND pins for silicon internal circuitry
12
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Specifications
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings.
Table 4. Maximum Ratings
Rating
Symbol
Minimum
Maximum
Unit
Supply voltage
Vdd
-0.3
3.3
V
Maximum operating temperature range
MC9328MX1VH20/MC9328MX1VM20
TA
0
70
°C
Maximum operating temperature range
MC9328MX1DVH20/MC9328MX1DVM20
TA
-30
70
°C
Maximum operating temperature range
MC9328MX1CVH15/MC9328MX1CVM15
TA
-40
85
°C
ESD at human body model (HBM)
VESD_HBM
–
2000
V
ESD at machine model (MM)
VESD_MM
–
100
V
ILatchup
–
200
mA
Storage temperature
Test
-55
150
°C
Power Consumption
Pmax
8001
13002
mW
Latch-up current
1.
2.
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction
fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and
instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These
calculations are based on the core running its heaviest OS application at 200MHz, and where the whole
image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst
measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle
GPIO consuming 4mA.
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor
has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for
internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and
VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels
in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data
transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used
in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as
other NVDD pins.
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MC9328MX1 Advance Information
13
Specifications
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5.
Table 5. Recommended Operating Range
Rating
Symbol
Minimum
Maximum
Unit
I/O supply voltage, MSHC, SPI, BTA, USBd, LCD and CSI are
only 3V interface
NVDD
2.70
3.30
V
I/O supply voltage
NVDD
1.70
3.30
V
Internal supply voltage (Core = 150 MHz)
QVDD
1.70
1.90
V
Internal supply voltage (Core = 200 MHz)
QVDD
1.80
2.00
V
Analog supply voltage
AVDD
1.70
3.30
V
Bluetooth I/O voltage (Bluetooth)
BTRFVDD1
1.70
3.10
V
Bluetooth I/O voltage (Non Bluetooth applications)
BTRFVDD2
1.70
3.30
V
3.3 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1.
Table 6. Maximum and Minimum DC Characteristics
Number
or Symbol
Parameter
Minimum
Typical
Maximum
Unit
Full running operating current at 1.8V
for QVDD, 3.3V for NVDD/AVDD (Core
= 96 MHz, System = 96 MHz, MPEG4
decoding playback from external
memory card to both external SSI
audio decoder and TFT display panel,
and OS with MMU enabled memory
system is running on external SDRAM)
Please refer to application note:
AN2537, Power Performance of
MC9328MX1.
–
QVDD at 1.8v
= 120mA; NVDD+AVDD
at 3.0v = 30mA
–
mA
Sidd1
Standby current (QVDD = 1.8V,
temp = 25°C)
–
25
–
µA
Sidd2
Standby current (QVDD = 1.8V,
temp = 55°C)
–
45
–
µA
Sidd3
Standby current (QVDD = 2.0V,
temp = 25°C)
–
35
–
µA
Sidd4
Standby current (QVDD = 2.0V,
temp = 55°C)
–
60
–
µA
Iop
14
VIH
Input high voltage
0.7VDD
–
Vdd+0.2
V
VIL
Input low voltage
–
–
0.4
V
MC9328MX1 Advance Information
MOTOROLA
Specifications
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number
or Symbol
Parameter
Minimum
Typical
Maximum
Unit
VOH
Output high voltage (IOH = 2.0 mA)
0.7VDD
–
Vdd
V
VOL
Output low voltage (IOL = -2.5 mA)
–
–
0.4
V
Vit+
Positive input threshold voltage,
Vi =Vih
–
–
1.126
V
Vit-
Negative input threshold voltage,
Vi =Vil
0.640
–
–
V
–
0.3
–
–
Vhys
Hysteresis (Vit+ − Vit-) = Vih
IIL
Input low leakage current
(VIN = GND, no pull-up or pull-down)
–
–
±1
µA
IIH
Input high leakage current
(VIN = VDD, no pull-up or pull-down)
–
–
±1
µA
IOH
Output high current
(VOH = 0.8VDD, VDD = 1.8V)
–
–
4.0
mA
IOL
Output low current
(VOL = 0.4V, VDD = 1.8V)
−4.0
–
–
mA
IOZ
Output leakage current
(Vout = VDD, output is tri-stated)
–
–
±5
µA
Ci
Input capacitance
–
–
5
pF
Co
Output capacitance
–
–
5
pF
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an
operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All
timing is measured at 30 pF loading.
Table 7. Tri-State Signal Timing
Pin
TRISTATE
Parameter
Minimum
Maximum
Unit
–
20.8
ns
Time from TRISTATE activate until I/O becomes Hi-Z
Table 8. 32k/16M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak) for both System PLL and
MCUPLL
–
5
20
ns
MOTOROLA
MC9328MX1 Advance Information
15
Specifications
Table 8. 32k/16M Oscillator Signal Timing (Continued)
Parameter
EXTAL32k input jitter (peak to peak) for MCUPLL only
EXTAL32k startup time
EXTAL16M input jitter (peak to peak)
EXTAL16M startup time
Minimum
RMS
Maximum
Unit
–
5
100
ns
800
–
–
ms
–
TBD
TBD
–
TBD
–
–
–
Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
16
Best
Case
Typical
Worst
Case
Units
Rise Time
0.80
1.00
1.40
ns
Fall Time
0.74
1.08
1.67
ns
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.5 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
•
32-bit data field
•
7-bit address field
•
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 10 on page 17 for the ETM9 timing
parameters used in Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Valid Data
Output Trace Port
Valid Data
4a
4b
Figure 2. Trace Port Timing Diagram
Table 10. Trace Port Timing Diagram Parameter Table
1.8V +/- 0.10V
Ref No.
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
0
85
0
100
MHz
2a
Clock high time
1.3
–
2
–
ns
2b
Clock low time
3
–
2
–
ns
3a
Clock rise time
–
4
–
3
ns
3b
Clock fall time
–
3
–
3
ns
4a
Output hold time
2.28
–
2
–
ns
4b
Output setup time
3.42
–
3
–
ns
MOTOROLA
MC9328MX1 Advance Information
17
Specifications
3.6 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 11. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock freq range
Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
Double clock freq range
Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5
–
15
–
MF
integer part
–
5
–
15
–
MF
numerator
Should be less than the
denominator
0
–
1022
–
MF
denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
µsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-must lock-in
time)
250
280
(56 µs)
300
Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
220
250
(~50 µs)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
300
350
(70 µs)
400
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
270
320
(64 µs)
370
Tref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2•Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
–
–
4
mW
18
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.7 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4. Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent
forward biasing.
90% AVDD
1
Could be adjust due to 32kHz
POR
10% AVDD
Crystal start-up time
2
Exact 300ms
RESET_POR
3
7 cycles @ CLK32
RESET_DRAM
4
14 cycles @ CLK32
HRESET
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
5
RESET_IN
14 cycles @ CLK32
HRESET
4
RESET_OUT
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
MOTOROLA
MC9328MX1 Advance Information
19
Specifications
Table 12. Reset Module Timing Parameter Table
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Min
Max
Min
Max
Parameter
Unit
1
Width of input POWER_ON_RESET 1
800
–
800
–
ns
2
Width of internal POWER_ON_RESET
(9600 *CLK32 at 32 KHz)
300
300
300
300
ms
3
7K to 32K-cycle stretcher for SDRAM reset
7
7
7
7
Cycles of
CLK32
4
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
14
14
14
14
Cycles of
CLK32
5
Width of external hard-reset RESET_IN
4
–
4
–
Cycles of
CLK32
6
4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
1 Timing waveforms shown are dependent on crystal start-up time. If a stable clock source is used instead of
a crystal, the width of the POR should be ignored in calculating timing for the startup process.
20
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.8 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1,
including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM
is shown in Figure 5, and Table 13 defines the parameters of signals.
(HCLK) Bus Clock
1a
1b
2a
2b
3a
3b
Address
Chip-select
Read (Write)
4a
OE (rising edge)
4b
4c
OE (falling edge)
4d
5a
EB (rising edge)
5b
5c
EB (falling edge)
5d
6a
LBA (negated falling edge)
6b
6a
LBA (negated rising edge)
6c
7a
Burst Clock (rising edge)
7b
7c
7d
Burst Clock (falling edge)
8b
Read Data
9a
8a
9b
Write Data (negated falling)
9a
9c
Write Data (negated rising)
10a
DTACK_B
10a
Figure 5. EIM Bus Timing Diagram
Table 13. EIM Bus Timing Parameter Table
1.8 ± 0.10V
Ref No.
3.0 ± 0.3V
Unit
Parameter
Min
Typical
Max
Min
Typical
Max
1a
Clock fall to address valid
2.48
3.31
9.11
2.4
3.2
8.8
ns
1b
Clock fall to address invalid
1.55
2.48
5.69
1.5
2.4
5.5
ns
MOTOROLA
MC9328MX1 Advance Information
21
Specifications
Table 13. EIM Bus Timing Parameter Table (Continued)
1.8 ± 0.10V
Ref No.
Unit
Min
Typical
Max
Min
Typical
Max
2a
Clock fall to chip-select valid
2.69
3.31
7.87
2.6
3.2
7.6
ns
2b
Clock fall to chip-select invalid
1.55
2.48
6.31
1.5
2.4
6.1
ns
3a
Clock fall to Read (Write) Valid
1.35
2.79
6.52
1.3
2.7
6.3
ns
3b
Clock fall to Read (Write) Invalid
1.86
2.59
6.11
1.8
2.5
5.9
ns
4a
Clock1 rise to Output Enable Valid
2.32
2.62
6.85
2.3
2.6
6.8
ns
4b
Clock1 rise to Output Enable Invalid
2.11
2.52
6.55
2.1
2.5
6.5
ns
4c
Clock1 fall to Output Enable Valid
2.38
2.69
7.04
2.3
2.6
6.8
ns
4d
Clock1 fall to Output Enable Invalid
2.17
2.59
6.73
2.1
2.5
6.5
ns
5a
Clock1 rise to Enable Bytes Valid
1.91
2.52
5.54
1.9
2.5
5.5
ns
5b
Clock1 rise to Enable Bytes Invalid
1.81
2.42
5.24
1.8
2.4
5.2
ns
5c
Clock1 fall to Enable Bytes Valid
1.97
2.59
5.69
1.9
2.5
5.5
ns
5d
Clock1 fall to Enable Bytes Invalid
1.76
2.48
5.38
1.7
2.4
5.2
ns
6a
Clock1 fall to Load Burst Address Valid
2.07
2.79
6.73
2.0
2.7
6.5
ns
6b
Clock1 fall to Load Burst Address Invalid
1.97
2.79
6.83
1.9
2.7
6.6
ns
6c
Clock1 rise to Load Burst Address Invalid
1.91
2.62
6.45
1.9
2.6
6.4
ns
7a
Clock1 rise to Burst Clock rise
1.61
2.62
5.64
1.6
2.6
5.6
ns
7b
Clock1rise to Burst Clock fall
1.61
2.62
5.84
1.6
2.6
5.8
ns
7c
Clock1 fall to Burst Clock rise
1.55
2.48
5.59
1.5
2.4
5.4
ns
7d
Clock1 fall to Burst Clock fall
1.55
2.59
5.80
1.5
2.5
5.6
ns
8a
Read Data setup time
5.54
–
–
5.5
–
–
ns
8b
Read Data hold time
0
–
–
0
–
–
ns
9a
Clock1 rise to Write Data Valid
1.81
2.72
6.85
1.8
2.7
6.8
ns
9b
Clock1 fall to Write Data Invalid
1.45
2.48
5.69
1.4
2.4
5.5
ns
9c
Clock1 rise to Write Data Invalid
1.63
–
–
1.62
–
–
ns
DTACK setup time
2.52
–
–
2.5
–
–
ns
10a
1.
22
3.0 ± 0.3V
Parameter
Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.8.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only CS5 group supports
DTACK signal function when using the external DTACK signal for data acknowledgement.
3.8.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
3.8.2.1 DTACK READ Cycle without DMA
(3)
Address
(2)
(8)
CS5
(1)
EB
(9)
programmable
min 0ns
(5)
OE
(4)
DTACK
(6)
(10)
Databus
(input to MX1)
(7)
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
See note 2
–
ns
3T
–
ns
46.44
–
ns
–
1019T
ns
1
OE and EB assertion time
2
CS5 pulse width
3
OE negated to address inactive
4
DTACK asserted after CS5 asserted
5
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
–
ns
MOTOROLA
MC9328MX1 Advance Information
23
Specifications
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
0
T
ns
0.5T+0.24
0.5T+0.67
ns
7
Data ready after DTACK asserted
8
OE negated to CS negated
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.8.2.2 DTACK Read Cycle DMA Enabled
(4)
Address
(2)
(9)
CS5
(1)
EB
(10)
programmable
min 0ns
(3)
(6)
OE
RW (logic high)
(5)
DTACK
(7)
Databus
(input to MX1)
(11)
(8)
Figure 7. DTACK Read Cycle DMA Enabled
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 ± 0.3) V
Number
1
24
Unit
Characteristic
OE and EB assertion time
Minimum
Maximum
See note 2
–
MC9328MX1 Advance Information
ns
MOTOROLA
Specifications
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
3T
–
ns
2
CS pulse width
3
OE negated before CS5 is negated
0.5T+0.24
0.5T+0.67
ns
4
Address inactive before CS negated
–
0.93
ns
5
DTACK asserted after CS5 asserted
–
1019T
ns
6
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
7
Data hold timing after OE negated
0
–
ns
8
Data ready after DTACK is asserted
–
T
ns
9
CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.5
1.5
ns
11
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only
when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MOTOROLA
MC9328MX1 Advance Information
25
Specifications
3.8.2.3 DTACK Write Cycle without DMA
(5)
Address
(1)
CS5
(2)
EB
(3)
programmable
min 0ns
(10)
programmable
min 0ns
(4)
(7)
RW
(6)
OE (logic high)
DTACK
(9)
(11)
Databus
(output from MX1)
(8)
Figure 8. DTACK Write Cycle without DMA
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
1
CS5 assertion time
See note 2.
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
RW negated to Address inactive
57.31
–
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated before CS5 is negated
0.5T+0.74
0.5T+2.17
ns
11
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
26
MC9328MX1 Advance Information
MOTOROLA
Specifications
3.8.2.4 DTACK Write Cycle DMA Enabled
(5)
Address
(1)
CS5
(2)
EB
(3)
(10)
programmable
min 0ns
(11)
programmable
min 0ns
(4)
(7)
RW
(6)
OE (logic high)
DTACK
(9)
(12)
Databus
(output from MX1)
(8)
Figure 9. DTACK Write Cycle DMA Enabled
Table 17. WSC = Parameters for Write Cycle 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
Address inactive before CS negated
–
0.93
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate to CS negate
0.5T+0.74
0.5T+2.17
ns
12
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MOTOROLA
MC9328MX1 Advance Information
27
Specifications
3.8.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Seq/Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1
weim_hready
BCLK
ADDR
Last Valid Address
V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
28
MC9328MX1 Advance Information
MOTOROLA
Specifications
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
weim_hrdata
Write Data (V1)
Unknown
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Address
V1
CS0
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MOTOROLA
MC9328MX1 Advance Information
29
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS0
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
30
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS0
R/W
Write
LBA
OE
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
31
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS[3]
R/W
Read
BA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
32
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS3
Write
R/W
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
33
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
34
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
35
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
36
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
V1 Word
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
37
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Unknown
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
38
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Unknown
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
39
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
40
MC9328MX1 Advance Information
MOTOROLA
Specifications
Read
Idle
Write
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Write Data
Last Valid Data
Last Valid Data
Read Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MOTOROLA
MC9328MX1 Advance Information
41
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
42
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V8
CS4
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MOTOROLA
MC9328MX1 Advance Information
43
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Read
haddr
V1
V2
Idle
Seq
hready
weim_hrdata
Last Valid Data
Read Data (V1)
Read Data (V2)
weim_hready
BCLK
ADDR
Last Valid
Address V1
Address V2
CNC
CS4
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Read Data
(V1)
Read Data
(V2)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
44
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Write
haddr
V1
V8
Idle
Nonseq
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
bclk
ADDR
Last Valid Addr
Address V1
Address V8
CNC
CS4
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MOTOROLA
MC9328MX1 Advance Information
45
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonse
hwrite
Read
Read
haddr
V1
V5
Idle
hready
weim_hrdata
weim_hready
BCLK
ADDR
Last Valid Addr
Address V1
Address V5
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V5 Word
V6 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
46
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
Seq
Seq
hwrite
Read
Read
Read
Read
haddr
V1
V2
V3
V4
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
weim_hready
BCLK
ADDR Last Valid Addr
Address V1
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MOTOROLA
MC9328MX1 Advance Information
47
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK
ADDR
Last Valid
Address V1
Address V2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
48
MC9328MX1 Advance Information
MOTOROLA
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MOTOROLA
MC9328MX1 Advance Information
49
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
50
MC9328MX1 Advance Information
MOTOROLA
Specifications
LSCLK
LD[15:0]
1
Figure 33. SCLK to LD Timing Diagram
Table 18. LCDC SCLK Timing
3.0 +/- 0.3V
Num
1
Characteristic
SCLK to LD valid
Minimum
Maximum
–
3
Unit
ns
3.8.4 Non-TFT Panel Timing
T1
T1
VSYN
T3
T2
T4
XMAX
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 34. Non-TFT Panel Timing
Table 19.
Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register Minimum
Value
Actual Value
Unit
T1
HSYN to VSYN delay
0
HWAIT2+2
Tpix
T2
HSYN pulse width
0
HWIDTH+1
Tpix
T3
VSYN to SCLK
–
0 max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.21.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 71 on page 89 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 43 on page 89.
1
VSYNC
6
4
5
PIXCLK
DATA[7:0]
Valid Data
2
Valid Data
Valid Data
3
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
88
MC9328MX1 Advance Information
MOTOROLA
Specifications
1
VSYNC
6
4
5
PIXCLK
Valid Data
DATA[7:0]
2
Valid Data
Valid Data
3
Figure 71. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 43. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Minimum
Maximum
Unit
9 * THCLK
–
ns
1
csi_vsync to csi_pixclk
2
csi_d setup time
1
–
ns
3
csi_d hold time
1
–
ns
4
csi_pixclk high time
10.42
–
ns
5
csi_pixclk low time
10.42
–
ns
6
csi_pixclk frequency
0
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
MOTOROLA
MC9328MX1 Advance Information
89
Specifications
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
90
MC9328MX1 Advance Information
MOTOROLA
MOTOROLA
4 Pin-Out and Package Information
Table 44. MC9328MX1 BGA Pin Assignments
2
3
A
VS
S
SD_D
AT3
SD_C
LK
B
A2
4
SD_D
AT1
C
A2
3
D
4
5
6
VSS
USBD_
AFE
NVDD
4
SD_C
MD
SIM_T
X
USBD_
OE
D31
SD_D
AT0
SIM_P
D
A2
2
D30
D29
E
A2
0
A21
F
A1
8
G
7
8
9
10
11
12
13
14
15
16
VSS
UART
1_RT
S
UART
1_RX
D
NVDD
3
BT5
BT3
QVDD
4
RVP
UIP
NC
USBD
_VP
SSI_R
XCLK
SSI_T
XCLK
SPI1_
SCLK
BT11
BT7
BT1
VSS
RVM
UIN
NC
USBD_
RCV
UART
2_CT
S
UART
2_RX
D
SSI_R
XFS
UART
1_TX
D
BTRF
GND
BT8
BTRFV
DD
NC
AVDD
2
VSS
R1B
SIM_S
VEN
USBD_
SUSPN
D
USBD
_VPO
USBD
_VMO
SSI_R
XDAT
SPI1_
SPI_R
DY
BT13
BT6
NC
NC
NC
R1A
R2B
D28
D26
SD_DA
T2
USBD
_VM
UART
2_RT
S
SSI_T
XDAT
SPI1_
SS
BT12
BT4
NC
NC
PY2
PX2
R2A
D27
D25
A19
A16
SIM_R
ST
UART
2_TX
D
SSI_T
XFS
SPI1_
MISO
BT10
BT2
REV
PY1
PX1
LSCLK
SPL_
SPR
A1
5
A17
D24
D23
D21
SIM_R
X
SIM_C
LK
UART
1_CT
S
SPI1_
MOSI
BT9
CLS
CONTR
AST
ACD/
OE
LP/
HSYN
C
FLM/
VSYNC
LD1
H
A1
3
D22
A14
D20
NVDD1
NVDD
1
VSS
VSS
QVDD
1
PS
LD0
LD2
LD4
LD5
LD9
LD3
J
A1
2
A11
D18
D19
NVDD1
NVDD
1
VSS
NVDD
1
VSS
VSS
LD6
LD7
LD8
LD11
QVDD3
VSS
K
A1
0
D16
A9
D17
NVDD1
VSS
VSS
NVDD
1
NVDD
2
NVDD
2
LD10
LD12
LD13
LD14
TMR2O
UT
LD15
91
Pin-Out and Package Information
MC9328MX1 Advance Information
1
92
Table 44. MC9328MX1 BGA Pin Assignments (Continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MC9328MX1 Advance Information
L
A8
A7
D13
D15
D14
NVDD
1
VSS
CAS
TCK
TIN
PWM
O
CSI_M
CLK
CSI_D
0
CSI_D
1
CSI_D2
CSI_D
3
M
A5
D12
D11
A6
SDCLK
VSS
RW
MA10
RAS
RESE
T_IN
BIG_E
NDIA
N
CSI_D4
CSI_H
SYNC
CSI_V
SYNC
CSI_D6
CSI_D
5
N
A4
EB1
D10
D7
A0
D4
PA17
D1
DQM1
RESE
T_SF
RESE
T_OU
T
BOOT2
CSI_P
IXCLK
CSI_D
7
TMS
TDI
P
A3
D9
EB0
CS3
D6
ECB
D2
D3
DQM3
SDCK
E1
BOOT
3
BOOT0
TRST
I2C_S
CL
I2C_SD
A
XTAL
32K
R
EB
2
EB3
A1
CS4
D8
D5
LBA
BCLK
D0
DQM0
SDCK
E0
POR
BOOT
1
TDO
QVDD2
EXTA
L32K
T
VS
S
A2
OE
CS5
CS2
CS1
CS0
MA11
DQM2
SDWE
CLKO
AVDD1
TRIST
ATE
EXTA
L16M
XTAL16
M
VSS
MOTOROLA
Pin-Out and Package Information
4.1 MAPBGA Package Dimensions
Figure 72 illustrates the MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing
between the pads. The device designator for the MAPBGA package is VH.
Figure 72. MC9328MX1 MAPBGA Mechanical Drawing
MOTOROLA
MC9328MX1 Advance Information
93
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USA/EUROPE/LOCATIONS NOT LISTED:
design or fabricate any integrated circuits or integrated circuits based on the information in this
Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
document.
JAPAN:
for any particular purpose, nor does Motorola assume any liability arising out of the application or
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
use of any product or circuit, and specifically disclaims any and all liability, including without
Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
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limitation consequential or incidental damages. “Typical” parameters which may be provided in
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