NANO103LD3AN

Nano103 ARM® Cortex® -M 32-bit Microcontroller NuMicro® Family Nano103 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact:Nuvoton Technology Corporation. www.nuvoton.com May. 02, 2018 Page 1 of 87 Rev 1.01 NANO103 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nano103 Table of Contents GENERAL DESCRIPTION ....................................................................... 7 1 Connectivity Support Table........................................................................... 7 1.1 2 FEATURES ......................................................................................... 8 3 ABBREVIATIONS ................................................................................ 14 4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 16 4.1 NuMicro® Nano103 Series Selection Code .......................................................16 4.2 NuMicro® Nano103 Products Selection Guide ...................................................17 4.2.1 NuMicro Nano103 Base Line Selection Guide .......................................................... 17 ® Pin Configuration......................................................................................18 4.3 4.3.1 NuMicro Nano103 Pin Diagrams .......................................................................... 18 ® Pin Description ........................................................................................21 4.4 4.4.1 NuMicro Nano103 Pin Description ........................................................................ 21 ® BLOCK DIAGRAM ............................................................................... 29 5 Nano103 Block Diagram .............................................................................29 5.1 FUNCTIONAL DESCRIPTION ................................................................. 30 6 6.1 ARM® Cortex® -M0 Core..............................................................................30 6.2 System Manager ......................................................................................32 NANO103 SERIES DATASHEET 6.2.1 Overview ....................................................................................................... 32 6.2.2 Features ........................................................................................................ 32 6.3 Clock Controller .......................................................................................33 6.3.1 Overview ....................................................................................................... 33 6.3.2 Features ........................................................................................................ 33 6.4 Flash Memory Controller (FMC) ....................................................................34 6.4.1 Overview ....................................................................................................... 34 6.4.2 Features ........................................................................................................ 34 6.5 General Purpose I/O Controller.....................................................................35 6.5.1 Overview ....................................................................................................... 35 6.5.2 Features ........................................................................................................ 35 6.6 PDMA Controller (PDMA) ...........................................................................36 6.6.1 Overview ....................................................................................................... 36 6.6.2 Features ........................................................................................................ 36 6.7 6.7.1 Timer Controller .......................................................................................38 Overview ....................................................................................................... 38 May. 02, 2018 Page 2 of 87 Rev 1.01 Nano103 6.7.2 Features ........................................................................................................ 38 PWM Generator and Capture Timer (PWM) .....................................................39 6.8 6.8.1 Overview ....................................................................................................... 39 6.8.2 Features ........................................................................................................ 39 Watchdog Timer Controller ..........................................................................41 6.9 6.9.1 Overview ....................................................................................................... 41 6.9.2 Features ........................................................................................................ 41 6.10 Window Watchdog Timer Controller ...............................................................42 6.10.1 Overview ....................................................................................................... 42 6.10.2 Features ........................................................................................................ 42 6.11 Real Time Clock (RTC) ..............................................................................43 6.11.1 Overview ....................................................................................................... 43 6.11.2 Features ........................................................................................................ 43 6.12 UART Controller ......................................................................................44 6.12.1 Overview ....................................................................................................... 44 6.12.2 Features ........................................................................................................ 44 6.13 Smart Card Host Interface (SC) ....................................................................45 6.13.1 Overview ....................................................................................................... 45 6.13.2 Features ........................................................................................................ 45 6.14 I2C Serial Interface Controller (I2C) ................................................................46 Overview ....................................................................................................... 46 6.14.2 Features ........................................................................................................ 46 6.15 SPI ......................................................................................................47 6.15.1 Overview ....................................................................................................... 47 6.15.2 Features ........................................................................................................ 47 6.16 Analog to Digital Converter (ADC) .................................................................48 6.16.1 Overview ....................................................................................................... 48 6.16.2 Features ........................................................................................................ 48 6.17 Analog Comparator Controller (ACMP0) ..........................................................49 6.17.1 Overview ....................................................................................................... 49 6.17.2 Features ........................................................................................................ 49 7 APPLICATION CIRCUIT ........................................................................ 50 8 Power COMSUMPTION ........................................................................ 51 9 ELECTRICAL CHARACTERISTICS .......................................................... 53 9.1 Absolute Maximum Ratings .........................................................................53 May. 02, 2018 Page 3 of 87 Rev 1.01 NANO103 SERIES DATASHEET 6.14.1 Nano103 9.2 Nano103 DC Electrical Characteristics ............................................................54 9.3 AC Electrical Characteristics ........................................................................72 9.3.1 External Input Clock .......................................................................................... 72 9.3.2 External 4~24 MHz XTAL Oscillator ....................................................................... 72 9.3.3 External 32.768 kHz Crystal ................................................................................ 73 9.3.4 Internal 36 MHz Oscillator ................................................................................... 74 9.3.5 Internal 12 MHz Oscillator ................................................................................... 74 9.3.6 Internal 4 MHz Oscillator .................................................................................... 75 9.3.7 Internal 10 kHz Oscillator .................................................................................... 76 Analog Characteristics ...............................................................................77 9.4 10 9.4.1 12-bit ADC ..................................................................................................... 77 9.4.2 Brown-out Detector ........................................................................................... 78 9.4.3 Power-on Reset ............................................................................................... 79 9.4.4 Low-Voltage Reset ........................................................................................... 79 9.4.5 Temperature Sensor ......................................................................................... 79 9.4.6 Internal Voltage Reference .................................................................................. 80 9.4.7 Comparator .................................................................................................... 80 PACKAGE DIMENSIONS ...................................................................... 81 NANO103 SERIES DATASHEET 10.1 64S LQFP (7x7x1.4 mm footprint 2.0 mm) .......................................................81 10.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm)........................................................83 10.3 33L QFN (5x5x1.4 mm footprint 2.0 mm) .........................................................84 11 REVISION HISTORY ............................................................................ 86 May. 02, 2018 Page 4 of 87 Rev 1.01 Nano103 LIST OF FIGURES ® 16 ® 18 ® 19 ® 20 ® Figure 5.1-1 NuMicro Nano103 Block Diagram 29 Figure 6.1-1 Functional Block Diagram 30 Figure 9‑1 Typical Crystal Application Circuit 73 Figure 9‑2 Typical Crystal Application Circuit 73 Figure 4.1-1 NuMicro Nano103 Series Selection Code Figure 4.3-1 NuMicro Nano103 LQFP 64-pin Diagram Figure 4.3-2 NuMicro Nano103 LQFP 48-pin Diagram Figure 4.3-3 NuMicro Nano103 QFN32-pin Diagram NANO103 SERIES DATASHEET May. 02, 2018 Page 5 of 87 Rev 1.01 Nano103 LIST OF TABLES Table 1.1-1 Connectivity Support Table ........................................................................................... 7 Table 1.1-1 List of Abbreviations .................................................................................................... 15 NANO103 SERIES DATASHEET May. 02, 2018 Page 6 of 87 Rev 1.01 Nano103 1 GENERAL DESCRIPTION ® ® The Nano103 series ultra-low-power 32-bit microcontroller embeded with ARM Cortex -M0 core operates at low voltage ranged from 2.2V to 3.6V and runs up to 36 MHz frequency with 64 Kbytes embedded Flash (APROM) and 16 Kbytes embedded SRAM and 4 Kbytes Flash loader memory (LDROM) for In-System Programming (ISP). The Nano103 series integrates RTC with independent VBAT pin, 12-bit SAR ADC, comparator and 2 provides high performance connectivity peripheral interfaces such as UART, SPI, I C, GPIOs, and ISO-7816-3 for Smart card. The Nano103 series supports main power off with only VBAT and RTC on less than 1.0 uA and Deep Power-down mode with RAM retention is less than 1.6 uA and fast wake-up via many peripheral interfaces. The Nano103 series provides low voltage, low operating power consumption, low standby current, high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost 32-bit microcontrollers. The Nano103 series is suitable for a wide range of battery device applications such as:  Hand-Held Medical Device  Wearable Device & Smart Watch  Wireless Gaming Control, Thermostats, Sensors Node Device (WSND)  Wireless Auto Meter Reading (AMR)  RFID Reader  Portable Wireless Data Collector  Mobile Payment Smart Card Reader  Security Alarm System  Smart Home Appliance  Smart Water, Gas, Heat Meters Product Line UART SPI I2C ADC ACMP RTC/Vbat SC Timer Nano103 ● ● ● ● ● ● ● ● Table 1.1-1 Connectivity Support Table May. 02, 2018 Page 7 of 87 Rev 1.01 NANO103 SERIES DATASHEET 1.1 Connectivity Support Table Nano103 2 FEATURES  Low Supply Voltage Range: 2.2V to 3.6V  Operating Temperature: -40℃~105℃  Four power modes   Normal mode  Idle mode  Power-down mode with RTC on and RAM retention  RTC domain only Wake-up sources  RTC, WDT, I²C, Timer, UART, SPI, BOD, GPIO  Fast wake-up from power-down mode: less than 3.5 μs when using HIRC0  Brown-out  NANO103 SERIES DATASHEET     Built-in 1.7~3.1V BOD for wide operating voltage range operation  Built-in low power 2.0/2.5V BOD Core ® ARM Cortex -M0 core running up to 36 MHz  One 24-bit system timer  Supports Low Power Sleep mode  Single-cycle 32-bit hardware multiplier  NVIC for the 32 interrupt inputs, each with 4-levels of priority  Serial Wire Debug supports with 2 watchpoints/4 breakpoints Flash EPROM Memory  64 Kbytes application program memory (APROM)  4 Kbytes in system programming (ISP) loader program memory (LDROM)  Programmable data flash start address and memory size with 512 bytes page erase unit  In System Program (ISP)/In Application Program (IAP) to update on-chip Flash EPROM SRAM Memory  16 Kbytes embedded SRAM  Supports DMA mode DMA: Supports Five channels includingfour PDMA channels and one CRC channel  May. 02, 2018 ®  PDMA  Three modes: peripheral-to-memory, memory-to-peripheral, and memoryto-memory transfer  Source address and destination address must be word alignment in all modes.  Memory-to-memory mode: transfer length must be word alignment.  Peripheral-to-memory and memory-to-peripheral mode: transfer length Page 8 of 87 Rev 1.01 Nano103 could be word/half-word/byte alignment.   Peripheral-to-memory and memory-to-peripheral mode: transfer data width could be word/half-word/byte alignment  Supports source and destination address direction: increment, fixed, and wrap around CRC    12 5 CRC-CCITT: X  CRC-8: X + X + X + 1  CRC-16: X  CRC-32: X + X 4 2 X +X +X+1 8 +X +X +1 2 16 +X 32 15 +X +1 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 +X +X +X +  Built-in 12/16MHz OSC (HIRC0) has 2 % deviation within all temperarure range. Deviation could be reduced to 1% if turning on auto-trim function.  Built-in 36MHz OSC(HIRC1)  Built-in 4MHz OSC(MIRC)  Supports one PLL, up to 36 MHz, for high performance system operation  External 4~24 MHz(HXT) crystal input for precise timing operation  Low power 10 kHz OSC(LIRC) for watchdog and low power system operation  External 32.768 kHz(LXT) crystal input for RTC and low power system operation GPIO NANO103 SERIES DATASHEET May. 02, 2018 16  Clock Control   Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 Three I/O modes:  Push-Pull output  Open-Drain output  Input only with high impendence  All inputs with Schmitt trigger  I/O pin configured as interrupt source with edge/level setting  Supports input 5V tolerance, except  PA.0 ~ PA.7 (sharing pin with ADC),  PA.12~ PA.13 (sharing pin with comparator),  PF.0~ PF.1 and PF.6 ~ PF.7(sharing pin with HXT and LXT)  PA.8, PB.4 and PB.5 Timer  Supports 4 sets of 32-bit timers, each timer with 24-bit up-counting timer and one 8-bit pre-scale counter  Each timer could have independent clock source selection  Supports one-shot,periodic, output toggle and continuous operation modes Page 9 of 87 Rev 1.01 Nano103    NANO103 SERIES DATASHEET   May. 02, 2018  Internal trigger event to ADC and PDMA  Supports PDMA mode  Wake system up from Power-down mode Watchdog Timer  Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)  Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)  Interrupt or reset selectable when watchdog time-out  Wakes system up from Power-down mode Window Watchdog Timer(WWDT)  6-bit down counter and 6-bit compare value to make the window period flexible  Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable. RTC  Supports software compensation by setting frequency compensate register (FREQADJ)  Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)  Supports Alarm registers (second, minute, hour, day, month, year)  Selectable 12-hour or 24-hour mode  Automatic leap year recognition  Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second  Wake system up from Power-down mode  Supports 20 bytes spare registers and a tamper pin to clear the content of these spare registers  Supports 1 Hz clock output  Support independent VBAT power domain to provide for PF.6~PF.7 (sharing pin with LXT) and tamper pins (LQFP64: PB.13/LQFP48: PA.9/QFN32: PB.8) PWM/Capture  Supports one PWM module to provides 6 output channels  Supports independent mode for PWM output/Capture input channe  Supports complementary mode for 3 complementary paired PWM output channel  Supports 16-bit resolution PWM counter, each module provides 3 PWM counters  Supports PWM triggerADC function  Supports up to 12 capture input channels with 16-bit resolution UART  Supports up to two sets of UART  Up to 1 Mbit/s baud rate  Support 9600 baud rate at 32.768 kHz Page 10 of 87 Rev 1.01 Nano103  May. 02, 2018 Up to two 16-byte FIFO UART controllers  UART ports with flow control (TX, RX, nCTS and nRTS)  Supports IrDA (SIR) function  Supports LIN function  Supports RS-485 9 bit mode and direction control.  Programmable baud rate generator  Supports PDMA mode  Supports wake-up function (nCTS, incoming RX data, RS-485 AAD mode address matched or received FIFO is equal to the RFITL) SPI  Up to two sets of SPI controllers  Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation  Supports 1 bit and 2 bit transfer mode  Support Dual IO transfer mode  Configurable bit length of a transaction from 8 to 32-bit  Supports MSB first or LSB first transfer sequence  Two slave select lines supported in Master mode  Configurable byte or word suspend mode  Supports byte re-ordering function  Supports variable serial clock in Master mode  Provide separate 8-level depth transmit and receive FIFO buffer  Supports wake-up function(SPI clock toggle in Power-down mode)  Supports PDMA transfer  Supports 3-wires, no slave select signal, bi-direction interface 2 IC 2  Up to two sets of I C device  Master/Slave up to 1 Mbit/s  Bi-directional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allows devices with different bit rates to communicate via one serial bus  Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer  Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode 2 Page 11 of 87 2 Rev 1.01 NANO103 SERIES DATASHEET   Nano103   NANO103 SERIES DATASHEET   Supports multiple address recognition (four slave addresses with mask option)  Wake system up(address match) from Power-down mode ADC  12-bit SAR ADC  Up to 12 channels: 8 external channel(PA.0 ~ PA.6 and PC.7) and 4 internal channels.  Four internal channels: internal reference voltage (Int_VREF), Temperature sensor, AVDD, and AVSS.  Supports three reference voltage sources: VREF pin, internal reference voltage (Int_VREF: 2.5V/1.8V/1.5V), and AVDD.  Supports Single Scan, Single Cycle Scan, and Continuous Scan mode  Each channel with individual result register  Threshold voltage detection (comparator function)  Conversion started by software programming or external input  Supports PDMA mode  Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to enable ADC SmartCard (SC)  Compliant to ISO-7816-3 T=0, T=1  Supports up to two ISO-7816-3 ports  Separates receive/transmit 4 bytes entry FIFO for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 267 ETU)  A 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error limit function  Supports hardware activation sequence process  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detect the card is removal  Supports UART mode (full–duplex) ACMP  Supports one comparator  Analog input voltage range: 0~AVDD  Supports Hysteresis function  96-bit unique ID  128-bit unique customer ID May. 02, 2018 Page 12 of 87 Rev 1.01 Nano103  Packages:  All Green package (RoHS)  LQFP 64-pin(7x7)  LQFP 48-pin(7x7)  QFN 33-pin(5x5) NANO103 SERIES DATASHEET May. 02, 2018 Page 13 of 87 Rev 1.01 Nano103 3 ABBREVIATIONS NANO103 SERIES DATASHEET Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 12/16 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NTC Negative Temperature Coefficient NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PTC Positive Temperature Coefficient PT1000 Thermal Resistance PWM Pulse Width Modulation May. 02, 2018 Page 14 of 87 Rev 1.01 Nano103 QEI Quadrature Encoder Interface SDIO Secure Digital Input/Output SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 1.1-1 List of Abbreviations NANO103 SERIES DATASHEET May. 02, 2018 Page 15 of 87 Rev 1.01 Nano103 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro® Nano103 Series Selection Code NANO 1 0 3 - X X X A E Temperature Ultra-low Power M0 E : - 40 ℃ ~ +105℃ Product Line Function 1 : Base Line Version A : Version Package Type SRAM Size 1 : 4KB 2 : 8KB 3 : 16KB Z : QFN 33 (5x5mm.0.5mm pitch) L : LQFP 48 (7x7mm,0.5mm pitch) S : LQFP 64 (7x7mm,0.4mm pitch) Flash ROM B: 16KB C: 32KB D: 64KB ® Figure 4.1-1 NuMicro Nano103 Series Selection Code NANO103 SERIES DATASHEET May. 02, 2018 Page 16 of 87 Rev 1.01 Nano103 4.2 NuMicro® Nano103 Products Selection Guide Part No. SRAM (KB) Data Flash Shared AP ROM (KB) LDROM (ISP Loader) (KB) I/O Timer UART* I2S SPI PWM 12-bit ADC ACMP RTC I2C IRC 10 kHz 4 MHz 12/16 MHz 36 MHz PDMA ISO-7816-3* ISP/ICP Package NuMicro® Nano103 Base Line Selection Guide Flash (KB) 4.2.1 NANO103ZD3AE 64 16 Configurable 4 26 4x32-bit 2+2 4 2 - 2 6 1 V V 4 2 V QFN33 NANO103LD3AE 64 16 Configurable 4 39 4x32-bit 2+2 4 2 - 6 8 1 V V 4 2 V LQFP48 NANO103SD3AE 64 16 Configurable 4 53 4x32-bit 2+2 4 2 - 6 8 1 V V 4 2 V LQFP64 Connectivity *Marked in the table (2+2) means 2 UART + 2 ISO-7816 UART *ISO-7816 UART supports UART full duplex mode NANO103 SERIES DATASHEET May. 02, 2018 Page 17 of 87 Rev 1.01 Nano103 4.3 Pin Configuration NuMicro® Nano103 Pin Diagrams ® PA.4 PA.3 PA.2 PA.1 PA.0 AVSS PF.1 PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro Nano103 LQFP 64-pin 47 4.3.1.1 48 4.3.1 PA.5 49 32 PB.9 PA.6 50 31 PB.10 51 30 PB.11 52 29 PE.5 PC.7 53 28 PC.0 PC.6 54 27 PC.1 PC.15 55 26 PC.2 PC.14 56 25 PC.3 PB.15 57 24 PD.15 PF.3 58 23 PD.14 PF.2 59 22 PD.7 nRESET 60 21 PD.6 VSS 61 20 PB.3 VDD 62 19 PB.2 PVSS 63 18 PB.1 PB.8 64 17 PB.0 14 15 16 PB.7 LDO_CAP VDD VSS 12 13 11 PB.6 PA.10 PB.5 7 PA.11 10 6 9 5 PF.7 PB.4 4 PF.6 PA.8 3 VBAT 8 2 PB.13 PA.9 1 LQFP64 PB.14 NANO103 SERIES DATASHEET VREF AVDD ® Figure 4.3-1 NuMicro Nano103 LQFP 64-pin Diagram May. 02, 2018 Page 18 of 87 Rev 1.01 Nano103 ® PA.4 PA.3 PA.2 PA.1 PA.0 AVSS PF.1 PF.0 PA.12 PA.13 PA.14 PA.15 35 34 33 32 31 30 29 28 27 26 25 NuMicro Nano103 LQFP 48-pin 36 4.3.1.2 PA.5 37 24 PB.9 PA.6 38 23 PB.10 VREF 39 22 PB.11 AVDD 40 21 PE.5 PC.7 41 20 PC.0 PC.6 42 19 PC.1 PB.15 43 18 PC.2 PF.3 44 17 PC.3 PF.2 45 16 PB.3 nRESET 46 15 PB.2 PVSS 47 14 PB.1 PB.8 48 13 PB.0 10 11 12 VDD VSS PB.5 LDO_CAP 9 PB.4 PA.10 8 5 PA.11 7 4 PA.8 3 PF.7 6 2 PF.6 PA.9 1 NANO103 SERIES DATASHEET VBAT LQFP48 ® Figure 4.3-2 NuMicro Nano103 LQFP 48-pin Diagram May. 02, 2018 Page 19 of 87 Rev 1.01 Nano103 ® PA.4 PA.3 PA.2 PA.0 PF.1 PF.0 PA.14 PA.15 24 23 22 21 20 19 18 17 NuMicro Nano103 QFN33-pin PA.5 25 16 PC.0 PA.6 26 15 PC.1 AVDD 27 14 PC.2 PF.3 28 13 PC.3 PF.2 29 12 PB.3 nRESET 30 11 PB.2 VBAT 31 10 PB.1 PF.6 32 9 PB.0 2 3 4 5 6 7 8 PA.9 PA.8 PB.4 PB.5 LDO_CAP VDD VSS NANO103 SERIES DATASHEET 1 QFN33 PF.7 4.3.1.3 ® Figure 4.3-3 NuMicro Nano103 QFN32-pin Diagram May. 02, 2018 Page 20 of 87 Rev 1.01 Nano103 4.4 Pin Description 4.4.1 NuMicro® Nano103 Pin Description Pin No. Pin Name 64-pin 1 2 3 4 5 6 - - 1 2 3 - 4 May. 02, 2018 Pin Type MFP* Description 32-pin PB.14 I/O INT0 I - - 1 MFP1 External interrupt0 input pin. SPI2_MOSI1 I/O MFP3 SPI2 2nd MOSI (Master Out, Slave In) pin. SPI2_SS1 I/O MFP4 SPI2 2nd slave select pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI2_MISO1 I/O MFP3 SPI2 2nd MISO (Master In, Slave Out) pin. SNOOPER I MFP7 Snooper pin. VBAT P MFP0 Power supply for tamper pin (LQFP64: PB.13/LQFP48: PA.9/QFN32: PB.8) and RTC. PF.6 I/O MFP0 General purpose digital I/O pin. I2C1_SDA I/O MFP1 I2C1 data input/output pin. X32_OUT O MFP7 External 32.768 kHz crystal output pin(default). PF.7 I/O MFP0 General purpose digital I/O pin. I2C1_SCL I/O MFP1 I2C1 clock pin. 31 32 MFP0 General purpose digital I/O pin. SC0_CD I MFP3 SmartCard0 card detect pin. X32_IN I MFP7 External 32.768 kHz crystal input pin(default). PA.9 I/O MFP0 General purpose digital I/O pin. I2C0_SCL I/O MFP1 I2C0 clock pin. TM1_CNT I SC0_DAT I/O MFP3 SmartCard0 data pin. SPI2_CLK I/O MFP4 SPI2 serial clock pin. TM1_OUT O MFP5 Timer1 toggle output. UART1_nRTS O MFP6 UART1 Request to Send output pin. SNOOPER I MFP7 Snooper pin. MFP2 Timer1 event counter input. 2 PA.11 I/O MFP0 General purpose digital I/O pin. I2C1_SCL I/O MFP1 I2C1 clock pin. TM3_CNT I MFP2 Timer3 event counter input. SC0_RST O MFP3 SmartCard0 reset pin. SPI2_MOSI0 I/O MFP4 SPI2 1st MOSI (Master Out, Slave In) pin. TM3_OUT O MFP5 Timer3 toggle output. - Page 21 of 87 Rev 1.01 NANO103 SERIES DATASHEET - 48-pin Nano103 Pin No. Pin Name 64-pin 7 8 9 48-pin 5 6 7 NANO103 SERIES DATASHEET 11 12 8 9 - May. 02, 2018 MFP* Description PA.10 I/O MFP0 General purpose digital I/O pin. I2C1_SDA I/O MFP1 I2C1 data input/output pin. TM2_CNT I MFP2 Timer2 event counter input. SC0_PWR O MFP3 SmartCard0 power pin. SPI2_MISO0 I/O MFP4 SPI2 1st MISO (Master In, Slave Out) pin. TM2_OUT O MFP5 Timer2 toggle output. PA.9 I/O MFP0 General purpose digital I/O pin. I2C0_SCL I/O MFP1 I2C0 clock pin. TM1_CNT I SC0_DAT I/O MFP3 SmartCard0 data pin. SPI2_CLK I/O MFP4 SPI2 serial clock pin. TM1_OUT O MFP5 Timer1 toggle output. UART1_nRTS O MFP6 UART1 Request to Send output pin. SNOOPER I MFP7 Snooper pin. - MFP2 Timer1 event counter input. - 3 PA.8 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP1 I2C0 data input/output pin. TM0_CNT I MFP2 Timer0 event counter input. SC0_CLK O MFP3 SmartCard0 clock pin. SPI2_SS0 I/O MFP4 SPI2 1st slave select pin. TM0_OUT O MFP5 Timer0 toggle output. UART1_nCTS I MFP6 UART1 Clear to Send input pin. I/O MFP0 General purpose digital I/O pin. PB.4 10 Pin Type 32-pin 4 UART1_RXD I MFP1 Data receiver input pin for UART1. SC0_CD I MFP3 SmartCard0 card detect pin. SPI2_SS0 I/O MFP4 SPI2 1st slave select pin. RTC_HZ O MFP6 RTC 1Hz output. PB.5 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP1 Data transmitter output pin for UART1. SC0_RST O MFP3 SmartCard0 reset pin. SPI2_CLK I/O MFP4 SPI2 serial clock pin. PB.6 I/O MFP0 General purpose digital I/O pin. UART1_RSTn O MFP1 UART1 Request to Send output pin. SPI2_MISO0 I/O MFP4 SPI2 1st MISO (Master In, Slave Out) pin. 5 - Page 22 of 87 Rev 1.01 Nano103 Pin No. Pin Name 64-pin 48-pin PB.7 13 - - 14 10 6 15 11 7 16 12 8 17 18 19 13 14 15 9 10 MFP0 General purpose digital I/O pin. UART1_nCTS I MFP1 UART1 Clear to Send input pin. SPI2_MOSI0 I/O MFP4 SPI21stMOSI (Master Out, Slave In) pin. LDO_CAP AO MFP0 LDO output pin. VDD P MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function. VSS G MFP0 Ground pin for digital circuit. PB.0 I/O MFP0 General purpose digital I/O pin. UART0_RXD I SPI1_MOSI0 I/O MFP3 SPI11stMOSI (Master Out, Slave In) pin. PB.1 I/O MFP0 General purpose digital I/O pin. UART0_TXD O MFP1 Data transmitter output pin for UART0. SPI1_MISO0 I/O MFP3 SPI11st MISO (Master In, Slave Out) pin. PB.2 I/O MFP0 General purpose digital I/O pin. UART0_nRTS O MFP1 UART0 Request to Send output pin. SPI1_CLK I/O MFP3 SPI1 serial clock pin. CLKO O MFP4 Frequency Divider output pin. PB.3 I/O MFP0 General purpose digital I/O pin. I MFP1 UART0 Clear to Send input pin. 12 SC1_CD 22 23 24 25 - - - - 17 May. 02, 2018 MFP1 Data receiver input pin for UART0. 11 SPI1_SS0 21 Description - - I/O I 13 MFP4 SmartCard1 card detect pin. PD.6 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI1 I/O MFP3 SPI1 2nd MOSI (Master Out, Slave In) pin. SC1_RST O MFP4 SmartCard1 reset pin. PD.7 I/O MFP0 General purpose digital I/O pin. SPI1_MISO1 I/O MFP3 SPI1 2nd MISO (Master In, Slave Out) pin. SC1_PWR O MFP4 SmartCard1 power pin. PD.14 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI1 I/O MFP1 SPI0 2nd MOSI (Master Out, Slave In) pin. SC1_DAT I/O MFP4 SmartCard1 data pin. PD.15 I/O MFP0 General purpose digital I/O pin. SPI0_MISO1 I/O MFP1 SPI0 2nd MISO (Master In, Slave Out) pin. SC1_CLK O MFP4 SmartCard1 clock pin. PC.3 I/O MFP0 General purpose digital I/O pin. - - MFP3 SPI1 1st slave select pin. Page 23 of 87 Rev 1.01 NANO103 SERIES DATASHEET 16 MFP* I/O UART0_nCTS 20 Pin Type 32-pin Nano103 Pin No. Pin Name 64-pin 26 27 48-pin 18 19 29 NANO103 SERIES DATASHEET 30 31 32 20 21 22 23 24 May. 02, 2018 MFP* Description SPI0_MOSI0 I/O MFP1 SPI0 1stMOSI (Master Out, Slave In) pin. SC1_RST O MFP4 SmartCard1 reset pin. PWM0_BRAKE0 I MFP5 PWM0 Brake0 input pin . PC.2 I/O MFP0 General purpose digital I/O pin. SPI0_MISO0 I/O MFP1 SPI0 1st MISO (Master In, Slave Out) pin. SC1_PWR O MFP4 SmartCard1 power pin. PWM0_BRAKE1 I MFP5 PWM0 Brake1 input pin. 14 PC.1 I/O MFP0 General purpose digital I/O pin. SPI0_CLK I/O MFP1 SPI0 serial clock pin. SC1_DAT I/O MFP4 SmartCard1 data pin. 15 PWM0_BRAKE0 28 Pin Type 32-pin I MFP5 PWM0 Brake0 input pin. PC.0 I/O MFP0 General purpose digital I/O pin. SPI0_SS0 I/O MFP1 SPI0 1st slave select pin. SC1_CLK O MFP4 SmartCard1 clock pin. PWM0_BRAKE1 I MFP5 PWM0 Brake1 input pin.. 16 - - - - PE.5 I/O MFP0 General purpose digital I/O pin. PWM0_CH5 I/O MFP1 PWM0 channel5 output/capture input. RTC_HZ O MFP6 RTC 1Hz output. PB.11 I/O MFP0 General purpose digital I/O pin. PWM0_CH4 I/O MFP1 PWM0 channel4 output/capture input. TM3_CNT I MFP2 Timer3 event counter input. TM3_OUT O MFP4 Timer3 toggle output. SPI0_MISO0 I/O MFP5 SPI0 1st MISO (Master In, Slave Out) pin. PB.10 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI0 I/O MFP1 SPI0 1stMOSI (Master Out, Slave In) pin. TM2_CNT I MFP2 Timer2 event counter input. TM2_OUT O MFP4 Timer2 toggle output. SPI0_SS1 I/O MFP5 SPI0 2nd slave select pin. PB.9 I/O MFP0 General purpose digital I/O pin. SPI1_SS1 I/O MFP1 SPI1 1st slave select pin. TM1_CNT I MFP2 Timer1 event counter input. TM1_OUT O MFP4 Timer1 toggle output. INT0 I MFP5 External interrupt0 input pin. Page 24 of 87 Rev 1.01 Nano103 Pin No. Pin Name 64-pin 33 34 35 36 37 39 40 - - - - 25 26 27 28 May. 02, 2018 Pin Type MFP* Description 32-pin - - - - PC.11 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI0 I/O MFP1 SPI1 1st MOSI (Master Out, Slave In) pin. UART1_TXD O MFP5 Data transmitter output pin for UART1. PC.10 I/O MFP0 General purpose digital I/O pin. SPI1_MISO0 I/O MFP1 SPI1 1st MISO (Master In, Slave Out) pin. UART1_RXD I MFP5 Data receiver input pin for UART1. PC.9 I/O MFP0 General purpose digital I/O pin. SPI1_CLK I/O MFP1 SPI1 serial clock pin. I2C1_SCL I/O MFP5 I2C1 clock pin. PC.8 I/O MFP0 General purpose digital I/O pin. SPI1_SS0 I/O MFP1 SPI1 1st slave select pin. I2C1_SDA I/O MFP5 I2C1 data input/output pin. PA.15 I/O MFP0 General purpose digital I/O pin. PWM0_CH3 I/O MFP1 PWM0 channel3 output/capture input. I2C1_SCL I/O MFP2 I2C1 clock pin. TM3_EXT I MFP3 Timer3 external capture input. SC0_PWR O MFP4 SmartCard0 power pin. TM3_CNT I MFP5 Timer3 event counter input. UART0_TXD O MFP6 Data transmitter output pin for UART0. TM3_OUT O MFP7 Timer3 toggle output. PA.14 I/O MFP0 General purpose digital I/O pin. PWM0_CH2 I/O MFP1 PWM0 channel2 output/capture input. I2C1_SDA I/O MFP2 I2C1 data input/output pin. TM2_EXT I MFP3 Timer2 external capture input. TM2_CNT I MFP5 Timer2 event counter input. UART0_RXD I MFP6 Data receiver input pin for UART0. TM2_OUT O MFP7 Timer2 toggle output. PA.13 I/O MFP0 General purpose digital I/O pin. PWM0_CH1 I/O MFP1 PWM0 channel1 output/capture input. 17 18 TM1_EXT I MFP3 Timer1 external capture input. I2C0_SCL I/O MFP5 I2C0 clock pin. PA.12 I/O MFP0 General purpose digital I/O pin. PWM0_CH0 I/O MFP1 PWM0 channel0 output/capture input. - Page 25 of 87 Rev 1.01 NANO103 SERIES DATASHEET 38 48-pin Nano103 Pin No. 64-pin 41 42 43 44 45 NANO103 SERIES DATASHEET 46 48-pin 29 30 31 32 33 34 Pin Name Pin Type TM0_EXT I I2C0_SDA I/O MFP5 I2C0 data input/output pin. PF.0 I/O MFP0 General purpose digital I/O pin. 19 INT0 I 48 49 35 36 37 May. 02, 2018 Description MFP3 Timer0 external capture input. MFP5 External interrupt0 input pin. ICE_DAT I/O MFP7 Serial wired debugger data pin PF.1 I/O MFP0 General purpose digital I/O pin. CLKO O MFP4 Frequency Divider output pin. INT1 I MFP5 External interrupt1 input pin. ICE_CLK I MFP7 Serial wired debugger clock pin. AVSS G MFP0 Ground pin for analog circuit. PA.0 I/O MFP0 General purpose digital I/O pin. ADC_CH0 AI MFP1 ADC analog input0. ACMP0_P AI MFP2 Comparator0 P-end input. TM2_EXT I 20 - 21 MFP3 Timer2 external capture input. PWM0_CH2 I/O MFP5 PWM0 channel2 output/capture input. SPI3_MOSI1 I/O MFP6 SPI3 2ndMOSI (Master Out, Slave In) pin. PA.1 I/O MFP0 General purpose digital I/O pin. ADC_CH1 AI MFP1 ADC analog input1. ACMP0_N AI MFP2 Comparator0 N-end input. SPI3_MISO1 I/O MFP6 SPI3 2nd MISO (Master In, Slave Out) pin. PA.2 I/O MFP0 General purpose digital I/O pin. ADC_CH2 AI MFP1 ADC analog input2. - 22 UART1_RXD 47 MFP* 32-pin I MFP5 Data receiver input pin for UART1. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 AI MFP1 ADC analog input3. UART1_TXD O MFP5 Data transmitter output pin for UART1. SPI3_MOSI0 I/O MFP6 SPI3 1st MOSI (Master Out, Slave In) pin. PA.4 I/O MFP0 General purpose digital I/O pin. ADC_CH4 AI MFP1 ADC analog input4. I2C0_SDA I/O MFP5 I2C0 data input/output pin. SPI3_MISO0 I/O MFP6 SPI3 1st MISO (Master In, Slave Out) pin. PA.5 I/O MFP0 General purpose digital I/O pin. ADC_CH5 AI MFP1 ADC analog input5. 23 24 25 Page 26 of 87 Rev 1.01 Nano103 Pin No. 64-pin 50 48-pin 38 Pin Name Pin Type MFP* Description I2C0_SCL I/O MFP5 I2C0 clock pin. SPI3_SCLK I/O MFP6 SPI3 serial clock pin. PA.6 I/O MFP0 General purpose digital I/O pin. ADC_CH6 AI MFP1 ADC analog input6. ACMP0_O O MFP2 Comparator0 output. TM3_EXT I MFP3 Timer3 external capture input. TM3_CNT I MFP4 Timer3 event counter input. 32-pin 26 PWM0_CH3 I/O MFP5 PWM0 channel3 output/capture input. SPI3_SS0 I/O MFP6 SPI3 1st slave select pin. TM3_OUT O MFP7 Timer3 toggle output. MFP0 Voltage reference input for ADC. 51 39 - VREF I 52 40 27 AVDD AP MFP0 Power supply for internal analog circuit. PC.7 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP1 Data transmitter output pin for UART1. ADC_CH7 AI MFP2 ADC analog input7. TM1_EXT I 53 55 42 - - - - PWM0_CH1 I/O MFP5 PWM0 channel1 output/capture input. PC.6 I/O MFP0 General purpose digital I/O pin. UART1_RXD I MFP1 Data receiver input pin for UART1. TM0_EXT I MFP3 Timer0 external capture input. SC1_CD I MFP4 SmartCard1 card detect pin. PWM0_CH0 I/O MFP5 PWM0 channel0 output/capture input. PC.15 I/O MFP0 General purpose digital I/O pin. UART1_nRTS O MFP1 UART1 Request to Send output pin. TM0_EXT I MFP3 Timer0 external capture input. I/O MFP0 General purpose digital I/O pin. I MFP1 UART1 Clear to Send input pin. PB.15 I/O MFP0 General purpose digital I/O pin. INT1 I MFP1 External interrupt1 input pin. SNOOPER I MFP3 Snooper pin. SC1_CD I MFP4 SmartCard1 card detect pin. PC.14 56 - UART1_nCTS 57 43 - PF.3 58 44 May. 02, 2018 MFP3 Timer1 external capture input. 28 XT1_IN I/O I Page 27 of 87 MFP0 General purpose digital I/O pin. MFP7 External 4~24 MHz (high speed) crystal input pin. Rev 1.01 NANO103 SERIES DATASHEET 54 41 Nano103 Pin No. Pin Name 64-pin 48-pin 59 45 29 60 46 30 61 - - 62 - - 63 47 - 64 48 Pin Type MFP* Description 32-pin PF.2 I/O MFP0 General purpose digital I/O pin. XT1_OUT O MFP7 External 4~24 MHz (high speed) crystal output pin. nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. VSS G MFP0 Ground pin for digital circuit. VDD P MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function. VSS G MFP0 Ground pin for digital circuit. PB.8 I/O MFP0 General purpose digital I/O pin. STADC I MFP1 ADC external trigger input. TM0_CNT I MFP2 Timer0 event counter input. INT0 I MFP3 External interrupt0 input pin. TM0_OUT O MFP4 Timer0 toggle output. SNOOPER I MFP7 Snooper pin. - Note:Pin Type: I = Digital Input, O=Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog Power. NANO103 SERIES DATASHEET May. 02, 2018 Page 28 of 87 Rev 1.01 Nano103 5 BLOCK DIAGRAM 5.1 Nano103 Block Diagram Memory RTC / PWM / Timer Analog Interface RTC (VBAT) APROM 64 KB ARM Cortex-M0 36 MHz LDROM 4 KB PDMA x 5 DataFlash Configurable SRAM 16 KB 32-bit Timer x 4 12-bit ADC x 8 Watchdog Timer Analog Comparator x 1 Window Watchdog Timer PWM/Capture Timer x 6 Bridge AHB Bus Power Control Clock Control PLL LDO 1.8V/1.6V/1.2V Power On Reset LVR High Speed Oscillator(HIRC1) 36 MHz High Speed Oscillator(HIRC0) 12/16 MHz Medium Speed Oscillator(MIRC) 4 MHz Low Speed Crystal Osc.(LXT) 32.768 kHz Low Speed Oscillator(LIRC) 10 kHz Connectivity I/O Ports UART x 4 (2 from ISO-7816-3) General Purpose I/O x 53 SPI x 4 External Interrupt x 32 I2C x 2 Reset Pin x 1 ISO-7816-3 x 2 ® Figure 5.1-1 NuMicro Nano103 Block Diagram May. 02, 2018 Page 29 of 87 Rev 1.01 NANO103 SERIES DATASHEET BOD High Speed Crystal Osc.(HXT) 4 ~ 24 MHz APB Bus Nano103 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex® -M0 Core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ® functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processor. The profile supports two modes –Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. The Figure 6.1-1shows the functional controller of processor. Cortex-M0 Components Cortex-M0 Processor Nested Vectored Interrupt Controller (NVIC) Interrupts Wakeup Interrupt Controller (WIC) Debug Cortex-M0 Processor Core Breakpoint and Watchpoint Unit Bus matrix Debugger interface AHB-Lite interface Debug Access Port (DAP) Serial Wire or JTAG debug port NANO103 SERIES DATASHEET Figure 6.1-1 Functional Block Diagram The implemented device provides:  A low gate count processor:           ® ARMv6-M Thumb instruction set Thumb-2 technology ARMv6-M compliant 24-bit SysTick timer A 32-bit hardware multiplier System interface supported with little-endian data accesses Ability to have deterministic, fixed-latency, interrupt handling Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature NVIC:  32 external interrupt inputs, each with four levels of priority May. 02, 2018 Page 30 of 87 Rev 1.01 Nano103     Debug support:      Dedicated Non-maskable Interrupt (NMI) input Supports for both level-sensitive and pulse-sensitive interrupt lines Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Four hardware breakpoints Two watchpoints Program Counter Sampling Register (PCSR) for non-intrusive code profiling Single step and vector catch capabilities Bus interfaces:   Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory Single 32-bit slave port that supports the DAP (Debug Access Port) NANO103 SERIES DATASHEET May. 02, 2018 Page 31 of 87 Rev 1.01 Nano103 6.2 System Manager 6.2.1 Overview The system manager provides the functions of power modes, wake-up sources, power architecture, reset sources, scalable LDO, system memory map, product ID and multi-function pin control. 6.2.2 Features  Power modes and wake-up sources  System power architecture  Reset sources  Scalable LDO  HIRC0, HIRC1, and MIRC Auto-trim  System memory map  System manager Control registers map  System timer (SysTick)  System control register  Nested vectored interrupt controller (NVIC) NANO103 SERIES DATASHEET May. 02, 2018 Page 32 of 87 Rev 1.01 Nano103 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[6]) and ® Cortex -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal (HXT), 12~16 MHz internal high speed RC oscillator (HIRC0), 36 MHz internal high speed RC oscillator (HIRC1), and 4 MHz internal medium speed RC oscillator (MIRC) to reduce the overall system power consumption. The following figure shows the clock generator and the overview of the clock source control. The clock controller consists of 7 sources as listed below:        6.3.2 32768 Hz external low speedcrystal oscillator (LXT) 4~24 MHz external high speed crystal oscillator (HXT) 12~16 MHz internal high speed RC oscillator (HIRC0) 36 MHz internal high speed RC oscillator (HIRC1) 4 MHz internal medium speed RC oscillator (MIRC) One programmable PLL FOUT (PLL source can be selected from HXT, HIRC0,HIRC1 or MIRC) 10 kHz internal low speed RC oscillator (LIRC) Features    Page 33 of 87 Rev 1.01 NANO103 SERIES DATASHEET May. 02, 2018 Generates clocks for system clocks and all peripheral module clocks. Each peripheral module clock can be turned on/off. In Power-down mode, the clock controller turns off the external high speed crystal (HXT) and internal high speed RC oscillator (HIRC0,HIRC1 and MIRC) to reduce the overall system power consumption. Nano103 6.4 Flash Memory Controller (FMC) 6.4.1 Overview The Nano103 series is equipped with 32/64 Kbytes on-chip embedded flash for application and Data Flash to store some application dependent data. A User Configuration block provides for system initiation. A 4K bytes loader ROM (LDROM) is used for In-System-Programming (ISP) function. This chip also supports In-Application-Programming (IAP) function, user switches the code executing without the chip reset after the embedded flash updated. 6.4.2 Features  Supports 32/64 Kbytesapplication ROM (APROM).  Supports 4 Kbytesloader ROM (LDROM).  Supports Data Flash with configurable memory size.  Supports 12 bytes User Configuration block to control system initiation.  Supports 512 bytes page erase for all embedded flash.  Supports fast flash programming verification function.  Supports CRC-32 checksum calculation function.  Supports Flash All-One verification function.  Supports In-System-Programming (ISP) /In-Application-Programming (IAP)to update embedded flash memory.  Supports cache memory to improve flash access performance and reduce power consumption. NANO103 SERIES DATASHEET May. 02, 2018 Page 34 of 87 Rev 1.01 Nano103 6.5 General Purpose I/O Controller 6.5.1 Overview The Nano103 series hasup to 53 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 53 pins are arranged in 6 ports named as PA, PB, PC, PD, PE and PF.The PA, PB, PC, PD and PE have 16 pins on port, and the PF has 8 pins on port. Each of the 53 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each I/O pin can be configured by software individually as Input, Push-pull output, and Open-drain output. Each I/O pin has a very weak individual pull-up resistor which is about 110 k~40 k and VDD is from 2.2 V to 3.6 V. 6.5.2 Features  Three I/O modes:  Schmitt triggerInput-only with high impendence  Push-Pull Output mode  Open-Drain Output mode  I/O pin can be configured as interrupt source with edge/level setting  Enabling the pin interrupt function will also enable the wake-up function NANO103 SERIES DATASHEET May. 02, 2018 Page 35 of 87 Rev 1.01 Nano103 6.6 PDMA Controller (PDMA) 6.6.1 Overview The peripheral direct memory access (PDMA) controllerin the Nano103 series contains a four-channel DMA controller and a cyclic redundancy check (CRC) generator. The PDMA controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a total of 4 channels and each channel can perform transfer between memory and peripherals or between memory and memory. The PDMA controller also contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine supports CPU mode and DMA transfer mode. 6.6.2 Features  Supports 4 independently configurable channels and 1 CRC channel  Supports hardware round robin priority scheme. PDMA channel 1 has the highest priority and channel 4 has the lowest priority  PDMA NANO103 SERIES DATASHEET   Supports transfer data width of 8, 16, or 32 bits  Supports software and SPI, UART, TIMER and ADC request  Supports source and destination address increment size can be byte, half-word, word, no increment or wrap around  Supports periodic transfer count interrupt  Supports time-out function for each channel Cyclic Redundancy Check (CRC)  May. 02, 2018 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 16 12  CRC-CCITT: X  CRC-8:X + X + X + 1  CRC-16: X  CRC-32: X 2 X +X+1 8 +X 5 +X +1 2 16 +X 15 +X +1 32 +X 2 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 8 7 5 4 +X +X +X +X +  Programmable seed value  Supports programmable order reverse setting for input data and CRC checksum  Supports programmable 1’s complement setting for input data and CRC checksum  Supports CPU mode or DMA transfer mode  Supports transfer data width of 8, 16, or 32 bits in CRC CPU mode  8-bit write mode: 1-AHB clock cycle operation  16-bit write mode: 2-AHB clock cycle operation  32-bit write mode: 4-AHB clock cycle operation Page 36 of 87 Rev 1.01 Nano103  Supports transfer data width of 8 bits in CRC DMA mode NANO103 SERIES DATASHEET May. 02, 2018 Page 37 of 87 Rev 1.01 Nano103 6.7 Timer Controller 6.7.1 Overview The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent Clock Source for each Timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])  Supports event counting function to count input event from pin TMx_CNT (x = 0~3)  24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])  Supports event capture from external pin TMx_EXT (x = 0~3) for interval measurement  Supports event capture from external pin TMx_EXT (x = 0~3) to reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated  Supports time-out interrupt or capture interrupt to trigger ADC, PDMA and PWM.  Supports Inter-Timer trigger that Timer 0 can trigger Timer 1 and Timer 2 can trigger Timer 3 NANO103 SERIES DATASHEET May. 02, 2018 Page 38 of 87 Rev 1.01 Nano103 6.8 PWM Generator and Capture Timer (PWM) 6.8.1 Overview The Nano103 provides one PWM generator － PWM0. The PWM0 supports 6 channels for PWM0 output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM0 counter with 16-bit comparator. The PWM0 counter supports up, down and up-down counter types and uses a comparator compared with counter to generate events. These events are used to generate PWM0 pulse, interrupt and trigger signal for ADC to start conversion. The PWM0 generator supports two standard PWM0 output modes: Independent mode and Complementary mode, which have different architecture. In Complementary mode, there are two comparators that generate various PWM0 pulse with 12-bit dead-time generator. The PWM0 output control unit supports polarity output, independent pin mask, tri-state output enable and brake functions. The PWM0 generator also supports input capture function. It supports latch PWM0 counter value to a corresponding register when input channel has a rising transition, falling transition or both transitions. 6.8.2 6.8.2.1 Features PWM0 function features  Supports one PWM0 module to provides 6 output channels  Supports independent mode for PWM0 output/Capture input channel  Supports complementary mode for 3 complementary paired PWM0 output channel  Dead-time insertion with 12-bit resolution  Two compared values during one period Supports 12-bit pre-scalar from 1 to 4096  Supports 16-bit resolution PWM0 counter, each module provides 3 PWM0 counters  Up, down and up/down counter operation type  Supports mask function and tri-state enable for each PWM0 pin  Supports brake function    Brake source from pin and system safety events (Brown-out detection and CPU lockup)  Noise filter for brake source from pin  Edge detect brake source to control brake state until brake interrupt cleared  Level detect brake source to auto recover function after brake condition removed Supports interrupt on the following events:  PWM0 counter match zero, period value or compared value  Brake condition happened Supports trigger ADCon the following events:  May. 02, 2018 PWM0 counter match zero, period value or compared value Page 39 of 87 Rev 1.01 NANO103 SERIES DATASHEET  Nano103 6.8.2.2 Capture Function Features  Supportsup to 12 capture input channels with 16-bit resolution  Supports rising or falling capture condition  Supports input rising/falling capture interrupt  Supports rising/falling capture with counter reload option NANO103 SERIES DATASHEET May. 02, 2018 Page 40 of 87 Rev 1.01 Nano103 6.9 Watchdog Timer Controller 6.9.1 Overview The Watchdog Timer (WDT) is used to perform a system reset after system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up CPU from Power-down mode. The watchdog timer includes an 18-bit free running up counter with programmable time-out intervals. 6.9.2 Features  18-bit free running up counter for Watchdog timer time-out interval.  Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214 s (if WDT_CLK = 10 kHz).  System kept in reset state for a period of (1 / WDT_CLK) * 63.  Supports selectable WDT reset delay period, including 1026 、 130 、 18 or 3 WDT_CLK reset delay period.  Supports to force WDT enabled after chip powered on or reset by setting CWDT_EN[2:0] in Config0 register.  Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT. 4 18 NANO103 SERIES DATASHEET May. 02, 2018 Page 41 of 87 Rev 1.01 Nano103 6.10 Window Watchdog Timer Controller 6.10.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. The WWDT down counter value will stop to update when chip is in Idle or Power-down mode. 6.10.2 Features  6-bit down counter (WWDT_CNT) and 6-bit compare value (WINCMP) to make the WWDT time-out window period flexible  Supports 4-bit value (PERIODSEL) to programmable maximum 11-bit prescale counter period of WWDT counter NANO103 SERIES DATASHEET May. 02, 2018 Page 42 of 87 Rev 1.01 Nano103 6.11 Real Time Clock (RTC) 6.11.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick andalarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. The RTC controller also offers 80 bytes spare registers to store user’s important information. The spare registers content is cleared when specified event on tamper pin is detected. 6.11.2 Features Supportsreal time counterin RTC_TIME (hour, minute, second) and calendar counter in RTC_CAL (year,month, day) for RTC time and calendar check  Supportsalarm time (hour, minute, second) and calendar (year,month, day) settings in RTC_TALM and RTC_CALM  Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in RTC_TAMSK and RTC_CAMSK  Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register  Supports Leap Year indication in RTC_LEAPYEAR register  Supports Day of the Week counterin RTC_WEEKDAY register  Frequency of RTC clock source compensateby RTC_FREQADJ register  All time and calendar message expressed in BCD format  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second  Supports RTC Time Tick and Alarm Match interrupt  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated  Supports 20 bytes spare registers and a snoop pin detection to clear the content of these spare registers May. 02, 2018 Page 43 of 87 Rev 1.01 NANO103 SERIES DATASHEET  Nano103 6.12 UART Controller 6.12.1 Overview The UART Controller provides up to two channels of Universal Asynchronous Receiver/Transmitter (UART). The UART Controller performs Normal Speed UART and supports flow control function. In addtion, the UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN Master/Slave, RS-485 and auto-baud rate measuring function. 6.12.2 Features  Full duplex asynchronous communications.  Separate receiving and transmitting 16/16 bytes entry FIFO for data payloads.  Supports hardware auto-flow control  Supports programmable receiver buffer trigger level.  Supports programmable baud rate generator for each channel individually.  Supports nCTS, incoming RX data, RS-485 AAD mode address matched or received FIFO is equal to the RFITL to wake-up function.  Supports 9-bit receiver buffer time-out detection function.  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UART_TOUT [15:8])  Supports Auto-Baud Rate measurement and baud rate compensation  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface characteristics NANO103 SERIES DATASHEET   Programmable number of data bit, 5-, 6-, 7-, 8- bit character  Programmable parity bit, even, odd, no parity or stick parity bit generation and detection  Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports IrDA SIR function mode     May. 02, 2018 Supports for 3/16 bit duration for normal mode Supports LIN function mode  Supports LIN master/slave mode  Supports programmable break generation function for transmitter  Supports break detection function for receiver Supports RS-485 function mode  Supports RS-485 9-bit mode  Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction All UART Controller can be served by the PDMA. Page 44 of 87 Rev 1.01 Nano103 Smart Card Host Interface (SC) 6.13 6.13.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also can be set as UART mode to communicate with other device. 6.13.2 Features ISO-7816-3 T = 0, T = 1 compliant  EMV2000 compliant  Up to two ISO-7816-3 ports  Separates receive/transmit 4 byte entry FIFO for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 267 ETU)  One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error number limitation function  Supports hardware activation sequence process ,and the time between PWR on and CLK start is configurable  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detected the card removal  Provides card insert/removal status  Supports UART mode May. 02, 2018  Full duplex, asynchronous communications  Separates receiving / transmitting 4 bytes entry FIFO for data payloads  Supports programmable baud rate generator for each channel  Supports programmable receiver buffer trigger level  Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion by setting SC_EGTR register  Programmable even, odd or no parity bit generation and detection  Programmable stop bit, 1 or 2 stop bit generation Page 45 of 87 Rev 1.01 NANO103 SERIES DATASHEET  Nano103 I2C Serial Interface Controller (I2C) 6.14 6.14.1 Overview 2 I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data 2 exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. 2 There are two sets of I C controllers which support Power-down wake-up function. 6.14.2 Features 2 The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to 2 the bus. The main features of the I C bus include: 2 NANO103 SERIES DATASHEET  Supports up to two I C ports  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allow devices with different bit rates to communicate via one serial bus  Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows.  Programmable clocks allow for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition ( two slave address with mask option)  Supports Power-down wake-up function  Supports two-level buffer  Supports data transmit or receive directly mode. 2 May. 02, 2018 Page 46 of 87 2 Rev 1.01 Nano103 6.15 SPI 6.15.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. It is used to perform a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The SPI controller can be configured as a master or a slave device. The SPI controller supports wake-up function. When this chip stays in Power-down mode, it can be woken up by off-chip device. The SPI controller supports 2-bit transfer mode to connect 2 off-chip slave devices and then perform full-duplex 2-bit data transfer. It also supports PDMA function to access the data buffer. 6.15.2 Features Up to four sets of SPI controllers  Supports Master or Slave mode operation  Supports 1 bit and 2 bit transfer mode  Supports Dual I/O transfer mode  Configurable bit length of a transaction word from 8 to 32-bit  Supports MSB first or LSB first transfer sequence  Two slave select lines supported in Master mode  Configurable byte or word suspend mode  Supports byte re-ordering function  Provide separate 8-level depth transmit and receive FIFO buffer  Supports wake-up function  Supports PDMA transfer  Supports 3-wires, no slave select signal, bi-direction interface May. 02, 2018 Page 47 of 87 NANO103 SERIES DATASHEET  Rev 1.01 Nano103 Analog to Digital Converter (ADC) 6.16 6.16.1 Overview The Nano103 series contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with 8 external input channels and 6 internal channels. The A/D converter supports three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started by software, external STADC(PB.8) pin, timer event trigger and PWM trigger. Note that the I/O pins used as ADC analog input pins must configure the Pin Function (SYS_GPA_MFPL/SYS_GPC_MFPL) to ADC input and off digital input path disable control (Px_DINOFF) should be turned on before ADC function is enabled. 6.16.2 Features  Analog input voltage range: 0~VREF (Max to AVDD).  Selectable 12-bit, 10-bit, 8-bit and 6-bit resolution.  Supports sampling time settings for channel 0~7 individually and channel 12~17 share the same one sampling time setting.  Supports two power saving modes:  Power-down mode.  Standby mode. NANO103 SERIES DATASHEET  Up to 8 external analog input channels (channel0 ~ channel7), and 6 internal channels (channel12 - channel17) converting six voltage sources (internal band-gap voltage, internal reference voltage, internal temperature sensor output, battery voltage, AVDD, and AVSS).  Maximum ADC clock frequency is 36 MHz and each conversion needs 19 clocks and sampling time depending on the input resistance (Rin).  Three operating modes:   Single mode: A/D conversion is performed one time on a specified channel.  Single-cycle Scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel.  Continuous Scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion. An A/D conversion can be started by:  Software write 1 to SWTRG (ADC_CTL[11]) bit.  External pin STADC.  PWM trigger.  Selects one of four timer events to trigger ADC and transfer A/D results by PDMA.  Each conversion result is held in data registers for each channel with valid and overrun indicators.  Conversion results can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting.  Supports calibration and load calibration words capability. May. 02, 2018 Page 48 of 87 Rev 1.01 Nano103 6.17 Analog Comparator Controller (ACMP0) 6.17.1 Overview The Nano103 series contains one comparator. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. The comparator can be configured to generate an interrupt when the comparator output value changes. 6.17.2 Features  Analog input voltage range: 0 ~ AVDD(voltage of AVDD pin)  Supports hysteresis function  Supports wake-up function  Selectableinput sources of negative input  Comparator ACMP supports  1 positive source   PA.0(ACMP0_P) 4 negative sources  PA.1(ACMP0_N)  Comparator Reference Voltage (CRV)  Int_VREF  AGND NANO103 SERIES DATASHEET May. 02, 2018 Page 49 of 87 Rev 1.01 Nano103 7 APPLICATION CIRCUIT Power DVCC [1] AVDD AVDD 1uF//10nF In Case VREF = AVDD VREF SPISS SPICLK MISO MOSI VREF CS CLK MISO MOSI VDD SPI Device VSS 1uF//10nF AVSS AVSS VBAT 1uF//10nF VBAT 1uF//10nF VDD VDD DVCC 4.7K 4.7K CLK SCL VSS DVCC SDA DIO VDD I2C Device VSS 20p X32_IN LDO_CAP 32.768 KHz crystal Crystal LDO 1uF Nano103AE 20p X32_OUT 20p XT1_IN 4~24 MHz crystal Crystal 20p VDD ICE_DAT ICE_CLK /RESET VSS SWD Interface XT1_OUT RS232 Transceiver DVDD RXD ROUT TXD TIN RIN TOUT PC COM Port UART NANO103 SERIES DATASHEET 10K nRESET Reset Circuit 10uF/25V May. 02, 2018 Note: For the SPI device, the Nano103 chip supply voltage must be equal to SPI device working voltage. For example, when the SPI Flash working voltage is 3.3 V, the Nano103 chip supply voltage must also be 3.3V. Page 50 of 87 Rev 1.01 Nano103 8 POWER COMSUMPTION Part No Test Condition May. 02, 2018 Page 51 of 87 CPU clock Current 3.6V 36 MHz 6.7mA 186uA/MHz 3.6V 36 MHz 2.2mA 61uA/MHz 3.6V 36 MHz 6.7mA 186uA/MHz 3.6V 36 MHz 1.9mA 53uA/MHz 3.6V 16 MHz 2.9mA 181uA/MHz 3.6V 16 MHz 1.2mA 75uA/MHz 3.6V 16 MHz 2.8mA 175uA/MHz 3.6V 16 MHz 1.1mA 69uA/MHz 3.6V 12 MHz 2.2mA 183uA/MHz 3.6V 12 MHz 900uA 75uA/MHz Rev 1.01 NANO103 SERIES DATASHEET Operating Mode: CPU run while(1) in FLASH ROM Clock = 36MHz (from PLL and its clock source is 12 MHz Crystal Oscillator) Disable all peripheral Set LDO output = 1.8V Idle Mode: CPU stop Clock = 36MHz (from PLL and its clock source is 12 MHz Crystal Oscillator) Disable all peripheral Set LDO output = 1.8V Operating Mode: CPU run while(1) in FLASH ROM Clock = 36MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.8V Idle Mode: CPU stop Clock = 36MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.8V Operating Mode: CPU run while(1) in FLASH ROM Nano103 Clock = 16MHz Crystal Oscillator series Disable all peripheral Set LDO output = 1.6V Idle Mode: CPU stop Clock = 16MHz Crystal Oscillator Disable all peripheral Set LDO output = 1.6V Operating Mode: CPU run while(1) in FLASH ROM Clock = 36MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.6V Idle Mode: CPU stop Clock = 36MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.6V Operating Mode: CPU run while(1) in FLASH ROM Clock = 12MHz Crystal Oscillator Disable all peripheral Set LDO output = 1.6V Idle Mode: CPU stop Clock = 12MHz Crystal Oscillator VDD Nano103 Disable all peripheral Set LDO output = 1.6V NANO103 SERIES DATASHEET Operating Mode: CPU run while(1) in FLASH ROM Clock = 12MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.6V Idle Mode: CPU stop Clock = 12MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.6V Operating Mode: CPU run while(1) in FLASH ROM Clock = 4MHz Crystal Oscillator Disable all peripheral Set LDO output = 1.2V Idle Mode: CPU stop Clock = 4MHz Crystal Oscillator Disable all peripheral Set LDO output = 1.2V Operating Mode: CPU run while(1) in FLASH ROM Clock = 4MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.2V Idle Mode: CPU stop Clock = 4MHz Internal RC Oscillator Disable all peripheral Set LDO output = 1.2V RTC Mode: (RAM retention) (Main power off and only VBAT and RTC on) CPU stop Clock = 32.768KHz Crystal Oscillator Disable all peripheral except RTC circuit RTC Mode: (RAM retention) (Power down with LXT enable) CPU stop Clock = 32.768KHz Crystal Oscillator Disable all peripheral except RTC circuit Set LDO output = 1.2V Power Down Mode: (RAM retention) CPU and all clocks stop Set LDO output = 1.2V May. 02, 2018 Page 52 of 87 3.6V 12 MHz 2.2mA 183uA/MHz 3.6V 12 MHz 900uA 75uA/MHz 3.6V 4 MHz 600uA 150uA/MHz 3.6V 4 MHz 500uA 125uA/MHz 3.6V 4 MHz 900uA 225uA/MHz 3.6V 4 MHz 500uA 125uA/MHz 3.6V Stop 1uA 3.6V Stop 2.1uA 3.6V Stop 1.6uA Rev 1.01 Nano103 9 ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT DC Power Supply VDD-VSS -0.3 +3.6 V Battery Power Supply VBAT-VSS -0.3 +3.6 V Input Voltage on 5V Tolerance Pin VIN VSS -0.3 5.5 V Input Voltage on Any Other Pin without 5V Tolerance Pin VIN VSS -0.3 VDD +0.3 V 1/tCLCL 4 24 MHz Operating Temperature TA -40 +105 C Storage Temperature TST -55 +150 C Maximum Current into VDD - 150 mA Maximum Current out of VSS - 150 mA Maximum Current sunk by a I/O Pin - 25 mA Maximum Current Sourced by a I/O Pin - 25 mA Maximum Current Sunk by Total I/O Pins - 100 mA Maximum Current Sourced by Total I/O Pins - 100 mA Oscillator Frequency Note: Output voltage for ADC/ACMP/HXT/LXT/PA.8/PB.4/PB.5 shared pins cannot be higher than V DD because these pins are without 5V tolerance. NANO103 SERIES DATASHEET May. 02, 2018 Page 53 of 87 Rev 1.01 Nano103 9.2 Nano103 DC Electrical Characteristics (VDD-VSS=3.3V, TA = 25C, FOSC = 36 MHz unless otherwise specified.) SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. TYP. 2.2 - 3.6 V -0.3 - - V 1.62 1.8 1.98 V MCU operating in Run, Idle or Power-down mode 1.44 1.6 1.76 V Set LDO_LEVEL(LDO_CTL[3:2]) = 0x1 1.08 1.2 1.32 V Set LDO_LEVEL(LDO_CTL[3:2]) = 0x0 CLDO 1 - 1 uF Connect to LDO_CAP pin Analog Operating Voltage AVDD - VDD - V Battery Operating Voltage VBAT - VDD - V IDD1 - 14 - mA Operation Voltage Power Ground VDD VSS AVSS VLDO MAX. UNIT VDD = 2.2V up to 36 MHz LDO Output Voltage NANO103 SERIES DATASHEET Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X V V IDD2 - 6.9 - mA 3.6 V 16 MHz X V X IDD3 - 13.1 - mA 2.2 V 16 MHz X V V IDD4 - 6.7 - mA 2.2 V 16 MHz X V X Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash IDD5 - 13.7 - mA 3.6 V 12 MHz X V V IDD6 - 6.7 - mA 3.6 V 12 MHz X V X IDD7 - 12.9 - mA 2.2 V 12 MHz X V V VLDO=1.8 V IDD8 - 6.6 - mA 2.2 V 12 MHz X V X Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash IDD10 - 13.6 - mA 3.6 V 4 MHz X V V IDD11 - 6.4 - mA 3.6 V 4 MHz X V X IDD12 - 12.8 - mA 2.2 V 4 MHz X V V VLDO=1.8 V IDD13 - 6.3 - mA 2.2 V 4 MHz X V X IDD14 - 13.6 - mA VDD HXT HIRC1 PLL All digital module 3.6 V X 36 MHz X V 3.6 V X 36 MHz X X VLDO=1.8 V Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash May. 02, 2018 IDD15 - 6.7 - mA Page 54 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER VLDO=1.8 V Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD16 - 12.8 - mA 2.2 V X 36 MHz X V IDD17 - 6.3 - mA 2.2 V X 36 MHz X X IDD18 - 14.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V IDD19 - 6.7 - mA 3.6 V X 16 MHz V X IDD20 - 13.6 - mA 2.2 V X 16 MHz V V IDD21 - 6.5 - mA 2.2 V X 16 MHz V X Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash IDD22 - 14.5 - mA 3.6 V X 12 MHz V V IDD23 - 6.7 - mA 3.6 V X 12 MHz V X IDD24 - 13.6 - mA 2.2 V X 12 MHz V V VLDO=1.8 V IDD25 - 6.6 - mA 2.2 V X 12 MHz V X Operating Current Normal Run Mode HCLK =36 MHz while(1){}executed from flash IDD26 - 13.3 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.8 V IDD27 - 6.4 - mA 3.6 V X 4 MHz V X IDD28 - 12.6 - mA 2.2 V X 4 MHz V V IDD29 - 6.3 - mA 2.2 V X 4 MHz V X IDD30 - 7.3 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 18 MHz X X V VLDO=1.8 V IDD31 - 3.8 - mA 3.6 V 18 MHz X X X IDD32 - 7.1 - mA 2.2 V 18 MHz X X V IDD33 - 3.7 - mA 2.2 V 18 MHz X X X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD34 - 7.5 - mA 3.6 V 16 MHz X V V IDD35 - 3.9 - mA 3.6 V 16 MHz X V X IDD36 - 7.3 - mA 2.2 V 16 MHz X V V VLDO=1.8 V IDD37 - 3.8 - mA 2.2 V 16 MHz X V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD38 - 7.3 - mA 3.6 V 12 MHz X V V IDD39 - 3.7 - mA 3.6 V 12 MHz X V X IDD40 - 7.1 - mA 2.2 V 12 MHz X V V VLDO=1.8 V IDD41 - 3.7 - mA 2.2 V 12 MHz X V X IDD42 - 7.1 - mA 3.6 V 4 MHz X V V IDD43 - 3.5 - mA 3.6 V 4 MHz X V X IDD44 - 6.9 - mA 2.2 V 4 MHz X V V VLDO=1.8 V Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed May. 02, 2018 Page 55 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash Nano103 SPECIFICATIONS PARAMETER from flash VLDO=1.8 V Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD45 - 3.5 - mA IDD46 - 7.9 - mA 2.2 V 4 MHz X V X VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V IDD47 - 3.7 - mA 3.6 V X 16 MHz V X IDD48 - 7.7 - mA 2.2 V X 16 MHz V V IDD49 - 3.7 - mA 2.2 V X 16 MHz V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD50 - 7.7 - mA 3.6 V X 12 MHz V V IDD51 - 3.7 - mA 3.6 V X 12 MHz V X IDD52 - 7.5 - mA 2.2 V X 12 MHz V V VLDO1=1.8 V IDD53 - 3.6 - mA 2.2 V X 12 MHz V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD54 - 6.9 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.8 V IDD55 - 3.4 - mA 3.6 V X 4 MHz V X IDD56 - 6.8 - mA 2.2 V X 4 MHz V V IDD57 - 3.4 - mA 2.2 V X 4 MHz V X IDD58 - 6.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X X V VLDO=1.8 V NANO103 SERIES DATASHEET Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD59 - 3.3 - mA 3.6 V 16 MHz X X X IDD60 - 6.3 - mA 2.2 V 16 MHz X X V IDD61 - 3.3 - mA 2.2 V 16 MHz X X X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD62 - 6.5 - mA 3.6 V 12 MHz X V V IDD63 - 3.4 - mA 3.6 V 12 MHz X V X IDD64 - 6.4 - mA 2.2 V 12 MHz X V V VLDO1=1.8 V IDD65 - 3.4 - mA 2.2 V 12 MHz X V X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD66 - 6.3 - mA 3.6 V 4 MHz X V V IDD67 - 3.1 - mA 3.6 V 4 MHz X V X IDD68 - 6.3 - mA 2.2 V 4 MHz X V V VLDO1=1.8 V IDD69 - 3.1 - mA 2.2 V 4 MHz X V X IDD70 - 6.8 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz X V VLDO=1.8 V Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash VLDO=1.8 V May. 02, 2018 IDD71 - 3.1 - mA 3.6 V X 16 MHz X X IDD72 - 6.7 - mA 2.2 V X 16 MHz X V Page 56 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD73 - 3.1 - mA 2.2 V X 16 MHz X X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD74 - 7 - mA 3.6 V X 12 MHz V V IDD75 - 3.3 - mA 3.6 V X 12 MHz V X IDD76 - 6.8 - mA 2.2 V X 12 MHz V V VLDO1=1.8 V IDD77 - 3.2 - mA 2.2 V X 12 MHz V X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD78 - 6.2 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IDD79 - 3.1 - mA 3.6 V X 4 MHz V X IDD80 - 6.1 - mA 2.2 V X 4 MHz V V IDD81 - 3.1 - mA 2.2 V X 4 MHz V X IDD82 - 4.9 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 12 MHz X X V VLDO=1.8 V Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD83 - 2.5 - mA 3.6 V 12 MHz X X X IDD84 - 4.8 - mA 2.2 V 12 MHz X X V IDD85 - 2.5 - mA 2.2 V 12 MHz X X X Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD86 - 4.9 - mA 3.6 V 4 MHz X V V IDD87 - 2.5 - mA 3.6 V 4 MHz X V X IDD88 - 4.8 - mA 2.2 V 4 MHz X V V VLDO=1.8 V IDD89 - 2.5 - mA 2.2 V 4 MHz X V X Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD90 - 5.3 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 12 MHz X V VLDO=1.8 V - 2.5 - mA 3.6 V X 12 MHz X X IDD92 - 5.2 - mA 2.2 V X 12 MHz X V IDD93 - 2.5 - mA 2.2 V X 12 MHz X X IDD94 - 4.8 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.8 V Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD95 - 2.4 - mA 3.6 V X 4 MHz V X IDD96 - 4.7 - mA 2.2 V X 4 MHz V V IDD97 - 2.4 - mA 2.2 V X 4 MHz V X IDD98 - 1.1 - mA VDD HXT MIRC PLL All digital module 3.6 V 4 MHz X X V 3.6 V 4 MHz X X X VLDO=1.8 V Operating Current Normal Run Mode HCLK =4 MHz while(1){}executed from flash May. 02, 2018 IDD99 - 0.7 - mA Page 57 of 87 Rev 1.01 NANO103 SERIES DATASHEET IDD91 Nano103 SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. TYP. IDD100 - 1.1 - mA 2.2 V 4 MHz X X V IDD101 - 0.7 - mA 2.2 V 4 MHz X X X Operating Current Normal Run Mode HCLK =4 MHz while(1){}executed from flash IDD102 - 1.7 - mA 3.6 V X 4 MHz X V IDD103 - 1 - mA 3.6 V X 4 MHz X X IDD104 - 1.7 - mA 2.2 V X 4 MHz X V VLDO=1.8 V IDD105 - 0.9 - mA 2.2 V X 4 MHz X X Operating Current Normal Run Mode HCLK =32.768 kHz while(1){}executed from flash IDD106 - 148 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V VLDO=1.8 V MAX. UNIT IDD107 - 130 - uA 3.6 V 32.768 kHz X X X IDD108 - 126 - uA 2.2 V 32.768 kHz X X V IDD109 - 120 - uA 2.2 V 32.768 kHz X X X Operating Current Normal Run Mode HCLK =10 kHz while(1){}executed from flash IDD110 - 128 - uA 3.6 V X 10 kHz X V IDD111 - 126 - uA 3.6 V X 10 kHz X X IDD112 - 118 - uA 2.2 V X 10 kHz X V VLDO=1.8 V IDD113 - 116 - uA 2.2 V X 10 kHz X X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD114 - 6.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 18 MHz X X V VLDO=1.8 V NANO103 SERIES DATASHEET IDD115 - 3.4 - mA 3.6 V 18 MHz X X X IDD116 - 6.4 - mA 2.2 V 18 MHz X X V IDD117 - 3.3 - mA 2.2 V 18 MHz X X X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD118 - 6.6 - mA 3.6 V 16 MHz X V V IDD119 - 3.5 - mA 3.6 V 16 MHz X V X IDD120 - 6.6 - mA 2.2 V 16 MHz X V V VLDO=1.6 V IDD121 - 3.4 - mA 2.2 V 16 MHz X V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD122 - 6.5 - mA 3.6 V 12 MHz X V V IDD123 - 3.3 - mA 3.6 V 12 MHz X V X IDD124 - 6.4 - mA 2.2 V 12 MHz X V V VLDO=1.6 V IDD125 - 3.3 - mA 2.2 V 12 MHz X V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD126 - 6.2 - mA 3.6 V 4 MHz X V V IDD127 - 3.1 - mA 3.6 V 4 MHz X V X IDD128 - 6.2 - mA 2.2 V 4 MHz X V V VLDO=1.6 V IDD129 - 3.1 - mA 2.2 V 4 MHz X V X VLDO=1.6 V May. 02, 2018 Page 58 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash SYM. IDD130 TEST CONDITIONS MIN. TYP. - 7 MAX. UNIT - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V IDD131 - 3.3 - mA 3.6 V X 16 MHz V X IDD132 - 7 - mA 2.2 V X 16 MHz V V IDD133 - 3.3 - mA 2.2 V X 16 MHz V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD134 - 6.9 - mA 3.6 V X 12 MHz V V IDD135 - 3.3 - mA 3.6 V X 12 MHz V X IDD136 - 6.8 - mA 2.2 V X 12 MHz V V VLDO1=1.6 V IDD137 - 3.3 - mA 2.2 V X 12 MHz V X Operating Current Normal Run Mode HCLK =18 MHz while(1){}executed from flash IDD138 - 6.2 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.6 V IDD139 - 3.1 - mA 3.6 V X 4 MHz V X IDD140 - 6.1 - mA 2.2 V X 4 MHz V V IDD141 - 3 - mA 2.2 V X 4 MHz V X IDD142 - 5.7 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X X V VLDO=1.6 V Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash - 2.9 - mA 3.6 V 16 MHz X X X IDD144 - 5.7 - mA 2.2 V 16 MHz X X V IDD145 - 2.9 - mA 2.2 V 16 MHz X X X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD146 - 5.8 - mA 3.6 V 12 MHz X V V IDD147 - 3 - mA 3.6 V 12 MHz X V X IDD148 - 5.7 - mA 2.2 V 12 MHz X V V VLDO1=1.6 V IDD149 - 3 - mA 2.2 V 12 MHz X V X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD150 - 5.6 - mA 3.6 V 4 MHz X V V IDD151 - 2.8 - mA 3.6 V 4 MHz X V X IDD152 - 5.6 - mA 2.2 V 4 MHz X V V VLDO1=1.6 V IDD153 - 2.8 - mA 2.2 V 4 MHz X V X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD154 - 6 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz X V VLDO=1.6 V IDD155 - 2.8 - mA 3.6 V X 16 MHz X X IDD156 - 5.9 - mA 2.2 V X 16 MHz X V IDD157 - 2.8 - mA 2.2 V X 16 MHz X X VLDO=1.6 V May. 02, 2018 Page 59 of 87 Rev 1.01 NANO103 SERIES DATASHEET IDD143 Nano103 SPECIFICATIONS PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD158 - 6.2 - mA 3.6 V X 12 MHz V V IDD159 - 3 - mA 3.6 V X 12 MHz V X IDD160 - 6.2 - mA 2.2 V X 12 MHz V V VLDO1=1.6 V IDD161 - 3 - mA 2.2 V X 12 MHz V X Operating Current Normal Run Mode HCLK =16 MHz while(1){}executed from flash IDD162 - 5.5 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IDD163 - 2.8 - mA 3.6 V X 4 MHz V X IDD164 - 5.5 - mA 2.2 V X 4 MHz V V IDD165 - 2.8 - mA 2.2 V X 4 MHz V X IDD166 - 4.3 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 12 MHz X X V VLDO=1.6 V Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD167 - 2.2 - mA 3.6 V 12 MHz X X X IDD168 - 4.3 - mA 2.2 V 12 MHz X X V IDD169 - 2.2 - mA 2.2 V 12 MHz X X X Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD170 - 4.3 - mA 3.6 V 4 MHz X V V IDD171 - 2.3 - mA 3.6 V 4 MHz X V X IDD172 - 4.3 - mA 2.2 V 4 MHz X V V VLDO=1.6 V IDD173 - 2.3 - mA 2.2 V 4 MHz X V X Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD174 - 4.7 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 12 MHz X V VLDO=1.6 V NANO103 SERIES DATASHEET IDD175 - 2.2 - mA 3.6 V X 12 MHz X X IDD176 - 4.7 - mA 2.2 V X 12 MHz X V IDD177 - 2.2 - mA 2.2 V X 12 MHz X X IDD178 - 4.3 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.6 V Operating Current Normal Run Mode HCLK =12 MHz while(1){}executed from flash IDD179 - 2.2 - mA 3.6 V X 4 MHz V X IDD180 - 4.2 - mA 2.2 V X 4 MHz V V IDD181 - 2.2 - mA 2.2 V X 4 MHz V X IDD182 - 1 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 4 MHz X X V VLDO=1.6 V Operating Current Normal Run Mode HCLK =4 MHz while(1){}executed from flash VLDO=1.6 V May. 02, 2018 IDD183 - 0.6 - mA 3.6 V 4 MHz X X X IDD184 - 1 - mA 2.2 V 4 MHz X X V Page 60 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER Operating Current Normal Run Mode HCLK =4 MHz while(1){}executed from flash SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD185 - 0.6 - mA IDD186 - 1.6 - mA 2.2 V 4 MHz X X X VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz X V IDD187 - 0.9 - mA 3.6 V X 4 MHz X X IDD188 - 1.5 - mA 2.2 V X 4 MHz X V IDD189 - 0.9 - mA 2.2 V X 4 MHz X X IDD190 - 147 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V VLDO=1.6 V Operating Current Normal Run Mode HCLK =32.768 kHz while(1){}executed from flash IDD191 - 141 - uA 3.6 V 32.768 kHz X X X IDD192 - 124 - uA 2.2 V 32.768 kHz X X V IDD193 - 119 - uA 2.2 V 32.768 kHz X X X Operating Current Normal Run Mode HCLK =10 kHz while(1){}executed from flash IDD194 - 139 - uA 3.6 V X 10 kHz X V IDD195 - 137 - uA 3.6 V X 10 kHz X X IDD196 - 117 - uA 2.2 V X 10 kHz X V VLDO=1.6 V IDD197 - 115 - uA 2.2 V X 10 kHz X X IDD198 - 0.9 - mA VDD HXT MIRC PLL Operating Current Normal Run Mode HCLK =2 MHz while(1){}executed from flash VLDO=1.2 V All digital module 3.6 V 4 MHz X X V VLDO=1.6 V Operating Current Normal Run Mode HCLK =32 kHz while(1){}executed from flash VLDO=1.2 V Operating Current Normal Run Mode HCLK =10 kHz May. 02, 2018 - 0.6 - mA 3.6 V 4 MHz X X X IDD200 - 0.9 - mA 2.2 V 4 MHz X X V IDD4 - 0.6 - mA 2.2 V 4 MHz X X X IDD201 - 0.8 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz X V IDD202 - 0.5 - mA 3.6 V X 4 MHz X X IDD203 - 0.8 - mA 2.2 V X 4 MHz X V IDD204 - 0.5 - mA 2.2 V X 4 MHz X X IDD205 - 218 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V IDD206 - 225 - uA 3.6 V 32.768 kHz X X X IDD207 - 206 - uA 2.2 V 32.768 kHz X X V IDD208 - 202 - uA 2.2 V 32.768 kHz X X X IDD209 - 122 - uA VDD LXT MIRC PLL All digital module 3.6 V X 10 kHz X V Page 61 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Normal Run Mode HCLK =2 MHz while(1){}executed from flash VLDO=1.2 V IDD199 Nano103 SPECIFICATIONS PARAMETER while(1){}executed from flash VLDO=1.2 V SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD210 - 121 - uA 3.6 V X 10 kHz X X IDD211 - 112 - uA 2.2 V X 10 kHz X V IDD212 - 111 - uA 2.2 V X 10 kHz X X IIDLE1 - 9.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X V V Operating Current Idle Mode HCLK =36 MHz IIDLE2 - 2.4 - mA 3.6 V 16 MHz X V X VLDO=1.8 V IIDLE3 - 9.1 - mA 2.2 V 16 MHz X V V IIDLE4 - 2.4 - mA 2.2 V 16 MHz X V X IIDLE5 - 9.3 - mA 3.6 V 12 MHz X V V IIDLE6 - 2.2 - mA 3.6 V 12 MHz X V X IIDLE7 - 9 - mA 2.2 V 12 MHz X V V IIDLE8 - 2.2 - mA 2.2 V 12 MHz X V X IIDLE9 - 9.1 - mA 3.6 V 4 MHz X V V IIDLE10 - 2 - mA 3.6 V 4 MHz X V X IIDLE11 - 8.8 - mA 2.2 V 4 MHz X V V IIDLE12 - 2 - mA 2.2 V 4 MHz X V X IIDLE13 - 9 - mA VDD HXT HIRC1 PLL All digital module 3.6 V X 36 MHz X V Operating Current Idle Mode HCLK =36 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =36 MHz VLDO=1.8 V NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =36 MHz VLDO=1.8 V IIDLE14 - 1.9 - mA 3.6 V X 36 MHz X X IIDLE15 - 8.8 - mA 2.2 V X 36 MHz X V IIDLE16 - 1.9 - mA 2.2 V X 36 MHz X X IIDLE17 - 10.1 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V Operating Current Idle Mode HCLK =36 MHz IIDLE18 - 2.3 - mA 3.6 V X 16 MHz V X VLDO=1.8 V IIDLE19 - 9.7 - mA 2.2 V X 16 MHz V V IIDLE20 - 2.2 - mA 2.2 V X 16 MHz V X IIDLE21 - 10 - mA 3.6 V X 12 MHz V V IIDLE22 - 2.2 - mA 3.6 V X 12 MHz V X IIDLE23 - 9.6 - mA 2.2 V X 12 MHz V V IIDLE24 - 2.2 - mA 2.2 V X 12 MHz V X IIDLE25 - 9 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V Operating Current Idle Mode HCLK =36 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =36 MHz May. 02, 2018 Page 62 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER VLDO=1.8 V SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE26 - 6.3 - mA 3.6 V X 4 MHz V X IIDLE27 - 8.7 - mA 2.2 V X 4 MHz V V IIDLE28 - 6.2 - mA 2.2 V X 4 MHz V X IIDLE29 - 5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 18 MHz X X V IIDLE30 - 1.5 - mA 3.6 V 18 MHz X X X VLDO=1.8 V IIDLE31 - 5 - mA 2.2 V 18 MHz X X V IIDLE32 - 1.5 - mA 2.2 V 18 MHz X X X IIDLE33 - 5.2 - mA 3.6 V 16 MHz X V V IIDLE34 - 1.7 - mA 3.6 V 16 MHz X V X IIDLE35 - 5.1 - mA 2.2 V 16 MHz X V V IIDLE36 - 1.6 - mA 2.2 V 16 MHz X V X IIDLE37 - 5.1 - mA 3.6 V 12 MHz X V V IIDLE38 - 1.5 - mA 3.6 V 12 MHz X V X IIDLE39 - 5. - mA 2.2 V 12 MHz X V V IIDLE40 - 1.5 - mA 2.2 V 12 MHz X V X IIDLE41 - 4.8 - mA 3.6 V 4 MHz X V V IIDLE42 - 1.3 - mA 3.6 V 4 MHz X V X IIDLE43 - 4.8 - mA 2.2 V 4 MHz X V V IIDLE44 - 1.2 - mA 2.2 V 4 MHz X V X IIDLE45 - 5.6 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V Operating Current Idle Mode HCLK =18 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =18 MHz IIDLE46 - 1.5 - mA 3.6 V X 16 MHz V X VLDO=1.8 V IIDLE47 - 5.6 - mA 2.2 V X 16 MHz V V IIDLE48 - 1.5 - mA 2.2 V X 16 MHz V X IIDLE49 - 5.5 - mA 3.6 V X 12 MHz V V IIDLE50 - 3.7 - mA 3.6 V X 12 MHz V X IIDLE51 - 5.4 - mA 2.2 V X 12 MHz V V IIDLE52 - 3.6 - mA 2.2 V X 12 MHz V X Operating Current Idle Mode HCLK =18 MHz IIDLE53 - 4.7 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V VLDO=1.8 V IIDLE54 3.6 V X 4 MHz V X Operating Current Idle Mode HCLK =18 MHz VLDO=1.8 V May. 02, 2018 - 1.2 - mA Page 63 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =18 MHz Nano103 SPECIFICATIONS PARAMETER Operating Current Idle Mode HCLK =16 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.8 V NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =16 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =16 MHz SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE55 - 4.7 - mA 2.2 V X 4 MHz V V IIDLE56 - 1.2 - mA 2.2 V X 4 MHz V X IIDLE57 - 4.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X X V IIDLE58 - 1.3 - mA 3.6 V 16 MHz X X X IIDLE59 - 4.4 - mA 2.2 V 16 MHz X X V IIDLE60 - 1.3 - mA 2.2 V 16 MHz X X X IIDLE61 - 4.6 - mA 3.6 V 12 MHz X V V IIDLE62 - 1.4 - mA 3.6 V 12 MHz X V X IIDLE63 - 4.5 - mA 2.2 V 12 MHz X V V IIDLE64 - 1.4 - mA 2.2 V 12 MHz X V X IIDLE65 - 4.3 - mA 3.6 V 4 MHz X V V IIDLE66 - 1.2 - mA 3.6 V 4 MHz X V X IIDLE67 - 4.3 - mA 2.2 V 4 MHz X V V IIDLE68 - 1.2 - mA 2.2 V 4 MHz X V X IIDLE69 - 4.9 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz X V IIDLE70 - 1.2 - mA 3.6 V X 16 MHz X X IIDLE71 - 4.8 - mA 2.2 V X 16 MHz X V IIDLE72 - 1.2 - mA 2.2 V X 16 MHz X X IIDLE73 - 5 - mA 3.6 V X 12 MHz V V IIDLE74 - 1.4 - mA 3.6 V X 12 MHz V X IIDLE75 - 5 - mA 2.2 V X 12 MHz V V IIDLE76 - 1.4 - mA 2.2 V X 12 MHz V X IIDLE77 - 4.3 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IIDLE78 - 1.1 - mA 3.6 V X 4 MHz V X IIDLE79 - 4.2 - mA 2.2 V X 4 MHz V V IIDLE80 - 1.1 - mA 2.2 V X 4 MHz V X Operating Current Idle Mode HCLK =12 MHz IIDLE81 - 3.4 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 12 MHz X X V VLDO=1.8 V IIDLE82 3.6 V 12 MHz X X X VLDO=1.8 V May. 02, 2018 - 1 - mA Page 64 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER Operating Current Idle Mode HCLK =12 MHz VLDO=1.8 V SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE83 - 3.3 - mA 2.2 V 12 MHz X X V IIDLE84 - 1 - mA 2.2 V 12 MHz X X X IIDLE85 - 3.4 - mA 3.6 V 4 MHz X V V IIDLE86 - 1 - mA 3.6 V 4 MHz X V X IIDLE87 - 3.3 - mA 2.2 V 4 MHz X V V IIDLE88 - 1 - mA 2.2 V 4 MHz X V X IIDLE89 - 3.8 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 12 MHz X V Operating Current Idle Mode HCLK =12 MHz IIDLE90 - 1 - mA 3.6 V X 12 MHz X X VLDO=1.8 V IIDLE91 - 3.7 - mA 2.2 V X 12 MHz X V IIDLE92 - 1 - mA 2.2 V X 12 MHz X X IIDLE93 - 3.3 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V Operating Current Idle Mode HCLK =12 MHz VLDO=1.8 V VLDO=1.8 V Operating Current Idle Mode HCLK =4 MHz VLDO=1.8 V Operating Current Idle Mode HCLK =32.768 kHz VLDO=1.8 V Operating Current Operating Current Idle Mode May. 02, 2018 - 1 - mA 3.6 V X 4 MHz V X IIDLE95 - 3.3 - mA 2.2 V X 4 MHz V V IIDLE96 - 0.9 - mA 2.2 V X 4 MHz V X IIDLE97 - 0.9 - mA VDD HXT MIRC PLL All digital module 3.6 V 4 MHz X X V IIDLE98 - 0.5 - mA 3.6 V 4 MHz X X X IIDLE99 - 0.9 - mA 2.2 V 4 MHz X X V IIDLE100 - 0.4 - mA 2.2 V 4 MHz X X X IIDLE101 - 1.2 - mA 3.6 V X 4 MHz X V IIDLE102 - 0.5 - mA 3.6 V X 4 MHz X X IIDLE103 - 1.2 - mA 2.2 V X 4 MHz X V IIDLE104 - 0.4 - mA 2.2 V X 4 MHz X X IIDLE105 - 132 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V IIDLE106 - 126 - uA 3.6 V 32.768 kHz X X X IIDLE107 - 122 - uA 2.2 V 32.768 kHz X X V IIDLE108 - 116 - uA 2.2 V 32.768 kHz X X X IIDLE109 - 127 - uA 3.6 V X 10 kHz X V IIDLE110 - 125 - uA 3.6 V X 10 kHz X X Page 65 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =4 MHz IIDLE94 Nano103 SPECIFICATIONS PARAMETER HCLK =10 kHz SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE111 - 116 - uA 2.2 V X 10 kHz X V IIDLE112 - 114 - uA 2.2 V X 10 kHz X X IIDLE113 - 4.5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 18 MHz X X V VLDO=1.8 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz NANO103 SERIES DATASHEET VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =18 MHz VLDO=1.6 V May. 02, 2018 IIDLE114 - 1.3 - mA 3.6 V 18 MHz X X X IIDLE115 - 4.4 - mA 2.2 V 18 MHz X X V IIDLE116 - 1.3 - mA 2.2 V 18 MHz X X X IIDLE117 - 4.6 - mA 3.6 V 16 MHz X V V mA 3.6 V 16 MHz X V X IIDLE118 1.5 IIDLE119 - 4.6 - mA 2.2 V 16 MHz X V V IIDLE120 - 1.4 - mA 2.2 V 16 MHz X V X IIDLE121 - 4.5 - mA 3.6 V 12 MHz X V V mA 3.6 V 12 MHz X V X IIDLE122 1.4 IIDLE123 - 4.4 - mA 2.2 V 12 MHz X V V IIDLE124 - 1.3 - mA 2.2 V 12 MHz X V X IIDLE125 - 4.3 - mA 3.6 V 4 MHz X V V mA 3.6 V 4 MHz X V X IIDLE126 1.1 IIDLE127 - 4.2 - mA 2.2 V 4 MHz X V V IIDLE128 - 1.1 - mA 2.2 V 4 MHz X V X IIDLE129 - 5 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz V V IIDLE130 - 1.4 - mA 3.6 V X 16 MHz V X IIDLE131 - 5 - mA 2.2 V X 16 MHz V V IIDLE132 - 1.3 - mA 2.2 V X 16 MHz V X IIDLE133 - 4.9 - mA 3.6 V X 12 MHz V V mA 3.6 V X 12 MHz V X IIDLE134 3.3 IIDLE135 - 4.8 - mA 2.2 V X 12 MHz V V IIDLE136 - 3.3 - mA 2.2 V X 12 MHz V X IIDLE137 - 4.2 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IIDLE138 - 1.1 - mA 3.6 V X 4 MHz V X IIDLE139 - 4.2 - mA 2.2 V X 4 MHz V V Page 66 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER Operating Current Idle Mode HCLK =16 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =16 MHz VLDO=1.6 V VLDO=1.6 V TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE140 - 1.1 - mA IIDLE141 - 3.9 - mA 2.2 V X 4 MHz V X VDD HXT HIRC0 PLL All digital module 3.6 V 16 MHz X X V IIDLE142 - 1.2 - mA 3.6 V 16 MHz X X X IIDLE143 - 3.9 - mA 2.2 V 16 MHz X X V IIDLE144 - 1.1 - mA 2.2 V 16 MHz X X X IIDLE145 - 4.1 - mA 3.6 V 12 MHz X V V IIDLE146 - 1.3 - mA 3.6 V 12 MHz X V X IIDLE147 - 4 - mA 2.2 V 12 MHz X V V IIDLE148 - 1.3 - mA 2.2 V 12 MHz X V X IIDLE149 - 3.9 - mA 3.6 V 4 MHz X V V IIDLE150 - 1.1 - mA 3.6 V 4 MHz X V X IIDLE151 - 3.8 - mA 2.2 V 4 MHz X V V IIDLE152 - 1 - mA 2.2 V 4 MHz X V X IIDLE153 - 4.3 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 16 MHz X V IIDLE154 - 1.1 - mA 3.6 V X 16 MHz X X IIDLE155 - 4.3 - mA 2.2 V X 16 MHz X V IIDLE156 - 1 - mA 2.2 V X 16 MHz X X IIDLE157 - 4.4 - mA 3.6 V X 12 MHz V V IIDLE158 - 1.3 - mA 3.6 V X 12 MHz V X IIDLE159 - 4.4 - mA 2.2 V X 12 MHz V V IIDLE160 - 1.2 - mA 2.2 V X 12 MHz V X IIDLE161 - 3.8 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V Operating Current Idle Mode HCLK =16 MHz IIDLE162 - 1 - mA 3.6 V X 4 MHz V X VLDO=1.6 V IIDLE163 - 3.8 - mA 2.2 V X 4 MHz V V IIDLE164 - 1 - mA 2.2 V X 4 MHz V X IIDLE165 - 3 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 12 MHz X X V Operating Current Idle Mode HCLK =12 MHz VLDO=1.6 V May. 02, 2018 IIDLE166 - 0.9 - mA 3.6 V 12 MHz X X X IIDLE167 - 3 - mA 2.2 V 12 MHz X X V Page 67 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =16 MHz SYM. Nano103 SPECIFICATIONS PARAMETER Operating Current Idle Mode HCLK =12 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =12 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =12 MHz VLDO=1.6 V NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =4 MHz VLDO=1.6 V Operating Current Idle Mode HCLK =4 MHz VLDO=1.6 V SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE168 - 0.9 - mA 2.2 V 12 MHz X X X IIDLE169 - 3 - mA 3.6 V 4 MHz X V V IIDLE170 - 0.9 - mA 3.6 V 4 MHz X V X IIDLE171 - 3 - mA 2.2 V 4 MHz X V V IIDLE172 - 0.9 - mA 2.2 V 4 MHz X V X IIDLE173 - 3.4 - mA VDD HXT HIRC0 PLL All digital module 3.6 V X 12 MHz X V IIDLE174 - 0.9 - mA 3.6 V X 12 MHz X X IIDLE175 - 3.3 - mA 2.2 V X 12 MHz X V IIDLE176 - 0.9 - mA 2.2 V X 12 MHz X X IIDLE177 - 3 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IIDLE178 - 0.9 - mA 3.6 V X 4 MHz V X IIDLE179 - 2.9 - mA 2.2 V X 4 MHz V V IIDLE180 - 0.9 - mA 2.2 V X 4 MHz V X IIDLE181 - 0.8 - mA VDD HXT HIRC0 PLL All digital module 3.6 V 4 MHz X X V IIDLE182 - 0.4 - mA 3.6 V 4 MHz X X X IIDLE183 - 0.8 - mA 2.2 V 4 MHz X X V IIDLE184 - 0.4 - mA 2.2 V 4 MHz X X X IIDLE185 - 1.1 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz V V IIDLE186 - 0.4 - mA 3.6 V X 4 MHz V X IIDLE187 - 1.1 - mA 2.2 V X 4 MHz V V IIDLE188 - 0.4 - mA 2.2 V X 4 MHz V X IIDLE189 - 143 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V Operating Current Idle Mode HCLK =32.768 kHz IIDLE190 - 138 - uA 3.6 V 32.768 kHz X X X VLDO=1.6 V IIDLE191 - 120 - uA 2.2 V 32.768 kHz X X V IIDLE192 - 115 - uA 2.2 V 32.768 kHz X X X IIDLE193 - 138 - uA 3.6 V X 10 kHz X V IIDLE194 - 136 - uA 3.6 V X 10 kHz X X Operating Current Idle Mode HCLK =10 kHz May. 02, 2018 Page 68 of 87 Rev 1.01 Nano103 SPECIFICATIONS PARAMETER VLDO=1.6 V Operating Current Idle Mode HCLK =2 MHz VLDO=1.2 V SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE195 - 116 - uA 2.2 V X 10 kHz X V IIDLE196 - 114 - uA 2.2 V X 10 kHz X X IIDLE197 - 0.7 - mA VDD HXT MIRC PLL All digital module 3.6 V 4 MHz X X V IIDLE198 - 0.4 - mA 3.6 V 4 MHz X X X IIDLE199 - 0.7 - mA 2.2 V 4 MHz X X V IIDLE200 - 0.4 - mA 2.2 V 4 MHz X X X IIDLE201 - 0.7 - mA VDD HXT MIRC PLL All digital module 3.6 V X 4 MHz X V Operating Current Idle Mode HCLK =2 MHz IIDLE202 - 0.3 - mA 3.6 V X 4 MHz X X VLDO=1.2 V IIDLE203 - 0.7 - mA 2.2 V X 4 MHz X V IIDLE204 - 0.3 - mA 2.2 V X 4 MHz X X IIDLE205 - 215 - uA VDD LXT LIRC PLL All digital module 3.6 V 32.768 kHz X X V Operating Current Idle Mode HCLK =32.768 kHz VLDO=1.2 V VLDO=1.2 V Standby Current Power-down Mode - 211 - uA 3.6 V 32.768 kHz X X X IIDLE207 - 204 - uA 2.2 V 32.768 kHz X X V IIDLE208 - 200 - uA 2.2 V 32.768 kHz X X X IIDLE209 - 122 - uA VDD LXT LIRC PLL All digital module 3.6 V X 10 kHz X V IIDLE210 - 132 - uA 3.6 V X 10 kHz X X IIDLE211 - 112 - uA 2.2 V X 10 kHz X V IIDLE212 - 111 - uA 2.2 V X 10 kHz X X IPWD1 - 1.7 - uA RTC RAM retention VDD HXT/HIRC/PLL LXT(kHz) 3.6 V X X X V IPWD2 - 2.3 - uA 3.6 V X 32.768 V V IPWD3 - 1.6 - uA 2.2 V X X X V IPWD4 - 2.2 - uA 2.2 V X 32.768 V V IPWD5 - 1.6 - uA 3.6 V X X X V Standby Current Power-down Mode IPWD6 - 2.2 - uA 3.6 V X 32.768 V V VLDO=1.6 V IPWD7 - 1.5 - uA 2.2 V X X X V IPWD8 - 2.1 - uA 2.2 V X 32.768 V V IPWD9 - 1.6 - uA 3.6 V X X X V VLDO=1.8 V Standby Current May. 02, 2018 Page 69 of 87 Rev 1.01 NANO103 SERIES DATASHEET Operating Current Idle Mode HCLK =10 kHz IIDLE206 Nano103 SPECIFICATIONS PARAMETER Power-down Mode SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IPWD10 - 2.1 - uA 3.6 V X 32.768 V V IPWD11 - 1.4 - uA 2.2 V X X X V IPWD12 - 2.0 - uA 2.2 V X 32.768 V V VLDO=1.2 V - 42 - KΩ VDD = 3.3V - 106 - KΩ VDD = 2.2V ILK -1 - 1 A VDD = 3.3V, 0