CD74HCT4515E




        
    
 SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 D 4.5-V to 5.5-V VCC Operation D Fanout (Over Temperature Range) D D D D − Standard Outputs . . . 10 LSTTL Loads − Bus-Driver Outputs . . . 15 LSTTL Loads Wide Operating Temperature Range of −55°C to 125°C Balanced Propagation Delays and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HCT Types − Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) − CMOS Input Compatibility, II ≤ 1 µA at VOL, VOH CD74HCT4514 . . . E PACKAGE CD74HCT4515 . . . E OR EN PACKAGE (TOP VIEW) LE A0 A1 Y7 Y6 Y5 Y4 Y3 Y1 Y2 Y0 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC E A3 A2 Y10 Y11 Y8 Y9 Y14 Y15 Y12 Y13 description/ordering information The CD74HCT4514 and CD74HCT4515 are high-speed silicon-gate devices consisting of a 4-bit strobed latch and a 4-line to 16-line decoder. The selected output is enabled by a low on the enable (E) input. A high on E inhibits selection of any output. Demultiplexing is accomplished by using E as the data input and the select inputs (A0−A3) as addresses. E also serves as a chip select when these devices are cascaded. When the latch enable (LE) is high, the output follows changes in the inputs (see decode function table). When LE is low, the output is isolated from changes in the input and remains at the level (high for the ’4514, low for the ’4515) it had before the latch was enabled. ORDERING INFORMATION PACKAGE† TA PDIP − E Tube PDIP − EN Tube −55°C 125°C −55 C to 125 C ORDERABLE PART NUMBER TOP-SIDE MARKING CD74HCT4514E CD74HCT4514E CD74HCT4515E CD74HCT4515E CD74HCT4515EN CD74HCT4515EN † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated 
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 SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 DECODE FUNCTION TABLE (LE = H) DECODER INPUTS E A1 A0 ADDRESSED OUTPUT CD74HCT4514 = H CD74HCT4515 = L A3 A2 L L L L L Y0 L L L L H Y1 L L L H L Y2 L L L H H Y3 L L H L L Y4 L L H L H Y5 L L H H L Y6 L L H H H Y7 L H L L L Y8 L H L L H Y9 L H L H L Y10 L H L H H Y11 L H H L L Y12 L H H L H Y13 L H H H L Y14 L H H H H Y15 H X X X X All outputs = L, CD74HCT4514 All outputs = H, CD74HCT4515 H = high, L = low, X = don’t care logic diagram (positive logic) CD74HCT4514 CD74HCT4515 A0 A1 A2 A3 LE 2 3 21 22 Latch 4-Line to 16-Line Decoder Y0 Y1 Y2 Y0 Y1 Y2 8 7 Y3 Y4 Y3 Y4 6 5 4 Y5 Y6 Y7 Y5 Y6 Y7 18 Y8 Y8 17 Y9 Y9 20 16 Y10 Y11 Y12 Y13 Y14 Y10 Y11 Y12 Y13 Y14 15 Y15 Y15 19 14 13 1 23 GND = 12 VCC = 24 E 2 11 9 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



        
    
 SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-3. recommended operating conditions (see Note 3) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage 2 2 0.8 Input transition rise or fall rate VCC VCC 2 0.8 0 0 500 VCC VCC 0 0 500 UNIT V V 0.8 V VCC VCC V 500 ns V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = −20 µA IOH = −4 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 4.5 V II ICC VI = VCC or 0 VI = VCC or 0, ∆ICC‡ One input at VCC − 2.1 V, IO = 0 Other inputs at 0 or VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX 4.4 4.4 4.4 3.98 3.7 3.84 UNIT MAX V 0.1 0.1 0.1 0.26 0.4 0.33 5.5 V ±0.1 ±1 ±1 µA 5.5 V 8 160 80 µA 360 490 450 µA 4.5 V to 5.5 V V Ci 10 10 10 pF ‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 



        
    
 SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 HCT INPUT LOADING TABLE INPUT UNIT LOAD A0−A3 0.15 LE 0.85 E 0.3 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 360 µA max at 25°C). timing requirements over recommended operating free-air temperature range, VCC = 4.5 V, CL = 15 pF (unless otherwise noted) (see Figure 1) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX UNIT MAX tw Pulse duration, LE high 30 45 38 ns tsu Setup time, data before LE↓ 20 30 25 ns th Hold time, data after LE↓ 5 5 5 ns switching characteristics over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE Y CL = 50 pF Y CL = 50 pF TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN A0−A3 tpd LE E tt MAX MAX UNIT MAX 55 83 69 50 75 63 40 60 50 15 22 19 ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TYP Power dissipation capacitance 75 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF 



        
    
 SCHS314D − MAY 2002 − REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT 3V 1.3 V Input 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.3 V 1.3 V 0V 0V tsu trec Data 1.3 V Input 0.3 V 3V 1.3 V CLK th 2.7 V 2.7 V tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% 90% tPHL 90% 1.3 V 1.3 V 0V tPHL 90% tr Out-of-Phase Output 3V Output Control VOH 1.3 V 10% tf VOL tPLH 1.3 V 10% tf 1.3 V 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ≈VCC 1.3 V Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL tPLZ tPZL Output Waveform 1 (see Note B) 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 29-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD74HCT4514E LIFEBUY PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4514E CD74HCT4514EE4 LIFEBUY PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4514E CD74HCT4515E LIFEBUY PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4515E CD74HCT4515EN LIFEBUY PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4515EN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-May-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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