IS32FL3237-TQLA3-TR

IS32FL3237 36-CHANNEL LED DRIVER January 2020 GENERAL DESCRIPTION FEATURES IS32FL3237 is an LED driver with 36 constant current channels. Each channel can be pulse width modulated (PWM) by 16 bits for smooth LED brightness control. In addition, each channel has an 8-bit output current control register which allows fine tuning the current for rich RGB color mixing, e.g., a pure white color LED application. The maximum output current of each channel is designed to be 38mA, which can be adjusted by one 8-bit global control register.   Proprietary programmable algorithms are used in IS32F3237 to minimize audible noise caused by the MLCC decoupling capacitor. All registers can be programmed via a high speed I2C (1MHz). IS32F3237 can be turned off with minimum current consumption by either pulling the SDB pin low or by using the software shutdown feature. IS32FL3237 is available in eTQFP-48 package. It operates from 2.7V to 5.5V over the temperature range of -40°C to +125°C.          2.7V to 5.5V VCC supply 1MHz I2C interface, automatic address increment function with readout function Four selectable I2C addresses Accurate color rendition - Selectable 8-bit/10-bit/12-bit/16-bit PWM - 8-bit dot correction - 8-bit global current adjust Open/Short detect function 62kHz PWM frequency (8-bit PWM) Temperature detect function EMI/noise reduction technology - Spread spectrum - Selectable Phase Delay - Selectable 180 degree Clock Phase -40°C to +125°C temperature range eTQFP-48 package AEC-Q100 Qualified APPLICATIONS      Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 Automotive clusters Dashboards Automotive interiors Ambient lighting Functional lighting 1 IS32FL3237 TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit *Note 1 *Note 3 VCC=5V 41 40 1 F VCC OUT1 AD 0.1 F OUT2 47 33 48 91 1 33 36 33 37 91 38 33 *Note 2 VIH 2k OUT3 *Note 1 VLED+=5V 2k 45 46 Micro Controller 39 SDA SCL IS32FL3237 SDB 100k 0.1 F OUT34 44 RISET 3.3k 4,18 19 OUT35 ISET GND Figure 2 OUT36 GND 33,42,43 Typical Application Circuit (VCC=5V) Note 1: VLED+ should be same as VCC voltage. Note 2: VIH is the high level voltage for IS32FL3237, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V, VIH=3.3V. If VCC=5V and VIH is lower than 2.8V, recommend to add a level shift circuit. 2 Note 3: These optional resistors are for offloading the thermal dissipation (P=I R) away from the IS32FL3237. Note 4: The output current is set up to 23mA when RISET= 3.3kΩ. The maximum global output current can be set by external resistor, RISET. Please refer to the detail application information in RISET section. Note 5: The IC and LED should be placed far away from any local antenna in order to prevent EMI contamination. Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 2 IS32FL3237 PIN CONFIGURATION 37 OUT35 38 OUT36 39 SDB 40 AD 41 VCC 42 GND 43 GND 44 ISET 45 SDA 46 SCL 47 OUT1 Pin Configuration (Top View) 48 OUT2 Package OUT3 1 36 OUT34 OUT4 2 35 OUT33 OUT5 3 34 OUT32 GND 4 27 OUT26 OUT12 11 26 OUT25 OUT13 12 25 OUT24 OUT23 24 OUT11 10 OUT22 23 28 OUT27 OUT21 22 OUT10 9 OUT20 21 29 OUT28 OUT19 20 OUT9 8 GND 19 30 OUT29 GND 18 OUT8 7 OUT18 17 31 OUT30 OUT17 16 OUT7 6 OUT16 15 32 OUT31 OUT15 14 OUT6 5 OUT14 13 eTQFP-48 33 GND PIN DESCRIPTION No. Pin Description 1~3,5~17 OUT3~OUT18 Output channel 3~18 for LEDs. 4,18,19,33, 42,43 GND Ground. 20~32, 34~38 OUT19~OUT36 Output channel 19~36 for LEDs. 39 SDB Shutdown the chip when pulled low. 40 AD I2C address setting. 41 VCC Power supply. 44 ISET Input terminal used to connect an external resistor. This regulates the global output current. When RISET=3.3kΩ, IOUT=23mA. 45 SDA I2C serial data. 46 SCL I2C serial clock. 47,48 OUT1, OUT2 Output channel 1, 2 for LEDs. Thermal Pad Connect to GND. Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 3 IS32FL3237 ORDERING INFORMATION Automotive Range: -40°C to +125°C Order Part No. Package QTY IS32FL3237-TQLA3-TR IS32FL3237-TQLA3 eTQFP-48, Lead-free, 2500/Reel 250/Tray Copyright  ©  2020  Lumissil  Microsystems.  All  rights  reserved.  Lumissil  Microsystems  reserves  the  right  to  make  changes  to  this  specification  and  its  products  at  any  time  without  notice.  Lumissil  Microsystems  assumes  no  liability  arising  out  of  the  application  or  use  of  any  information,  products  or  services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and  before placing orders for products.  Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in  such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:  a.) the risk of injury or damage has been minimized;  b.) the user assume all such risks; and  c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 4 IS32FL3237 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at SCL, SDA, SDB, OUT1 to OUT36 Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA=TJ Package thermal resistance, junction to ambient (4 layer standard test PCB based on JESD 51-2A), θJA Package thermal resistance, junction to thermal PAD (4 layer standard test PCB based on JESD 51-2A), θJP ESD (HBM) ESD (CDM) -0.3V ~ +6.0V -0.3V ~ VCC+0.3V +150°C -65°C ~ +150°C -40°C ~ +150°C 38.9°C/W 7.57°C/W ±2kV ±750V Note 6: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Typical values are TA = 25°C, VCC = 5V. Symbol VCC Parameter Condition Supply voltage Min. Typ. 2.7 Maximum output current VOUT= 0.8V, RISET= 2kΩ, GCC= 0xFF, Scaling= 0xFF (Note 7) 38 Output current VOUT= 0.6V, RISET= 3.3kΩ, GCC= 0xFF, 21.39 Scaling= 0xFF 23 ∆IMAT IOUT mismatch in chip RISET= 3.3kΩ, GCC= 0xFF, Scaling= 0xFF, IOUT= 23mA ∆IOUT IOUT mismatch between chip RISET= 3.3kΩ, GCC= 0xFF, Scaling= 0xFF, IOUT= 23mA Headroom voltage RISET= 3.3kΩ, GCC= 0xFF, Scaling= 0xFF, IOUT= 23mA IOUT VHR ICC ISD Quiescent power supply current Shutdown current Max. Unit 5.5 V mA 24.61 mA -7 7 % -7 7 % 0.3 0.5 V RISET=3.3kΩ,GCC=0xFF,Scaling=0xFF, IOUT=23mA,PWM=0x00,VCC=3.6V 4.7 7 mA RISET=3.3kΩ,GCC=0xFF,Scaling=0xFF, IOUT=23mA,PWM=0x00,VCC=5V 5.7 8 mA RISET= 3.3kΩ, VSDB= 0V or software shutdown, VCC= 3.6V 0.8 1.6 μA RISET= 3.3kΩ, VSDB= 0V or software shutdown, VCC= 5V 1.8 3 μA 0.1 μA IOZ Output leakage current VSDB= 0V or software shutdown, VOUT= 5.5V fOUT PWM frequency of output OSC= 8MHz, PWM Resolution= 8-bit 31.5 kHz TSD Thermal shutdown (Note 8) 165 °C Thermal shutdown hysteresis (Note 8) 20 °C VOD OUTx pin open detect threshold RISET=6.8kΩ, IOUT≥0.1mA, measured at OUTx 0.08 0.18 0.26 V VSD LED short detect threshold RISET=6.8kΩ, IOUT≥0.1mA, measured at (VCC-VOUTx) 0.7 1.3 1.5 V TSD_HY Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 5 IS32FL3237 ELECTRICAL CHARACTERISTICS (CONTINURE) Typical values are TA = 25°C, VCC = 5V. Symbol Parameter Condition Min. Typ. Max. Unit 0.4 V Logic Electrical Characteristics (SDA, SCL, SDB, AD) VIL Logic “0” input voltage VCC= 2.7V~5.5V VIH Logic “1” input voltage VCC= 2.7V~5.5V IIL Logic “0” input current VINPUT= 0V (Note 8) 5 nA IIH Logic “1” input current VINPUT= VCC (Note 8) 5 nA 1.4 V DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 8) Symbol Parameter Fast Mode Min. Typ. Fast Mode Plus Typ. Max. Unit Max. Min. - 400 - 1000 kHz fSCL Serial-clock frequency tBUF Bus free time between a STOP and a START condition 1.3 - 0.5 - μs tHD, STA Hold time (repeated) START condition 0.6 - 0.26 - μs tSU, STA Repeated START condition setup time 0.6 - 0.26 - μs tSU, STO STOP condition setup time 0.6 - 0.26 - μs tHD, DAT Data hold time - - - - μs tSU, DAT Data setup time 100 - 50 - ns tLOW SCL clock low period 1.3 - 0.5 - μs tHIGH SCL clock high period 0.7 - 0.26 - μs tR Rise time of both SDA and SCL signals, receiving - 300 - 120 ns tF Fall time of both SDA and SCL signals, receiving - 300 - 120 ns Note 7: The recommended minimum value of RISET is 2kΩ. Note 8: Guaranteed by design. Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 6 IS32FL3237 FUNCTIONAL BLOCK DIAGRAM VCC PWM Control SDA SCL Output Driver I2C Interface OUT1~OUT36 Register Bias AD ISET 6 Group CNT Bandgap MUX SD_Chip SDB OSC Spread Spectrum GND Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 7 IS32FL3237 DETAILED DESCRIPTION Then the master sends an SCL pulse. If the IS32FL3237 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. I2C INTERFACE The IS32FL3237 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS32FL3237 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Set A0 to “0” for a write command and set A0 to “1” for a read command. The value of bits A1 and A2 are decided by the connection of the AD pin. The complete slave address is: Following acknowledge of IS32FL3237, the register address byte is sent, most significant bit first. IS32FL3237 must generate another acknowledge indicating that the register address has been received. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS32FL3237 must generate another acknowledge to indicate that the data was received. Table 1 Slave Address Bit A7:A3 A2:A1 A0 Value 01101 AD 0/1 AD connected to GND, AD = 00; AD connected to VCC, AD = 11; AD connected to SCL, AD = 01; AD connected to SDA, AD = 10; The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. ADDRESS AUTO INCREMENT The SCL line is uni-directional. The SDA line is bi-directional (open-drain) with a pull-up resistor (typically 2kΩ). The maximum clock frequency specified by the I2C standard is 1MHz. In this discussion, the master is the microcontroller and the slave is the IS32FL3237. To write multiple bytes of data into IS32FL3237, load the address of the data register that the first data byte is intended for. During the IS32FL3237 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS32FL3237 will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS32FL3237 (Figure 6). The timing diagram for the I2C is shown in Figure 3. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. READING OPERATION The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. After the last bit of the chip address is sent, the master checks for the IS32FL3237’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Figure 3 Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 Most of the registers can be read. To read the register, after I2C start condition, the bus master must send the IS32FL3237 device address ____ with the R/W bit set to “0”, followed by the register address which determines which register is accessed. Then restart I2C, the bus master should send the ____ IS32FL3237 device address with the R/W bit set to “1”. Data from the register defined by the command byte is then sent from the IS32FL3237 to the master (Figure 7). Interface Timing 8 IS32FL3237 Figure 4 Figure 5 Figure 6 Bit Transfer Writing to IS32FL3237 (Typical) Writing to IS32FL3237 (Automatic Address Increment) Figure 7 Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 Reading from IS32FL3237 9 IS32FL3237 REGISTER DEFINITIONS Table 2 Register Function Address Name 00h 01h~48h 49h Function R/W Table Control Register Power control register R/W 3 PWM Register Channel [36:1] PWM register byte R/W 5 Update Register Update the PWM and Scaling data W - Control each channel’s DC current R/W 7 4Ah~6Dh LED Scaling Register 6Eh Global Current Control Register Control Global DC current/SSD R/W 8 70h Phase Delay and Clock Phase Register Phase Delay and Clock Phase R/W 9 71h Open Short Detect Enable Register Open short detect enable R/W 10 LED Open/Short Register Open short information R/W 11 77h Temperature Sensor Register Temperature information R/W 12 78h Spread Spectrum Register Spread spectrum control register R/W 13 7Fh Reset Register Reset all registers W - 72h~76h Table 3 00h Control Register D7 D6:D4 D3 D2:D1 D0 Name - OSC - PMS SSD 8-bit 62k 32k 4k Default 0 000 0 00 0 10-bit 16k 8k 1k 12-bit 4k 2k 244 122 NA 16-bit 244 122 NA SSD 0 1 Software Shutdown Enable Software shutdown mode Normal operation PMS 00 01 10 11 PWM Resolution N=256, 8-bit N=1024, 10-bit N=4096, 12-bit N=65536, 16-bit OSC 000 001 010 011 100 101 110 111 Oscillator Clock Frequency Selection 16MHz 8MHz 1MHz 500kHz 250kHz 125kHz 62kHz 31kHz 0000 0000 Table 4 PWM Frequency PWM 16M 8M 1M 500k 250k 125k 62k 31k Resolution Bit The Control Register sets software shutdown mode, internal oscillator clock frequency and PWM resolution. The internal oscillator clock frequency and the PWM resolution will decide the output PWM frequency, Recommend using lower than 300Hz option or higher than 20kHz options to avoid the MLCC’s audible noise as shown in Table 4. Default 2k 1k 0.5k 244 122 0.5k 244 122 NA NA NA NA NA NA NA NA NA NA Table 5 01h~48h PWM Register Reg 02h (04h, 06h…) 01h (03h, 05h…) Bit D7:D0 D7:D0 Name PWM_H PWM_L Default 0000 0000 0000 0000 Each output has 2 bytes to modulate the PWM duty in 256/1024/4096/65536 steps. If using the 8 bit PWM resolution, only the PWM_L needs to be set. The value of the SL bit (LED Scaling Register) decides the peak current of each LED noted as IOUT. IOUT and the value of the PWM Registers decide the average current of each LED noted as ILED. IOUT computed by Formula (1): I OUT  I OUT ( MAX )  GCC SL  256 256 (1) ILED computed by Formula (2): I LED  PWM  I OUT N N=256: PWM  (2) 7  D[ n ]  2 n n0 Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 10 IS32FL3237 N=1024: PWM  Table 6 PWM and Scaling Register Map PWM OUT PWM_H PWM_L 9  D[n ]  2 n n0 N=4096: PWM  11  D[ n ]  2 n n0 N=65536: PWM  15  D[ n ]  2 n (3) n0 Where IOUT(MAX) is the maximum output current decided by RISET (Check RISET section for more information), GCC is the global current setting (6Eh), and SL is the scaling of each output (4Ah~6Dh), N=256/1024/4096/65536(8/10/12/16 bit PWM resolution. For example: RISET=3.3kΩ, GCC=0xFF, SL=0xFF, PMS= “11” (16-bit PWM resolution), PWM_H=0xFF, PWM_L=0xFF, IOUT(MAX) = 23.18mA I OUT  I OUT ( MAX )  PWM  255 255   23 mA (1) 256 256 15  D[ n ]  2 n  65535 (3) n0 N= 65536 I LED 65535   23 mA  23 mA 65536 (2) Where IOUT(MAX) is the maximum output current decided by RISET (Check RISET section for more information) The IOUT of each channel is set by the SL bits of LED Scaling Register (4Ah~6Dh). Please refer to the detail information in Table 7. If RISET=3.3kΩ, GCC=0xFF, SL=0xFF, PMS= “00” (8-bit PWM resolution, only use the PWM_L, the PWM_H will be ignored), PWM_H=0x77, PWM_L=0xAA, IOUT(MAX) = 23.18mA I OUT  I OUT ( MAX )  255 255   23 mA (1) 256 256 7 PWM   D [ n ]  2 n  170 (3) n0 N= 256 I LED  170  23 mA 256 (2) Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 SL 1 02h 01h 4Ah 2 04h 03h 4Bh 3 06h 05h 4Ch 4 08h 07h 4Dh 5 0Ah 09h 4Eh 6 0Ch 0Bh 4Fh 7 0Eh 0Dh 50h 8 10h 0Fh 51h 9 12h 11h 52h 10 14h 13h 53h 11 16h 15h 54h 12 18h 17h 55h 13 1Ah 19h 56h 14 1Ch 1Bh 57h 15 1Eh 1Dh 58h 16 20h 1Fh 59h 17 22h 21h 5Ah 18 24h 23h 5Bh 19 26h 25h 5Ch 20 28h 27h 5Dh 21 2Ah 29h 5Eh 22 2Ch 2Bh 5Fh 23 2Eh 2Dh 60h 24 30h 2Fh 61h 25 32h 31h 62h 26 34h 33h 63h 27 36h 35h 64h 28 38h 37h 65h 29 3Ah 39h 66h 30 3Ch 3Bh 67h 31 3Eh 3Dh 68h 32 40h 3Fh 69h 33 42h 41h 6Ah 34 44h 43h 6Bh 35 46h 45h 6Ch 36 48h 47h 6Dh 11 IS32FL3237 49h Update Register When SDB= “H” and SSD= “1”, a write of “0000 0000” to 49h will update the PWM Registers (01h~48h) values. Table 7 4Ah~6Dh LED Scaling Register Bit D7:D0 Name SL Default 0000 0000 SL  GCC SL  256 256 Bit D7 D6 D5 Name PDE - Default 0 0 D4 D3 D2 D1 D0 PS6 PS5 PS4 PS3 PS2 PS1 0 0 0 0 0 0 The PDE bit is for enabling channel group delay to minimize peak load current draw from the LED power supply rail. Each output has 8 bits to modulate DC current in 256 steps. The value of the SL Registers decides the DC peak current of each LED noted by IOUT. IOUT computed by Formula (1): I OUT  I OUT ( MAX )  Table 9 70h Phase Delay and Clock Phase Register PDE 0 1 Phase Delay Enable Phase delay disable Phase delay enable PS[n] 0 1 Clock Phase Select All outputs work as scheme of Clock Phase 1 Outputs OUT[2+(n-1)*6], OUT[4+(n-1)*6], OUT[6+(n-1)*6] work as scheme of Clock Phase 2 (1) 7  D[ n ]  2 n (4) n0 Where IOUT(MAX) is the maximum output current decided by RISET, GCC is the global current setting (6Eh) 4Ah~6Dh don’t need to be updated by writing to 49h, each register will be updated immediately when it is written. Table 8 6Eh Global Current Control Register Bit D7:D0 Name GCC Default 0000 0000 GCC and SL registers control IOUT as shown in Formula (1). GCC  7  D[ n ]  2 n (5) n0 If GCC=0xFF, SL=0xFF, IOUT=IOUT(MAX) If GCC=0x01, SL=0xFF, I OUT  I OUT ( MAX )  1 255  256 256 Where IOUT(MAX) is the maximum output current decided by RISET (Check RISET section for more information). Phase Delay separates 36 outputs as 6 groups, OUT1~OUT6 as group 1, OUT7~OUT12 as group 2…OUT31~OUT36 as group 6. When Phase Delay is enabled, group 2 has a 1/(6*fOUT) time delay than group 1, group 3 also has a 1/(6*fOUT) time delay than group 2, group 4 also has a 1/(6*fOUT) time delay than group 3, and so on. For each group of 6 outputs there is a Clock Phase option PS[n](n=1~6), when PSn is set to ‘1’, OUT[1+(n-1)*6], OUT[3+(n-1)*6], OUT[5+(n-1)*6] keep the phase, phase 1, the turning on edge of the PWM pulse is fixed from starting of PWM cycle, but OUT[2+(n-1)*6], OUT[4+(n-1)*6], OUT[6+(n-1)*6] change to phase 2, the turning off edge of the PWM pulse is fixed from ending of PWM cycle as below, the rising and falling edges will cancel the power ripple. Phase Delay feature and Clock Phase options can work together to minimize the voltage ripple of LED power supply. Table 10 71h Open Short Detect Enable Register Bit D7:D2 D1:D0 Name - OSDE Default 0000 00 00 OSDE enables the open and/or short LED channel detection with the result stored in 72h~76h, note either open or short information is saved not both. OSDE 00 01 10 11 Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 Open Detect Enable Detect disable Detect disable Short detect enable Open detect enable 12 IS32FL3237 Table 11-1 72h~75h LED Open/Short Register Table 13 78h Spread Spectrum Register 72h D7:D0 Bit D7:D5 D4 D3:D2 D1:D0 Name OP/ST[8:1] Name DCPWM SSP RNG CLT Default 0000 0000 Default 000 0 00 00 Table 11-2 76h LED Open/Short Register Bit D7:D4 D3:D0 Name - OP/ST[36:33] Default 0000 0000 Open or short status is stored in 72h to 76h. OP[36:1] 0 1 Open Information of OUT36:OUT1 Open not detected Open detected ST[36:1] 0 1 Short Information of OUT36:OUT1 Short not detected Short detected Table 12 77h Temperature Sensor Register Bit D7:D6 D5 D4 D3:D2 D1:D0 Name TROF - T_Flag - TS Default 00 0 0 00 00 TS stores the temperature/thermal roll-off point. TROF stores percentage of output current of the thermal roll-off function. T_Flag=1 indicates die temperature exceeds the temperature set point (TS). Before each reading of 77h register, TROF and TS must be re-written. When DCPWM is set to “0”, the PWM outputs are decided by 01h~48h, and the PWM range is 0/256~255/256(8-bit PWM, 0/1024~1023/1024 for 10 bit PWM, 0/4096~4095/4096 for 12 bit PWM, 0/65536~65535/65536 for 16 bit PWM), still the 1/256(8-bit PWM, 1/1024 for 10 bit PWM, 1/4096 for 12 bit PWM, 1/65536 for 16 bit PWM), can’t be turned on. When the DCPWM is set to “1”, PWM dimming is disabled and dimming will be done by current adjust GCC and SL registers. Spread spectrum register configures the spread spectrum function, adjust the cycle time and range. DCPWM xx0 xx1 x0x x1x 0xx 1xx Setting the output to work in DC mode Output 1~12 PWM data set by registers 01h~18h Output 1~12 set to turn on (PWM is disabled) Output 13~24 PWM data set by registers 19h~30h Output 13~24 set to turn on (PWM is disabled) Output 25~36 PWM data set by registers 31h~48h Output 25~36 set to turn on (PWM is disabled) SSP 0 1 Spread Spectrum Enable Disable Enable 100% 75% 55% 30% CLT 00 01 10 11 Spread Spectrum Cycle Time ±1980μs ±1200μs ±820μs ±660μs 00 01 10 11 Temperature Point, Thermal roll off start point 140°C 120°C 100°C 90°C RNG 00 01 10 11 Spread Spectrum Range ±5% ±15% ±24% ±34% T_Flag 0 1 Temperature Flag Temperature point not exceeded Temperature point exceeded TROF current 00 01 10 11 TS Thermal roll off percentage of output Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 7Fh Reset Register When power on, all registers values are reset to 0x00 (default). A write of “0000 0000” to 7Fh will also reset all registers to their default values. 13 IS32FL3237 APPLICATION INFORMATION RISET The maximum output current IOUT(MAX) for OUT1~OUT36 can be adjusted by the external resistor, RISET, as described in Formula (6). I OUT ( MAX )  x  V ISET R ISET (6) x = 58.84, VISET = 1.3V. The recommended minimum value of RISET is 2kΩ. When RISET=3.3kΩ, IOUT(MAX)=23.18mA When RISET=2kΩ, IOUT(MAX)=38.25mA RISET should be close to the chip and the ground side should well connect to the GND plane. CURRENT SETTING The maximum output current is set by the external resistor RISET. The Global Current Control register GCC can be used to set a lower current than set by RISET. The 8-bit SL registers (4Ah~6Dh) control the individual currents for each of the outputs. Some applications may require the IOUT of each channel to be adjusted independently. For example, if OUT1 drives 1 LED and OUT2 drives 2 parallel LEDs, and they should have the same average current like 18mA, we can set the IOUT(MAX) to 36mA, and GCC=0xFF, 4Ah=0x80 for OUT1, 4Bh=0xFF for OUT2. The result is OUT1 will sink 18mA and OUT2 will sink 36mA which will be 18mA through each of the parallel LEDs. Another example, OUT1, OUT2 and OUT3 drive an RGB LED, OUT1 is Red LED, OUT2 is Green LED and OUT 3 is Blue LED. If GCC and SL bits are the same, then the RGB LED may appear a pinkish, or not so white. The SL bits can be used to adjust the IOUTx current so the RGB LED appears closer to a pure white color. We call this SL bit adjustment by another name: white balance registers. PWM CONTROL The PWM Registers (01h~48h) can modulate the LED brightness of each of the 36 channels with 256/1024/4096/65536 steps. For example, if the data in PWM_H Register is “0000 0000” and in PWM_L Register is “0000 0100”, then the PWM is the fourth step. The greater the step count, the more accurate the RGB color mixing. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. PWM FREQUENCY SELECT The IS32FL3237 output channels operate with a default 8 bit PWM resolution and the PWM frequency Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 of 62kHz (oscillator frequency is 16MHz). Because all the OUTx channels are synchronized, the DC power supply will experience large instantaneous current surges when the OUTx channels turn ON. These current surges will generate an AC ripple on the power supply which cause stress to the decoupling capacitors. When the AC ripple is applied to a monolithic ceramic capacitor chip (MLCC) it will expand and contract causing the PCB to flex and generate audible hum in the range of between 20Hz to 20kHz, To avoid this hum, there are many countermeasures, such as selecting the capacitor type and value which will not cause the PCB to flex and contract. An additional option for avoiding audible hum is to set the IS32FL3237’s output PWM frequency above the audible frequency range. The Control Register (00h) can be used to set the switching frequency to 122Hz~62kHz as shown in Table 4. Combination settings of the OSC and PMS bits will result in different PWM frequency, select a value higher than 20kHz to avoid the audible frequency range. PHASE DELAY and CLOCK PHASE To reduce audible noise due to PWM switching, the IS31FL3237 features Phase Delay and Clock Phase schemes. When Phase Delay and Clock Phase are disabled (default) all of the outputs turn on simultaneously causing large current draw from the ceramic capacitors and plausible audible noise. VCC OUT1~OUT6 Ton Toff OUT7~OUT12 OUT13~OUT18 OUT19~OUT24 OUT25~OUT30 OUT31~OUT36 1/fOUT Turn on together resulting power ripple Figure 8 Phase Delay and Clock Phase disable The PDE bit of register 70h will enable the Phase Delay function so at power-on the OUTx channel will not all turn on at the same time to minimize peak load current, resulting in reduced voltage ripple on the LED power supply rail. Phase Delay separates the 36 outputs as 6 groups, OUT1~OUT6 as group 1, OUT7~OUT12 as group 2…OUT31~OUT36 as group 6, when Phase Delay is enabled, group 2 will have a 14 IS32FL3237 1/(6×fOUT) time delay than group 1, group 3 will also have a 1/(6×fOUT) time delay than group 2, and so on. VCC VCC Clock Phase 1 OUT[1+(n-1)*6] Ton OUT1~OUT6 Toff OUT[3+(n-1)*6] Ton OUT7~OUT12 OUT13~OUT18 OUT[4+(n-1)*6] OUT19~OUT24 OUT[5+(n-1)*6] Ton Ton Toff 1/fOUT Toff PDE= ’1’ Phase Delay enable Figure 9 Also in each group of outputs, there is a Clock Phase option PS[n](n=1~6), when PSn of 71h register is set to ‘0’(default), all outputs in group n keep the phase 1. OUT[1+(n-1)*6] Ton Toff Ton 1/fOUT Rising & Falling edges canceled the power ripple 1/fOUT Clock Phase 1 OUT1/3/5 Ton Toff Clock Phase 2 OUT7/9/11 Toff OUT[3+(n-1)*6] Ton Toff OUT[4+(n-1)*6] Ton Toff OUT[5+(n-1)*6] Ton Toff OUT8/10/12 OUT[6+(n-1)*6] Ton Toff 1/fOUT Turn on together resulting power ripple OUT31/33/35 PSn=’0’ Clock Phase disable When PSn is set to ‘1’, OUT[1+(n-1)×6], OUT[3+(n-1)×6], OUT[5+(n-1)×6] will keep the phase 1, the turning on edge of the PWM pulse is fixed from starting of PWM cycle as below, but OUT[2+(n-1)×6], OUT[4+(n-1)*6], OUT[6+(n-1)×6] will change to phase 2, the turning off edge of the PWM pulse is fixed from ending of PWM cycle as below, the rising and falling edges will cancel the power ripple. Ton Ton Toff Clock Phase 2 Toff Ton tDELAY=1/(6*fOUT) Clock Phase 1 OUT32/34/36 Figure 10 Toff tDELAY=1/(6*fOUT) Clock Phase 1 Clock Phase 1 Toff OUT[2+(n-1)*6] Ton PSn=’1’ Clock Phase enable Phase Delay feature and Clock Phase options can work together to minimize the voltage ripple of LED power supply. OUT2/4/6 VCC Ton Toff Figure 11 tDELAY =1/(6*fOUT) Ton Toff OUT[6+(n-1)*6] OUT25~OUT30 OUT31~OUT36 Toff Clock Phase 2 OUT[2+(n-1)*6] Figure 12 Ton Toff Clock Phase 2 Toff Ton PDE=’1’ Phase Delay enable, PSn=’1’(n=1~6) Clock Phase enable OPEN/SHORT DETECT FUNCTION IS32FL3237 has open and short detect bit for each LED. See Open (VOD) and Short (VSD) detection thresholds in the Electrical Characteristics table. By setting the OSDE bit of Open Short Detect Enable Register (71h) from “00” to “10” (store short information) or “11” (store open information), the LED Open/Short Register will store the open/short information immediately the MCU can get the open/short information by reading the 72h~76h. SPREAD SPECTRUM FUNCTION PWM current switching of LED outputs can be particularly troublesome when the EMI is concerned. To optimize the EMI performance, the IS32FL3237 includes a spread spectrum function. By setting the RNG bit of Spread Spectrum Register (78h), Spread Spectrum range can be chosen from ±5% /±15% Lumissil Microsystems – www.lumissil.com Rev. B, 01/02/2020 15 IS32FL3237 /±24% /±34%. The spread spectrum function willlower the total electromagnetic emitting energy by spreading the energy into a wider range to significantly degrades the peak energy of EMI. With spread spectrum, the EMI test is easier to pass with a smaller size and lower cost filter circuit. OPERATING MODE IS32FL3237 can operate in PWM Mode. The brightness of each LED can be modulated with 256/1024/4096/65536 steps by PWM registers. For example, if N=256, the data in PWM Register is “0000 0100”, then the PWM is the fourth step. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. SHUTDOWN MODE Shutdown mode can be used as a means of reducing power consumption. During shutdown mode all registers retain their data. Software Shutdown By setting the SSD bit of the Control Register (00h) to “0”, the IS32FL3237 will operate in software shutdown mode. When the IS32FL3237 is in software shutdown, all current sources are switched off, so the LEDs are OFF but all registers remain accessible. Typical current consumption is 0.8μA (VCC=3.6V). Hardware Shutdown The IS32FL3237 enters hardware shutdown when it’s SDB pin is pulled low. All analog circuits are disabled during hardware shutdown, typical current consumption is 0.8μA (VCC=3.6V). The over temperature of the chip may result in deterioration of the properties of the chip. The thermal pad of IS32FL3237 should connect to GND net and need to use 9 or 16 vias connect to GND copper area, the GND area should be as large area as possible to help radiate the heat from the IS32FL3237. Current Rating Example For a RISET=3.3kΩ application, the current rating for each net is as follows: • VCC pin maximum current is 8mA when VCC=5V, but the VLED+ net is provide total current of all outputs, its current can as much as 23mA×36=828mA, recommend trace width for VCC pin: 0.20mm~0.3mm, recommend trace width for VLED+ net: 0.3mm~0.5mm, • Output pins=23mA, recommend trace width is 0.2mm~0.254mm • All other pins