IS31FL3729
16×8/15×9 MATRIX LED DRIVER
January 2021
GENERAL DESCRIPTION
FEATURES
The IS31FL3729 is a general purpose 16×8 or 15×9
matrix LED driver programmed via a 1MHz I2C bus
compatible interface. Each LED can be dimmed
individually with 8-bit PWM data, and each CSx has
8-bit DC current scaling for color calibration. The
combination enables 256 steps of linear PWM dimming
for each dot and 256 steps of DC current adjustment
for each CSx.
Additionally, the open or short state of each LED can be
detected and stored in Open-Short Registers. The
MCU can then read the Open-Short Registers via the
I2C bus and identify which LED in the array is open or
short.
The IS31FL3729 features a very low shutdown and
quiescent (operational) current. It also supports
selectable noise reduction features such as PWM clock
spread spectrum and 180 degree phase shifting.
IS31FL3729 is available in QFN-32 (4mm×4mm) and
eTQFP-32 packages. It operates from 2.7V to 5.5V
over the full temperature range of -40°C to +125°C.
Supply voltage range: 2.7V to 5.5V
16 current sinks
Support 16×n (n=1~8), 15×9 LED matrix
configurations
Individual 256 PWM control steps
256 DC current steps for each CSx
64 global current steps
SDB rising edge resets the I2C interface
Register programmable PWM frequency: 0.25kHz
to 55kHz
1MHz I2C-compatible interface
Individual open and short error detect function
PWM 180 degree phase shift
Spread spectrum
De-ghost
QFN-32 (4mm×4mm) and eTQFP-32 packages
APPLICATIONS
White goods LED display panel.
IOT device
TYPICAL APPLICATION CIRCUIT
Figure 1
Typical Application Circuit (16×8)
Note 1: The VIH of I2C bus should be smaller than VCC. And if VIH is lower than 3.0V, it is recommended add a level shift circuit to avoid extra
shutdown current.
2
Note 2: These optional resistors are for offloading the thermal dissipation (P=I R) away from the IS31FL3729, for mono red/yellow/orange LED,
if PVCC=VCC=3.3V, don’t need these resistors.
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1
IS31FL3729
TYPICAL APPLICATION CIRCUIT (CONTINUED)
Figure 2
Figure 3
Typical Application Circuit (15×9)
Typical Application Circuit (45 RGBs)
2
Note 3: These optional resistors are for offloading the thermal dissipation (P=I R) away from the IS31FL3729, for red LED, it is recommended to
use about 30Ohm more than blue/green LED, to offload more extra voltage due to lower forward voltage of red LED.
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2
IS31FL3729
PIN CONFIGURATION
eTQFP-32
25 ISET
26 SDA
27 SCL
28 AD
29 SDB
30 CS1
21 SW2
CS8 5
20 SW3
CS9 6
19 SW4
CS10 7
18 SW5
CS11 8
17 SW6
SW7 16
CS7 4
SW8 15
22 SW1
SW9/CS16 14
CS6 3
CS15 13
23 VCC
CS14 12
CS5 2
CS13 11
24 GND
CS12 10
CS4 1
GND 9
QFN-32
31 CS2
Pin Configuration (Top View)
32 CS3
Package
CS4 1
24 GND
CS5 2
23 VCC
CS6 3
22 SW1
CS7 4
21 SW2
CS8 5
20 SW3
CS9 6
19 SW4
CS10 7
18 SW5
CS11 8
17 SW6
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3
IS31FL3729
PIN DESCRIPTION
No.
Pin
Description
1~8, 10~13
CS4~CS15
Current sinks output.
9,24
GND
Ground.
14
SW9/CS16
Switch power source.
15~22
SW8~SW1
Switch power source.
23
VCC
Power supply.
25
ISET
Current setting pin.
26
SDA
Serial data.
27
SCL
Serial clock.
28
AD
I2C Address setting.
29
SDB
Shutdown the chip when pull to low.
30~32
CS1~CS3
Current sinks output.
Thermal Pad
Need to connect to GND pins.
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4
IS31FL3729
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3729-QFLS4-TR
IS31FL3729-TQLS4-TR
QFN-32, Lead-free
eTQFP-32, Lead-free
2500
Copyright © 2020 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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5
IS31FL3729
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4 layer standard test
PCB based on JESD 51-2A), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~+6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~+150°C
-40°C ~ +125°C
52.2°C/W (QFN)
36.1°C/W (eTQFP)
±8kV
±750V
Note 4: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC = 5V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
VCC
Supply voltage
ICC
Quiescent power supply current
ISD
Shutdown current
IOUT
ILED
Conditions
Min.
Typ.
2.7
Max.
Unit
5.5
V
mA
VSDB=VCC, all LEDs off
2
3
VSDB=0V
3
5
VSDB= VCC, Configuration Register
written “0000 0000”
3
5
Maximum constant current of CSx
RISET=10kΩ, GCC= “100 0000”
SL=0xFF
35
mA
Average current on each LED
ILED = IOUT(PEAK)/Duty
RISET=10kΩ, GCC= “100 0000”
SL=0xFF, n=8, Duty=1/8.29
4.22
mA
Current switch headroom voltage
SWx
ISWITCH=600mA RISET=10kΩ,
GCC= “100 0000”, SL=0xFF
500
Current sink headroom voltage
CSx
ISINK=34mA, RISET=10kΩ,
GCC= “100 0000”, SL=0xFF
400
tSCAN
Period of scanning
B2h= “0x01”
(PWM frequency = 32kHz)
30
µs
tNOL1
Non-overlap blanking time during
B2h= “0x01”
scan, the SWx and CSy are all off
(PWM frequency = 32kHz)
during this time
0.8
µs
tNOL2
Delay total time for CS1 to CS16,
during this time, the SWx is on
but CSx is not all turned on
0.27
µs
VHR
μA
550
mV
B2h= “0x01”
(PWM frequency = 32kHz)
500
Logic Electrical Characteristics (SDA, SCL, AD, SDB)
VIL
Logic “0” input voltage
VCC=2.7V~5.5V, LGC= “0”
GND
0.4
V
VIH
Logic “1” input voltage
VCC=2.7V~5.5V, LGC= “0”
1.4
VCC
V
VIL
Logic “0” input voltage
VCC=2.7V~5.5V, LGC= “1”
GND
0.6
V
VIH
Logic “1” input voltage
VCC=2.7V~5.5V, LGC= “1”
2.4
VCC
V
Input schmitt trigger hysteresis
VCC=3.6V, LGC= “0”, LGC= “1”
IIL
Logic “0” input current
IIH
Logic “1” input current
VHYS
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0.2
V
SDB=L, VINPUT= L (Note 5)
5
nA
SDB=L, VINPUT= H (Note 5)
5
nA
6
IS31FL3729
DIGITAL INPUT I2C SWITCHING CHARACTERISTICS (NOTE 5)
Fast Mode
Symbol
Parameter
Min.
Typ. Max.
fSCL
Serial-clock frequency
tBUF
Fast Mode Plus
Min.
Typ.
Max.
Units
-
400
-
1000
kHz
Bus free time between a STOP and a
START condition
1.3
-
0.5
-
μs
tHD, STA
Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA
Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO
STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT
Data hold time
-
-
-
-
μs
tSU, DAT
Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving
-
300
-
120
ns
Note 5: Guaranteed by design.
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7
IS31FL3729
FUNCTIONAL BLOCK DIAGRAM
ISET
VCC
Global Curr ent
64 Step s
Bias
Trim
Bandgap
SDB
OSC
SSD
Con fig
SWX
Seq uence
SDA
SCL
I2C
Interface
PWM
Cou nter 1
Pointer
PWM
PWM
Cou nter 16
AD
Scan Switch
Curren t Sink
CS1~CS16
SW1~SW9
Scaling
Pull-down
Resister
Selection
Ope n/Short
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Ghost
Eliminatin g
GND
8
IS31FL3729
DETAILED DESCRIPTION
I2C INTERFACE
IS31FL3729 uses a serial bus, which conforms to the
I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3729 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0. Set
A0 to “0” for a write command and set A0 to “1” for a
read command. The value of bits A1 and A2 are
decided by the connection of the AD pin.
Table 1 Slave Address
AD
A7:A3
A2:A1
GND
SCL
SDA
A0
00
01101
VCC
01
10
0/1
11
AD connected to GND, A2:A1=00;
AD connected to VCC, A2:A1=11;
AD connected to SCL, A2:A1=01;
AD connected to SDA, A2:A1=10;
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 400kHz I2C with 4.7kΩ, 1MHz I2C with 2kΩ).
The maximum clock frequency specified by the I2C
standard is 1MHz. In this discussion, the master is the
microcontroller and the slave is the IS31FL3729.
The timing diagram for the I2C is shown in Figure 4.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS31FL3729’s acknowledge. The master
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releases the SDA line high (through a pull-up resistor).
Then the master sends an SCL pulse. If the
IS31FL3729 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
Following acknowledge of IS31FL3729, the register
address byte is sent, most significant bit first.
IS31FL3729 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3729 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
To write multiple bytes of data into IS31FL3729, load
the address of the data register that the first data byte
is intended for. During the IS31FL3729 acknowledge
of receiving the data byte, the internal address pointer
will increment by one. The next data byte sent to
IS31FL3729 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3729
(Figure 7).
READING OPERATION
Most of the registers can be read.
To read the register, after I2C start condition, the bus
master must send the IS31FL3729 device address
____
with the R/W bit set to “0”, followed by the register
address which determines which register is accessed.
Then restart I2C, the bus master should send the
____
IS31FL3729 device address with the R/W bit set to
“1”. Data from the register defined by the command
byte is then sent from the IS31FL3729 to the master
(Figure 8).
9
IS31FL3729
Figure 4
I2C Interface Timing
Figure 5
Figure 6
Figure 7
I2C Bit Transfer
I2C Writing to IS31FL3729 (Typical)
I2C Writing to IS31FL3729 (Automatic Address Increment)
Figure 8
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I2C Reading from IS31FL3729
10
IS31FL3729
Table 5 Register Definition
Address
Name
Function
Table
R/W
Default
01h~8Fh
PWM Register
Set PWM value for LED
6
R/W
0000 0000
90h~9Fh
Scaling Register
Control the DC output current of each
CSy
7
R/W
0000 0000
A0h
Configuration Register
Configure the operation mode
8
R/W
0000 0000
A1h
Global Current Control
Register
Set the global current
9
R/W
0000 0000
B0h
Pull Down/Up Resistor
Selection Register
Set the pull down resistor for SWx and
pull up resistor for CSy
10
R/W
0011 0011
B1h
Spread Spectrum Register
Spread spectrum function enable
11
R/W
0000 0000
B2h
PWM Frequency Register
Set the PWM frequency
12
R/W
0000 0001
Open/Short Register
Store the open or short information
13
R/W
0000 0000
Reset Register
Reset all register to POR state
-
W
0000 0000
B3h~C4h
CFh
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IS31FL3729
PWM Register
T01
T02
T03
T04
T05
T06
T07
T08
T09
VCC
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
PWM PWM PWM
CS16
10
20
30
40
50
60
70
80
90
CS15
0F
1F
2F
3F
4F
5F
6F
7F
8F
CS14
0E
1E
2E
3E
4E
5E
6E
7E
8E
16×8
15×9
Y
X
PWM PWM PWM
CS3
03
13
23
33
43
53
63
73
83
CS2
02
12
22
32
42
52
62
72
82
01
11
21
31
41
51
61
71
81
CS1
Figure 9
Table 6 01h~8Fh PWM Register
Duty
Bit
D7:D0
Name
PWM
Default
0000 0000
PWM
I OUT ( PEAK ) Duty
256
PWM
(1)
7
D[n ] 2
n
n 0
Where Duty is the duty cycle of SWx, when n=9,
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30s
1
1
30s 0.8s 0.27s 9 9.32
(2)
When n=8,
Each dot has a byte to modulate the PWM duty in
256 steps. The PWM clock frequency is set by the
PWM Frequency Register (B2h). The following
calculations assume B2h is configured for 32kHz
PWM, B2h= “0x01” for tSCAN=30µs, the period of
scanning and 0.8μs is tNOL1, the non-overlap time and
0.27μs is the CSx delay time.
The value of the PWM Registers decides the
average current of each LED noted ILED.
ILED computed by Formula (1):
I LED
PWM Register
Duty
30s
1 1
30s 0.8s 0.27s 8 8.29
(2)
IOUT is the output current of CSy (y=1~16),
I OUT( PEAK)
342 GCC SL
RISET 64 256
(3)
GCC is the Global Current Control Register (A1h)
value, SL is the Scaling Register value as Table 9
and RISET is the external resistor of ISET pin. D[n]
stands for the individual bit value, 1 or 0, in location
n.
For example: if D7:D0=1011 0101 (0xB5, 181),
GCC= 100 0000, RISET=10kΩ, SL=1111 1111:
I LED
342
64 255
1
181
10 k 64 256 9 . 32 256
12
IS31FL3729
Scaling Register
T01
T02
T03
T04
T05
T06
T07
T08
T09
VCC
SW1
SW2
SW3
SW4
SW5
CS16
9F
CS15
9E
CS14
9D
CS3
92
CS2
91
CS1
90
SW6
SW7
SW8
SW9
Y
X
Figure 10
IOUT is the output current of CSy (y=1~16), GCC is
the Global Current Control Register (A1h) value and
RISET is the external resistor of RISET pin. D[n] stands
for the individual bit value, 1 or 0, in location n.
For example: if RISET=10kΩ, GCC=100 0000,
SL=0111 1111:
Table 7 90h ~ 9Fh Scaling Register
Bit
D7:D0
Name
SL
Default
0000 0000
Scaling register control the DC output current of each
CSy. Each CSy has a byte to modulate the scaling in
256 steps.
The value of the Scaling Register decides the peak
current of each LED noted IOUT(PEAK).
IOUT(PEAK) computed by Formula (3):
342 GCC SL
IOUT( PEAK)
RISET 64 256
SL
Scaling Register
(3)
SL
7
D[n] 2
n
127
n0
IOUT
342 64 127
16.9mA
10k 64 256
I LED 16 . 9 mA
1
PWM
9 . 27
256
7
D[n] 2
n
n0
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13
IS31FL3729
Table 8 A0h Configuration Register
Table 9 A1h Global Current Control Register
Bit
D7:D4
D3
D2:D1
D0
Bit
D7
D6:D0
Name
SWS
LGC
OSDE
SSD
Name
-
GCC
Default
0001
0
00
0
Default
0
000 0000
The Configuration Register sets operating mode of
IS31FL3729.
SSD
0
1
Software Shutdown Control
Software shutdown
Normal operation
OSDE
00
01/11
10
Open Short Detection Enable
Disable open/short detection
Enable open detection
Enable short detection
LGC
0
1
H/L logic
1.4V/0.4V
2.4V/0.6V
SWS
0000
0001
0010
SWx Setting
n=9, SW1~SW9, 9SW×15CS matrix
n=8, SW1~SW8, 8SW×16CS matrix
n=7, SW1~SW7, 7SW×16CS matrix, SW8
no-active
n=6, SW1~SW6, 6SW×16CS matrix,
SW7~SW8 no-active
n=5, SW1~SW5, 5SW×16CS matrix,
SW6~SW8 no-active
n=4, SW1~SW4, 4SW×16CS matrix,
SW5~SW8 no-active
n=3, SW1~SW3, 3SW×16CS matrix,
SW4~SW8 no-active
n=2, SW1~SW2, 2SW×16CS matrix,
SW3~SW8 no-active
SW1~SW9 with same phase, all on.
SW1~SW9, SW1~SW9, 9SW×15CS matrix
0011
0100
0101
0110
0111
1000
Others
When OSDE set to “01”, open detection will be trigger
once, the user could trigger open detection again by
set OSDE from “00” to “01”.
When OSDE set “10”, short detection will be trigger
once, the user could trigger short detection again by
set OSDE from “00” to “10”.
When SSD is “0”, IS31FL3729 works in software
shutdown mode and to normal operate the SSD bit
should set to “1”.
SWS control the duty cycle of the SWx, default mode is
1/8.
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The Global Current Control Register modulates all
CSy (y=1~16) DC current which is noted as IOUT in 65
steps, maximum GCC is “100 0000”, if GCC>
“1000000”, GCC= “100 0000”.
IOUT is computed by the Formula (3):
IOUT( PEAK)
342 GCC SL
RISET 64 256
7
GCC D[ n] 2 n
n 0
Where D[n] stands for the individual bit value 1 or 0, in
location n.
Table 10 B0h Pull Down/Up Resistor Selection
Register
Bit
D7
D6:D4
D3
D2:D0
Name
PHC
SWPDR
-
CSPUR
Default
0
011
0
011
Set pull down resistor for SWx and pull up resistor for
CSy.
PHC
0
1
Phase choice
0 degree phase delay
180 degree phase delay
SWPDR
000
001
010
011
100
101
110
111
SWx Pull down Resistor Selection Bit
No pull down resistor
0.5kΩ only in SWx off time
1.0kΩ only in SWx off time
2.0kΩ only in SWx off time
1.0kΩ all the time
2.0kΩ all the time
4.0kΩ all the time
8.0kΩ all the time
CSPUR
000
001
010
011
100
101
110
111
CSy Pull up Resistor Selection Bit
No pull up resistor
0.5kΩ only in CSx off time
1.0kΩ only in CSx off time
2.0kΩ only in CSx off time
1.0kΩ all the time
2.0kΩ all the time
4.0kΩ all the time
8.0kΩ all the time
14
IS31FL3729
Table 11 B1h Spread Spectrum Register
Bit
D7:D6
D4
D3:D2
D1:D0
Name
-
SSP
RNG
CLT
Default
00
0
00
00
When SSP enable, the spread spectrum function will
be enabled and the RNG & CLT bits will adjust the
range and cycle time of spread spectrum function.
SSP
0
1
Spread spectrum function enable
Disable
Enable
RNG
00
01
10
11
Spread spectrum range
±5%
±15%
±24%
±34%
Table 13 B3h~C4h Open/Short Register (Read
Only)
Bit
D7:D0
Name
CS16:CS09, CS08:CS01
Default
0000 0000
When OSDE (A0h) is set to “01”, open detection will
be trigger once, and the open information will be
stored at B3h~C4h.
When OSDE (A0h) set to “10”, short detection will be
trigger once, and the short information will be stored at
B3h~C4h.
Before set OSDE, the GCC should set to 0x01.
T01
T02
SW1
T03
SW2
T04
SW3
T05
SW4
T06
SW5
T07
SW6
T08
SW7
T09
SW8
SW9
VCC
CS16
Spread spectrum cycle time
1980μs
1200μs
820μs
660μs
CLT
00
01
10
11
CS15
CS14
CS13
CS12
CS11
Table 12 B2h PWM Frequency
Bit
D7:D3
D2:D0
Name
-
PWMF
Default
00000
001
Set the PWM frequency, default is 32kHz. In order to
avoid LED display flicker, it is recommended PWM
frequency ÷ n is higher than 100Hz, so when PWM
frequency is 0.5kHz, n cannot be more than 4, when
PWM frequency is 0.25kHz, n cannot be more than 2.
CS10
CS9
CS8
CS7
CS6
CS5
CS4
CS3
PWMF
000
001
010
011
100
101
110
111
PWM frequency setting
55kHz
32kHz
4kHz
2kHz
1kHz
0.5kHz, (n≤4)
0.25KHz, (n≤2)
80kHz
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CS2
CS1
Figure 11
Open/Short Register
CFh Reset Register
Once the Reset Register is updated with
IS31FL3729 registers will be reset to
values. Upon initial power-up, the
registers will also reset to their default
blank display.
0xAE, all the
their default
IS31FL3729
values for a
15
IS31FL3729
APPLICATION INFORMATION
Scanning cycle T=62.14µs((30µs+0.8µs+0.27µs)×2) (n=2)
Scanning cycle T=248.56µs((30µs+0.8µs+0.27µs)×8) (n=8)
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
CS16
CS1
tNOL2=0.27µs
tSCAN=30µs
tNOL1=0.8µs
Scanning cycle T=279.63µs((30µs+0.8µs+0.27µs)×9) (n=9)
De-Ghost time
PWM Duty is variable from 0/256~255/256
I OUT
342 GCC SL
RISET 256 256
Figure 12 Scanning Timing
SCANNING TIMING
As shown in Figure above, the SW1~SW9 is turned on
by serial, LED is driven 15 by 9 within the SWx (x=1~9)
on time (SWx, x=1~9 is source and it is high when LED
on) , including the non-overlap blanking time during
scan, the duty cycle of SWx (active high, x=1~9) is
(n=9):
Duty
30s
1
1
30s 0.8s 0.27s 9 9.32
(2)
≥2.4V
VCC
Or (n=8):
Duty
shutdown the state Function Registers can be
accessed but all analog circuits are disabled to
conserve power. Once VCC stabilizes > 2.4V, a rising
edge of the SDB signal will reset the I2C bus and cause
the chip to exit hardware shutdown mode. Since there
could be I2C bus transactions prior to the rising edge of
the SDB pin, it is recommended to allow 10us prior to
and after the rising edge before beginning any I2C bus
transaction.
*Note 6
30s
1 1
30s 0.8s 0.27s 8 8.29
≥10us
*Note 7
(2)
Where PWM Frequency Register B2h= “0x01” (PWM
frequency = 32kHz) for tSCAN = 30μs, the period of
scanning and 0.8μs is tNOL1, the non-overlap time and
0.27μs is the CSx delay time.
POWER ON SEQUENCE
The IS31FL3729 integrates a power-on reset (POR)
feature associated with the input supply voltage VCC.
The IS31FL3729 will be initialized when VCC exceeds
2.4V (typ., 2.7V max.) until then all the control circuits
and configuration registers will be held in reset while
the internal voltage stabilizes (≥2.4V).
SDA
Initial operation
SCL
SDB
*Note 8
≥10us
≥10us
Reset IIC bus at rising edge
Figure 13 SDB Pin Sequence
Note 6: There should be no I2C operation 10µs before VCC remain
≥2.4V.
Note 7: I2C operation is allowed while SDB is low and VCC ≥2.4V.
Note 8: There should be no I2C operation 10µs before and after SDB
rising edge.
The IS31FL3729 enters a hardware shutdown mode
when the SDB pin is pulled low. During hardware
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16
IS31FL3729
PWM CONTROL
256
After setting the IOUT and GCC, the brightness of each
LEDs (LED average current (ILED)) can be modulated
with 256 steps by PWM Register, as described in
Formula (1).
224
PWM
I OUT ( PEAK ) Duty
256
(1)
PWM Data
I LED
192
Where PWM is PWM Registers’ (01h~8Fh) data
showing in Table 6.
96
32
0
0
4
8
12
16
20
24
28
32
Intensity Steps
342 GCC SL
I OUT( PEAK)
RISET 64 256
Figure 14 Gamma Correction (32 Steps)
342
64 255
1
181
(n=9)
10 k 64 256 9 . 32 256
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
GAMMA CORRECTION
In order to perform a better visual LED breathing effect
we recommend using a gamma corrected PWM value
to set the LED intensity. This results in a reduced
number of steps for the LED intensity setting, but
causes the change in intensity to appear more linear to
the human eye.
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Since the IS31FL3729 can modulate the
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing
each subsequent LED intensity setting such that the
changes in brightness matches the human eye's
brightness curve.
Table 12 32 Gamma Steps with 256 PWM Steps
C(0)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
4
6
10
13
18
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
22
28
33
39
46
53
61
69
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
78
86
96
106
116
126
138
149
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
161
173
186
199
212
226
240
255
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128
64
For example, in Figure 1, if RISET= 10kΩ, PWM= 1011
0101 (0xB5, 181), and GCC= 100 0000, SL= 1111 1111,
then,
I LED
160
Choosing more gamma steps provides for a more
continuous looking breathing effect. This is useful for
very long breathing cycles. The recommended
configuration is defined by the breath cycle T. When
T=1s, choose 32 gamma steps, when T=2s, choose 64
gamma steps. The user must decide the final number
of gamma steps not only by the LED itself, but also
based on the visual performance of the finished
product.
Table 13 64 Gamma Steps with 256 PWM Steps
C(0)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
3
4
5
6
7
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
8
10
12
14
16
18
20
22
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
24
26
29
32
35
38
41
44
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
47
50
53
57
61
65
69
73
C(32)
C(33)
C(34)
C(35)
C(36)
C(37)
C(38)
C(39)
77
81
85
89
94
99
104
109
C(40)
C(41)
C(42)
C(43)
C(44)
C(45)
C(46)
C(47)
114
119
124
129
134
140
146
152
C(48)
C(49)
C(50)
C(51)
C(52)
C(53)
C(54)
C(55)
158
164
170
176
182
188
195
202
C(56)
C(57)
C(58)
C(59)
C(60)
C(61)
C(62)
C(63)
209
216
223
230
237
244
251
255
17
IS31FL3729
256
architecture any parasitic capacitance found in the
constant-current outputs or the PCB traces to the LEDs
may provide sufficient current to dimly light an LED to
create a ghosting effect.
224
PWM Data
192
To prevent this LED ghost effect, the IS31FL3729 has
integrated Pull down resistors for each SWx (x=1~9)
and Pull up resistors for each CSy (y=1~16). Select the
right SWx Pull down resistor (B0h) and CSy Pull up
resistor (B0h) which eliminates the ghost LED for a
particular matrix layout configuration.
160
128
96
64
Typically, selecting the 2kΩ will be sufficient to
eliminate the LED ghost phenomenon.
32
0
0
8
16
24
32
40
48
56
64
Intensity Steps
Figure 15 Gamma Correction (64 Steps)
Note: The data of 32 gamma steps is the standard value and the data
of 64 gamma steps is the recommended value.
OPERATING MODE
IS31FL3729 can only operate in PWM Mode. The
brightness of each LED can be modulated with 256
steps by PWM registers. For example, if the data in
PWM Register is “0000 0100”, then the PWM is the
fourth step.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
OPEN/SHORT DETECT FUNCTION
IS31FL3729 has individual LED open and short
detection capability.
By setting the OSDE bits of the Configuration Register
(A0h) from “00” to “01” or “10”, the LED Open/short
Register will begin storing the open/short information.
After 2 scan cycles, the MCU can read the open/short
information stored in registers B3h~C4h. The
open/short data will not get refreshed while setting the
OSDE bit of the Configuration Register.
There are two configurations which need to be set prior
to configuring the the OSDE bits:
1) 0x0F≤A1h≤0x40 adjust LED current
2) B0h=0x00, disable pullup/pulldown resistors
Where A1h is the Global Current Control Register and
B0h is the Pull Down/UP Resistor Selection Register.
The detect action is one-time event, so each time
before reading out the open/short information, the
OSDE bit of the Configuration Register (A0h) needs to
be set from “0” to “1” (clear before set operation).
DE-GHOST FUNCTION
The “ghost” term is used to describe the behavior of an
LED that should be OFF but instead glows dimly when
another LED is turned ON. A ghosting effect typically
can occur when multiplexing LEDs. In matrix
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The SWx Pull down resistors and CSy Pull up resistors
are active only when the CSy/SWx output working the
OFF state and therefore no power is lost through these
resistors.
SHUTDOWN MODE
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
Software Shutdown
By setting SSD bit of the Configuration Register (A0h)
to “0”, the IS31FL3729 will operate in software
shutdown mode. When the IS31FL3729 is in software
shutdown, all current sources are switched off, so that
the matrix is blanked. All registers can be operated.
Typical current consumption is 3μA.
Hardware Shutdown
The chip enters hardware shutdown when the SDB pin
is pulled low. When the IS31FL3729 is in hardware
shutdown, all current sources are switched off, so that
the matrix is blanked. All registers can be operated.
Typical current consumption is 3μA.
The chip releases hardware shutdown when the SDB
pin is pulled high.
If VCC has a risk of dropping below 1.75V but remain
above 0.1V while the SDB pin is pulled low, please
re-initialize all Function Registers before SDB is pulled
high.
LAYOUT
As described previously, depending on the current set
resistor (RISET) value and current register settings, the
chip can consumes lots of power. Please consider the
below factors during the PCB layout phase.
1. The VCC capacitors need to be close to the VCC pin
23 with their ground pins well connected to the GND of
the chip.
2. RISET should be close to the chip and the ground side
should well connect to the GND of the chip.
3. The thermal pad should connect to ground pins and
the PCB should have the thermal pad too, usually this
pad should have 9 or 16 vias thru the PCB to the other
18
IS31FL3729
side’s ground area to help radiate the heat. About the
thermal pad size, please refer to the land pattern of
each package.
4. The CSy pins will have a maximum current of 35mA
(RISET=10kΩ). However, the SWx pins maximum
current is larger since it is the combined current of the
CSy pins. Therefore, the width of the SWx trace needs
to be much wider than the CSy trace.
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Rev. C, 12/23/2020
19
IS31FL3729
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 15
Classification Profile
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Rev. C, 12/23/2020
20
IS31FL3729
PACKAGE INFORMATION
QFN-32
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Rev. C, 12/23/2020
21
IS31FL3729
eTQFP-32
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Rev. C, 12/23/2020
22
IS31FL3729
RECOMMENDED LAND PATTERN
QFN-32
eTQFP-32
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use.
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Rev. C, 12/23/2020
23
IS31FL3729
REVISION HISTORY
Revision
Detail Information
Date
0A
Preliminary release
2019.04.25
0B
Correct slave address setting in Table 1
2019.04.29
A
Add APPLICATION INFORMATION and functional block
2019.06.12
B
Add eTQFP-32 package
2019.11.29
C
1 Add test condition for tSCAN/ tNOL1/tNOL2
2 Add POWER ON SEQUENCE in APPLICATION INFORMATION
2012.12.23
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