MC9S08RC8/16/32/60
MC9S08RD8/16/32/60
MC9S08RE8/16/32/60
MC9S08RG32/60
Data Sheet
HCS08
Microcontrollers
MC9S08RG60/D
Rev. 1.08, 4/2004
WWW.MOTOROLA.COM/SEMICONDUCTORS
DOCUMENT NUMBER
MC9S08RG60/D
MC9S08RC/RD/RE/RG
SoC Guide
V1.08
22 APR 2004
8-/16-Bit Products Division
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
©Motorola, Inc., 2004
MOTOROLA
MC9S08RC/RD/RE/RG
3
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://motorola.com/semiconductors
The following revision history table summarizes changes contained in this document.
Version
Number
Revision
Date
1.07
2/4/2004
Initial external release.
1.08
4/22/2004
Changes to Table A-5 in electricals section.
Description of Changes
This product incorporates SuperFlash Technology licensed from SST.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
4
MC9S08RC/RD/RE/RG
Motorola, Inc., 2004
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
List of Sections
Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Section 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 5 Resets, Interrupts, and System Configuration . . . . . . . . . . . . . . . 57
Section 6 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Section 7 Carrier Modulator Timer (CMT) Module . . . . . . . . . . . . . . . . . . . . . 93
Section 8 Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Section 9 Keyboard Interrupt (KBI) Module . . . . . . . . . . . . . . . . . . . . . . . . . 121
Section 10 Timer/PWM Module (TPM) Module . . . . . . . . . . . . . . . . . . . . . . . 127
Section 11 Serial Communications Interface (SCI) Module. . . . . . . . . . . . . 143
Section 12 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . 161
Section 13 Analog Comparator (ACMP) Module . . . . . . . . . . . . . . . . . . . . . 177
Section 14 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Appendix B Ordering Information and Mechanical Drawings . . . . . . . . . . 223
MOTOROLA
MC9S08RC/RD/RE/RG
5
List of Sections
6
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Table of Contents
Section 1 Introduction
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standard Features of the HCS08 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features of MC9S08RC/RD/RE/RG Series of MCUs . . . . . . . . . . . . . . . . . . . . . 15
Devices in the MC9S08RC/RD/RE/RG Series. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Section 2 Pins and Connections
2.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
Device Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
Recommended System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.3
PTD1/RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.4
Background/Mode Select (PTD0/BKGD/MS). . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.5
IRO Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.6
General-Purpose I/O and Peripheral Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.7
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Section 3 Modes of Operation
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Active Background Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stop1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stop2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stop3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Active BDM Enabled in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVD Reset Enabled in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
On-Chip Peripheral Modules in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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MC9S08RC/RD/RE/RG
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Table of Contents
Section 4 Memory
4.1
4.1.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
MC9S08RC/RD/RE/RG Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset and Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register Addresses and Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Program and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Program and Erase Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Burst Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Access Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Vector Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FLASH Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FLASH Clock Divider Register (FCDIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FLASH Options Register (FOPT and NVOPT) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
FLASH Configuration Register (FCNFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FLASH Protection Register (FPROT and NVPROT) . . . . . . . . . . . . . . . . . . . . . . 52
FLASH Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FLASH Command Register (FCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 5 Resets, Interrupts, and System Configuration
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.6.1
5.6.2
5.6.3
5.6.4
8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
MCU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External Interrupt Request (IRQ) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Interrupt Vectors, Sources, and Local Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Low-Voltage Detect (LVD) System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LVD Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LVD Interrupt and Safe State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-Voltage Warning (LVW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
5.7
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.8
Reset, Interrupt, and System Control Registers and Control Bits . . . . . . . . . . . . . . 64
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC) . . . . . . . . . . . . . . . . 64
5.8.2
System Reset Status Register (SRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.8.3
System Background Debug Force Reset Register (SBDFR). . . . . . . . . . . . . . . . 67
5.8.4
System Options Register (SOPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.8.5
System Device Identification Register (SDIDH, SDIDL) . . . . . . . . . . . . . . . . . . . 69
5.8.6
System Real-Time Interrupt Status and Control Register (SRTISC) . . . . . . . . . . 69
5.8.7
System Power Management Status and Control 1 Register (SPMSC1) . . . . . . . 71
5.8.8
System Power Management Status and Control 2 Register (SPMSC2) . . . . . . . 72
Section 6 Central Processor Unit (CPU)
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Programmer’s Model and CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Inherent Addressing Mode (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Relative Addressing Mode (REL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Immediate Addressing Mode (IMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Direct Addressing Mode (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Extended Addressing Mode (EXT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Special Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
BGND Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MOTOROLA
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Table of Contents
Section 7 Carrier Modulator Timer (CMT) Module
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.6
7.6.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
CMT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
CMT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
CMT Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and
CMTCGL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.6.2
CMT Output Control Register (CMTOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.6.3
CMT Modulator Status and Control Register (CMTMSC) . . . . . . . . . . . . . . . . . 107
7.6.4
CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3, and
CMTCMD4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Section 8 Parallel Input/Output
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.4.1
8.4.2
8.5
10
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Parallel I/O Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Data Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Internal Pullup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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8.6
Parallel I/O Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.6.1
Port A Registers (PTAD, PTAPE, and PTADD) . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.6.2
Port B Registers (PTBD, PTBPE, and PTBDD) . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.6.3
Port C Registers (PTCD, PTCPE, and PTCDD) . . . . . . . . . . . . . . . . . . . . . . . . 118
8.6.4
Port D Registers (PTDD, PTDPE, and PTDDD) . . . . . . . . . . . . . . . . . . . . . . . . 119
8.6.5
Port E Registers (PTED, PTEPE, and PTEDD) . . . . . . . . . . . . . . . . . . . . . . . . . 120
Section 9 Keyboard Interrupt (KBI) Module
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.4
9.4.1
9.4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
KBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Keyboard Interrupt (KBI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Pin Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Edge and Level Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
KBI Interrupt Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
KBI Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
KBI x Status and Control Register (KBIxSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
KBI x Pin Enable Register (KBIxPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Section 10 Timer/PWM Module (TPM) Module
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.3 TPM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.4.1 External TPM Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.4.2 TPM1CHn — TPM1 Channel n I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.5.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.5.2 Channel Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.5.3 Center-Aligned PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.6 TPM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.1 Clearing Timer Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.2 Timer Overflow Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.3 Channel Event Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.6.4 PWM End-of-Duty-Cycle Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.7 TPM Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.7.1 Timer Status and Control Register (TPM1SC). . . . . . . . . . . . . . . . . . . . . . . . . . 136
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10.7.2
10.7.3
10.7.4
10.7.5
Timer Counter Registers (TPM1CNTH:TPM1CNTL) . . . . . . . . . . . . . . . . . . . . . 138
Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) . . . . . . . . . . . . . 139
Timer Channel n Status and Control Register (TPM1CnSC). . . . . . . . . . . . . . . 140
Timer Channel Value Registers (TPM1CnVH:TPM1CnVL) . . . . . . . . . . . . . . . . 142
Section 11 Serial Communications Interface (SCI) Module
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.2 SCI System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
11.4 Transmitter Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.4.1 Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.4.2 Send Break and Queued Idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.5 Receiver Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.5.1 Receiver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.5.2 Data Sampling Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.5.3 Receiver Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6 Interrupts and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.7 Additional SCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.7.1 8- and 9-Bit Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.8 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.8.1 Loop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.8.2 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9 SCI Registers and Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.1 SCI Baud Rate Registers (SCI1BDH, SCI1BHL) . . . . . . . . . . . . . . . . . . . . . . . . 153
11.9.2 SCI Control Register 1 (SCI1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.9.3 SCI Control Register 2 (SCI1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.9.4 SCI Status Register 1 (SCI1S1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.9.5 SCI Status Register 2 (SCI1S2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.9.6 SCI Control Register 3 (SCI1C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.9.7 SCI Data Register (SCI1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Section 12 Serial Peripheral Interface (SPI) Module
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.2.1 SPI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.2.2 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12
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12.2.3 SPI Baud Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.3.1 SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.3.2 SPI Pin Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.3.3 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.3.4 Mode Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.4 SPI Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.4.1 SPI Control Register 1 (SPI1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.4.2 SPI Control Register 2 (SPI1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.4.3 SPI Baud Rate Register (SPI1BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.4.4 SPI Status Register (SPI1S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.4.5 SPI Data Register (SPI1D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Section 13 Analog Comparator (ACMP) Module
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.4.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.4.2 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.4.3 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.4.4 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.5 ACMP Status and Control Register (ACMP1SC) . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Section 14 Development Support
14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.3 Background Debug Controller (BDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.3.1 BKGD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.3.2 Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.3.3 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.3.4 BDC Hardware Breakpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.4 On-Chip Debug System (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
14.4.1 Comparators A and B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
14.4.2 Bus Capture Information and FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.4.3 Change-of-Flow Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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14.4.4 Tag vs. Force Breakpoints and Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14.4.5 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14.4.6 Hardware Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.5 Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.5.1 BDC Registers and Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.5.2 System Background Debug Force Reset Register (SBDFR). . . . . . . . . . . . . . . 199
14.5.3 DBG Registers and Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Appendix A Electrical Characteristics
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.9.1
A.9.2
A.9.3
A.10
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Electrostatic Discharge (ESD) Protection Characteristics . . . . . . . . . . . . . . . . . . . 209
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Supply Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Analog Comparator (ACMP) Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Timer/PWM (TPM) Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
FLASH Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Appendix B Ordering Information and Mechanical Drawings
B.1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
B.2 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
B.2.1
28-Pin SOIC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
B.2.2
28-Pin PDIP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
B.2.3
32-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
B.2.4
44-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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SoC Guide — MC9S08RG60/D V1.08
Section 1 Introduction
1.1 Overview
The MC9S08RC/RD/RE/RG are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in this family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
1.2 Features
Features have been organized to reflect:
•
Standard features of the HCS08 Family
•
Additional features of the MC9S08RC/RD/RE/RG MCU
1.2.1 Standard Features of the HCS08 Family
•
HCS08 CPU (central processor unit)
•
HC08 instruction set with added BGND instruction
•
Background debugging system (see also the Development Support section)
•
Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
•
Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module supports both tag and force
breakpoints.
•
Support for up to 32 interrupt/reset sources
•
Power-saving modes: wait plus three stops
•
System protection features:
–
Optional computer operating properly (COP) reset
–
Low-voltage detection with reset or interrupt
–
Illegal opcode detection with reset
–
Illegal address detection with reset (some devices don’t have illegal addresses)
1.2.2 Features of MC9S08RC/RD/RE/RG Series of MCUs
•
8 MHz internal bus frequency
•
On-chip in-circuit programmable FLASH memory with block protection and security option (see
Table 1-1 for device specific information)
•
On-chip random-access memory (RAM) (see Table 1-1 for device specific information)
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Introduction
•
Low power oscillator capable of operating from crystal or resonator from 1 to 16 MHz
•
On-chip analog comparator with internal reference (ACMP1) see Table 1-1
–
Full rail-to-rail supply operation
–
Option to compare to a fixed internal bandgap reference voltage
•
Serial communications interface module (SCI1) — see Table 1-1
•
Serial peripheral interface module (SPI1) — see Table 1-1
•
2-channel, 16-bit timer/pulse-width modulator (TPM1) module with selectable input capture,
output compare, and edge-aligned or center-aligned PWM capability on each channel.
•
Keyboard interrupt ports (KBI1, KBI2)
•
–
Providing 12 keyboard interrupts
–
Eight with falling-edge/low-level plus four with selectable polarity
Carrier modulator timer (CMT) with dedicated infrared output (IRO) pin
–
Drives IRO pin for remote control communications
–
Can be disconnected from IRO pin and used as output compare timer
–
IRO output pin has high-current sink capability
•
Eight high-current pins (limited by maximum package dissipation)
•
Software selectable pullups on ports when used as input. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
•
39 general-purpose input/output (I/O) pins, depending on package selection
•
Four packages available
–
28-pin plastic dual in-line package (PDIP)
–
28-pin small outline integrated circuit (SOIC)
–
32-pin low-profile quad flat package (LQFP)
–
44-pin low-profile quad flat package (LQFP)
1.2.3 Devices in the MC9S08RC/RD/RE/RG Series
Table 1-1 below lists the devices available in the MC9S08RC/RD/RE/RG series and summarizes the
differences in functions and configuration between them.
Table 1-1 Devices in the MC9S08RC/RD/RE/RG Series
Device
9S08RG32/60
9S08RE8/16/32/60
9S08RD8/16/32/60
9S08RC8/16/32/60
FLASH
RAM(1)
ACMP(2)
SCI
SPI
32K/60K
8/16K/32K/60K
8/16K/32K/60K
8/16K/32K/60K
2K/2K
1K/1K/2K/2K
1K/1K/2K/2K
1K/1K/2K/2K
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
No
No
NOTES:
1. 3S08RC/RD/RE8/16 ROM MCU devices have 512 bytes RAM instead of 1K bytes.
2. Only available in 32- or 44-pin LQFP packages.
16
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
1.3 MCU Block Diagram
This block diagram shows the structure of the MC9S08RC/RD/RE/RG MCUs.
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
PTB7/TPM1CH1
PTE6
PTB5
PTB4
PTB3
PTB2
PTB1/RxD1
PTB0/TxD1
PTC7/SS1
PTC6/SPSCK1
PTC5/MISO1
PTC4/MOSI1
PTC3/KBI2P3
PTC2/KBI2P2
PTC1/KBI2P1
PTC0/KBI2P0
NOTE 1
PTD6/TPM1CH0
PTD5/ACMP1+
PTD4/ACMP1–
PTD3
PTD2/IRQ
PTD1/RESET
PTD0/BKGD/MS
NOTES
1, 3, 4
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
USER FLASH
(RC/RD/RE/RG60 = 63,364 BYTES)
(RC/RD/RE/RG32 = 32,768 BYTES)
(RC/RD/RE16 = 16,384 BYTES)
(RC/RD/RE8 = 8192 BYTES)
USER RAM
(RC/RD/RE/RG32/60 = 2048 BYTES)
(RC/RD/RE8/16 = 1024 BYTES)
LOW-POWER OSCILLATOR
VDD
VSS
2-CHANNEL TIMER/PWM
MODULE (TPM1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
PORT E
EXTAL
XTAL
ANALOG COMPARATOR
MODULE (ACMP1)
VOLTAGE
REGULATOR
NOTES1, 2, 6
PTA0/KBI1P0
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
4-BIT KEYBOARD
INTERRUPT MODULE (KBI2)
PTA7/KBI1P7–
PTA1/KBI1P1
PORT B
HCS08 SYSTEM CONTROL
DEBUG
MODULE (DBG)
PORT C
CPU
7
PORT D
BDC
PORT A
INTERNAL BUS
HCS08 CORE
8
NOTES 1, 5
PTE7– PTE0 NOTE 1
CARRIER MODULATOR
TIMER MODULE (CMT)
IRO NOTE 5
NOTES:
1. Port pins are software configurable with pullup device if input port
2. PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD.
3. IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1)
4. The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1)
5. High current drive
6. Pins PTA[7:0] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBI1Pn = 1).
Figure 1-1 MC9S08RC/RD/RE/RG Block Diagram
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17
Introduction
Table 1-2 lists the functional versions of the on-chip modules.
Table 1-2 Block Versions
Module
Version
Analog Comparator (ACMP)
1
Carrier Modulator Transmitter (CMT)
1
Keyboard Interrupt (KBI)
1
Serial Communications Interface (SCI)
1
Serial Peripheral Interface (SPI)
3
Timer Pulse-Width Modulator (TPM)
1
Central Processing Unit (CPU)
2
Debug Module (DBG)
1
FLASH
1
System Control
2
1.4 System Clock Distribution
RTI
OSC
RTICLKS
SYSTEM
CONTROL
LOGIC
TPM
CMT
SCI
SPI
RTI
÷2
OSCOUT*
OSC
CPU
BUSCLK
BDC
ACMP
* OSCOUT is the alternate BDC clock source for the MC9S08RC/RD/RE/RG.
RAM
FLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A.
Figure 1-2 System Clock Distribution Diagram
Figure 1-2 shows a simplified clock connection diagram for the MCU. The CPU operates at the input
frequency of the oscillator. The bus clock frequency is half of the oscillator frequency and is used by all
of the internal circuits with the exception of the CPU and RTI. The RTI can use either the oscillator input
or the internal RTI oscillator as its clock source.
18
MC9S08RC/RD/RE/RG
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SoC Guide — MC9S08RG60/D V1.08
Section 2 Pins and Connections
2.1 Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
34 PTA1/KBI1P1
PTA2/KBI1P2
PTE5
38
35
PTE6
39
PTA3/KBI1P3
PTE7
40
36
PTA4/KBI1P4
41
PTE4
PTA5/KBI1P5
42
PTB0/TxD1 1
37
PTA6/KBI1P6
43
44 PTA7/KBI1P7
2.2 Device Pin Assignment
33 PTA0/KBI1P0
28
XTAL
VSS
7
27
PTD3
IRO
8
26
PTD2/IRQ
PTB5
9
25
PTD1/RESET
PTB6
10
24
PTD0/BKGD/MS
23
PTC7/SS1
PTC6/SPSCK1 22
PTC0/KBI2P0 12
PTB7/TPM1CH1 11
21
6
PTC5/MISO1
VDD
20
EXTAL
PTC4/MOSI1
29
19
5
PTE3
PTB4
18
PTD4/ACMP1–
PTE2
30
17
4
PTE1
PTB3
16
PTD5/ACMP1+
PTE0
31
15
3
PTC3/KBI2P3
PTB2
14
PTD6/TPM1CH0
PTC2/KBI2P2
32
13
2
PTC1/KBI2P1
PTB1/RxD1
Figure 2-1 MC9S08RC/RD/RE/RG in 44-Pin LQFP Package
MOTOROLA
MC9S08RC/RD/RE/RG
19
PTA5/KBI1P5
PTA4/KBI1P4
PTA3/KBI1P3
PTA2/KBI1P2
PTA1/KBI1P1
PTA0/KBI1P0
30
29
28
27
26
25
1
PTA6/KBI1P6
PTB0/TxD1
31
32 PTA7/KBI1P7
Pins and Connections
24
PTD6/TPM1CH0
XTAL
IRO
6
19
PTD2/IRQ
PTB6
7
18
PTD1/RESET
PTB7/TPM1CH1
8
17
PTD0/BKGD/MS
PTC0/KBI2P0
16
20
PTC7/SS1
5
15
VSS
PTC6/SPSCK1
EXTAL
14
21
PTC5/MISO1
4
13
VDD
PTC4/MISO1
PTD4/ACMP1–
12
22
PTC3/KBI2P3
3
11
PTB2
PTC2/KBI2P2
PTD5/ACMP1+
10
23
PTC1/KBI2P1
2
9
PTB1/RxD1
Figure 2-2 MC9S08RC/RD/RE/RG in 32-Pin LQFP Package
20
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
PTA5/KBI1P5
1
28
PTA4/KBI1P4
PTA6/KBI1P6
2
27
PTA3/KBI1P3
PTA7/KBI1P7
3
26
PTA2/KBI1P2
PTB0/TxD1
4
25
PTA1/KBI1P1
PTB1/RxD1
5
24
PTA0/KBI1P0
PTB2
6
23
PTD6/TPM1CH0
VDD
7
22
EXTAL
VSS
8
21
XTAL
IRO
9
20
PTD1/RESET
PTB7/TPM1CH1
10
19
PTD0/BKGD/MS
PTC0/KBI2P0
11
18
PTC7/SS1
PTC1/KBI2P1
12
17
PTC6/SPSCK1
PTC2/KBI2P2
13
16
PTC5/MISO1
PTC3/KBI2P3
14
15
PTC4/MOSI1
Figure 2-3 MC9S08RC/RD/RE/RG in 28-Pin SOIC Package and 28-Pin PDIP Package
2.3 Recommended System Connections
Figure 2-4 shows pin connections that are common to almost all MC9S08RC/RD/RE/RG application
systems. A more detailed discussion of system connections follows.
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21
Pins and Connections
MC9S08RC/RD/RE/RG
+
3V
PTA0/KBI1P0
VDD
SYSTEM
POWER
PTA1/KBI1P1
PTA2/KBI1P2
VDD
CBLK +
10 µF
CBY
0.1 µF
PORT
A
VSS
PTA3/KBI1P3
PTA4/KBI1P4
PTA5/KBI1P5
PTA6/KBI1P6
RF
PTA7/KBI1P7
XTAL
C2
PTB0/TxD1
C1
X1
PTB1/RxD1
PTB2
EXTAL
BACKGROUND HEADER
PORT
B
PTB3
PTB4
PTB5
PTB6
1
VDD
PTB7/TPM1CH1
BKGD/MS
NOTE 1
PORT
C
PERIPHERAL
PTC0/KBI2P0
INTERFACE TO
PTC1/KBI2P1
APPLICATION
PTC2/KBI2P2
RESET
NOTE 2
I/O AND
PTC3/KBI2P3
SYSTEM
PTC4/MOSI1
PTC5/MISO1
OPTIONAL
MANUAL
RESET
PTC6/SPSCK1
PTC7/SS1
PTD0/BKGD/MS
PTD1/RESET
PTD2/IRQ
PORT
D
PTD3
PTD4/ACMP1–
PTD5/ACMP1+
PTD6/TPM1CH0
IRO
PTE0
PTE1
PTE2
PORT
E
NOTES:
1. BKGD/MS is the
same pin as PTD0.
2. RESET is the
same pin as PTD1.
PTE3
PTE4
PTE5
PTE6
PTE7
Figure 2-4 Basic System Connections
22
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
2.3.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-µF ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise.
2.3.2 Oscillator
The oscillator in the MC9S08RC/RD/RE/RG is a traditional Pierce oscillator that can accommodate a
crystal or ceramic resonator in the range of 1 MHz to 16 MHz.
Refer to Figure 2-4 for the following discussion. RF should be a low-inductance resistor such as a carbon
composition resistor. Wire-wound resistors, and some metal film resistors, have too much inductance. C1
and C2 normally should be high-quality ceramic capacitors specifically designed for high-frequency
applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 MΩ. Higher values are sensitive to humidity and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance that
is the series combination of C1 and C2, which are usually the same size. As a first-order approximation,
use 5 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).
2.3.3 PTD1/RESET
The external pin reset function is shared with an output-only port function on the PTD1/RESET pin. The
reset function is enabled when RSTPE in SOPT is set. RSTPE is set following any reset of the MCU and
must be cleared in order to use this pin as an output-only port.
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for about 34 cycles of fSelf_reset, released, and sampled again about 38 cycles of fSelf_reset
later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry
expects the reset pin sample to return a logic 1. If the pin is still low at this sample point, the reset is
assumed to be from an external source. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system control reset status register (SRS).
Never connect any significant capacitance to the reset pin because that would interfere with the circuit and
sequence that detects the source of reset. If an external capacitance prevents the reset pin from rising to a
valid logic 1 before the reset sample point, all resets will appear to be external resets.
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2.3.4 Background/Mode Select (PTD0/BKGD/MS)
The background/mode select function is shared with an output-only port function on the PTD0/BKDG/MS
pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises, the pin functions
as the background pin and can be used for background debug communication. While functioning as a
background/mode select pin, this pin has an internal pullup device enabled. To use as an output-only port,
BKGDPE in SOPT must be cleared.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset, which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5 IRO Pin Description
The IRO pin is the output of the CMT. See Carrier Modulator Timer (CMT) Module for a detailed
description of this pin function.
2.3.6 General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and serial I/O systems. (Not all pins are available in all packages. See Table 2-2.) Immediately after reset,
all 37 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices
disabled.
NOTE:
To avoid extra current drain from floating input pins, the reset initialization routine
in the application program should either enable on-chip pullup devices or change
the direction of unused pins to outputs so the pins do not float.
For information about controlling these pins as general-purpose I/O pins, see the Parallel Input/Output
section. For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
24
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Table 2-1 Pin Sharing References
Port Pins
PTA7–PTA0
PTB7
PTB6–PTB2
Alternate
Function
KBI1P7–KBI1P0
TPM1CH1
—
PTB1
PTB0
RxD1
TxD1
PTC7
PTC6
PTC5
PTC4
SS1
SPSCK1
MISO1
MOSI1
PTC3–PTC0
KBI2P3–KBI2P0
Reference(1)
Keyboard Interrupt (KBI) Module
Timer/PWM Module (TPM) Module
Parallel Input/Output
Serial Communications Interface (SCI) Module
Serial Peripheral Interface (SPI) Module
Keyboard Interrupt (KBI) Module
PTD6
TPM1CH0
Timer/PWM Module (TPM) Module
PTD5
PTD4
ACMP1+
ACMP1–
Analog Comparator (ACMP) Module
PTD2
IRQ
PTD1
RESET
PTD0
BKGD/MS
PTE7–PTE0
—
Resets, Interrupts, and System Configuration
Parallel Input/Output
NOTES:
1. See this section for information about modules that share these pins.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See the Parallel Input/Output section for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when PTD2 is
configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a
pulldown device rather than a pullup device.
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Pins and Connections
2.3.7 Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
Table 2-2 Signal Properties
Pin
Name
Dir(1)
VDD
VSS
High
Current Pin
Pullup(2)
—
—
Comments
—
—
XTAL
O
—
—
Crystal oscillator output
EXTAL
I
—
—
Crystal oscillator input
IRO
O
Y
—
Infrared output
PTA0/KBI1P0
I
N
SWC
PTA1/KBI1P1
I/O
N
SWC
PTA2/KBI1P2
I/O
N
SWC
PTA3/KBI1P3
I/O
N
SWC
PTA4/KBI1P4
I/O
N
SWC
PTA5/KBI1P5
I/O
N
SWC
PTA6/KBI1P6
I/O
N
SWC
PTA7/KBI1P7
I/O
N
SWC
PTA0 does not have a clamp diode to VDD. PTA0 should not be
driven above VDD.
PTB0/TxD1
I/O
Y
SWC
PTB1/RxD1
I/O
Y
SWC
PTB2
I/O
Y
SWC
PTB3
I/O
Y
SWC
Available only in 44-LQFP package
PTB4
I/O
Y
SWC
Available only in 44-LQFP package
PTB5
I/O
Y
SWC
Available only in 44-LQFP package
Available only in 32- or 44-LQFP packages
PTB6
I/O
Y
SWC
PTB7/TPM1CH1
I/O
Y
SWC
PTC0/KBI2P0
I/O
N
SWC
PTC1/KBI2P1
I/O
N
SWC
PTC2/KBI2P2
I/O
N
SWC
PTC3/KBI2P3
I/O
N
SWC
PTC4/MOSI1
I/O
N
SWC
PTC5/MISO1
I/O
N
SWC
PTC6/SPSCK1
I/O
N
SWC
PTC7/SS1
I/O
N
SWC
PTD0/BKGD/MS
I/O
N
SWC(3)
Output-only when configured as PTD0 pin. Pullup enabled and
slew rate disabled when BDM function enabled.
PTD1/RESET
I/O
N
SWC(3)
Output-only when configured as PTD1 pin.
PTD2/IRQ
I/O
N
SWC(4)
Available only in 32- or 44-LQFP packages
PTD3
I/O
N
SWC
Available only in 44-LQFP package
PTD4/ACMP1–
I/O
N
SWC
Available only in 32- or 44-LQFP packages
PTD5/ACMP1+
I/O
N
SWC
Available only in 32- or 44-LQFP packages
26
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SoC Guide — MC9S08RG60/D V1.08
Table 2-2 Signal Properties (Continued)
Pin
Name
Dir(1)
High
Current Pin
Pullup(2)
PTD6/TPM1CH0
I/O
N
SWC
PTE0
I/O
N
SWC
Available only in 44-LQFP package
PTE1
I/O
N
SWC
Available only in 44-LQFP package
PTE2
I/O
N
SWC
Available only in 44-LQFP package
PTE3
I/O
N
SWC
Available only in 44-LQFP package
PTE4
I/O
N
SWC
Available only in 44-LQFP package
PTE5
I/O
N
SWC
Available only in 44-LQFP package
PTE6
I/O
N
SWC
Available only in 44-LQFP package
PTE7
I/O
N
SWC
Available only in 44-LQFP package
Comments
NOTES:
1. Unless otherwise indicated, all digital inputs have input hysteresis.
2. SWC is software-controlled pullup resistor, the register is associated with the respective port.
3. When these pins are configured as RESET or BKGD/MS pullup device is enabled.
4. When configured for the IRQ function, this pin will have a pullup device enabled when the IRQ is set for falling edge
detection and a pulldown device enabled when the IRQ is set for rising edge detection.
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28
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Section 3 Modes of Operation
3.1 Introduction
The operating modes of the MC9S08RC/RD/RE/RG are described in this section. Entry into each mode,
exit from each mode, and functionality while in each of the modes are described.
3.2 Features
•
Active background mode for code development
•
Wait mode:
•
–
CPU shuts down to conserve power
–
System clocks running
–
Full voltage regulation maintained
Stop modes:
–
System clocks stopped; voltage regulator in standby
–
Stop1 — Full power down of internal circuits for maximum power savings
–
Stop2 — Partial power down of internal circuits, RAM remains operational
–
Stop3 — All internal circuits powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9S08RC/RD/RE/RG. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at $FFFE:$FFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
•
When the BKGD/MS pin is low at the rising edge of reset
•
When a BACKGROUND command is received through the BKGD pin
•
When a BGND instruction is executed
•
When encountering a BDC breakpoint
•
When encountering a DBG breakpoint
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Modes of Operation
After active background mode is entered, the CPU is held in a suspended state waiting for serial
background commands rather than executing instructions from the user’s application program.
Background commands are of two types:
•
•
Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
–
Memory access commands
–
Memory-access-with-status commands
–
BDC register access commands
–
BACKGROUND command
Active background commands, which can only be executed while the MCU is in active background
mode, include commands to:
–
Read or write CPU registers
–
Trace one user program instruction at a time
–
Leave active background mode to return to the user’s application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the
MC9S08RC/RD/RE/RG is shipped from the Motorola factory, the FLASH program memory is usually
erased so there is no program that could be executed in run mode until the FLASH memory is initially
programmed. The active background mode can also be used to erase and reprogram the FLASH memory
after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support section.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
Only the BACKGROUND command and memory-access-with-status commands are available when the
MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they
report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command
can be used to wake the MCU from wait mode and enter active background mode.
30
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
3.6 Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the
system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1 Stop Mode Behavior
CPU, Digital
PPDC Peripherals,
FLASH
Mode
PDC
RAM
OSC
ACMP
Regulator
I/O Pins
RTI
Stop1
1
0
Off
Off
Off
Standby
Standby
Reset
Off
Stop2
1
1
Off
Standby
Off
Standby
Standby
States
held
Optionally on
Stop3
0
Don’t
care
Standby
Standby
Off
Standby
Standby
States
held
Optionally on
3.6.1 Stop1 Mode
Stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of
the MCU to be powered down. To enter stop1, the user must execute a STOP instruction with the PDC bit
in SPMSC2 set and the PPDC bit clear. Stop1 can be entered only if the LVD reset is disabled
(LVDRE = 0).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are
turned off. The voltage regulator is in a low-power standby state, as are the OSC and ACMP.
Exit from stop1 is done by asserting any of the wakeup pins on the MCU: RESET, IRQ, or KBI, which
have been enabled. IRQ and KBI pins are always active-low when used as wakeup pins in stop1 regardless
of how they were configured before entering stop1.
Upon wakeup from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will
take the reset vector.
3.6.2 Stop2 Mode
Stop2 mode provides very low standby power consumption and maintains the contents of RAM and the
current state of all of the I/O pins. To select entry into stop2 upon execution of a STOP instruction, the
user must execute a STOP instruction with the PPDC and PDC bits in SPMSC2 set. Stop2 can be entered
only if LVDRE = 0.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers that they want to restore after exit of stop2, to locations in RAM. Upon exit
from stop2, these values can be restored by user software.
MOTOROLA
MC9S08RC/RD/RE/RG
31
Modes of Operation
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are
turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ACMP.
Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and
after exiting stop2 mode until a 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting any of the wakeup pins: RESET, IRQ, or KBI that have been enabled,
or through the real-time interrupt. IRQ and KBI pins are always active-low when used as wakeup pins in
stop2 regardless of how they were configured before entering stop2.
Upon wakeup from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
For pins that were configured as general-purpose I/O, the user must copy the contents of the I/O port
registers, which have been saved in RAM, back to the port registers before writing to the PPDACK bit. If
the port registers are not restored from RAM before writing to PPDACK, then the register bits will be in
their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 Stop3 Mode
Upon entering stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
OSC is turned off, the ACMP is disabled, and the voltage regulator is put in standby. The states of all of
the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not
latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving
the pins being maintained.
Exit from stop3 is done by asserting RESET, any asynchronous interrupt pin that has been enabled, or
through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but
in that case the real-time interrupt cannot wake the MCU from stop.
32
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
3.6.4 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Development Support section of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active
when the MCU enters stop mode so background debug communication is still possible. In addition, the
voltage regulator does not enter its low-power standby state but maintains full internal regulation. The
MCU cannot enter either stop1 mode or stop2 mode if ENBDM is set.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the active
background mode is enabled.
Table 3-2 BDM Enabled Stop Mode Behavior
Mode
PDC
CPU, Digital
PPDC Peripherals,
FLASH
Stop3
Don’t
care
Don’t
care
Standby
RAM
OSC
ACMP
Regulator
I/O Pins
RTI
Standby
On
Standby
On
States
held
Optionally on
3.6.5 LVD Reset Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops
below the LVD voltage. If the LVD reset is enabled in stop by setting the LVDRE bit in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD reset enabled (LVDRE = 1) the MCU will instead
enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-3 LVD Enabled Stop Mode Behavior
Mode
PDC
CPU, Digital
PPDC Peripherals,
FLASH
Stop3
Don’t
care
Don’t
care
Standby
RAM
OSC
ACMP
Regulator
I/O Pins
RTI
Standby
On
Standby
On
States
held
Optionally on
3.6.6 On-Chip Peripheral Modules in Stop Mode
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to
the peripheral systems are halted to reduce power consumption.
MOTOROLA
MC9S08RC/RD/RE/RG
33
Modes of Operation
I/O Pins
•
All I/O pin states remain unchanged when the MCU enters stop3 mode.
•
If the MCU is configured to go into stop2 mode, all I/O pin states are latched before entering stop.
Pin states remain latched until the PPDACK bit is written.
•
If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state
upon entry into stop.
Memory
•
All RAM and register contents are preserved while the MCU is in stop3 mode.
•
All registers will be reset upon wakeup from stop2, but the contents of RAM are preserved. The
user may save any memory-mapped register data into RAM before entering stop2 and restore the
data upon exit from stop2.
•
All registers will be reset upon wakeup from stop1 and the contents of RAM are not preserved. The
MCU must be initialized as upon reset. The contents of the FLASH memory are non-volatile and
are preserved in any of the stop modes.
OSC — In any of the stop modes, the OSC stops running.
TPM — When the MCU enters stop mode, the clock to the TPM module stops. The modules halt
operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM module will be reset upon
wakeup from stop and must be reinitialized.
ACMP — When the MCU enters any stop mode, the ACMP will enter a low-power standby state. No
compare operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the
ACMP will be reset upon wakeup from stop and must be reinitialized.
KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources. During stop1
or stop2, enabled KBI pins function as wakeup inputs. When functioning as a wakeup, a KBI pin is always
active low regardless of how it was configured before entering stop1 or stop2.
SCI — When the MCU enters stop mode, the clock to the SCI module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SCI module will be reset upon wakeup from
stop and must be reinitialized.
SPI — When the MCU enters stop mode, the clock to the SPI module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wakeup from
stop and must be reinitialized.
CMT — When the MCU enters stop mode, the clock to the CMT module stops. The module halts
operation. If the MCU is configured to go into stop2 or stop1 mode, the CMT module will be reset upon
wakeup from stop and must be reinitialized.
Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any
of the stop modes unless the LVD reset function is enabled or BDM is enabled.
34
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Section 4 Memory
4.1 MC9S08RC/RD/RE/RG Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08RC/RD/RE/RG series of MCUs consists of
RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The
registers are divided into three groups:
•
Direct-page registers ($0000 through $0045 for 32K and 60K parts, and $0000 through $003F for
16K and 8K parts)
•
High-page registers ($1800 through $182B)
•
Nonvolatile registers ($FFB0 through $FFBF)
$0000
DIRECT PAGE REGISTERS
$0045
$0046
RAM
2048 BYTES
$0845
$0846
$17FF
$1800
$182B
$182C
DIRECT PAGE REGISTERS
RAM
2048 BYTES
FLASH
4026 BYTES
UNIMPLEMENTED
4026 BYTES
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
$0000
$0045
$0046
DIRECT PAGE REGISTERS
RAM 1024 BYTES(1)
$0845
$0846
$0000
$003F
$0040
$043F
$0440
UNIMPLEMENTED
5056 BYTES
$17FF
$1800
$182B
$182C
HIGH PAGE REGISTERS
DIRECT PAGE REGISTERS
RAM 1024 BYTES(1)
$0000
$003F
$0040
$043F
$0440
UNIMPLEMENTED
5056 BYTES
$17FF
$1800
$182B
$182C
HIGH PAGE REGISTERS
$17FF
$1800
$182B
$182C
UNIMPLEMENTED
26580 BYTES
$8000
UNIMPLEMENTED
42964 BYTES
FLASH
59348 BYTES
UNIMPLEMENTED
51156 BYTES
FLASH
32768 BYTES
$BFFF
$C000
FLASH
16384 BYTES
$DFFF
$E000
FLASH
8192 BYTES
$FFFF
$FFFF
MC9S08RC/RD/RE/RG60
MC9S08RC/RD/RE/RG32
MC9S08RC/RD/RE16
$FFFF
MC9S08RC/RD/RE8
NOTE:
1. MC3S08RC/RD/RE16/8 ROM MCU devices have 512 bytes of RAM instead of 1K bytes.
Figure 4-1 MC9S08RC/RD/RE/RG Memory Map
MOTOROLA
MC9S08RC/RD/RE/RG
35
Memory
4.1.1 Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Motorola-provided equate file for the MC9S08RC/RD/RE/RG. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to the Resets, Interrupts,
and System Configuration section.
Table 4-1 Reset and Interrupt Vectors
Vector
Number
16
through
31
Address
(High/Low)
Vector
Vector Name
$FFC0:FFC1
Unused Vector Space
(available for user program)
$FFDE:FFDF
15
$FFE0:FFE1
SPI(1)
Vspi1
14
$FFE2:FFE3
RTI
Vrti
13
$FFE4:FFE5
KBI2
Vkeyboard2
12
$FFE6:FFE7
KBI1
Vkeyboard1
11
$FFE8:FFE9
ACMP(2)
Vacmp1
10
$FFEA:FFEB
CMT
Vcmt
Transmit(3)
Vsci1tx
9
$FFEC:FFED
SCI
8
$FFEE:FFEF
SCI Receive(3)
Vsci1rx
7
$FFF0:FFF1
SCI Error(3)
Vsci1err
6
$FFF2:FFF3
TPM Overflow
Vtpm1ovf
5
$FFF4:FFF5
TPM Channel 1
Vtpm1ch1
4
$FFF6:FFF7
TPM Channel 0
Vtpm1ch0
3
$FFF8:FFF9
IRQ
Virq
2
$FFFA:FFFB
Low Voltage Detect
Vlvd
1
$FFFC:FFFD
SWI
Vswi
0
$FFFE:FFFF
Reset
Vreset
NOTES:
1. The SPI module is not included on the MC9S08RC/RD/RE devices. This vector location is unused for those
devices.
2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This vector location is unused
for those devices.
3. The SCI module is not included on the MC9S08RC devices. This vector location is unused for those devices.
36
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
4.2 Register Addresses and Bit Assignments
The registers in the MC9S08RC/RD/RE/RG are divided into these three groups:
•
Direct-page registers are located within the first 256 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
•
High-page registers are used much less often, so they are located above $1800 in the memory map.
This leaves more room in the direct page for more frequently used registers and variables.
•
The nonvolatile register area consists of a block of 16 locations in FLASH memory at
$FFB0–$FFBF.
Nonvolatile register locations include:
–
Three values that are loaded into working registers at reset
–
An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MOTOROLA
MC9S08RC/RD/RE/RG
37
Memory
Table 4-2 Direct-Page Register Summary
Address
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
38
Register Name
PTAD
PTAPE
Reserved
PTADD
PTBD
PTBPE
Reserved
PTBDD
PTCD
PTCPE
Reserved
PTCDD
PTDD
PTDPE
Reserved
PTDDD
PTED
PTEPE
Reserved
PTEDD
KBI1SC
KBI1PE
KBI2SC
KBI2PE
SCI1BDH(1)
SCI1BDL(1)
SCI1C1(1)
SCI1C2(1)
SCI1S1(1)
SCI1S2(1)
SCI1C3(1)
SCI1D(1)
CMTCGH1
CMTCGL1
CMTCGH2
CMTCGL2
CMTOC
CMTMSC
CMTCMD1
CMTCMD2
Bit 7
PTAD7
PTAPE7
—
PTADD7
PTBD7
PTBPE7
—
PTBDD7
PTCD7
PTCPE7
—
PTCDD7
0
0
—
0
PTED7
PTEPE7
—
PTEDD7
KBEDG7
KBIPE7
0
0
0
SBR7
LOOPS
TIE
TDRE
0
R8
R7/T7
PH7
PL7
SH7
SL7
IROL
EOCF
MB15
MB7
6
PTAD6
PTAPE6
—
PTADD6
PTBD6
PTBPE6
—
PTBDD6
PTCD6
PTCPE6
—
PTCDD6
PTDD6
PTDPE6
—
PTDDD6
PTED6
PTEPE6
—
PTEDD6
KBEDG6
KBIPE6
0
0
0
SBR6
SCISWAI
TCIE
TC
0
T8
R6/T6
PH6
PL6
SH6
SL6
CMTPOL
CMTDIV1
MB14
MB6
5
PTAD5
PTAPE5
—
PTADD5
PTBD5
PTBPE5
—
PTBDD5
PTCD5
PTCPE5
—
PTCDD5
PTDD5
PTDPE5
—
PTDDD5
PTED5
PTEPE5
—
PTEDD5
KBEDG5
KBIPE5
0
0
0
SBR5
RSRC
RIE
RDRF
0
TXDIR
R5/T5
PH5
PL5
SH5
SL5
IROPEN
CMTDIV0
MB13
MB5
4
PTAD4
PTAPE4
—
PTADD4
PTBD4
PTBPE4
—
PTBDD4
PTCD4
PTCPE4
—
PTCDD4
PTDD4
PTDPE4
—
PTDDD4
PTED4
PTEPE4
—
PTEDD4
KBEDG4
KBIPE4
0
0
SBR12
SBR4
M
ILIE
IDLE
0
0
R4/T4
PH4
PL4
SH4
SL4
0
EXSPC
MB12
MB4
MC9S08RC/RD/RE/RG
3
PTAD3
PTAPE3
—
PTADD3
PTBD3
PTBPE3
—
PTBDD3
PTCD3
PTCPE3
—
PTCDD3
PTDD3
PTDPE3
—
PTDDD3
PTED3
PTEPE3
—
PTEDD3
KBF
KBIPE3
KBF
KBIPE3
SBR11
SBR3
WAKE
TE
OR
0
ORIE
R3/T3
PH3
PL3
SH3
SL3
0
BASE
MB11
MB3
2
PTAD2
PTAPE2
—
PTADD2
PTBD2
PTBPE2
—
PTBDD2
PTCD2
PTCPE2
—
PTCDD2
PTDD2
PTDPE2
—
PTDDD2
PTED2
PTEPE2
—
PTEDD2
KBACK
KBIPE2
KBACK
KBIPE2
SBR10
SBR2
ILT
RE
NF
0
NEIE
R2/T2
PH2
PL2
SH2
SL2
0
FSK
MB10
MB2
1
PTAD1
PTAPE1
—
PTADD1
PTBD1
PTBPE1
—
PTBDD1
PTCD1
PTCPE1
—
PTCDD1
PTDD1
PTDPE1
—
PTDDD1
PTED1
PTEPE1
—
PTEDD1
KBIE
KBIPE1
KBIE
KBIPE1
SBR9
SBR1
PE
RWU
FE
0
FEIE
R1/T1
PH1
PL1
SH1
SL1
0
EOCIE
MB9
MB1
Bit 0
PTAD0
PTAPE0
—
PTADD0
PTBD0
PTBPE0
—
PTBDD0
PTCD0
PTCPE0
—
PTCDD0
PTDD0
PTDPE0
—
PTDDD0
PTED0
PTEPE0
—
PTEDD0
KBIMOD
KBIPE0
KBIMOD
KBIPE0
SBR8
SBR0
PT
SBK
PF
RAF
PEIE
R0/T0
PH0
PL0
SH0
SL0
0
MCGEN
MB8
MB0
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Table 4-2 Direct-Page Register Summary (Continued)
Address
$0028
$0029
$002A
$002B
$002C–
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B–
$003F
$0040
$0041
$0042
$0043
$0044
$0045
Register Name
CMTCMD3
CMTCMD4
IRQSC
ACMP1SC(2)
Reserved
TPM1SC
TPM1CNTH
TPM1CNTL
TPM1MODH
TPM1MODL
TPM1C0SC
TPM1C0VH
TPM1C0VL
TPM1C1SC
TPM1C1VH
TPM1C1VL
Reserved
SPI1C1(3)
SPI1C2(3)
SPI1BR(3)
SPI1S(3)
Reserved
SPI1D(3)
Bit 7
SB15
SB7
0
ACME
—
—
TOF
Bit 15
Bit 7
Bit 15
Bit 7
CH0F
Bit 15
Bit 7
CH1F
Bit 15
Bit 7
—
—
SPIE
0
0
SPRF
—
Bit 7
6
SB14
SB6
0
ACBGS
—
—
TOIE
14
6
14
6
CH0IE
14
6
CH1IE
14
6
—
—
SPE
0
SPPR2
0
—
6
5
SB13
SB5
IRQEDG
ACF
—
—
CPWMS
13
5
13
5
MS0B
13
5
MS1B
13
5
—
—
SPTIE
0
SPPR1
SPTEF
—
5
4
SB12
SB4
IRQPE
ACIE
—
—
CLKSB
12
4
12
4
MS0A
12
4
MS1A
12
4
—
—
MSTR
MODFEN
SPPR0
MODF
—
4
3
SB11
SB3
IRQF
ACO
—
—
CLKSA
11
3
11
3
ELS0B
11
3
ELS1B
11
3
—
—
CPOL
BIDIROE
0
0
—
3
2
SB10
SB2
IRQACK
—
—
—
PS2
10
2
10
2
ELS0A
10
2
ELS1A
10
2
—
—
CPHA
0
SPR2
0
—
2
1
SB9
SB1
IRQIE
ACMOD1
—
—
PS1
9
1
9
1
0
9
1
0
9
1
—
—
SSOE
SPISWAI
SPR1
0
—
1
Bit 0
SB8
SB0
IRQMOD
ACMOD0
—
—
PS0
Bit 8
Bit 0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
—
—
LSBFE
SPC0
SPR0
0
—
Bit 0
NOTES:
1. The SCI module is not included on the MC9S08RC devices. This is a reserved location for those devices.
2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This is a reserved location for those
devices.
3. The SPI module is not included on the MC9S08RC/RD/RE devices. These are reserved locations on the 32K and 60K
versions of these devices. The address range $0040–$004F are RAM locations on the 16K and 8K devices. There are
no MC9S08RG8/16 devices.
MOTOROLA
MC9S08RC/RD/RE/RG
39
Memory
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at $1800.
Table 4-3 High-Page Register Summary
Address
$1800
$1801
$1802
$1803–
$1804
$1805
$1806
$1807
$1808
$1809
$180A
$180B–
$180F
$1810
$1811
$1812
$1813
$1814
$1815
$1816
$1817
$1818
$1819–
$181F
$1820
$1821
$1822
$1823
$1824
$1825
$1826
$1827–
$182B
Register Name
SRS
SBDFR
SOPT
Reserved
Reserved
SDIDH
SDIDL
SRTISC
SPMSC1
SPMSC2
Reserved
DBGCAH
DBGCAL
DBGCBH
DBGCBL
DBGFH
DBGFL
DBGC
DBGT
DBGS
Reserved
FCDIV
FOPT
Reserved
FCNFG
FPROT
FSTAT
FCMD
Reserved
Bit 7
POR
0
COPE
—
—
0
REV3
ID7
RTIF
LVDF
LVWF
—
—
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
DBGEN
TRGSEL
AF
—
—
DIVLD
KEYEN
—
0
FPOPEN
FCBEF
FCMD7
—
—
6
PIN
0
COPT
—
—
0
REV2
ID6
RTIACK
LVDACK
LVWACK
—
—
14
6
14
6
14
6
ARM
BEGIN
BF
—
—
PRDIV8
FNORED
—
0
FPDIS
FCCF
FCMD6
—
—
5
COP
0
STOPE
—
—
0
REV1
ID5
RTICLKS
LVDIE
0
—
—
13
5
13
5
13
5
TAG
0
ARMF
—
—
DIV5
0
—
KEYACC
FPS2
FPVIOL
FCMD5
—
—
4
ILOP
0
—
—
—
0
REV0
ID4
RTIE
SAFE
0
—
—
12
4
12
4
12
4
BRKEN
0
0
—
—
DIV4
0
—
0
FPS1
FACCERR
FCMD4
—
—
3
ILAD(1)
0
0
—
—
0
ID11
ID3
0
LVDRE
PPDF
—
—
11
3
11
3
11
3
RWA
TRG3
CNT3
—
—
DIV3
0
—
0
FPS0
0
FCMD3
—
—
2
0
0
0
—
—
0
ID10
ID2
RTIS2
—
PPDACK
—
—
10
2
10
2
10
2
RWAEN
TRG2
CNT2
—
—
DIV2
0
—
0
0
FBLANK
FCMD2
—
—
1
LVD
0
BKGDPE
—
—
0
ID9
ID1
RTIS1
—
PDC
—
—
9
1
9
1
9
1
RWB
TRG1
CNT1
—
—
DIV1
SEC01
—
0
0
0
FCMD1
—
—
Bit 0
0
BDFR
RSTPE
—
—
0
ID8
ID0
RTIS0
—
PPDC
—
—
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
RWBEN
TRG0
CNT0
—
—
DIV0
SEC00
—
0
0
0
FCMD0
—
—
NOTES:
1. The ILAD bit is only present on 16K and 8K versions of the devices.
40
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
Table 4-4 Nonvolatile Register Summary
Address
Register Name
$FFB0–
NVBACKKEY
$FFB7
$FFB8–
Reserved
$FFBC
$FFBD
NVPROT
$FFBE
Reserved
$FFBF
NVOPT
Bit 7
6
5
4
3
2
1
Bit 0
—
—
0
—
0
—
—
0
—
SEC01
—
—
0
—
SEC00
8-Byte Comparison Key
—
—
FPOPEN
—
KEYEN
—
—
FPDIS
—
FNORED
—
—
FPS2
—
0
—
—
FPS1
—
0
—
—
FPS0
—
0
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in
secure memory. (A security key cannot be entered directly through background debug commands.) This
security key can be disabled completely by programming the KEYEN bit to 0. If the security key is
disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through
the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode
after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3 RAM
The MC9S08RC/RD/RE/RG includes static RAM. The locations in RAM below $0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the
bit-manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently
accessed program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to $00FF. In the
MC9S08RC/RD/RE/RG, it is usually best to reinitialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast
is equated to the highest address of the RAM in the Motorola-provided equate file).
LDHX
TXS
MOTOROLA
#RamLast+1
;point one past RAM
;SP B)
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
14.3 Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit
programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike
debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources.
It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
BDC commands are divided into two groups:
•
Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.
•
Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET,
and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the
on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However, if the pod is
powered separately, it can be connected to a running target system without forcing a target system reset or
otherwise disturbing the running application program.
BKGD 1
2 GND
NO CONNECT 3
4 RESET
NO CONNECT 5
6 VDD
Figure 14-1 BDM Tool Connector
14.3.1 BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers. This protocol assumes the host knows the communication clock rate that is determined
MOTOROLA
MC9S08RC/RD/RE/RG
185
Development Support
by the target BDC clock rate. All communication is initiated and controlled by the host that drives a
high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant
bit first (MSB first). For a detailed description of the communications protocol, refer to 14.3.2
Communication Details.
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to 14.3.2 Communication Details for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a development system is connected, it can pull both BKGD and
RESET low, release RESET to select active background mode rather than normal operating mode, then
release BKGD. It is not necessary to reset the target MCU to communicate with it through the background
debug interface.
14.3.2 Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
186
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Figure 14-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD
pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the
BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain
signal during this period.
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
EARLIEST START
OF NEXT BIT
TARGET SENSES BIT LEVEL
PERCEIVED START
OF BIT TIME
Figure 14-2 BDC Host-to-Target Serial Bit Timing
MOTOROLA
MC9S08RC/RD/RE/RG
187
Development Support
Figure 14-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of
the bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
HIGH-IMPEDANCE
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 14-3 BDC Target-to-Host Serial Bit Timing (Logic 1)
188
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MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Figure 14-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin
low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the
bit level about 10 cycles after starting the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
HIGH-IMPEDANCE
SPEEDUP
PULSE
TARGET MCU
DRIVE AND
SPEED-UP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 14-4 BDM Target-to-Host Serial Bit Timing (Logic 0)
MOTOROLA
MC9S08RC/RD/RE/RG
189
Development Support
14.3.3 BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 14-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 14-1 to describe the coding structure of the BDC commands.
190
/
d
AAAA
RD
WD
RD16
WD16
SS
CC
RBKP
=
=
=
=
=
=
=
=
=
=
WBKP
=
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
separates parts of the command
delay 16 target BDC clock cycles
a 16-bit address in the host-to-target direction
8 bits of read data in the target-to-host direction
8 bits of write data in the host-to-target direction
16 bits of read data in the target-to-host direction
16 bits of write data in the host-to-target direction
the contents of BDCSCR in the target-to-host direction (STATUS)
8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
Table 14-1 BDC Command Summary
Command
Mnemonic
Active BDM/
Non-intrusive
Coding
Structure
Description
SYNC
Non-intrusive
n/a(1)
Request a timed reference pulse to determine
target BDC communication speed
ACK_ENABLE
Non-intrusive
D5/d
Enable acknowledge protocol. Refer to
Motorola document order no. HCS08RMv1/D.
ACK_DISABLE
Non-intrusive
D6/d
Disable acknowledge protocol. Refer to
Motorola document order no. HCS08RMv1/D.
BACKGROUND
Non-intrusive
90/d
Enter active background mode if enabled
(ignore if ENBDM bit equals 0)
READ_STATUS
Non-intrusive
E4/SS
Read BDC status from BDCSCR
WRITE_CONTROL
Non-intrusive
C4/CC
Write BDC controls in BDCSCR
READ_BYTE
Non-intrusive
E0/AAAA/d/RD
Read a byte from target memory
READ_BYTE_WS
Non-intrusive
E1/AAAA/d/SS/RD
Read a byte and report status
READ_LAST
Non-intrusive
E8/SS/RD
Re-read byte from address just read and
report status
WRITE_BYTE
Non-intrusive
C0/AAAA/WD/d
Write a byte to target memory
WRITE_BYTE_WS
Non-intrusive
C1/AAAA/WD/d/SS
Write a byte and report status
READ_BKPT
Non-intrusive
E2/RBKP
Read BDCBKPT breakpoint register
WRITE_BKPT
Non-intrusive
C2/WBKP
Write BDCBKPT breakpoint register
GO
Active BDM
08/d
Go to execute the user application program
starting at the address currently in the PC
TRACE1
Active BDM
10/d
Trace 1 user instruction at the address in the
PC, then return to active background mode
TAGGO
Active BDM
18/d
Same as GO but enable external tagging
(HCS08 devices have no external tagging pin)
READ_A
Active BDM
68/d/RD
Read accumulator (A)
READ_CCR
Active BDM
69/d/RD
Read condition code register (CCR)
READ_PC
Active BDM
6B/d/RD16
Read program counter (PC)
READ_HX
Active BDM
6C/d/RD16
Read H and X register pair (H:X)
READ_SP
Active BDM
6F/d/RD16
Read stack pointer (SP)
READ_NEXT
Active BDM
70/d/RD
Increment H:X by one then read memory byte
located at H:X
READ_NEXT_WS
Active BDM
710/d/SS/RD
Increment H:X by one then read memory byte
located at H:X. Report status and data.
WRITE_A
Active BDM
48/WD/d
Write accumulator (A)
WRITE_CCR
Active BDM
49/WD/d
Write condition code register (CCR)
WRITE_PC
Active BDM
4B/WD16/d
Write program counter (PC)
WRITE_HX
Active BDM
4C/WD16/d
Write H and X register pair (H:X)
WRITE_SP
Active BDM
4F/WD16/d
Write stack pointer (SP)
WRITE_NEXT
Active BDM
50/WD/d
Increment H:X by one, then write memory byte
located at H:X
WRITE_NEXT_WS
Active BDM
51/WD/d/SS
Increment H:X by one, then write memory byte
located at H:X. Also report status.
NOTES:
1. The SYNC command is a special operation that does not have a command code.
MOTOROLA
MC9S08RC/RD/RE/RG
191
Development Support
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct communications speed to use for BDC communications until after it has analyzed the response to
the SYNC command.
To issue a SYNC command, the host:
•
Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest
clock is normally the reference oscillator/64 or the self-clocked rate/64.)
•
Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically
one cycle of the fastest clock in the system.)
•
Removes all drive to the BKGD pin so it reverts to high impedance
•
Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would
ever occur during normal BDC communications):
•
Waits for BKGD to return to a logic high
•
Delays 16 cycles to allow the host to stop driving the high speedup pulse
•
Drives BKGD low for 128 BDC clock cycles
•
Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
•
Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
14.3.4 BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a
16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged
breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction
boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction
opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can
be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to
enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the
breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC
breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select
forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are
more flexible than the simple breakpoint in the BDC module.
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SoC Guide — MC9S08RG60/D V1.08
14.4 On-Chip Debug System (DBG)
Because HCS08 devices do not have external address and data buses, the most important functions of an
in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage
FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture
bus information and what information to capture. The system relies on the single-wire background debug
system to access debug control registers and to read results out of the eight stage FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map.
These registers are located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any
of the control and status registers for the debug module. The one exception is that the debug system can
provide the means to implement a form of ROM patching. This topic is discussed in greater detail in 14.4.6
Hardware Breakpoints.
14.4.1 Comparators A and B
Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking
circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry
optionally allows you to specify that a trigger will occur only if the opcode at the specified address is
actually executed as opposed to only being read from memory into the instruction queue. The comparators
are also capable of magnitude comparisons to support the inside range and outside range trigger modes.
Comparators are disabled temporarily during all BDC accesses.
The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the
CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data
bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an
additional purpose, in full address plus data comparisons they are used to decide which of these buses to
use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s
write data bus is used. Otherwise, the CPU’s read data bus is used.
The currently selected trigger mode determines what the debugger logic does when a comparator detects
a qualified match condition. A match can cause:
•
Generation of a breakpoint to the CPU
•
Storage of data bus values into the FIFO
•
Starting to store change-of-flow addresses into the FIFO (begin type trace)
•
Stopping the storage of change-of-flow addresses into the FIFO (end type trace)
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14.4.2 Bus Capture Information and FIFO Operation
The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the
debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would
read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of
words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by
writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and
the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry
in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In
these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading
DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information
is available at the FIFO data port. In the event-only trigger modes (see 14.4.5 Trigger Modes), 8-bit data
information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used
and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted
so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU
addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a
change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger
event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is
a change-of-flow, it will be saved as the last change-of-flow entry for that debug run.
The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is
not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be
saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by
reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded
because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic
reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a profile of executed instruction addresses.
14.4.3 Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that
cause a change to the normal sequential execution of instructions is stored. With knowledge of the source
and object code program stored in the target system, an external debugger system can reconstruct the path
of execution through many instructions from the change-of-flow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source
address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are
not conditional, these events do not cause change-of-flow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the
destination address, so the debug system stores the run-time destination address for any indirect JMP or
JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow
information.
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14.4.4 Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue,
but not taking any other action until and unless that instruction is actually executed by the CPU. This
distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt
causes some instructions that have been fetched into the instruction queue to be thrown away without being
executed.
A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint
request. The usual action in response to a breakpoint is to go to active background mode rather than
continuing to the next instruction in the user application program.
The tag vs. force terminology is used in two contexts within the debug module. The first context refers to
breakpoint requests from the debug module to the CPU. The second refers to match signals from the
comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is
entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the
CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active
background mode rather than executing the tagged instruction. When the TRGSEL control bit in the
DBGT register is set to select tag-type operation, the output from comparator A or B is qualified by a block
of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode
at the compare address is actually executed. There is separate opcode tracking logic for each comparator
so more than one compare event can be tracked through the instruction queue at a time.
14.4.5 Trigger Modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register
selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator
must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in
DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace),
or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and
clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets
full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually
by writing a 0 to the ARM bit or DBGEN bit in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only
trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type
traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons
because opcode tags would only apply to opcode fetches that are always read cycles. It would also be
unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally
known at a particular address.
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The following trigger mode descriptions only state the primary comparator conditions that lead to a
trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and
the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with
optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines
whether the CPU request will be a tag request or a force request.
A-Only — Trigger when the address matches the value in comparator A
A OR B — Trigger when the address matches either the value in comparator A or the value in
comparator B
A Then B — Trigger when the address matches the value in comparator B but only after the address for
another cycle matched the value in comparator A. There can be any number of cycles after the A match
and before the B match.
A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally)
must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte
of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of
comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low
half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within
the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
Event-Only B (Store Data) — Trigger events occur each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the
FIFO becomes full.
A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger
event occurs each time the address matches the value in comparator B. Trigger events cause the data to be
captured into the FIFO. The debug run ends when the FIFO becomes full.
Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value
in comparator A and less than or equal to the value in comparator B at the same time.
Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than
the value in comparator A or greater than the value in comparator B.
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14.4.6 Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in 14.4.5 Trigger Modes to be used to generate a hardware breakpoint request to the CPU. The
TAG bit in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.
14.5 Registers and Control Bits
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the Memory section of this data sheet for the absolute address
assignments for all DBG registers. This section refers to registers and control bits only by their names. A
Motorola-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.5.1 BDC Registers and Control Bits
The BDC has two registers:
•
The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
•
The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
14.5.1.1 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
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Bit 7
Read:
6
5
4
3
BKPTEN
FTS
CLKSW
BDMACT
ENBDM
2
1
Bit 0
WS
WSF
DVF
Write:
Normal Reset:
0
0
0
0
0
0
0
0
Reset in Active BDM:
1
1
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 14-5 BDC Status and Control Register (BDCSCR)
ENBDM — Enable BDM (Permit Active Background Mode)
Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or
whenever the debug host resets the target and remains 1 until a normal reset clears it.
1 = BDM can be made active to allow active background mode commands.
0 = BDM cannot be made active (non-intrusive commands still allowed).
BDMACT — Background Mode Active Status
This is a read-only status bit.
1 = BDM active and waiting for serial commands.
0 = BDM not active (user application program running).
BKPTEN — BDC Breakpoint Enable
If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and
BDCBKPT match register are ignored.
1 = BDC breakpoint enabled.
0 = BDC breakpoint disabled.
FTS — Force/Tag Select
When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT
match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction
queue, the CPU enters active background mode rather than executing the tagged opcode.
1 = Breakpoint match forces active background mode at next instruction boundary (address need
not be an opcode).
0 = Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute
that instruction.
CLKSW — Select Source for BDC Communications Clock
CLKSW defaults to 0, which selects the alternate BDC clock source.
1 = MCU bus clock.
0 = Alternate BDC clock source.
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WS — Wait or Stop Status
When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the
BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into
active background mode, the host should issue a READ_STATUS command to check that
BDMACT = 1 before attempting other BDC commands.
1 = Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from
wait or stop to active background mode.
0 = Target CPU is running user application code or in active background mode (was not in wait or
stop mode when background became active).
WSF — Wait or Stop Failure Status
This status bit is set if a memory access command failed due to the target CPU executing a wait or stop
instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND
command to get out of wait or stop mode into active background mode, repeat the command that failed,
then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
1 = Memory access command failed because the CPU entered wait or stop mode.
0 = Memory access did not conflict with a wait or stop instruction.
DVF — Data Valid Failure Status
This status bit is not used in the MC9S08RC/RD/RE/RG because it does not have any slow access
memory.
1 = Memory access command failed because CPU was not finished with a slow memory access.
0 = Memory access did not conflict with a slow memory access.
14.5.1.2 BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to 14.3.4 BDC Hardware Breakpoint.
14.5.2 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial active background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return $00.
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Read:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BDFR(1)
Write:
Reset:
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
NOTES:
1. BDFR is writable only through serial active background mode debug commands, not from user programs.
Figure 14-6 System Background Debug Force Reset Register (SBDFR)
BDFR — Background Debug Force Reset
A serial active background mode command such as WRITE_BYTE allows an external debug host to
force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from
a user program.
14.5.3 DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
14.5.3.1 Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.2 Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.3 Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.4 Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
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14.5.3.5 Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have
no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte
of each FIFO word, so this register is not used and will read $00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the
FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the
next word of information.
14.5.3.6 Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have
no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug
module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each
FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get
successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled
or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can
interfere with normal sequencing of reads from the FIFO.
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode
to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host
software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will
return the information that was stored as a result of the first read. To use the profiling feature, read the
FIFO eight times without using the data to prime the sequence and then begin using the data to get a
delayed picture of what addresses were being executed. The information stored into the FIFO on reads of
DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode.
14.5.3.7 Debug Control Register (DBGC)
This register can be read or written at any time.
Bit 7
6
5
4
3
2
1
Bit 0
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 14-7 Debug Control Register (DBGC)
DBGEN — Debug Module Enable
Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
1 = DBG enabled.
0 = DBG disabled.
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ARM — Arm Control
Controls whether the debugger is comparing and storing information in the FIFO. A write is used to
set this bit (and the ARMF bit) and completion of a debug run automatically clears it. Any debug run
can be manually stopped by writing 0 to ARM or to DBGEN.
1 = Debugger armed.
0 = Debugger not armed.
TAG — Tag/Force Select
Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit
has no meaning or effect.
1 = CPU breaks requested as tag type requests.
0 = CPU breaks requested as force type requests.
BRKEN — Break Enable
Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause
information to be stored in the FIFO without generating a break request to the CPU. For an end trace,
CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger
requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL
does not affect the timing of CPU break requests.
1 = Triggers cause a break request to the CPU.
0 = CPU break requests not enabled.
RWA — R/W Comparison Value for Comparator A
When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When
RWAEN = 0, RWA and the R/W signal do not affect comparator A.
1 = Comparator A can only match on a read cycle.
0 = Comparator A can only match on a write cycle.
RWAEN — Enable R/W for Comparator A
Controls whether the level of R/W is considered for a comparator A match.
1 = R/W is used in comparison A.
0 = R/W is not used in comparison A.
RWB — R/W Comparison Value for Comparator B
When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When
RWBEN = 0, RWB and the R/W signal do not affect comparator B.
1 = Comparator B can match only on a read cycle.
0 = Comparator B can match only on a write cycle.
RWBEN — Enable R/W for Comparator B
Controls whether the level of R/W is considered for a comparator B match.
1 = R/W is used in comparison B.
0 = R/W is not used in comparison B.
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14.5.3.8 Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
Bit 7
6
TRGSEL
BEGIN
0
0
Read:
5
4
0
0
3
2
1
Bit 0
TRG3
TRG2
TRG1
TRG0
0
0
0
0
Write:
Reset:
0
0
= Unimplemented or Reserved
Figure 14-8 Debug Trigger Register (DBGT)
TRGSEL — Trigger Type
Controls whether the match outputs from comparators A and B are qualified with the opcode tracking
logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode
at the match address is actually executed.
1 = Trigger if opcode at compare address is executed (tag).
0 = Trigger on access to compare address (force).
BEGIN — Begin/End Trigger Select
Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the
capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed
to be begin traces.
1 = Trigger initiates data storage (begin trace).
0 = Data stored in FIFO until trigger (end trace).
TRG3:TRG2:TRG1:TRG0 — Select Trigger Mode
Selects one of nine triggering modes
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Table 14-2 Trigger Mode Selection
TRG[3:0]
Triggering Mode
0000
A-only
0001
A OR B
0010
A Then B
0011
Event-only B (store data)
0100
A then event-only B (store data)
0101
A AND B data (full mode)
0110
A AND NOT B data (full mode)
0111
Inside range: A ≤ address ≤ B
1000
Outside range: address < A or address > B
1001 – 1111
No trigger
14.5.3.9 Debug Status Register (DBGS)
This is a read-only status register.
Read:
Bit 7
6
5
4
3
2
1
Bit 0
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented or Reserved
Figure 14-9 Debug Status Register (DBGS)
AF — Trigger Match A Flag
AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met
since arming.
1 = Comparator A match.
0 = Comparator A has not matched.
BF — Trigger Match B Flag
BF is cleared at the start of a debug run and indicates whether a trigger match B condition was met
since arming.
1 = Comparator B match.
0 = Comparator B has not matched.
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ARMF — Arm Flag
While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. This bit is set by
writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end
of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event
is detected (end trace). A debug run can also be ended manually by writing 0 to the ARM or DBGEN
bits in DBGC.
1 = Debugger armed.
0 = Debugger not armed.
CNT3:CNT2:CNT1:CNT0 — FIFO Valid Count
These bits are cleared at the start of a debug run and indicate the number of words of valid data in the
FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the
FIFO.
Table 14-3 CNT Status Bits
MOTOROLA
CNT[3:0]
Valid Words in FIFO
0000
No valid data
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
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Appendix A Electrical Characteristics
A.1 Introduction
This section contains electrical and timing specifications.
A.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table A-1 Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)(1), (2), (3)
ID
± 25
mA
Tstg
–55 to 150
°C
Storage temperature range
NOTES:
1. Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS)
clamp voltages, then use the larger of the two resistance values.
2. All functional non-supply pins are internally clamped to VSS and VDD.
3. Power supply must maintain regulation within operating VDD range during instantaneous
and operating maximum current conditions. If positive injection current (VIn > VDD) is
greater than IDD, the injection current may flow out of VDD and could result in external
power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if the clock rate is very
low (which would reduce overall power consumption).
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Electrical Characteristics
A.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the
MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table A-2 Thermal Characteristics
Rating
Operating temperature range (packaged)
Thermal resistance
28-pin PDIP
28-pin SOIC
32-pin LQFP
44-pin LQFP
Symbol
Value
Unit
TA
TL to TH
–40 to 85
°C
75
70
72
70
°C/W
θJA
The average chip-junction temperature (TJ) in °C can be obtained from:
Equation 1 TJ = TA + (PD × θJA)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O 2.3 V) (all digital inputs)
VIH
0.70 × VDD
—
V
Input high voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs)
VIH
0.85 × VDD
—
V
Input low voltage (VDD > 2.3 V) (all digital inputs)
VIL
—
0.35 ×
VDD
V
Supply voltage (run, wait and stop modes.)
0 < fBus < 8 MHz
Minimum RAM retention supply voltage applied to VDD
Typical
Max
Unit
V
Low-voltage detection threshold
Low-voltage warning threshold
Power on reset (POR) voltage
Maximum low-voltage safe state re-arm(3)
MOTOROLA
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Electrical Characteristics
Table A-4 DC Characteristics (Continued)(Temperature Range = –40 to 85°C Ambient)
Parameter
Symbol
Min
Input low voltage (1.8 V ≤ VDD ≤ 2.3 V)
(all digital inputs)
VIL
Input hysteresis (all digital inputs)
Typical
Max
Unit
—
0.30 ×
VDD
V
Vhys
0.06 × VDD
—
V
Input leakage current (Per pin)
VIn = VDD or VSS, all input only pins
|IIn|
—
0.025
1.0
µA
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output
|IOZ|
—
0.025
1.0
µA
Internal pullup resistors(4) (5)
RPU
17.5
52.5
kΩ
Internal pulldown resistor (IRQ)
RPD
17.5
52.5
kΩ
VDD – 0.5
—
Output high voltage (VDD ≥ 1.8 V)
IOH = –2 mA (ports A, C, D and E)
VOH
Output high voltage (port B and IRO)
IOH = –10 mA (VDD ≥ 2.7 V)
IOH = –6 mA (VDD ≥ 2.3 V)
IOH = –3 mA (VDD ≥ 1.8 V)
VDD – 0.5
Maximum total IOH for all port pins
|IOHT|
V
—
—
—
—
60
Output low voltage (VDD ≥ 1.8 V)
IOL = 2.0 mA (ports A, C, D and E)
—
0.5
Output low voltage (port B)
IOL = 10.0 mA (VDD ≥ 2.7 V)
IOL = 6 mA (VDD ≥ 2.3 V)
IOL = 3 mA (VDD ≥ 1.8 V)
—
—
—
0.5
0.5
0.5
—
—
—
1.2
1.2
1.2
—
60
mA
—
—
0.2
5
mA
mA
—
7
pF
VOL
Output low voltage (IRO)
IOL = 16 mA (VDD ≥ 2.7 V)
IOL =TBD mA (VDD ≥ 2.3 V)
IOL = TBD mA (VDD ≥ 1.8 V)
Maximum total IOL for all port pins
IOLT
dc injection current(2), (6), (7), (8),, (9)
VIN < VSS, VIN > VDD
Single pin limit
Total MCU limit, includes sum of all stressed pins
|IIC|
Input capacitance (all non-supply pins)
CIn
mA
V
NOTES:
1. RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR.
2. This parameter is characterized and not tested on each device.
3. If SAFE bit is set, VDD must be above re-arm voltage to allow MCU to accept interrupts, refer to 5.6 Low-Voltage Detect
(LVD) System.
4. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
5. The PTA0 pullup resistor may not pull up to the specified minimum VIH. However, all ports are functionally tested to
guarantee that a logic 1 will be read on any port input when the pullup is enabled and no dc load is present on the pin. In
addition, the test checks that the pin is pulled up from VSS to a logic 1 within 20 µs with a nominal capacitance of 75 pF.
6. All functional non-supply pins are internally clamped to VSS and VDD.
7. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
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8. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock
is present, or if clock rate is very low (which would reduce overall power consumption).
9. PTA0 does not have a clamp diode to VDD. Do not drive PTA0 above VDD.
PULLUP RESISTOR TYPICALS
85°C
25°C
–40°C
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
PULLDOWN RESISTOR TYPICALS
40
PULLDOWN RESISTANCE (kΩ)
PULL-UP RESISTOR (kΩ)
40
85°C
25°C
–40°C
35
30
25
20
3.6
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure A-1 Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
85°C
25°C
–40°C
0.8
85°C
25°C
–40°C
0.3
VOL (V)
VOL (V)
0.6
0.4
0.2
IOL = 10 mA
IOL = 6 mA
0.1
0.2
IOL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure A-2 Typical Low-Side Driver (Sink) Characteristics (Port B and IRO)
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
85°C
25°C
–40°C
0.6
0.4
0.1
85°C, IOL = 2 mA
25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0.05
0.2
0
0
0
5
10
IOL (mA)
15
20
1
2
3
4
VDD (V)
Figure A-3 Typical Low-Side Driver (Sink) Characteristics (Ports A, C, D and E)
MOTOROLA
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Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.8
85°C
25°C
–40°C
0.6
0.4
0.2
0
0
85°C
25°C
–40°C
0.3
VDD – VOH (V)
VDD – VOH (V)
0.4
–5
–10
–15
–20
–25
0.2
IOH = –10 mA
IOH = –6 mA
0.1
–30
IOH = –3 mA
0
IOH (mA)
1
2
3
4
VDD (V)
Figure A-4 Typical High-Side Driver (Source) Characteristics (Port B and IRO)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
1.2
85°C
25°C
–40°C
85°C, IOH = 2 mA
25°C, IOH = 2 mA
–40°C, IOH = 2 mA
0.2
VDD – VOH (V)
1
VDD – VOH (V)
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
0.8
0.6
0.4
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure A-5 Typical High-Side (Source) Characteristics (Ports A, C, D and E)
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SoC Guide — MC9S08RG60/D V1.08
A.6 Supply Current Characteristics
Table A-5 Supply Current Characteristics
Parameter
Symbol
(3)
Run supply current measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
Stop1 mode supply current
Stop2 mode supply current
Stop3 mode supply current
RTI adder from stop2 or stop3
Typical(2)
Max
Temp.
(°C)
3
500 µA
1.525 µA
1.525 µA
70
85
2
450 µA
1.475 µA
1.475 µA
70
85
3
3.8 mA
4.8 mA
4.8 mA
70
85
2
2.6 mA
3.6 mA
3.6 mA
70
85
3
100 nA
350 nA
736 nA
70
85
2
100 nA
150 nA
450 nA
70
85
3
500 nA
1.20 µA
1.90 µA
70
85
2
500 nA
1.00 µA
1.70 µA
70
85
3
600 nA
2.65 µA
4.65 µA
70
85
2
500 nA
2.30 µA
4.30 µA
70
85
3
300 nA
2
300 nA
3
70 µA
2
60 µA
RIDD
(3)
Run supply current measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
VDD
(V)(1)
RIDD
S1IDD
S2IDD
S3IDD
Adder for LVD reset enabled in stop3
NOTES:
1. 3 V values are 100% tested; 2 V values are characterized but not tested.
2. Typicals are measured at 25°C.
3. Does not include any dc loads on port pins
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A.7 Analog Comparator (ACMP) Electricals
Table A-6 ACMP Electrical Specifications (Temp Range = -40 to 85° C Ambient)
Characteristic
Symbol
Min
Typical
Max
Unit
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
Analog input offset voltage
VAIO
—
40
mV
Analog Comparator initialization delay
tAINIT
—
1
µs
Analog Comparator bandgap reference voltage
VBG
1.218
1.228
V
1.208
A.8 Oscillator Characteristics
OSC
EXTAL
XTAL
RF
C1
Crystal or Resonator
C2
Table A-7 OSC Electrical Specifications (Temperature Range = -40 to 85°C Ambient)
Symbol
Min
Typ(1)
Max
Unit
Frequency
fOSC
1
—
16
MHz
Load Capacitors
C1
C2
Feedback resistor
RF
Characteristic
(2)
1
MΩ
NOTES:
1. Data in typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2. See crystal or resonator manufacturer’s recommendation.
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SoC Guide — MC9S08RG60/D V1.08
A.9 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.9.1 Control Timing
Table A-8 Control Timing
Parameter
Symbol
Min
Typical
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
8
MHz
Real time interrupt internal oscillator
fRTI
700
1300
Hz
External reset pulse width(1)
textrst
1.5 tcyc
—
ns
Reset low drive(2)
trstdrv
34 tcyc
—
ns
Active background debug mode latch setup time
tMSSU
25
—
ns
Active background debug mode latch hold time
tMSH
25
—
ns
IRQ pulse width(3)
tILIH
1.5 tcyc
—
ns
tRise, tFall
—
Port rise and fall time (load = 50 pF)(4)
3
ns
NOTES:
1. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed
to override reset requests from internal sources.
2. When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of fBus and then samples the
level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst
RESET PIN
Figure A-6 Reset Timing
MOTOROLA
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Electrical Characteristics
BKGD/MS
RESET
tMSH
tMSSU
Figure A-7 Active Background Debug Mode Latch Timing
tILIH
IRQ
Figure A-8 IRQ Timing
A.9.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-9 TPM Input Timing
Function
Symbol
Min
Max
Unit
External clock frequency
fTPMext
dc
fBus/4
MHz
External clock period
tTPMext
4
—
tcyc
External clock high time
tclkh
1.5
—
tcyc
External clock low time
tclkl
1.5
—
tcyc
tICPW
1.5
—
tcyc
Input capture pulse width
tText
tclkh
TPM1CHn
tclkl
Figure A-9 Timer External Clock
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tICPW
TPM1CHn
TPM1CHn
tICPW
Figure A-10 Timer Input Capture Pulse
A.9.3 SPI Timing
Table A-10 and Figure A-11 through Figure A-14 describe the timing requirements for the SPI system.
Table A-10 SPI Timing
No.
Function
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
tSPSCK
2
4
2048
—
tcyc
tcyc
1
SPSCK period
Master
Slave
2
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSPSCK
tcyc
3
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSPSCK
tcyc
4
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
5
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
Slave access time
ta
—
1
tcyc
8
Slave MISO disable time
tdis
—
1
tcyc
9
Data valid (after SPSCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
MOTOROLA
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Electrical Characteristics
Table A-10 SPI Timing (Continued)
No.
Function
Symbol
Min
Max
Unit
tHO
0
0
—
—
ns
ns
10
Data hold time (outputs)
Master
Slave
11
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
SS1
(OUTPUT)
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
11
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT)
3
4
BIT 6 . . . 1
LSB IN
9
MSB OUT2
BIT 6 . . . 1
10
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-11 SPI Master Timing (CPHA = 0)
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SoC Guide — MC9S08RG60/D V1.08
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
BIT 6 . . . 1
9
LSB IN
10
MOSI
(OUTPUT) PORT DATA
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-12 SPI Master Timing (CPHA =1)
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
SLAVE
5
MOSI
(INPUT)
9
MSB OUT
BIT 6 . . . 1
10
10
SLAVE LSB OUT
SEE
NOTE
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure A-13 SPI Slave Timing (CPHA = 0)
MOTOROLA
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Electrical Characteristics
SS
(INPUT)
1
3
2
12
11
11
12
SPSCK
(CPOL = 0)
(INPUT)
4
4
SPSCK
(CPOL = 1)
(INPUT)
9
MISO
(OUTPUT)
SEE
NOTE
7
MOSI
(INPUT)
SLAVE
10
MSB OUT
5
BIT 6 . . . 1
8
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure A-14 SPI Slave Timing (CPHA = 1)
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SoC Guide — MC9S08RG60/D V1.08
A.10 FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table A-11 FLASH Characteristics
Characteristic
Symbol
Min
Supply voltage for program/erase
Vprog/erase
Supply voltage for read operation
0 < fBus < 8 MHz
Max
Unit
2.05
3.6
V
VRead
1.8
3.6
Internal FCLK frequency(1)
fFCLK
150
200
kHz
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
µs
Byte program time (random location)(2)
tprog
9
tFcyc
Byte program time (burst mode)(2)
tBurst
4
tFcyc
Page erase time(2)
tPage
4000
tFcyc
Mass erase time(2)
tMass
20,000
tFcyc
Program/erase endurance(3)
TL to TH = –40°C to + 85°C
T = 25°C
Data retention(4)
Typical
10,000
tD_ret
15
V
—
—
cycles
100,000
100
—
years
NOTES:
1. The frequency of this clock is controlled by a software setting.
2. These values are hardware state machine controlled. User code does not need to count cycles. This
information supplied for calculating approximate time to program and erase.
3. Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional
information on how Motorola defines typical endurance, please refer to Engineering Bulletin EB619/D,
Typical Endurance for Nonvolatile Memory.
4. Typical data retention values are based on intrinsic capability of the technology measured at high
temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how
Motorola defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data
Retention for Nonvolatile Memory.
MOTOROLA
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SoC Guide — MC9S08RG60/D V1.08
Appendix B Ordering Information and Mechanical
Drawings
B.1 Ordering Information
This section contains ordering numbers for MC9S08RC/RD/RE/RG devices. See below for an example of
the device numbering system.
Table 14-4 Orderable Part Numbers
FLASH
Memory
RAM
ACMP
SCI
SPI
Available Package Type
(Part Number Suffix)
MC9S08RG32(C)FJ
32K
2K
Yes
Yes
Yes
32 LQFP (FJ)
MC9S08RG32(C)FG
32K
2K
Yes
Yes
Yes
44 LQFP (FG)
MC9S08RG60(C)FJ
60K
2K
Yes
Yes
Yes
32 LQFP (FJ)
MC9S08RG60(C)FG
60K
2K
Yes
Yes
Yes
44 LQFP (FG)
MC9S08RE8(C)FJ
8K
1K
Yes
Yes
No
32 LQFP (FJ)
MC9S08RE8(C)FG
8K
1K
Yes
Yes
No
44 LQFP (FG)
MC9S08RE16(C)FJ
16K
1K
Yes
Yes
No
32 LQFP (FJ)
MC9S08RE16(C)FG
16K
1K
Yes
Yes
No
44 LQFP (FG)
MC9S08RE32(C)FJ
32K
2K
Yes
Yes
No
32 LQFP (FJ)
MC9S08RE32(C)FG
32K
2K
Yes
Yes
No
44 LQFP (FG)
MC9S08RE60(C)FJ
60K
2K
Yes
Yes
No
32 LQFP (FJ)
MC9S08RE60(C)FG
60K
2K
Yes
Yes
No
44 LQFP (FG)
MC9S08RD8(C)PE
8K
1K
No
Yes
No
28 PDIP (P)
MC9S08RD8(C)DWE
8K
1K
No
Yes
No
28 SOIC (DW)
MC9S08RD8(C)FJ
8K
1K
No
Yes
No
32 LQFP (FJ)
MC9S08RD8(C)FG
8K
1K
No
Yes
No
44 LQFP (FG)
MC9S08RD16(C)PE
16K
1K
No
Yes
No
28 PDIP (P)
MC9S08RD16(C)DWE
16K
1K
No
Yes
No
28 SOIC (DW)
MC9S08RD16(C)FJ
16K
1K
No
Yes
No
32 LQFP (FJ)
MC9S08RD16(C)FG
16K
1K
No
Yes
No
44 LQFP (FG)
MC9S08RD32(C)PE
32K
2K
No
Yes
No
28 PDIP (P)
MC9S08RD32(C)DWE
32K
2K
No
Yes
No
28 SOIC (DW)
MC9S08RD32(C)FJ
32K
2K
No
Yes
No
32 LQFP (FJ)
MC Order Number
MOTOROLA
MC9S08RC/RD/RE/RG
223
Ordering Information and Mechanical Drawings
Table 14-4 Orderable Part Numbers (Continued)
FLASH
Memory
RAM
ACMP
SCI
SPI
Available Package Type
(Part Number Suffix)
MC9S08RD32(C)FG
32K
2K
No
Yes
No
44 LQFP (FG)
MC9S08RD60(C)PE
60K
2K
No
Yes
No
28 PDIP (P)
MC9S08RD60(C)DWE
60K
2K
No
Yes
No
28 SOIC (DW)
MC9S08RD60(C)FJ
60K
2K
No
Yes
No
32 LQFP (FJ)
MC9S08RD60(C)FG
60K
2K
No
Yes
No
44 LQFP (FG)
MC9S08RC8(C)FJ
8K
1K
Yes
No
No
32 LQFP (FJ)
MC9S08RC8(C)FG
8K
1K
Yes
No
No
44 LQFP (FG)
MC9S08RC16(C)FJ
16K
1K
Yes
No
No
32 LQFP (FJ)
MC9S08RC16(C)FG
16K
1K
Yes
No
No
44 LQFP (FG)
MC9S08RC32(C)FJ
32K
2K
Yes
No
No
32 LQFP (FJ)
MC9S08RC32(C)FG
32K
2K
Yes
No
No
44 LQFP (FG)
MC9S08RC60(C)FJ
60K
2K
Yes
No
No
32 LQFP (FJ)
MC9S08RC60(C)FG
60K
2K
Yes
No
No
44 LQFP (FG)
MC Order Number
Package designators:
DW =28-pin Small Outline Integrated Circuit (SOIC)
P = 28-pin Plastic Dual In-Line Package (PDIP)
FG = 44-pin Low Quad Flat Package (LQFP)
FJ = 32-pin Low Quad Flat Package (LQFP)
MC 9 S08 RG60 (C) XX E
Indicates lead-free packag
Package designator
Status
Memory
Type
Core
Temperature range
designator
C = –40 thru 85°C
Blank = 0 thru 70°C
Family
B.2 Mechanical Drawings
This appendix contains mechanical specification for MC9S08RC/RD/RE/RG MCU.
224
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
B.2.1 28-Pin SOIC Package Drawing
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION
AT MAXIMUM MATERIAL CONDITION.
15
H
E
1
14
PIN 1 IDENT
A1
A
B
0.25 M
B
M
28
e
B
0.025
L
0.10
C
C
M
C A
S
B
SEATING
PLANE
q
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.13
0.29
B
0.35
0.49
C
0.23
0.32
D 17.80 18.05
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
L
0.41
0.90
q
0_
8_
S
CASE 751F-05
ISSUE F
DATE 05/27/97
MOTOROLA
MC9S08RC/RD/RE/RG
225
Ordering Information and Mechanical Drawings
B.2.2 28-Pin PDIP Package Drawing
226
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
B.2.3 32-Pin LQFP Package Drawing
A
32
-T-, -U-, -Z-
4X
A1
0.20 (0.008) AB T-U Z
25
1
-U-
-TB
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
-Z9
0.20 (0.008) AC T-U Z
S1
S
DETAIL AD
G
-AB-AC0.10 (0.004) AC
AC T-U Z
SEATING
PLANE
BASE
METAL
F
8X
D
M
R
J
0.20 (0.008)
M
N
SECTION AE-AE
W
K
X
DETAIL AD
Q
GAUGE PLANE
H
0.250 (0.010)
C E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT
DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.250
(0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE DETERMINED AT DATUM
PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY FROM
DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 _ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
CASE 873A-02
ISSUE A
DATE 12/16/93
MOTOROLA
MC9S08RC/RD/RE/RG
227
Ordering Information and Mechanical Drawings
B.2.4 44-Pin LQFP Package Drawing
0.2 (0.008) H L-M N
4X
4X 11 TIPS
PLATING
-X-
0.2 (0.008) T L-M N
BASE METAL
F
X=L, M, N
44
34
CL
33
1
J
AB
40X
U
G
D
3X
-L-
VIEW Y
0.20 (0.008)
AB
-M-
B1
11
V1
-NA1
S1
A
S
4X
(q 2)
VIEW AA
0.1 (0.004) T
-H-TSEATING
PLANE
4X
(q 3)
C2
0.05 (0.002)
S
(W)
q1
2X R
R1
0.25 (0.010)
GAGE PLANE
(K)
E
(Z)
C1
N
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT
DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE DETERMINED AT DATUM
PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE D DIMENSION TO EXCEED 0.53 (0.021).
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
22
C
S
ROTATED 90 ° CLOCKWISE
V
23
12
T L-M
SECTION AB-AB
VIEW Y
B
M
q
VIEW AA
DIM
A
A1
B
B2
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
q
q1
q2
q3
MILLIMETERS
MIN
MAX
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
--1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.45
0.75
0.30
0.40
0.80 BSC
0.09
0.20
0.50 REF
0.09
0.20
12.00 BSC
6.00 BSC
0.09
0.16
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0°
7°
0°
--12° REF
12° REF
INCHES
MIN
MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
--0.063
0.002
0.006
0.053
0.057
0.012
0.018
0.018
0.030
0.012
0.016
0.031 BSC
0.004
0.008
0.020 REF
0.004
0.008
0.472 BSC
0.236 BSC
0.004
0.006
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
0°
7°
0°
--12° REF
12° REF
CASE 824D-02
ISSUE A
DATE 08/09/95
228
MC9S08RC/RD/RE/RG
MOTOROLA
SoC Guide — MC9S08RG60/D V1.08
SoC Guide End Sheet
need need more than 13 words type on blank page or will turn page landscape in pdf file??
turned white so this would not show up on customer page.
MOTOROLA
MC9S08RC/RD/RE/RG
229
FINAL PAGE OF
230
PAGES
230
MC9S08RC/RD/RE/RG
MOTOROLA
HOW TO REACH US:
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81-3-3440-3569
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HOME PAGE:
http://motorola.com/semiconductors
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There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola
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© Motorola Inc. 2004
MC9S08RG60/D
Rev. 1.08
4/2004
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