5962-9459901MXA

STK12C68 (SMD5962-94599) 8Kx8 AutoStore nvSRAM FEATURES DESCRIPTION • 25, 35, 45, 55 ns Read Access & Write Cycle Time The Simtek STK12C68 is a 64Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Software Control • Automatic RECALL to SRAM on Power Up The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. • Unlimited RECALL Cycles • 1 Million STORE Cycles • 100-Year Non-volatile Data Retention • Single 5V ± 10% Power Supply The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available. • Commercial, Industrial, Military Temperatures • 28-pin 330-mil SOIC, 300-mil PDIP, and 600-mil PDIP Packages (RoHS-Compliant) • 28-Pin CDIP and LCC Military Packages Block Diagram VCCX DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE STATIC RAM ARRAY 128 X 512 RECALL POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 ROW DECODER QUANTUM TRAP 128 x 512 VCAP A0 – A12 COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A10 G E W This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 Document Control #ML0008 Rev 0.7 February 2007 STK12C68 (SMD5962-94599) Packages VCAP 1 A12 2 A7 3 28 VCCX 27 W HSB A8 26 A6 4 25 A5 24 A4 5 6 A3 7 22 A2 8 21 A1 9 20 23 A0 10 DQ0 11 19 18 DQ1 12 17 16 15 DQ2 13 VSS 14 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28-pin SOIC 28-pin DIP 28-pin LCC Pin Descriptions Pin Name I/O Description A12-A0 Input Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCCX Power Supply Power: 5.0V, +10%, -10% HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground Document Control #ML0008 Rev 0.7 February 2007 2 STK12C68 (SMD5962-94599) ABSOLUTE MAXIMUM RATINGS a Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA (VCC = 5.0V ± 10%)e DC CHARACTERISTICS INDUSTRIAL MILITARY COMMERCIAL SYMBOL PARAMETER MIN MAX MIN UNITS NOTES MAX ICC1b Average VCC Current 85 75 65 -- 85 75 65 55 mA mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns ICC2c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ICC4c Average VCAP Current during AutoStore Cycle 2 2 mA ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) 27 24 20 -- 27 24 20 19 mA mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH tAVAV = 55ns, E ≥ VIH ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) 1.5 2.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA except HSB VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 8mA except HSB VBL Logic “0” Voltage on HSB Output 0.4 0.4 V IOUT = 3mA TA Operating Temperature 85/125 °C ICC3 b Note b: Note c: Note d: Note e: 2.4 0 2.4 70 –40/-55 All Inputs Don’t Care ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. AC TEST CONDITIONS 5.0V Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEf SYMBOL OUTPUT (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V Note f: 480 Ohms 255 Ohms These parameters are guaranteed but not tested. Document Control #ML0008 Rev 0.7 February 2007 30 pF INCLUDING SCOPE AND FIXTURE Figure 1. AC Output Loading 3 STK12C68 (SMD5962-94599) (VCC = 5.0V ± 10%)e SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55 MIN MIN MIN MIN PARAMETER UNITS #1, #2 Alt. 1 tELQV tACS Chip Enable Access Time 2 tAVAVg tRC Read Cycle Time 3 tAVQVh tAA Address Access Time 4 tGLQV tOE Output Enable to Data Valid 5 tAXQXh tOH Output Hold after Address Change 5 6 tELQX tLZ Chip Enable to Output Active 5 7 tEHQZi tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active i 25 25 tOHZ Output Disable to Output Inactive tELICCHf tPA Chip Enable to Power Active 11 f tPS Chip Disable to Power Standby 5 10 12 35 45 3 tAVQV tAXQX DATA VALID SRAM READ CYCLE #2: E Controlledg 2 tAVAV ADDRESS 1 11 tELQV tEHICCL 6 tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQX DQ (DATA OUT) DATA VALID 10 tELICCH ICC ACTIVE STANDBY Document Control #ML0008 Rev 0.7 February 2007 4 ns ns ns ns ns 55 ADDRESS tGLQV ns 0 2 tAVAV E ns 12 0 SRAM READ CYCLE #1: Address Controlledg, h DQ (DATA OUT) 35 0 Note g: W and HSB must be high during SRAM READ cycles. Note h: Device is continuously selected with E and G both low. Note i: Measured ± 200mV from steady state output voltage. 5 ns 12 0 0 55 5 12 ns ns 5 10 10 25 20 5 0 0 55 45 15 5 MAX 55 35 10 tGHQZ 45 45 5 0 MAX 35 10 9 MAX 35 25 10 tEHICCL MAX ns STK12C68 (SMD5962-94599) (VCC = 5.0V ± 10%)e SRAM WRITE CYCLES #1 & #2 SYMBOLS STK12C68-25 NO. STK12C68-35 STK12C68-45 STK12C68-55 PARAMETER UNITS #1 #2 Alt. MIN MAX MIN 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 25 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 0 ns 20 tWLQZ i, j tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 10 MAX MIN MAX 13 5 5 14 5 SRAM WRITE CYCLE #1: W Controlledk, l 12 tAVAV ADDRESS 19 tWHAX E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX SRAM WRITE CYCLE #2: E Controlledk, l 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT Document Control #ML0008 Rev 0.7 February 2007 16 tEHDX DATA VALID HIGH IMPEDANCE 5 MAX 15 5 Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles. 14 tELWH MIN ns ns STK12C68 (SMD5962-94599) HARDWARE MODE SELECTION E W HSB A12 - A0 (hex) MODE I/O POWER H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z lCC2 H 0000 1555 0AAA 1FFF 10F0 0F0F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z H 0000 1555 0AAA 1FFF 10F0 0F0E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z L L H H NOTES o m Active n, o lCC2 n, o Active Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. (VCC = 5.0V ± 10%)e HARDWARE STORE CYCLE SYMBOLS STK12C68 NO. PARAMETER Standard Alternate 22 tSTORE tHLHZ STORE Cycle Duration 23 tDELAY tHLQZ Time Allowed to Complete SRAM Cycle 24 tRECOVER tHHQX Hardware STORE High to Inhibit Off 25 tHLHX Hardware STORE Pulse Width 26 tHLBL Hardware STORE Low to Store Busy UNITS NOTES MIN MAX 10 1 700 15 ms i, p μs i, q ns p, r ns 300 ns Note p: E and G low for output behavior. Note q: E and G low and W high for output behavior. Note r: tRECOVER is only applicable after tSTORE is complete. HARDWARE STORE CYCLE 25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE HSB (OUT) 26 tHLBL HIGH IMPEDANCE HIGH IMPEDANCE 23 tDELAY DQ (DATA OUT) DATA VALID DATA VALID Document Control #ML0008 Rev 0.7 February 2007 6 STK12C68 (SMD5962-94599) (VCC = 5.0V ± 10%)e AutoStore / POWER-UP RECALL SYMBOLS STK12C68 NO. PARAMETER Standard UNITS NOTES 550 μs s STORE Cycle Duration 10 ms p, q, t Low Voltage Trigger (VSWITCH) to HSB Low 300 ns l μs p Alternate MIN 27 tRESTORE Power-up RECALL Duration 28 tSTORE 29 tVSBL 30 tDELAY 31 VSWITCH Low Voltage Trigger Level 32 VRESET Low Voltage Reset Level tHLHZ tBLQZ Time Allowed to Complete SRAM Cycle MAX 1 4.0 4.5 V 3.9 V Note s: tRESTORE starts from the time VCC rises above VSWITCH. Note t: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no STORE will take place. AutoStore / POWER-UP RECALL VCC 31 VSWITCH 32 VRESET AutoStoreTM POWER-UP RECALL 29 tVSBL 27 tRESTORE 28 tSTORE HSB 30 tDELAY W DQ (DATA OUT) POWER-UP RECALL BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT AutoStore BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Document Control #ML0008 Rev 0.7 February 2007 7 STK12C68 (SMD5962-94599) SOFTWARE-CONTROLLED STORE/RECALL CYCLEv SYMBOLS STK12C68-25 NO. (VCC = 5.0V ± 10%)e STK12C68-35 STK12C68-45 STK12C68-55 PARAMETER UNITS NOTES Standard Alternate MIN MAX MIN MAX 33 tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 55 ns p 34 tAVEL tAS Address Set-up Time 0 0 0 0 ns u 35 tELEH tCW Clock Pulse Width 20 25 30 30 ns u 36 tELAX Address Hold Time 20 20 20 20 ns u 37 tRECALL RECALL Duration 20 MIN MAX 20 MIN 20 MAX 20 μs Note u: The software sequence is clocked with E controlled READs. Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledv 33 33 tAVAV ADDRESS tAVAV ADDRESS #1 34 tAVEL ADDRESS #6 35 tELEH E 36 tELAX 28 tSTORE DQ (DATA OUT) DATA VALID DATA VALID Document Control #ML0008 Rev 0.7 February 2007 8 37 / tRECALL HIGH IMPEDANCE STK12C68 (SMD5962-94599) DEVICE OPERATION The STK12C68 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to Nonvolatile Elements (the STORE operation) or from Nonvolatile Elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled. NOISE CONSIDERATIONS The STK12C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK12C68 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low. SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. Document Control #ML0008 Rev 0.7 February 2007 9 POWER-UP RECALL During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request will be latched. When VCAP once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK12C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. SOFTWARE NONVOLATILE STORE The STK12C68 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. STK12C68 (SMD5962-94599) capacitor having a capacity of between 68μF and 220μF (± 20%) rated at 6V should be provided. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle If an automatic STORE on power loss is not required, then VCCX can be tied to ground and + 5V applied to VCAP (Figure 4). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the STK12C68 is operated in this configuration, references to VCCX should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered through software control or the HSB pin. It is not permissible to change between these three options “on the fly.” Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. This can be used to signal the system that the AutoStore cycle is in progress. AutoStore OPERATION The STK12C68 can be powered in one of three modes. During normal AutoStore operation, the STK12C68 will draw current from VCCX to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation. Figure 2. AutoStore Mode Document Control #ML0008 Rev 0.7 February 2007 1 28 27 26 14 15 Figure 3. System Power Mode 10 1 28 27 26 14 15 10K O* 15 10K O* 14 10K O 28 27 26 0.1 μF Bypass + 1 0.1μF 68μF 6V ±20% Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage 10K O If the power supply drops faster than 20 μs/volt before VCCX reaches VSWITCH, then a 2.2 ohm resistor should be inserted between VCCX and the system supply to avoid momentary excess of current between Vccx and Vcap. 0.1 μF Bypass 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) 10K O* Read address Read address Read address Read address Read address Read address 10K O 1. 2. 3. 4. 5. 6. In system power mode (Figure 3), both VCCX and VCAP are connected to the + 5V power supply without the 68μF capacitor. In this mode the AutoStore function of the STK12C68 will operate on the stored system charge as power goes down. The user must, however, guarantee that VCCX does not drop below 3.6V during the 10ms STORE cycle. Figure 4. AutoStore Inhibit Mode STK12C68 (SMD5962-94599) If HSB is not used, it should be left unconnected. HSB OPERATION The STK12C68 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK12C68 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK12C68 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK12C68s while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other STK12C68s. An external pull-up resistor to + 5V is required since HSB acts as an open drain pull down. The VCAP pins from the other STK12C68 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK12C68s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK12C68s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK12C68 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK12C68 will remain disabled until the HSB pin returns high. Document Control #ML0008 Rev 0.7 February 2007 11 PREVENTING STORES The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20μs at the onset of a STORE. When the STK12C68 is connected for AutoStore operation (system VCC connected to VCCX and a 68μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68 will attempt to pull HSB low; if HSB doesn’t actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt. HARDWARE PROTECT The STK12C68 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore can be completely disabled by tying VCCX to ground and applying + 5V to VCAP . This is the AutoStore Inhibit mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin. LOW AVERAGE ACTIVE POWER The STK12C68 draws significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 6 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK12C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. 100 100 80 80 Average Active Current (mA) Average Active Current (mA) STK12C68 (SMD5962-94599) 60 40 TTL 20 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 200 50 Figure 5: Icc (max) Reads 100 150 Cycle Time (ns) Figure 6: Icc (max) Writes Commercial and Industrial Ordering Information STK12C68 - S F 45 I TR Packing Option Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish F = 100% Sn (Matte Tin) Package S = Plastic 28-pin 330 mil SOIC W = Plastic 28-pin 600 mil DIP P = Plastic 28-pin 300 mil DIP C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin LLC Document Control #ML0008 Rev 0.7 February 2007 12 200 STK12C68 (SMD5962-94599) Military Ordering Information STK12C68 - 5 C 35 M Temperature Range M = Military (–55 to 125°C) Access Time 35 = 35ns 55 = 55ns Package C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC Retention / Endurance 5 = Military (10 years or 105cycles) 5962 - 94599 01 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Case Outline X = Ceramic 28 pin 300-mil DIP Y = Ceramic 28 pin LCC Device Class Indicator - Class M Device Type 01 = 55ns 03 = 35ns Document Control #ML0008 Rev 0.7 February 2007 13 STK12C68 (SMD5962-94599) Ordering Information Part Number STK12C68-C35 STK12C68-C45 STK12C68-L35 STK12C68-L45 Description 5V 8Kx8 AutoStore 5V 8Kx8 AutoStore 5V 8Kx8 AutoStore 5V 8Kx8 AutoStore STK12C68-PF25 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial STK12C68-PF45 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial STK12C68-SF25 5V 8Kx8 AutoStore nvSRAM SOP28-330 Commercial STK12C68-SF25TR STK12C68-SF45 STK12C68-SF45TR STK12C68-W F25 STK12C68-W F45 STK12C68-C35I STK12C68-C45I STK12C68-L35I STK12C68-L45I STK12C68-PF25I STK12C68-PF45I STK12C68-SF25I STK12C68-SF25ITR STK12C68-SF45I STK12C68-SF45ITR STK12C68-W F25I STK12C68-W F45I SMD5962-9459901MXA SMD5962-9459901MXC SMD5962-9459901MXX SMD5962-9459901MYA SMD5962-9459901MYX SMD5962-9459903MXA SMD5962-9459903MXC SMD5962-9459903MXX SMD5962-9459903MYA SMD5962-9459903MYX STK12C68-5C35M STK12C68-5C55M STK12C68-5K35M STK12C68-5K55M STK12C68-5L35M STK12C68-5L55M 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military Military 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 8Kx8 Document Control #ML0008 Rev 0.7 February 2007 AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore AutoStore nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM 14 CDIP28-300 CDIP28-300 LCC28 LCC28 SOP28-330 SOP28-330 SOP28-330 PDIP28-600 PDIP28-600 CDIP28-300 CDIP28-300 LCC28 LCC28 PDIP28-600 PDIP28-600 SOP28-330 SOP28-330 SOP28-330 SOP28-330 PDIP28-600 PDIP28-600 CDIP28-300 CDIP28-300 CDIP28-300 LCC28 LCC28 CDIP28-300 CDIP28-300 CDIP28-300 LCC28 LCC28 CDIP28-300 CDIP28-300 CDIP28-300 CDIP28-300 LCC28 LCC28 Temperature Commercial Commercial Commercial Commercial STK12C68 (SMD5962-94599) Package Diagrams 28-Lead, 330 mil SOIC Gull Wing 0.713 0.733 ( 18.11 ) 18.62 0.112 (2.845) 0.020 0.014 ( 0.508 ) 0.356 0.050 (1.270) 0.103 0.093 0.336 0.326 0.004 (0.102) ( 2.616 ) 2.362 ( 8.534 ) 8.280 0.477 0.453 ( 12.116 ) 11.506 Pin 1 0.014 0.008 10° 0° ( 0.356 ) 0.203 0.044 0.028 DIM = INCHES DIM = mm Document Control #ML0008 Rev 0.7 February 2007 15 MIN MAX MIN ) ( MAX ( 1.117 ) 0.711 STK12C68 (SMD5962-94599) 28-Lead 300 mil PDIP ( ) .275 6.98 .295 7.49 Pin 1 Index .020 .030 ( 0.51 0.76) 1.345 1.385 ( 34.16 35.18 ) ------(4.57 ).180 .015 ---.125 (3.18) MIN .030 .045 (0.76 1.14) ( ) .014 0.36 .022 0.56 .300 .325 ( ) .045 1.14 .060 1.52 .100 (2.54) BSC ( 7.62 8.26) DIM = INCHES DIM = mm 0o 15o .008 .015 .300 (7.62) BSC ------.430 10.92 ( ) Document Control #ML0008 Rev 0.7 February 2007 16 ( 0.20 0.38) MIN MAX MIN ( MAX ) ( 0.38 ---- ) STK12C68 (SMD5962-94599) 28-Lead, 600 mil PDIP ( 0.530 13.46 0.550 13.97 Pin 1 Index ) ( ) 0.040 1.02 0.050 1.27 ( 1.440 36.58 1.460 37.08 ) ---- ---(4.57) .180 0.015 (0.38) ------0.125 (3.18) MIN ( 0.014 0.36 0.022 0.56 0.595 0.625 ) ( 0.045 1.14 0.060 1.52 ) 0.10 (2.54) BSC ( 15.11 15.88 ) DIM = INCHES o 0o 15 ( 0.008 0.20 0.015 0.38 0.600 0.660 (15.24 16.76 ) Document Control #ML0008 Rev 0.7 February 2007 17 ) DIM = mm MIN MAX MIN ) ( MAX STK12C68 (SMD5962-94599) 28-Lead, 300 mil Side Braze DIL 1.386 1.414 35.20 (35.92 ) .280 .310 --.060 --(1.52 ) (7.36 7.87) PIN 14 .124 ( 3.15 4.14 ).162 .040 .060 .125 (3.18) MIN .016 .020 .290 .310 ( ) 0.41 0.51 .048 .052 ( 7.37 7.87 ) ( ) 1.22 1.32 ( ) .090 2.29 .110 2.79 DIM = INCHES DIM = mm ( ) .009 0.23 .012 0.30 ( ) .300 7.62 .320 8.13 Document Control #ML0008 Rev 0.7 February 2007 18 MIN MAX MIN ( MAX ) (1.02 1.52) STK12C68 (SMD5962-94599) 28-Pad, 350 mil Ceramic LCC 0.542 13.77 0.558 14.17 ( ο ) (1.02) 0.040 REF X 45 3 places ( 0.342 8.69 0.358 9.09 ) ο (0.51) 0.020 REF X 45 1.91 ( 2.41 ) 0.045 1.14 0.055 ( 1.40 ) 0.075 0.095 (0.23) 0.009 REF 28 places Pad 1 Index ( 0.022 0.028 0.56 0.71 )( 0.006 0.022 0.15 0.56 ) 0.045 0.055 ( 1.14 1.40 ) ( 0.070 1.78 0.090 2.29 ( --0.558 ( --14.17 ) ) ( ) 0.015 --0.381 --- 0.062 1.57 0.078 1.98 ) DIM = INCHES DIM = mm Document Control #ML0008 Rev 0.7 February 2007 19 MIN MAX MIN ( MAX ) STK12C68 (SMD5962-94599) Document Revision History Revision Date Summary 0.0 December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device. 0.1 January 2003 Added 35ns SMD to order information 0.2 July 2003 Added “28 - SOIC” label to page 1 pinout drawing 0.3 September 2003 Added lead-free lead finish 0.4 October 2003 Restored “W” 600 mil DIP package to ordering information 0.5 March 2006 Removed Commercial 35 ns and leaded lead finish, Removed Military 45ns device 0.6 August 2006 Reformat SMD Ordering Information to SDDC Part Number Format 0.7 February 2007 Add Fast Power-Down Slew Rate Information Restore Comm/Ind C & L Package Options Add Tape Reel Ordering Options Add Product Ordering Code Listing Add Package Outline Drawings Reformat Entire Document SIMTEK STK12C68 Datasheet, February 2007 Copyright 2007, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0008 Rev 0.7 February 2007 20