NUC121/125
ARM Cortex® -M0
32-bit Microcontroller
NuMicro® Family
NUC121/125 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Aug. 17, 2018
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NUC121/125 SERIES DATASHEET
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
NUC121/125
TABLE OF CONTENTS
GENERAL DESCRIPTION .......................................................................9
1
Key Features Support Table ......................................................................... 9
1.1
FEATURES .......................................................................................10
2
NuMicro® NUC121/125 Features...................................................................10
2.1
Abbreviations ....................................................................................16
3
Abbreviations .......................................................................................... 16
3.1
PARTS INFORMATION LIST AND PIN CONFIGURATION .............................18
4
NuMicro® NUC121/125 Selection Guide .......................................................... 18
4.1
4.1.1
NuMicro NUC121/125 Naming Rule ..................................................................... 18
4.1.2
NuMicro NUC121 USB Series Selection Guide ........................................................ 19
4.1.3
NuMicro NUC125 USB Series Selection Guide ........................................................ 19
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Pin Configuration...................................................................................... 20
4.2
NUC121/125 SERIES DATASHEET
4.2.1
NuMicro NUC121 QFN 33-Pin Diagram ................................................................. 20
4.2.2
NuMicro NUC121 QFN 33-Pin Function Diagram ...................................................... 21
4.2.3
NuMicro NUC121 LQFP 48-Pin Diagram ................................................................ 22
4.2.4
NuMicro NUC121 LQFP 48-Pin Function Diagram .................................................... 23
4.2.5
NuMicro NUC121 LQFP 64-Pin Diagram ................................................................ 24
4.2.6
NuMicro NUC121 LQFP 64-Pin Function Diagram .................................................... 25
4.2.7
NuMicro NUC125 QFN 33-Pin Diagram ................................................................. 26
4.2.8
NuMicro NUC125 QFN 33-Pin Function Diagram ...................................................... 27
4.2.9
NuMicro NUC125 LQFP 48-Pin Diagram ................................................................ 28
4.2.10
NuMicro NUC125 LQFP 48-Pin Function Diagram .................................................... 29
4.2.11
NuMicro NUC125 LQFP 64-Pin Diagram ................................................................ 30
4.2.12
NuMicro NUC125 LQFP 64-Pin Function Diagram .................................................... 31
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Pin Description ........................................................................................ 32
4.3
5
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4.3.1
NUC121 USB Series QFN33 Pin Description ............................................................ 32
4.3.2
NUC121 USB Series LQFP48 Pin Description .......................................................... 37
4.3.3
NUC121 USB Series LQFP64 Pin Description .......................................................... 44
4.3.4
NUC125 USB Series QFN33 Pin Description ............................................................ 52
4.3.5
NUC125 USB Series LQFP48 Pin Description .......................................................... 57
4.3.6
NUC125 USB Series LQFP64 Pin Description .......................................................... 64
4.3.7
GPIO Multi-function Pin Summary ......................................................................... 72
BLOCK DIAGRAM ..............................................................................78
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NuMicro® NUC121/125 Block Diagram............................................................ 78
5.1
FUNCTIONAL DESCRIPTION ................................................................79
6
6.1
ARM® Cortex® -M0 Core..............................................................................79
6.2
System Manager ...................................................................................... 81
6.2.1
Overview ....................................................................................................... 81
6.2.2
System Reset ................................................................................................. 81
6.2.3
Power Modes and Wake-up Sources...................................................................... 88
6.2.4
System Power Distribution .................................................................................. 90
6.3
Clock Controller ....................................................................................... 92
6.3.1
Overview ....................................................................................................... 92
6.3.2
Clock Generator ............................................................................................... 94
6.3.3
System Clock and SysTick Clock .......................................................................... 96
6.3.4
Peripherals Clock ............................................................................................. 98
6.3.5
Power-down Mode Clock .................................................................................... 98
6.3.6
Clock Output ................................................................................................... 98
6.4
Flash Memory Controller (FMC) .................................................................. 100
6.4.1
Overview ..................................................................................................... 100
6.4.2
Features ...................................................................................................... 100
6.5
General Purpose I/O (GPIO) ...................................................................... 101
Overview ..................................................................................................... 101
6.5.2
Features ...................................................................................................... 101
6.6
PDMA Controller (PDMA) ......................................................................... 102
6.6.1
Overview ..................................................................................................... 102
6.6.2
Features ...................................................................................................... 102
6.7
Timer Controller (TMR) ............................................................................ 103
6.7.1
Overview ..................................................................................................... 103
6.7.2
Features ...................................................................................................... 103
6.8
Basic PWM Generator and Capture Timer (BPWM) .......................................... 104
6.8.1
Overview ..................................................................................................... 104
6.8.2
Features ...................................................................................................... 104
6.9
PWM Generator and Capture Timer (PWM) ................................................... 105
6.9.1
Overview ..................................................................................................... 105
6.9.2
Features ...................................................................................................... 105
6.10
Watchdog Timer (WDT) ........................................................................... 107
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6.5.1
NUC121/125
6.10.1
Overview ..................................................................................................... 107
6.10.2
Features ...................................................................................................... 107
6.11
Window Watchdog Timer (WWDT) .............................................................. 108
6.11.1
Overview ..................................................................................................... 108
6.11.2
Features ...................................................................................................... 108
6.12
USCI - Universal Serial Control Interface Controller .......................................... 109
6.12.1
Overview ..................................................................................................... 109
6.12.2
Features ...................................................................................................... 109
6.13
USCI - UART Mode ................................................................................ 110
6.13.1
Overview ..................................................................................................... 110
6.13.2
Features ...................................................................................................... 110
6.14
USCI - SPI Mode.................................................................................... 111
6.14.1
Overview ..................................................................................................... 111
6.14.2
Features ...................................................................................................... 111
6.15
USCI - I2C Mode .................................................................................... 113
6.15.1
Overview ..................................................................................................... 113
6.15.2
Features ...................................................................................................... 113
6.16
UART Interface Controller (UART) ............................................................... 114
Overview ..................................................................................................... 114
6.16.1
Features ...................................................................................................... 114
6.16.2
NUC121/125 SERIES DATASHEET
6.17
I C Serial Interface Controller (I2C) .............................................................. 115
2
6.17.1
Overview ..................................................................................................... 115
6.17.2
Features ...................................................................................................... 115
6.18
Serial Peripheral Interface (SPI) .................................................................. 116
6.18.1
Overview ..................................................................................................... 116
6.18.2
Features ...................................................................................................... 116
6.19
USB Device Controller (USBD) ................................................................... 117
6.19.1
Overview ..................................................................................................... 117
6.19.2
Features ...................................................................................................... 117
6.20
Analog-to-Digital Converter (ADC) ............................................................... 118
6.20.1
Overview ..................................................................................................... 118
6.20.2
Features ...................................................................................................... 118
7
APPLICATION CIRCUIT .....................................................................119
8
ELECTRICAL CHARACTERISTICS .......................................................121
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8.1
Absolute Maximum Ratings ....................................................................... 121
8.2
DC Electrical Characteristics ...................................................................... 122
8.3
AC Electrical Characteristics ...................................................................... 130
8.3.1
External 4~24 MHz High Speed Crystal (HXT) Input Clock .......................................... 130
8.3.2
External 4~24 MHz High Speed Crystal (HXT) Oscillator ............................................ 130
8.3.3
External 32.768 kHz Low Speed Crystal (LXT) Input Clock ......................................... 131
8.3.4
External 32.768 kHz Low Speed Crystal (LXT) Oscillator ............................................ 131
Analog Characteristics ............................................................................. 134
8.4
8.4.1
12-bit ADC ................................................................................................... 134
8.4.2
LDO ........................................................................................................... 136
8.4.3
Low-Voltage Reset ......................................................................................... 136
8.4.4
Brown-out Detector ......................................................................................... 136
8.4.5
Power-on Reset ............................................................................................. 137
8.4.6
Temperature Sensor ....................................................................................... 138
8.4.7
USB PHY ..................................................................................................... 139
8.5
Flash DC Electrical Characteris .................................................................. 140
8.6
I2C Dynamic Characteristics ...................................................................... 141
8.7
SPI Dynamic Characteristics ...................................................................... 142
8.7.1
Dynamic Characteristics of Data Input and Output Pin ............................................... 142
9.1
LQFP 64S (7x7x1.4 mm) .......................................................................... 144
9.2
LQFP 48L (7x7x1.4 mm) .......................................................................... 145
9.3
QFN 33Z (5x5x0.8 mm) ............................................................................ 146
10
REVISION HISTORY ..........................................................................147
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PACKAGE DIMENSIONS ....................................................................144
9
NUC121/125
List of Figures
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Figure 4.1-1 NuMicro NUC121/125 Selection Code .................................................................... 18
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Figure 4.2-1 NuMicro NUC121 QFN 33-Pin Diagram .................................................................. 20
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Figure 4.2-2 NuMicro NUC121 QFN 33-Pin Function Diagram ................................................... 21
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Figure 4.2-3 NuMicro NUC121 LQFP 48-Pin Diagram ................................................................ 22
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Figure 4.2-4 NuMicro NUC121 LQFP 48-Pin Function Diagram ................................................. 23
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Figure 4.2-5 NuMicro NUC121 LQFP 64-Pin Diagram ................................................................ 24
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Figure 4.2-6 NuMicro NUC121 LQFP 64-Pin Function Diagram ................................................. 25
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Figure 4.2-7 NuMicro NUC125 QFN 33-Pin Diagram .................................................................. 26
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Figure 4.2-8 NuMicro NUC125 QFN 33-Pin Function Diagram ................................................... 27
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Figure 4.2-9 NuMicro NUC125 LQFP 48-Pin Diagram ................................................................ 28
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Figure 4.2-10 NuMicro NUC125 LQFP 48-Pin Function Diagram ............................................... 29
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Figure 4.2-11 NuMicro NUC125 LQFP 64-Pin Diagram .............................................................. 30
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Figure 4.2-12 NuMicro NUC125 LQFP 64-Pin Function Diagram ............................................... 31
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Figure 5.1-1 NuMicro NUC121/125 Block Diagram ..................................................................... 78
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Figure 6.1-1 Cortex -M0 Block Diagram ........................................................................................ 79
Figure 6.2-1 System Reset Sources .............................................................................................. 82
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 85
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 85
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 86
NUC121/125 SERIES DATASHEET
Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 87
Figure 6.2-6 Power Mode State Machine ...................................................................................... 88
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Figure 6.2-7 NuMicro NUC121/125 Power Distribution Diagram ................................................. 91
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 93
Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 95
Figure 6.3-3 System Clock Block Diagram .................................................................................... 96
Figure 6.3-4 HXT Stop Protect Procedure ..................................................................................... 97
Figure 6.3-5 SysTick Clock Control Block Diagram ....................................................................... 98
Figure 6.3-6 Clock Source of Clock Output ................................................................................... 99
Figure 6.3-7 Clock Output Block Diagram ..................................................................................... 99
Figure 6.14-1 SPI Master Mode Application Block Diagram ........................................................ 111
Figure 6.14-2 SPI Slave Mode Application Block Diagram .......................................................... 111
2
Figure 6.15-1 I C Bus Timing ....................................................................................................... 113
Figure 8.3-1 Typical Crystal Application Circuit ........................................................................... 131
Figure 8.3-2 Typical Crystal Application Circuit ........................................................................... 132
Figure 8.4-1 Power-up Ramp Condition ...................................................................................... 137
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Figure 8.6-1 I C Timing Diagram ................................................................................................. 141
Figure 8.7-1 SPI Master Mode Timing Diagram .......................................................................... 142
Figure 8.7-2 SPI Slave Mode Timing Diagram ............................................................................ 143
NUC121/125 SERIES DATASHEET
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List of Tables
Table 1.1-1 Key Features Support Table ......................................................................................... 9
Table 3.1-1 List of Abbreviations.................................................................................................... 17
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Table 4.1-1 NuMicro NUC121 USB Series Selection Guide ........................................................ 19
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Table 4.1-2 NuMicro NUC125 USB Series Selection Guide ........................................................ 19
Table 4.3-1 NUC121 USB Series QFN33 Pin Description ............................................................ 36
Table 4.3-2 NUC121 USB Series LQFP48 Pin Description ........................................................... 43
Table 4.3-3 NUC121 USB Series LQFP64 Pin Description ........................................................... 51
Table 4.3-4 NUC125 USB Series QFN33 Pin Description ............................................................ 56
Table 4.3-5 NUC125 USB Series LQFP48 Pin Description ........................................................... 63
Table 4.3-6 NUC125 USB Series LQFP64 Pin Description ........................................................... 71
Table 4.3-7 NUC121/125 GPIO Multi-function Table .................................................................... 77
Table 6.2-1 Reset Value of Registers ............................................................................................ 84
Table 6.2-2 Power Mode Difference Table .................................................................................... 88
Table 6.2-3 Clocks in Power Modes .............................................................................................. 89
Table 6.2-4 Condition of Entering Power-down Mode Again ......................................................... 90
Table 6.3-1 Clock Stable Count Value Table ................................................................................. 94
NUC121/125 SERIES DATASHEET
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1
GENERAL DESCRIPTION
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The NuMicro NUC121/125 series is a 32-bit Cortex -M0 microcontroller with USB 2.0 Full-speed
device, a 12-bit ADC and 4 sets of 6-channel BPWM. The NUC121/125 series provides the high
50 MHz operating speed, 8 Kbytes SRAM, 8 USB endpoints and 24 channels of BPWM, which
make it powerful in USB communication and data processing. The NUC121/125 series is ideal for
industrial control, consumer electronics, and communication system applications such as printers,
touch panel, gaming keyboard, gaming joystick, USB audio, PC peripherals, and alarm systems.
The NUC121/125 series runs up to 50 MHz and supports 32-bit multiplier, structure NVIC (Nested
Vector Interrupt Control), dual-channel APB and PDMA (Peripheral Direct Memory Access) with
CRC function. Besides, the NUC121/125 series is equipped with 32 Kbytes Flash memory, 8
Kbytes SRAM, and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V
~ 5.5V and temperature range of -40℃ ~ +105℃. It is also equipped with plenty of peripheral
2
2
devices, such as 8-channel 12-bit ADC, USCI, UART, SPI, I C, I S, USB 2.0 FS device, and
offers low-voltage reset and Brown-out detection, PWM (Pulse-width Modulation), capture and
compare features, four sets of 32-bit timers, Watchdog Timer, and internal RC oscillator. All these
peripherals have been incorporated into the NUC121/125 series to reduce component count,
board space and system cost.
Additionally, the NUC121/125 series is equipped with ISP (In-System Programming), IAP (InApplication-Programming) and ICP (In-Circuit Programming) functions, which allows the user to
update the program under software control through the on-chip connectivity interface, such as
SWD, UART and USB. Also all series support SPROM. Moreover, the NUC125 support Voltage
Adjustable Interface with individual I/O (1.8V-5.5V) for saving additional cost on adjusting the
interface voltage difference of peripheral components.
1.1
Key Features Support Table
2
* USCI can be set to UART, I C or SPI
USBD
USCI
UART
I2C
SPI/ I2S
Timer
BPWM
ADC
NUC121
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1
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1
4
24
12
NUC125
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1
1
2
1
4
23
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Table 1.1-1 Key Features Support Table
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The NuMicro NUC121/125 series is suitable for a wide range of applications such as:
USB Keyboard / Mouse
Gaming - Joystick
Industrial Automation
Home Automation
VR peripheral application
USB audio
Alarm system
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Product Line
NUC121/125
2
FEATURES
2.1 NuMicro® NUC121/125 Features
Core
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ARM® Cortex® -M0 core running up to 50 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
Supports programmable 4 level priorities of Nested Vectored Interrupt Controller
(NVIC)
Supports programmable mask-able interrupts
Supports Serial Wire Debug(SWD) with 2 watch-points/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Flash Memory
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SRAM Memory
NUC121/125 SERIES DATASHEET
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8 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
PDMA (Peripheral DMA)
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Supports 32 KB application ROM (APROM)
Supports 4.5 KB Flash for loader (LDROM)
Supports 512 bytes Security Protection Rom (SPROM)
Supports 12 bytes User Configuration block to control system initiation
Supports Data Flash with configurable memory size
Supports 512 bytes page erase for all embedded flash
Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
Supports CRC-32 checksum calculation function
Supports flash all one verification function
Hardware external read protection of whole flash memory by Security Lock Bit
Supports 2-wired ICP update through SWD/ICE interface
Supports 5 independent configurable channels for automatic data transfer between
memories and peripherals
Supports single and burst transfer type
Supports Normal and Scatter-Gather Transfer modes
Supports two types of priorities modes: Fixed-priority and Round-robin modes
Supports byte-, half-word- and word-access
Supports incrementing mode for the source and destination address for each channel
Supports time-out function for channel 0 and channel 1
Supports software and SPI/I2S, UART, USCI, USB, ADC, PWM and TIMER request
Clock Control
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Aug. 17, 2018
Built-in 48 MHz internal high speed RC oscillator (HIRC) for USB device operation
(Frequency variation < 2% at -40℃ ~ +105℃)
Dynamically calibrating the HIRC OSC to 48 MHz ±0.25% from -40℃ to 105℃
by external 32.768K crystal oscillator (LXT) or internal USB synchronous mode
Built-in 10 kHz internal low speed RC oscillator for Watchdog Timer and Wake-up
operation
Supports one interface to connect external crystal oscillator for high speed or low
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GPIO
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Watchdog Timer
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Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT
Supports 8 selections of time-out period (1.6ms ~ 26.0sec for LIRC)
Supports wake up from Power-down or Idle mode
Supports Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
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Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
BPWM, PWM, ADC and PDMA function
Supports Inter-Timer trigger mode
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Supports Window set by 6-bit counter with 11-bit prescale
Supports Interrupt
BPWM/Capture
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Aug. 17, 2018
Supports maximum clock frequency up to 100MHz
Supports up to two BPWM modules, each module provides one 16-bit counter and 6
output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution BPWM counter
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt on the following events:
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Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports up to 52/38/22 GPIOs for LQFP64/48 and QFN33 respectively
Timer
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speed application
Built-in 4~24 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Built-in 32.768 kHz external low speed crystal oscillator (LXT) for low-power
system operation
Supports one PLL up to 100 MHz for high performance system operation, sourced
from HIRC and HXT
Supports clock on-the-fly switch
Supports clock failure detection for high/low speed external crystal oscillator
Supports auto clock switch once clock failure detected
Supports exception (NMI) generated once a clock failure detected
Supports divided clock output
NUC121/125
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PWM/Capture
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NUC121/125 SERIES DATASHEET
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BPWM counter match zero, period value or compared value
Supports trigger ADC on the following events:
BPWM counter match zero, period value or compared value
Supports capture mode with 16-bit resolution for each BPWM pin
Supports rising edges, falling edges or both edges capture condition
Supports input rising edges, falling edges or both edges capture interrupt
Supports rising edges, falling edges or both edges capture with counter reload option
Supports maximum clock frequency up to 100MHz
Supports up to two PWM modules, each module provides three 16-bit counter and 6
output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out
detection and CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
Supports capture mode with 16-bit resolution for each PWM pin
Supports rising edges, falling edges or both edges capture condition
Supports input rising edges, falling edges or both edges capture interrupt
Supports rising edges, falling edges or both edges capture with counter reload option
Supports PDMA for capture mode
USCI
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Aug. 17, 2018
UART Mode
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-Bit Data Transfer (Support 9-Bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports Wake-up function (Data and nCTS Wakeup Only)
Supports PDMA transfer
SPI Mode
Supports Master or Slave mode operation (the maximum frequency -- Master =
fPCLK / 2, Slave = fPCLK / 5)
Supports one transmit buffer and two receive buffers for data payload
Configurable bit length of a transfer word from 4 to 16-bit
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
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UART
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Supports one set of UART
Supports maximum clock frequency up to 10 Mbps
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control (RX, TX, CTS and RTS)
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports PDMA transfer
2
SPI / I S
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Aug. 17, 2018
SPI
Supports one set of SPI controller
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
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Supports one data channel half-duplex transfer
Supports PDMA transfer
2
I C Mode
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
NUC121/125
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IC
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Supports up to two sets of I C devices
Supports speed up to 1Mbps
Supports Master/Slave mode
Supports bidirectional data transfer between masters and slaves
Supports multi-master bus bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
2
2
Supports 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up
and timer-out counter overflows
Programmable clocks allow versatile rate control
Supports multiple address recognition, four slave address with mask option
Supports two-level buffer function
Supports setup/hold time programmable
Supports wake-up function
USB 2.0 FS Device Controller
NUC121/125 SERIES DATASHEET
–
–
–
–
–
–
–
–
–
–
Supports Master or Slave mode operation
2
Capable of handling 8-, 16-, 24- and 32-bit word sizes in I S mode
2
Provides separate 4-level depth transmit and receive FIFO buffers in I S mode
2
Supports monaural and stereo audio data in I S mode
2
2
Supports PCM mode A, PCM mode B, I S and MSB justified data format in I S
mode
Supports PDMA transfer
2
–
–
–
–
–
–
Supports PDMA transfer
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 768 bytes buffer size
Provides remote wake-up capability
Start of Frame (SOF) locked clock pulse generation
Supports USB 2.0 Link Power Management (LPM)
Supports Crystal-less function
Supports PDMA transfer
ADC
–
–
–
–
–
–
–
–
Aug. 17, 2018
Supports 12-bit SAR ADC
12-bit resolution and 10-bit accuracy is guaranteed
Analog input voltage range: 0~ AVDD
Up to 12 single-end analog input channels or 6 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Conversion rate up to 800K SPS at 5V
Configurable ADC internal sampling time
Supports single, burst, single-cycle scan, and continuous scan modes on enabled
channels
Page 14 of 148
Rev 1.02
NUC121/125
–
–
–
–
–
Supports individual conversion result register with valid and overrun indicators for each
channel
Supports digital comparator to monitor conversion result and user can select whether
to generate an interrupt when conversion result matches the compare register setting
An A/D conversion can be triggered by:
Software enable
External pin (STADC)
Timer 0~3 overflow pulse trigger
PWM triggers with optional start delay period
Supports 2 internal channels for
Band-gap VBG input
Temperature sensor input
Supports PDMA transfer
Supports 96-bit Unique ID (UID)
Supports 128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out detector
–
–
With 4 levels: 4.3 V/ 3.7V/ 2.7V/ 2.2V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 2.0 V
Operating Temperature: -40℃~105℃
Packages
Aug. 17, 2018
All Green package (RoHS)
LQFP 64-pin (7mm x 7mm)
LQFP 48-pin (7mm x 7mm)
QFN 33-pin (5mm x 5 mm)
NUC121/125 SERIES DATASHEET
–
–
–
–
Page 15 of 148
Rev 1.02
NUC121/125
3
ABBREVIATIONS
3.1
Abbreviations
Acronym
Description
NUC121/125 SERIES DATASHEET
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
DAP
Debug Access Port
DES
Data Encryption Standard
EBI
External Bus Interface
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
48 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL
Phase-Locked Loop
PWM
Pulse Width Modulation
QEI
Quadrature Encoder Interface
SD
Secure Digital
Aug. 17, 2018
Page 16 of 148
Rev 1.02
NUC121/125
SPI
Serial Peripheral Interface
SPS
Samples per Second
TDES
Triple Data Encryption Standard
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
USB
Universal Serial Bus
WDT
Watchdog Timer
WWDT
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 17 of 148
Rev 1.02
NUC121/125
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC121/125 Selection Guide
4.1.1
NuMicro® NUC121/125 Naming Rule
ARM–Based
32-bit Microcontroller
NUC 1 2 X - X X X X X
CPU Core
Temperature
1: Cortex® -M0
E: -40oC ~ +105oC
Product Line Function
Reserved
2: USB Line
SRAM Size
Sub-Line
2: 8 KB
1: Without VDDIO
5: With VDDIO
Flash ROM
C: 32 KB
Package Type
NUC121/125 SERIES DATASHEET
Z: QFN 33 5x5mm
L: LQFP 48 7x7mm
S: LQFP 64 7x7mm
®
Figure 4.1-1 NuMicro NUC121/125 Selection Code
Aug. 17, 2018
Page 18 of 148
Rev 1.02
NUC121/125
4.1.2
NuMicro® NUC121 USB Series Selection Guide
2
* USCI can be set to UART, I C or SPI
Part Number
Flash (KB)
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer/PWM
USCI*
UART
SPI/I2S
I2C
USBD
PWM
ADC (12-Bit)
PDMA
ICP/ISP/IAP
1.8V Power Pin
Package
Connectivity
NUC121ZC2AE
32
8
4.5
22
4
1
1
1
2
1
17
4-ch
5-ch
√
-
QFN 33
NUC121LC2AE
32
8
4.5
38
4
1
1
1
2
1
24
10-ch
5-ch
√
-
LQFP 48
NUC121SC2AE
32
8
4.5
52
4
1
1
1
2
1
24
12-ch
5-ch
√
-
LQFP 64
®
Table 4.1-1 NuMicro NUC121 USB Series Selection Guide
4.1.3
NuMicro® NUC125 USB Series Selection Guide
* USCI can be set to UART, I2C or SPI
Part Number
Flash (KB)
SRAM (KB)
ISP Loader ROM
(KB)
I/O
Timer/PWM
USCI*
UART
SPI/I2S
I2C
USBD
PWM
ADC (12-Bit)
PDMA
ICP/ISP/IAP
1.8V Power Pin
Package
Connectivity
NUC125ZC2AE
32
8
4.5
22
4
1
1
1
2
1
17
4-ch
5-ch
√
√
QFN 33
NUC125LC2AE
32
8
4.5
37
4
1
1
1
2
1
23
9-ch
5-ch
√
√
LQFP 48
NUC125SC2AE
32
8
4.5
51
4
1
1
1
2
1
23
11-ch
5-ch
√
√
LQFP 64
NUC121/125 SERIES DATASHEET
®
Table 4.1-2 NuMicro NUC125 USB Series Selection Guide
Aug. 17, 2018
Page 19 of 148
Rev 1.02
NUC121/125
4.2 Pin Configuration
AVDD
25
PD.1
PF.5
PF.4
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
24
23
22
21
20
19
18
17
NuMicro® NUC121 QFN 33-Pin Diagram
16
PC.0
26
15
PC.1
PD.2
27
14
PC.2
PD.3
28
13
PC.3
PF.0
29
12
USB_D+
PF.1
30
11
USB_D-
nRESET
31
10
USB_VDD33_CAP
NUC121Z
QFN33
33 VSS
3
4
5
6
7
8
PB.4
PB.5
LDO_CAP
VDD
VSS
9
PA.10
2
NUC121/125 SERIES DATASHEET
PA.11
32
1
VSS
Top transparent view
PB.14
4.2.1
USB_VBUS
®
Figure 4.2-1 NuMicro NUC121 QFN 33-Pin Diagram
Aug. 17, 2018
Page 20 of 148
Rev 1.02
NUC121/125
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
24
23
22
21
20
19
18
17
NuMicro® NUC121 QFN 33-Pin Function Diagram
AVDD
25
16
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
26
15
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
27
14
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
28
13
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
TM3 / BPWM1_CH3 / XT_OUT / PF.0
29
12
USB_D+
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
30
11
USB_D-
nRESET
31
10
USB_VDD33_CAP
VSS
32
Top transparent view
NUC121Z
QFN33
33 VSS
1
2
3
4
5
6
7
8
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
LDO_CAP
VDD
VSS
USB_VBUS
NUC121/125 SERIES DATASHEET
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
9
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
4.2.2
®
Figure 4.2-2 NuMicro NUC121 QFN 33-Pin Function Diagram
Aug. 17, 2018
Page 21 of 148
Rev 1.02
NUC121/125
PF.5
PF.4
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
36
35
34
33
32
31
30
29
28
27
26
25
NuMicro® NUC121 LQFP 48-Pin Diagram
AVDD
37
24
PB.9
PD.0
38
23
PB.10
PD.1
39
22
PC.0
PD.2
40
21
PC.1
PD.3
41
20
PC.2
PD.4
42
19
PC.3
PD.5
43
18
PC.4
PF.0
44
17
PC.5
PF.1
45
16
USB_D+
nRESET
46
15
USB_D-
PF.2
47
14
USB_VDD33_CAP
PF.3
48
13
USB_VBUS
7
8
9
PB.5
PB.6
PB.7
VSS
6
PB.4
12
5
PA.10
11
4
PA.11
VDD
3
PB.14
LDO_CAP
2
10
1
NUC121/125 SERIES DATASHEET
VSS
NUC121L
LQFP48
PB.8
4.2.3
®
Figure 4.2-3 NuMicro NUC121 LQFP 48-Pin Diagram
Aug. 17, 2018
Page 22 of 148
Rev 1.02
NUC121/125
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PA.12 / PWM0_CH0 / I2C1_SCL / UART0_RXD
PA.13 / PWM0_CH1 / I2C1_SDA / UART0_TXD
PA.14 / PWM0_CH2 / UART0_nCTS / PWM0_BRAKE0
PA.15 / PWM0_CH3 / SPI_I2SMCLK / CLKO / PWM1_BRAKE1 / UART0_nRTS
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
36
35
34
33
32
31
30
29
28
27
26
25
NuMicro® NUC121 LQFP 48-Pin Function Diagram
AVDD
37
24
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
38
23
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
39
22
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
40
21
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
41
20
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
42
19
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
NUC121L
LQFP48
BPWM1_CH4 / ADC_CH5 / PD.5
43
18
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
44
17
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
45
16
USB_D+
11
12
VSS
9
USCI0_CTL0 / USCI0_DAT1 / BPWM0_CH0 / PB.7
10
8
USCI0_CTL1 / USCI0_DAT0 / BPWM0_CH1 / PB.6
VDD
7
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
LDO_CAP
6
VSS
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
NUC121/125 SERIES DATASHEET
5
USB_VBUS
4
13
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
48
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
USB_VDD33_CAP
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
3
USB_D-
14
2
15
47
1
46
BPWM1_CH1 / ADC_CH8 / TM0 / PB.8
nRESET
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
4.2.4
®
Figure 4.2-4 NuMicro NUC121 LQFP 48-Pin Function Diagram
Aug. 17, 2018
Page 23 of 148
Rev 1.02
NUC121/125
AVDD
PF.5
PF.4
PA.12
PA.13
PA.14
PE.0
PA.15
PC.8
PC.9
PE.1
PC.10
PC.11
PC.12
PC.13
PE.2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NuMicro® NUC121 LQFP 64-Pin Diagram
PD.0
49
32
PB.9
PD.1
50
31
PB.10
PD.2
51
30
PC.0
PD.3
52
29
PC.1
PD.4
53
28
PC.2
PD.5
54
27
PC.3
PB.15
55
26
PC.4
PF.0
56
25
PC.5
PF.1
57
24
PB.3
nRESET
58
23
PB.2
VSS
59
22
PB.1
VDD
60
21
PB.0
PF.2
61
20
USB_D+
PF.3
62
19
USB_D-
VSS
63
18
USB_VDD33_CAP
PB.8
64
17
USB_VBUS
8
9
10
11
12
13
14
15
16
PD.10
PD.11
PB.4
PB.5
PB.6
PB.7
LDO_CAP
VDD
VSS
5
PA.10
7
4
PA.11
PD.9
3
PB.12
6
2
PD.8
1
NUC121/125 SERIES DATASHEET
PB.13
NUC121S
LQFP64
PB.14
4.2.5
®
Figure 4.2-5 NuMicro NUC121 LQFP 64-Pin Diagram
Aug. 17, 2018
Page 24 of 148
Rev 1.02
NUC121/125
AVDD
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PA.12 / PWM0_CH0 / I2C1_SCL / UART0_RXD
PA.13 / PWM0_CH1 / I2C1_SDA / UART0_TXD
PA.14 / PWM0_CH2 / UART0_nCTS / PWM0_BRAKE0
PE.0 / INT0 / CLKO / PWM0_CH3 / TM1_EXT / USCI0_DAT0
PA.15 / PWM0_CH3 / SPI_I2SMCLK / CLKO / PWM1_BRAKE1 / UART0_nRTS
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PE.1 / STADC / CLKO / TM3 / USCI0_DAT1
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
PE.2 / INT1 / TM0_EXT / I2C0_SCL / USCI0_CTL1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NuMicro® NUC121 LQFP 64-Pin Function Diagram
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
49
32
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
50
31
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
51
30
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
52
29
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
53
28
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
BPWM1_CH4 / ADC_CH5 / PD.5
54
27
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
BPWM1_CH5 / TM0_EXT / INT1 / PB.15
55
26
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
56
25
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
57
24
PB.3 / UART0_nCTS / TM3_EXT / PWM1_CH3
nRESET
58
23
PB.2 / UART0_nRTS / TM2_EXT / PWM1_CH2
VSS
59
22
PB.1 / UART0_TXD / PWM1_CH1
VDD
60
21
PB.0 / UART0_RXD / PWM1_CH0
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
61
20
USB_D+
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
62
19
USB_D-
VSS
63
18
USB_VDD33_CAP
BPWM1_CH1 / ADC_CH8 / TM0 / PB.8
64
17
USB_VBUS
14
15
16
LDO_CAP
VDD
VSS
9
BPWM0_CH4 / INT1 / PD.11
13
8
BPWM0_CH5 / CLKO / PD.10
USCI0_CTL0 / USCI0_DAT1 / BPWM0_CH0 / PB.7
7
PWM0_BRAKE1 / PD.9
12
6
USCI0_DAT0 / PD.8
USCI0_CTL1 / USCI0_DAT0 / BPWM0_CH1 / PB.6
5
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
11
4
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
3
USCI0_CTL0 / ADC_CH11 / CLKO / PB.12
10
2
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
1
NUC121/125 SERIES DATASHEET
USCI0_CTL1 / ADC_CH10 / PB.13
NUC121S
LQFP64
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
4.2.6
®
Figure 4.2-6 NuMicro NUC121 LQFP 64-Pin Function Diagram
Aug. 17, 2018
Page 25 of 148
Rev 1.02
NUC121/125
AVDD
25
PD.1
PF.5
PF.4
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
24
23
22
21
20
19
18
17
NuMicro® NUC125 QFN 33-Pin Diagram
16
PC.0
26
15
PC.1
PD.2
27
14
PC.2
PD.3
28
13
PC.3
PF.0
29
12
USB_D+
PF.1
30
11
USB_D-
nRESET
31
10
USB_VDD33_CAP
NUC125Z
QFN33
33 VSS
4
5
6
7
8
PB.4
PB.5
LDO_CAP
VDD
VSS
NUC121/125 SERIES DATASHEET
3
9
PA.10
2
PA.11
32
1
VDDIO
Top transparent view
PB.14
4.2.7
USB_VBUS
VDDIO power domain
®
Figure 4.2-7 NuMicro NUC125 QFN 33-Pin Diagram
Aug. 17, 2018
Page 26 of 148
Rev 1.02
NUC121/125
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
24
23
22
21
20
19
18
17
NuMicro® NUC125 QFN 33-Pin Function Diagram
AVDD
25
16
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
26
15
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
27
14
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
28
13
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
TM3 / BPWM1_CH3 / XT_OUT / PF.0
29
12
USB_D+
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
30
11
USB_D-
nRESET
31
10
USB_VDD33_CAP
VDDIO
32
Top transparent view
NUC125Z
QFN33
33 VSS
1
2
3
4
5
6
7
8
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
LDO_CAP
VDD
VSS
USB_VBUS
NUC121/125 SERIES DATASHEET
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
9
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
4.2.8
VDDIO power domain
®
Figure 4.2-8 NuMicro NUC125 QFN 33-Pin Function Diagram
Aug. 17, 2018
Page 27 of 148
Rev 1.02
NUC121/125
PF.5
PF.4
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
36
35
34
33
32
31
30
29
28
27
26
25
NuMicro® NUC125 LQFP 48-Pin Diagram
AVDD
37
24
PB.9
PD.0
38
23
PB.10
PD.1
39
22
PC.0
PD.2
40
21
PC.1
PD.3
41
20
PC.2
PD.4
42
19
PC.3
PD.5
43
18
PC.4
PF.0
44
17
PC.5
NUC125L
LQFP48
10
11
12
VDD
VSS
9
8
PB.6
PB.7
7
PB.5
LDO_CAP
6
NUC121/125 SERIES DATASHEET
5
USB_VBUS
PB.4
USB_VDD33_CAP
13
PA.10
14
48
4
47
PF.3
3
PF.2
PA.11
USB_D-
PB.14
USB_D+
15
2
16
46
1
45
VSS
PF.1
nRESET
VDDIO
4.2.9
VDDIO power domain
®
Figure 4.2-9 NuMicro NUC125 LQFP 48-Pin Diagram
Aug. 17, 2018
Page 28 of 148
Rev 1.02
NUC121/125
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PA.12 / PWM0_CH0 / I2C1_SCL / UART0_RXD
PA.13 / PWM0_CH1 / I2C1_SDA / UART0_TXD
PA.14 / PWM0_CH2 / UART0_nCTS / PWM0_BRAKE0
PA.15 / PWM0_CH3 / SPI_I2SMCLK / CLKO / PWM1_BRAKE1 / UART0_nRTS
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
36
35
34
33
32
31
30
29
28
27
26
25
4.2.10 NuMicro® NUC125 LQFP 48-Pin Function Diagram
AVDD
37
24
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
38
23
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
39
22
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
40
21
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
41
20
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
42
19
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
NUC125L
LQFP48
BPWM1_CH4 / ADC_CH5 / PD.5
43
18
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
44
17
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
45
16
USB_D+
12
9
USCI0_CTL0 / USCI0_DAT1 / BPWM0_CH0 / PB.7
VSS
8
USCI0_CTL1 / USCI0_DAT0 / BPWM0_CH1 / PB.6
11
7
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
10
6
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
VDD
5
LDO_CAP
4
NUC121/125 SERIES DATASHEET
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
USB_VBUS
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
13
3
48
2
USB_VDD33_CAP
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
1
USB_D-
14
VSS
15
47
VDDIO
46
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
nRESET
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
VDDIO power domain
®
Figure 4.2-10 NuMicro NUC125 LQFP 48-Pin Function Diagram
Aug. 17, 2018
Page 29 of 148
Rev 1.02
NUC121/125
AVDD
PF.5
PF.4
PA.12
PA.13
PA.14
PE.0
PA.15
PC.8
PC.9
PE.1
PC.10
PC.11
PC.12
PC.13
PE.2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4.2.11 NuMicro® NUC125 LQFP 64-Pin Diagram
PD.0
49
32
PB.9
PD.1
50
31
PB.10
PD.2
51
30
PC.0
PD.3
52
29
PC.1
PD.4
53
28
PC.2
PD.5
54
27
PC.3
PB.15
55
26
PC.4
PF.0
56
25
PC.5
PF.1
57
24
PB.3
nRESET
58
23
PB.2
VSS
59
22
PB.1
VDD
60
21
PB.0
PF.2
61
20
USB_D+
PF.3
62
19
USB_D-
VSS
63
18
USB_VDD33_CAP
VDDIO
64
17
USB_VBUS
8
9
10
11
12
13
14
15
16
PD.10
PD.11
PB.4
PB.5
PB.6
PB.7
LDO_CAP
VDD
VSS
5
PA.10
7
4
PA.11
PD.9
3
PB.12
6
2
PD.8
1
PB.13
NUC121/125 SERIES DATASHEET
PB.14
NUC125S
LQFP64
VDDIO power domain
®
Figure 4.2-11 NuMicro NUC125 LQFP 64-Pin Diagram
Aug. 17, 2018
Page 30 of 148
Rev 1.02
NUC121/125
AVDD
PF.5 / ICE_CLK / I2C0_SCL / UART0_RXD
PF.4 / ICE_DAT / I2C0_SDA / UART0_TXD / PWM0_CH3
PA.12 / PWM0_CH0 / I2C1_SCL / UART0_RXD
PA.13 / PWM0_CH1 / I2C1_SDA / UART0_TXD
PA.14 / PWM0_CH2 / UART0_nCTS / PWM0_BRAKE0
PE.0 / INT0 / CLKO / PWM0_CH3 / TM1_EXT / USCI0_DAT0
PA.15 / PWM0_CH3 / SPI_I2SMCLK / CLKO / PWM1_BRAKE1 / UART0_nRTS
PC.8 / STADC / SPI0_SS / PWM0_CH4 / PWM1_BRAKE0 / USCI0_CTL0
PC.9 / SPI0_CLK / PWM0_CH5 / PWM0_BRAKE1 / USCI0_CLK
PE.1 / STADC / CLKO / TM3 / USCI0_DAT1
PC.10 / SPI0_MISO / PWM0_CH0 / USCI0_DAT1
PC.11 / SPI0_MOSI / PWM0_CH1 / TM1 / I2C0_SDA / USCI0_DAT0
PC.12 / PWM0_CH2 / SPI0_I2SMCLK / CLKO / INT0 / I2C0_SCL / USCI0_CTL1
PC.13 / PWM0_CH3 / CLKO / INT0 / I2C0_SDA
PE.2 / INT1 / TM0_EXT / I2C0_SCL / USCI0_CTL1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4.2.12 NuMicro® NUC125 LQFP 64-Pin Function Diagram
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
49
32
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
50
31
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
51
30
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
52
29
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
53
28
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
BPWM1_CH4 / ADC_CH5 / PD.5
54
27
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
BPWM1_CH5 / TM0_EXT / INT1 / PB.15
55
26
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
56
25
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
57
24
PB.3 / UART0_nCTS / TM3_EXT / PWM1_CH3
nRESET
58
23
PB.2 / UART0_nRTS / TM2_EXT / PWM1_CH2
VSS
59
22
PB.1 / UART0_TXD / PWM1_CH1
VDD
60
21
PB.0 / UART0_RXD / PWM1_CH0
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
61
20
USB_D+
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
62
19
USB_D-
VSS
63
18
USB_VDD33_CAP
VDDIO
64
17
USB_VBUS
14
15
16
LDO_CAP
VDD
VSS
9
BPWM0_CH4 / INT1 / PD.11
13
8
BPWM0_CH5 / CLKO / PD.10
USCI0_CTL0 / USCI0_DAT1 / BPWM0_CH0 / PB.7
7
PWM0_BRAKE1 / PD.9
12
6
USCI0_DAT0 / PD.8
USCI0_CTL1 / USCI0_DAT0 / BPWM0_CH1 / PB.6
5
USCI0_DAT1 / PWM0_BRAKE0 / BPWM0_CH4 / I2C1_SDA / PA.10
11
4
USCI0_DAT0 / USCI0_CLK / TM0 / BPWM0_CH5 / I2C1_SCL / PA.11
USCI0_DAT1 / USCI0_CLK / TM3 / BPWM0_CH2 / PB.5
3
USCI0_CTL0 / ADC_CH11 / CLKO / PB.12
10
2
USCI0_DAT0 / USCI0_CTL0 / TM2_EXT / BPWM0_CH3 / PB.4
1
USCI0_CTL1 / ADC_CH10 / PB.13
NUC121/125 SERIES DATASHEET
VDDIO power domain
SPI0_SS / BPWM1_CH0 / ADC_CH9 / UART0_nRTS / INT0 / PB.14
NUC125S
LQFP64
®
Figure 4.2-12 NuMicro NUC125 LQFP 64-Pin Function Diagram
Aug. 17, 2018
Page 31 of 148
Rev 1.02
NUC121/125
4.3 Pin Description
4.3.1
NUC121 USB Series QFN33 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
1
2
3
Pin Name
NUC121/125 SERIES DATASHEET
Type
MFP*
Description
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
A
MFP0
LDO output pin.
PWM0_BRAKE0
4
TM2_EXT
5
6
LDO_CAP
Aug. 17, 2018
Page 32 of 148
Rev 1.02
NUC121/125
Pin No.
MFP*
Description
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
8
VSS
A
MFP0
Ground pin for digital circuit.
9
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
10
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
11
USB_D-
I
MFP0
USB differential signal D-.
12
USB_D+
I
MFP0
USB differential signal D+.
13
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
14
15
16
17
Aug. 17, 2018
Page 33 of 148
NUC121/125 SERIES DATASHEET
Type
7
Pin Name
Rev 1.02
NUC121/125
Pin No.
18
19
20
21
NUC121/125 SERIES DATASHEET
Pin Name
Type
MFP*
Description
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_BRAKE1
22
STADC
PWM1_BRAKE0
23
Aug. 17, 2018
Page 34 of 148
Rev 1.02
NUC121/125
Pin No.
MFP*
Description
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
PF.5
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
25
AVDD
A
MFP0
Power supply for internal analog circuit.
26
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PF.0
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
I
MFP5
Timer1 external counter input
27
ADC_CH2
28
29
30
XT_IN
BPWM1_CH2
TM1_EXT
Aug. 17, 2018
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NUC121/125 SERIES DATASHEET
Type
24
Pin Name
NUC121/125
Pin No.
Type
MFP*
Description
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
32
VSS
A
MFP0
Ground pin for digital circuit.
33
VSS
A
MFP0
Ground pin for digital circuit.
31
Pin Name
Table 4.3-1 NUC121 USB Series QFN33 Pin Description
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 36 of 148
Rev 1.02
NUC121/125
4.3.2
NUC121 USB Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0..
Pin No.
Pin Name
Type
MFP*
Description
A
MFP0
Ground pin for digital circuit.
VSS
2
PB.8
I/O
MFP0
General purpose digital I/O pin.
TM0
I/O
MFP1
Timer0event counter input / toggle output
A
MFP3
ADC channel 8 analog input.
BPWM1_CH1
I/O
MFP4
BPWM1 channel 1 output/capture input.
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
ADC_CH8
3
4
5
PWM0_BRAKE0
6
TM2_EXT
7
Aug. 17, 2018
Page 37 of 148
NUC121/125 SERIES DATASHEET
1
Rev 1.02
NUC121/125
Pin No.
Type
MFP*
Description
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PB.6
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH1
I/O
MFP4
BPWM0 channel 1 output/capture input.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PB.7
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH0
I/O
MFP4
BPWM0 channel 0 output/capture input.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin.
LDO_CAP
A
MFP0
LDO output pin.
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
12
VSS
A
MFP0
Ground pin for digital circuit.
13
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
14
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
15
USB_D-
I
MFP0
USB differential signal D-.
16
USB_D+
I
MFP0
USB differential signal D+.
17
PC.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
PWM1_CH5
I/O
MFP4
PWM1 channel5 output/capture input.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.4
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM1_CH4
I/O
MFP4
PWM1 channel4 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
8
9
10
11
NUC121/125 SERIES DATASHEET
18
19
Pin Name
Aug. 17, 2018
Page 38 of 148
Rev 1.02
NUC121/125
Pin No.
20
21
22
23
25
26
Type
MFP*
Description
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PB.10
I/O
MFP0
General purpose digital I/O pin.
TM2
I/O
MFP1
Timer2 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
TM1
I/O
MFP1
Timer1 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
Aug. 17, 2018
Page 39 of 148
NUC121/125 SERIES DATASHEET
24
Pin Name
Rev 1.02
NUC121/125
Pin No.
27
28
29
Pin Name
Type
MFP*
Description
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP1
PWM0 channel3 output/capture input.
SPI_I2SMCLK
O
MFP2
I2S0 master clock output pin.
CLKO
O
MFP3
Clock Out
PWM1_BRAKE1
I
MFP4
Brake input pin 1 of PWM1.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
PA.14
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP1
PWM0 channel2 output/capture input.
PWM0_BRAKE1
NUC121/125 SERIES DATASHEET
30
STADC
PWM1_BRAKE0
31
32
Aug. 17, 2018
Page 40 of 148
Rev 1.02
NUC121/125
Pin No.
MFP*
Description
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
PWM0_BRAKE0
I
MFP4
Brake input pin 0 of PWM0.
PA.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH1
I/O
MFP1
PWM0 channel1 output/capture input.
I2C1_SDA
I/O
MFP2
I2C1 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PA.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH0
I/O
MFP1
PWM0 channel0 output/capture input.
I2C1_SCL
I/O
MFP2
I2C1 clock pin.
I
MFP3
Data receiver input pin for UART0.
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
PF.5
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
37
AVDD
A
MFP0
Power supply for internal analog circuit.
38
PD.0
I/O
MFP0
General purpose digital I/O pin.
ADC_CH0
A
MFP3
ADC channel 0 analog input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
34
UART0_RXD
35
36
39
40
ADC_CH2
Aug. 17, 2018
Page 41 of 148
NUC121/125 SERIES DATASHEET
Type
33
Pin Name
Rev 1.02
NUC121/125
Pin No.
41
42
Pin Name
Type
MFP*
Description
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 4 analog input.
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.5
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 5 analog input.
BPWM1_CH4
I/O
MFP4
BPWM1 channel 4 output/capture input.
PF.0
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
TM1_EXT
I
MFP5
Timer1 external counter input
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PF.2
I/O
MFP0
General purpose digital I/O pin.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
ADC_CH6
A
MFP3
ADC channel 6 analog input.
I/O
MFP4
BPWM1 channel 3 output/capture input.
ADC_CH4
43
ADC_CH5
NUC121/125 SERIES DATASHEET
44
45
XT_IN
BPWM1_CH2
46
47
BPWM1_CH3
Aug. 17, 2018
Page 42 of 148
Rev 1.02
NUC121/125
Pin No.
48
Pin Name
Type
MFP*
Description
PF.3
I/O
MFP0
General purpose digital I/O pin.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
ADC_CH7
A
MFP3
ADC channel 7 analog input.
I/O
MFP4
BPWM1 channel 2 output/capture input.
BPWM1_CH2
Table 4.3-2 NUC121 USB Series LQFP48 Pin Description
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 43 of 148
Rev 1.02
NUC121/125
4.3.3
NUC121 USB Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
1
2
Pin Name
Type
MFP*
Description
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PB.13
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 10 analog input.
USCI0_CTL1
I/O
MFP6
USCI0 CTL1 pin.
PB.12
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP2
Clock Out
ADC_CH11
A
MFP3
ADC channel 11 analog input.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
I
MFP5
Brake input pin 1 of PWM0.
I/O
MFP0
General purpose digital I/O pin.
ADC_CH10
3
4
NUC121/125 SERIES DATASHEET
5
PWM0_BRAKE0
6
7
PWM0_BRAKE1
8
PD.10
Aug. 17, 2018
Page 44 of 148
Rev 1.02
NUC121/125
Pin No.
MFP*
Description
CLKO
O
MFP1
Clock Out
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
PD.11
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External interrupt1 input pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PB.6
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH1
I/O
MFP4
BPWM0 channel 1 output/capture input.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PB.7
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH0
I/O
MFP4
BPWM0 channel 0 output/capture input.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin.
LDO_CAP
A
MFP0
LDO output pin.
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
16
VSS
A
MFP0
Ground pin for digital circuit.
17
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
18
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
19
USB_D-
I
MFP0
USB differential signal D-.
20
USB_D+
I
MFP0
USB differential signal D+.
21
PB.0
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP1
Data receiver input pin for UART0.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
INT1
10
TM2_EXT
11
12
13
14
15
Aug. 17, 2018
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Rev 1.02
NUC121/125 SERIES DATASHEET
Type
9
Pin Name
NUC121/125
Pin No.
22
23
24
25
26
NUC121/125 SERIES DATASHEET
27
28
29
Pin Name
Type
MFP*
Description
PB.1
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP1
Data transmitter output pin for UART0.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
PB.2
I/O
MFP0
General purpose digital I/O pin.
UART0_nRTS
O
MFP1
Request to Send output pin for UART0.
TM2_EXT
I
MFP2
Timer2 external counter input
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
PB.3
I/O
MFP0
General purpose digital I/O pin.
UART0_nCTS
I
MFP1
Clear to Send input pin for UART0.
TM3_EXT
I
MFP2
Timer3 external counter input
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
PC.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
PWM1_CH5
I/O
MFP4
PWM1 channel5 output/capture input.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.4
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM1_CH4
I/O
MFP4
PWM1 channel4 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
Aug. 17, 2018
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Rev 1.02
NUC121/125
Pin No.
30
31
32
33
35
Type
MFP*
Description
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PB.10
I/O
MFP0
General purpose digital I/O pin.
TM2
I/O
MFP1
Timer2 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
TM1
I/O
MFP1
Timer1 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
PE.2
I/O
MFP0
General purpose digital I/O pin.
INT1
I
MFP1
External interrupt1 input pin.
TM0_EXT
I
MFP5
Timer0 external counter input
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
Aug. 17, 2018
Page 47 of 148
NUC121/125 SERIES DATASHEET
34
Pin Name
Rev 1.02
NUC121/125
Pin No.
36
37
38
39
NUC121/125 SERIES DATASHEET
Pin Name
Type
MFP*
Description
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PE.1
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP2
ADC external trigger input.
CLKO
O
MFP3
Clock Out
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP1
PWM0 channel3 output/capture input.
SPI_I2SMCLK
O
MFP2
I2S0 master clock output pin.
CLKO
O
MFP3
Clock Out
PWM1_BRAKE1
I
MFP4
Brake input pin 1 of PWM1.
PWM0_BRAKE1
40
STADC
PWM1_BRAKE0
41
Aug. 17, 2018
Page 48 of 148
Rev 1.02
NUC121/125
Pin No.
MFP*
Description
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
PE.0
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
CLKO
O
MFP3
Clock Out
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
I
MFP5
Timer1 external counter input
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.14
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP1
PWM0 channel2 output/capture input.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
PWM0_BRAKE0
I
MFP4
Brake input pin 0 of PWM0.
PA.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH1
I/O
MFP1
PWM0 channel1 output/capture input.
I2C1_SDA
I/O
MFP2
I2C1 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PA.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH0
I/O
MFP1
PWM0 channel0 output/capture input.
I2C1_SCL
I/O
MFP2
I2C1 clock pin.
I
MFP3
Data receiver input pin for UART0.
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
PF.5
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
48
AVDD
A
MFP0
Power supply for internal analog circuit.
49
PD.0
I/O
MFP0
General purpose digital I/O pin.
ADC_CH0
A
MFP3
ADC channel 0 analog input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
TM1_EXT
43
44
45
UART0_RXD
46
47
Aug. 17, 2018
Page 49 of 148
NUC121/125 SERIES DATASHEET
Type
42
Pin Name
Rev 1.02
NUC121/125
Pin No.
50
51
Pin Name
Type
MFP*
Description
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 4 analog input.
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.5
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 5 analog input.
BPWM1_CH4
I/O
MFP4
BPWM1 channel 4 output/capture input.
PB.15
I/O
MFP0
General purpose digital I/O pin.
INT1
I
MFP1
External interrupt1 input pin.
TM0_EXT
I
MFP2
Timer0 external counter input
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
PF.0
I/O
MFP0
General purpose digital I/O pin.
ADC_CH2
52
NUC121/125 SERIES DATASHEET
53
ADC_CH4
54
ADC_CH5
55
56
Aug. 17, 2018
Page 50 of 148
Rev 1.02
NUC121/125
Pin No.
57
Pin Name
MFP*
Description
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
TM1_EXT
I
MFP5
Timer1 external counter input
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
VSS
A
MFP0
Ground pin for digital circuit.
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
PF.2
I/O
MFP0
General purpose digital I/O pin.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
ADC_CH6
A
MFP3
ADC channel 6 analog input.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
PF.3
I/O
MFP0
General purpose digital I/O pin.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
ADC_CH7
A
MFP3
ADC channel 7 analog input.
I/O
MFP4
BPWM1 channel 2 output/capture input.
A
MFP0
Ground pin for digital circuit.
XT_IN
BPWM1_CH2
58
59
60
61
62
BPWM1_CH2
63
VSS
64
PB.8
I/O
MFP0
General purpose digital I/O pin.
TM0
I/O
MFP1
Timer0event counter input / toggle output
A
MFP3
ADC channel 8 analog input.
I/O
MFP4
BPWM1 channel 1 output/capture input.
ADC_CH8
BPWM1_CH1
NUC121/125 SERIES DATASHEET
Type
Table 4.3-3 NUC121 USB Series LQFP64 Pin Description
Aug. 17, 2018
Page 51 of 148
Rev 1.02
NUC121/125
4.3.4
NUC125 USB Series QFN33 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
Type
MFP*
Description
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
1
2
3
NUC121/125 SERIES DATASHEET
PWM0_BRAKE0
4
5
TM2_EXT
6
LDO_CAP
A
MFP0
LDO output pin.
7
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
Aug. 17, 2018
Page 52 of 148
Rev 1.02
NUC121/125
Pin No.
Pin Name
Type
MFP*
Description
8
VSS
A
MFP0
Ground pin for digital circuit.
9
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
10
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
11
USB_D-
I
MFP0
USB differential signal D-.
12
USB_D+
I
MFP0
USB differential signal D+.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I/O
MFP6
I2C0 data input/output pin.
13
14
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16
17
I2C0_SDA
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Pin No.
18
Pin Name
Type
MFP*
Description
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
19
20
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PWM0_BRAKE1
STADC
22
PWM1_BRAKE0
23
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Pin No.
Pin Name
Type
MFP*
Description
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
AVDD
A
MFP0
Power supply for internal analog circuit.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PF.0
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
TM1_EXT
I
MFP5
Timer1 external counter input
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PF.5
24
25
26
ADC_CH2
27
29
XT_IN
30
BPWM1_CH2
31
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Pin No.
Pin Name
Type
MFP*
Description
32
VDDIO
A
MFP0
Power supply for PB.14, PA.11, PA.10, PB.4 and PB.5.
33
VSS
A
MFP0
Ground pin for digital circuit.
Table 4.3-4 NUC125 USB Series QFN33 Pin Description
NUC121/125 SERIES DATASHEET
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4.3.5
NUC125 USB Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0..
Pin No.
Pin Name
Type
MFP*
Description
1
VSS
A
MFP0
Ground pin for digital circuit.
2
VDDIO
A
MFP0
Power supply for PB.14, PA.11, PA.10, PB.4, PB.5, PB.6
and PB.7.
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
3
4
PWM0_BRAKE0
6
TM2_EXT
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7
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Pin No.
Pin Name
Type
MFP*
Description
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PB.6
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH1
I/O
MFP4
BPWM0 channel 1 output/capture input.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PB.7
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH0
I/O
MFP4
BPWM0 channel 0 output/capture input.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin.
8
9
10
LDO_CAP
A
MFP0
LDO output pin.
11
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
12
VSS
A
MFP0
Ground pin for digital circuit.
13
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
14
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
15
USB_D-
I
MFP0
USB differential signal D-.
16
USB_D+
I
MFP0
USB differential signal D+.
PC.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
PWM1_CH5
I/O
MFP4
PWM1 channel5 output/capture input.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.4
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM1_CH4
I/O
MFP4
PWM1 channel4 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
17
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19
20
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Pin No.
21
Pin Name
Type
MFP*
Description
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PB.10
I/O
MFP0
General purpose digital I/O pin.
TM2
I/O
MFP1
Timer2 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
TM1
I/O
MFP1
Timer1 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
22
23
NUC121/125 SERIES DATASHEET
24
25
26
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Pin No.
Pin Name
Type
MFP*
Description
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP1
PWM0 channel3 output/capture input.
SPI_I2SMCLK
O
MFP2
I2S0 master clock output pin.
CLKO
O
MFP3
Clock Out
PWM1_BRAKE1
I
MFP4
Brake input pin 1 of PWM1.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
PA.14
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP1
PWM0 channel2 output/capture input.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
PWM0_BRAKE0
I
MFP4
Brake input pin 0 of PWM0.
27
28
29
PWM0_BRAKE1
STADC
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PWM1_BRAKE0
31
32
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Pin No.
Pin Name
MFP*
Description
PA.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH1
I/O
MFP1
PWM0 channel1 output/capture input.
I2C1_SDA
I/O
MFP2
I2C1 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PA.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH0
I/O
MFP1
PWM0 channel0 output/capture input.
I2C1_SCL
I/O
MFP2
I2C1 clock pin.
I
MFP3
Data receiver input pin for UART0.
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
PF.5
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
AVDD
A
MFP0
Power supply for internal analog circuit.
PD.0
I/O
MFP0
General purpose digital I/O pin.
ADC_CH0
A
MFP3
ADC channel 0 analog input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
33
34
UART0_RXD
35
36
37
38
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ADC_CH2
40
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Pin No.
Pin Name
Type
MFP*
Description
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 4 analog input.
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.5
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 5 analog input.
BPWM1_CH4
I/O
MFP4
BPWM1 channel 4 output/capture input.
PF.0
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
TM1_EXT
I
MFP5
Timer1 external counter input
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PF.2
I/O
MFP0
General purpose digital I/O pin.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
ADC_CH6
A
MFP3
ADC channel 6 analog input.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
PF.3
I/O
MFP0
General purpose digital I/O pin.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
41
ADC_CH4
42
43
ADC_CH5
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44
XT_IN
45
BPWM1_CH2
46
47
48
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Pin No.
Pin Name
Type
MFP*
Description
ADC_CH7
A
MFP3
ADC channel 7 analog input.
I/O
MFP4
BPWM1 channel 2 output/capture input.
BPWM1_CH2
Table 4.3-5 NUC125 USB Series LQFP48 Pin Description
NUC121/125 SERIES DATASHEET
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Rev 1.02
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4.3.6
NUC125 USB Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
Type
MFP*
Description
PB.14
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
UART0_nRTS
O
MFP2
Request to Send output pin for UART0.
ADC_CH9
A
MFP3
ADC channel 9 analog input.
BPWM1_CH0
I/O
MFP4
BPWM1 channel 0 output/capture input.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PB.13
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 10 analog input.
USCI0_CTL1
I/O
MFP6
USCI0 CTL1 pin.
PB.12
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP2
Clock Out
ADC_CH11
A
MFP3
ADC channel 11 analog input.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MFP1
I2C1 clock pin.
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
TM0
I/O
MFP5
Timer0event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
I
MFP5
Brake input pin 0 of PWM0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
I
MFP5
Brake input pin 1 of PWM0.
I/O
MFP0
General purpose digital I/O pin.
1
2
ADC_CH10
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PWM0_BRAKE0
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PWM0_BRAKE1
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PD.10
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Pin No.
9
10
11
Pin Name
Type
MFP*
Description
CLKO
O
MFP1
Clock Out
BPWM0_CH5
I/O
MFP4
BPWM0 channel 5 output/capture input.
PD.11
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External interrupt1 input pin.
BPWM0_CH4
I/O
MFP4
BPWM0 channel 4 output/capture input.
PB.4
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH3
I/O
MFP4
BPWM0 channel 3 output/capture input.
I
MFP5
Timer2 external counter input
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH2
I/O
MFP4
BPWM0 channel 2 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PB.6
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH1
I/O
MFP4
BPWM0 channel 1 output/capture input.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PB.7
I/O
MFP0
General purpose digital I/O pin.
BPWM0_CH0
I/O
MFP4
BPWM0 channel 0 output/capture input.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin.
INT1
TM2_EXT
12
14
LDO_CAP
A
MFP0
LDO output pin.
15
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
16
VSS
A
MFP0
Ground pin for digital circuit.
17
USB_VBUS
A
MFP0
Power supply from USB host or HUB.
18
USB_VDD33_CAP
A
MFP0
Internal power regulator output 3.3V decoupling pin.
19
USB_D-
I
MFP0
USB differential signal D-.
20
USB_D+
I
MFP0
USB differential signal D+.
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP1
Data receiver input pin for UART0.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
PB.0
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Pin No.
22
Pin Name
Type
MFP*
Description
PB.1
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP1
Data transmitter output pin for UART0.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
PB.2
I/O
MFP0
General purpose digital I/O pin.
UART0_nRTS
O
MFP1
Request to Send output pin for UART0.
TM2_EXT
I
MFP2
Timer2 external counter input
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
PB.3
I/O
MFP0
General purpose digital I/O pin.
UART0_nCTS
I
MFP1
Clear to Send input pin for UART0.
TM3_EXT
I
MFP2
Timer3 external counter input
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
PC.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP2
Data transmitter output pin for UART0.
PWM1_CH5
I/O
MFP4
PWM1 channel5 output/capture input.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.4
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP2
Data receiver input pin for UART0.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM1_CH4
I/O
MFP4
PWM1 channel4 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP1
SPI0 MOSI (Master Out, Slave In) pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
PWM1_CH3
I/O
MFP4
PWM1 channel3 output/capture input.
UART0_nRTS
O
MFP6
Request to Send output pin for UART0.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP1
SPI0 MISO (Master In, Slave Out) pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
PWM1_CH2
I/O
MFP4
PWM1 channel2 output/capture input.
UART0_nCTS
I
MFP6
Clear to Send input pin for UART0.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
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Pin No.
Pin Name
Type
MFP*
Description
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
PWM1_CH1
I/O
MFP4
PWM1 channel1 output/capture input.
UART0_TXD
O
MFP6
Data transmitter output pin for UART0.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PC.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
MFP1
SPI0 slave select pin.
PWM1_CH0
I/O
MFP4
PWM1 channel0 output/capture input.
TM2
I/O
MFP5
Timer2 event counter input / toggle output
UART0_RXD
I
MFP6
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
PB.10
I/O
MFP0
General purpose digital I/O pin.
TM2
I/O
MFP1
Timer2 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
TM1
I/O
MFP1
Timer1 event counter input / toggle output
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
PE.2
I/O
MFP0
General purpose digital I/O pin.
INT1
I
MFP1
External interrupt1 input pin.
TM0_EXT
I
MFP5
Timer0 external counter input
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
CLKO
O
MFP3
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
SPI0_I2SMCLK
O
MFP3
I2S0 master clock output pin.
CLKO
O
MFP4
Clock Out
INT0
I
MFP5
External interrupt0 input pin.
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34
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Pin No.
Pin Name
Type
MFP*
Description
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
USCI0_CTL1
I/O
MFP7
USCI0 CTL1 pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
MFP3
SPI0 MOSI (Master Out, Slave In) pin.
PWM0_CH1
I/O
MFP4
PWM0 channel1 output/capture input.
TM1
I/O
MFP5
Timer1 event counter input / toggle output
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
MFP3
SPI0 MISO (Master In, Slave Out) pin.
PWM0_CH0
I/O
MFP4
PWM0 channel0 output/capture input.
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PE.1
I/O
MFP0
General purpose digital I/O pin.
STADC
I
MFP2
ADC external trigger input.
CLKO
O
MFP3
Clock Out
TM3
I/O
MFP5
Timer3 event counter input / toggle output
USCI0_DAT1
I/O
MFP7
USCI0 DAT1 pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP3
SPI0 serial clock pin.
PWM0_CH5
I/O
MFP4
PWM0 channel5 output/capture input.
I
MFP5
Brake input pin 1 of PWM0.
USCI0_CLK
I/O
MFP7
USCI0 clock pin
PC.8
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
ADC external trigger input.
SPI0_SS
I/O
MFP3
SPI0 slave select pin.
PWM0_CH4
I/O
MFP4
PWM0 channel4 output/capture input.
I
MFP5
Brake input pin 0 of PWM1.
USCI0_CTL0
I/O
MFP7
USCI0 CTL0 pin
PA.15
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP1
PWM0 channel3 output/capture input.
SPI_I2SMCLK
O
MFP2
I2S0 master clock output pin.
CLKO
O
MFP3
Clock Out
PWM1_BRAKE1
I
MFP4
Brake input pin 1 of PWM1.
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37
38
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PWM0_BRAKE1
STADC
40
PWM1_BRAKE0
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Pin No.
Pin Name
Type
MFP*
Description
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
PE.0
I/O
MFP0
General purpose digital I/O pin.
INT0
I
MFP1
External interrupt0 input pin.
CLKO
O
MFP3
Clock Out
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
I
MFP5
Timer1 external counter input
USCI0_DAT0
I/O
MFP7
USCI0 DAT0 pin.
PA.14
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP1
PWM0 channel2 output/capture input.
UART0_nCTS
I
MFP3
Clear to Send input pin for UART0.
PWM0_BRAKE0
I
MFP4
Brake input pin 0 of PWM0.
PA.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH1
I/O
MFP1
PWM0 channel1 output/capture input.
I2C1_SDA
I/O
MFP2
I2C1 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PA.12
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH0
I/O
MFP1
PWM0 channel0 output/capture input.
I2C1_SCL
I/O
MFP2
I2C1 clock pin.
I
MFP3
Data receiver input pin for UART0.
PF.4
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
UART0_TXD
O
MFP3
Data transmitter output pin for UART0.
PWM0_CH3
I/O
MFP4
PWM0 channel3 output/capture input.
PF.5
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
UART0_RXD
I
MFP3
Data receiver input pin for UART0.
AVDD
A
MFP0
Power supply for internal analog circuit.
PD.0
I/O
MFP0
General purpose digital I/O pin.
ADC_CH0
A
MFP3
ADC channel 0 analog input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
42
TM1_EXT
43
44
45
UART0_RXD
47
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Pin No.
Pin Name
Type
MFP*
Description
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ADC_CH1
A
MFP3
ADC channel 1 analog input.
TM0_EXT
I
MFP4
Timer0 external counter input
UART0_RXD
I
MFP5
Data receiver input pin for UART0.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
SPI0_CLK
I/O
MFP7
SPI0 serial clock pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
A
MFP3
ADC channel 2 analog input.
TM3
I/O
MFP4
Timer3 event counter input / toggle output
UART0_TXD
O
MFP5
Data transmitter output pin for UART0.
USCI0_DAT1
I/O
MFP6
USCI0 DAT1 pin.
SPI0_MISO
I/O
MFP7
SPI0 MISO (Master In, Slave Out) pin.
PD.3
I/O
MFP0
General purpose digital I/O pin.
ADC_CH3
A
MFP3
ADC channel 3 analog input.
TM1_EXT
I
MFP4
Timer1 external counter input
UART0_nCTS
I
MFP5
Clear to Send input pin for UART0.
USCI0_DAT0
I/O
MFP6
USCI0 DAT0 pin.
SPI0_MOSI
I/O
MFP7
SPI0 MOSI (Master Out, Slave In) pin.
PD.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 4 analog input.
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
UART0_nRTS
O
MFP5
Request to Send output pin for UART0.
USCI0_CTL0
I/O
MFP6
USCI0 CTL0 pin.
SPI0_SS
I/O
MFP7
SPI0 slave select pin.
PD.5
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC channel 5 analog input.
BPWM1_CH4
I/O
MFP4
BPWM1 channel 4 output/capture input.
PB.15
I/O
MFP0
General purpose digital I/O pin.
INT1
I
MFP1
External interrupt1 input pin.
TM0_EXT
I
MFP2
Timer0 external counter input
BPWM1_CH5
I/O
MFP4
BPWM1 channel 5 output/capture input.
PF.0
I/O
MFP0
General purpose digital I/O pin.
50
ADC_CH2
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54
ADC_CH5
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Pin No.
Pin Name
Type
MFP*
Description
XT_OUT
O
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
TM3
I/O
MFP5
Timer3 event counter input / toggle output
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
I/O
MFP4
BPWM1 channel 2 output/capture input.
TM1_EXT
I
MFP5
Timer1 external counter input
58
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
59
VSS
A
MFP0
Ground pin for digital circuit.
60
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
PF.2
I/O
MFP0
General purpose digital I/O pin.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
ADC_CH6
A
MFP3
ADC channel 6 analog input.
BPWM1_CH3
I/O
MFP4
BPWM1 channel 3 output/capture input.
PF.3
I/O
MFP0
General purpose digital I/O pin.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
ADC_CH7
A
MFP3
ADC channel 7 analog input.
I/O
MFP4
BPWM1 channel 2 output/capture input.
XT_IN
57
BPWM1_CH2
61
62
63
VSS
A
MFP0
Ground pin for digital circuit.
64
VDDIO
A
MFP0
Power supply for PB.14, PB.13, PB.12, PA.11, PA.10,
PD.8, PD.9, PD.10, PD.11, PB.4, PB.5, PB.6 and PB.7.
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4.3.7
GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Group
Pin Name
GPIO
MFP*
Type
Description
ADC0_CH0
PD.0
MFP3
A
ADC0 analog input.
ADC0_CH1
PD.1
MFP3
A
ADC1 analog input.
ADC0_CH2
PD.2
MFP3
A
ADC2 analog input.
ADC0_CH3
PD.3
MFP3
A
ADC3 analog input.
ADC0_CH4
PD.4
MFP2
A
ADC4 analog input.
ADC0_CH5
PD.5
MFP2
A
ADC5 analog input.
ADC0_CH6
PF.2
MFP3
A
ADC6 analog input.
ADC0_CH7
PF.3
MFP3
A
ADC7 analog input.
ADC0_CH8
PB.8
MFP3
A
ADC8 analog input.
ADC0_CH9
PB.14
MFP3
A
ADC9 analog input.
ADC0_CH10
PB.13
MFP3
A
ADC10 analog input.
ADC0_CH11
PB.12
MFP3
A
ADC11 analog input.
STADC
PC.8
MFP2
I
ADC external trigger input.
STADC
PE.1
MFP2
I
ADC external trigger input
BPWM0_CH0
PB.7
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH1
PB.6
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH2
PB.5
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH3
PB.4
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH4
PA.10
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH4
PD.11
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH5
PA.11
MFP4
I/O
BPWM0 output/capture input.
BPWM0_CH5
PD.10
MFP4
I/O
BPWM0 output/capture input.
BPWM1_CH0
PB.14
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH1
PB.8
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH2
PF.1
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH2
PF.3
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH3
PF.0
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH3
PF.2
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH4
PD.5
MFP4
I/O
BPWM1 output/capture input.
ADC0
NUC121/125 SERIES DATASHEET
BPWM0
BPWM1
Aug. 17, 2018
Page 72 of 148
Rev 1.02
NUC121/125
Group
CLKO
Pin Name
GPIO
MFP*
Type
Description
BPWM1_CH5
PB.15
MFP4
I/O
BPWM1 output/capture input.
BPWM1_CH5
PD.4
MFP4
I/O
BPWM1 output/capture input.
CLKO
PA.15
MFP3
O
Clock Out.
CLKO
PB.12
MFP2
O
Clock Out.
CLKO
PC.12
MFP4
O
Clock Out.
CLKO
PC.13
MFP3
O
Clock Out.
CLKO
PD.10
MFP1
O
Clock Out.
CLKO
PE.0
MFP3
O
Clock Out.
CLKO
PE.1
MFP3
O
Clock Out.
I2C0_SCL
PC.12
MFP6
I/O
I2C0 clock pin.
I2C0_SCL
PE.2
MFP6
I/O
I2C0 clock pin.
I2C0_SCL
PF.3
MFP2
I/O
I2C0 clock pin.
I2C0_SCL
PF.5
MFP2
I/O
I2C0 clock pin.
I2C0_SDA
PC.11
MFP6
I/O
I2C0 data input/output pin.
I2C0_SDA
PC.13
MFP6
I/O
I2C0 data input/output pin.
I2C0_SDA
PF.2
MFP2
I/O
I2C0 data input/output pin.
I2C0_SDA
PF.4
MFP2
I/O
I2C0 data input/output pin.
I2C1_SCL
PA.11
MFP1
I/O
I2C1 clock pin.
I2C1_SCL
PA.12
MFP2
I/O
I2C1 clock pin.
I2C1_SCL
PC.2
MFP3
I/O
I2C1 clock pin.
I2C1_SDA
PA.10
MFP1
I/O
I2C1 data input/output pin.
I2C1_SDA
PA.13
MFP2
I/O
I2C1 data input/output pin.
I2C1_SDA
PC.3
MFP3
I/O
I2C1 data input/output pin.
ICE_CLK
PF.5
MFP1
I
Serial wired debugger clock pin.
ICE_DAT
PF.4
MFP1
I/O
Serial wired debugger data pin.
INT0
PB.14
MFP1
I
External interrupt0 input pin.
INT0
PC.12
MFP5
I
External interrupt0 input pin.
INT0
PC.13
MFP5
I
External interrupt0 input pin.
INT0
PE.0
MFP1
I
External interrupt0 input pin.
INT1
PB.15
MFP1
I
External interrupt1 input pin.
INT1
PD.11
MFP1
I
External interrupt1 input pin.
INT1
PE.2
MFP1
I
External interrupt1 input pin.
PWM0_BRAKE0
PA.10
MFP5
I
PWM0 brake input 0.
I2C0
NUC121/125 SERIES DATASHEET
I2C1
ICE
INT0
INT1
PWM0
Aug. 17, 2018
Page 73 of 148
Rev 1.02
NUC121/125
Group
NUC121/125 SERIES DATASHEET
Pin Name
GPIO
MFP*
Type
Description
PWM0_BRAKE0
PA.14
MFP4
I
PWM0 brake input 0.
PWM0_BRAKE1
PC.9
MFP5
I
PWM0 brake input 1.
PWM0_BRAKE1
PD.9
MFP5
I
PWM0 brake input 1.
PWM0_CH0
PA.12
MFP1
I/O
PWM0 output/capture input.
PWM0_CH0
PC.10
MFP4
I/O
PWM0 output/capture input.
PWM0_CH1
PA.13
MFP1
I/O
PWM0 output/capture input.
PWM0_CH1
PC.11
MFP4
I/O
PWM0 output/capture input.
PWM0_CH2
PA.14
MFP1
I/O
PWM0 output/capture input.
PWM0_CH2
PC.12
MFP2
I/O
PWM0 output/capture input.
PWM0_CH3
PA.15
MFP1
I/O
PWM0 output/capture input.
PWM0_CH3
PC.13
MFP2
I/O
PWM0 output/capture input.
PWM0_CH3
PE.0
MFP4
I/O
PWM0 output/capture input.
PWM0_CH3
PF.4
MFP4
I/O
PWM0 output/capture input.
PWM0_CH4
PB.9
MFP4
I/O
PWM0 output/capture input.
PWM0_CH4
PC.8
MFP4
I/O
PWM0 output/capture input.
PWM0_CH5
PB.10
MFP4
I/O
PWM0 output/capture input.
PWM0_CH5
PC.9
MFP4
I/O
PWM0 output/capture input.
PWM1_BRAKE0
PC.8
MFP4
I
PWM1 brake input 0.
PWM1_BRAKE1
PA.15
MFP4
I
PWM1 brake input 1.
PWM1_CH0
PB.0
MFP4
I/O
PWM1 output/capture input.
PWM1_CH0
PC.0
MFP4
I/O
PWM1 output/capture input.
PWM1_CH1
PB.1
MFP4
I/O
PWM1 output/capture input.
PWM1_CH1
PC.1
MFP4
I/O
PWM1 output/capture input.
PWM1_CH2
PB.2
MFP4
I/O
PWM1 output/capture input.
PWM1_CH2
PC.2
MFP4
I/O
PWM1 output/capture input.
PWM1_CH3
PB.3
MFP4
I/O
PWM1 output/capture input.
PWM1_CH3
PC.3
MFP4
I/O
PWM1 output/capture input.
PWM1_CH4
PC.4
MFP4
I/O
PWM1 output/capture input.
PWM1_CH5
PC.5
MFP4
I/O
PWM1 output/capture input.
SPI0_CLK
PC.1
MFP1
I/O
SPI0 serial clock pin.
SPI0_CLK
PC.9
MFP3
I/O
SPI0 serial clock pin.
SPI0_CLK
PD.1
MFP7
I/O
SPI0 serial clock pin.
SPI0_MISO0
PC.2
MFP1
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
PWM1
SPI0
Aug. 17, 2018
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Rev 1.02
NUC121/125
Group
TM0
GPIO
MFP*
Type
Description
SPI0_MISO0
PC.10
MFP3
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0_MISO0
PD.2
MFP7
I/O
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0_MOSI0
PC.3
MFP1
I/O
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
PC.11
MFP3
I/O
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0_MOSI0
PD.3
MFP7
I/O
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0_SS
PB.14
MFP7
I/O
SPI0 slave select pin.
SPI0_SS
PC.0
MFP1
I/O
SPI0 slave select pin.
SPI0_SS
PC.8
MFP3
I/O
SPI0 slave select pin.
SPI0_SS
PD.0
MFP7
I/O
SPI0 slave select pin.
SPI0_SS
PD.4
MFP7
I/O
SPI0 slave select pin.
SPI0_I2SMCLK
PA.15
MFP2
O
I2S0 master clock output pin.
SPI0_I2SMCLK
PB.9
MFP3
O
I2S0 master clock output pin.
SPI0_I2SMCLK
PB.10
MFP3
O
I2S0 master clock output pin.
SPI0_I2SMCLK
PC.4
MFP3
O
I2S0 master clock output pin.
SPI0_I2SMCLK
PC.12
MFP3
O
I2S0 master clock output pin.
TM0
PA.11
MFP5
I/O
Timer0 event counter input / toggle output.
TM0
PB.8
MFP1
I/O
Timer0 event counter input / toggle output.
TM0_EXT
PB.15
MFP2
I
Timer0 external counter input.
TM0_EXT
PD.1
MFP4
I
Timer0 external counter input.
TM0_EXT
PE.2
MFP5
I
Timer0 external counter input.
TM1
PB.9
MFP5
I/O
Timer1 event counter input / toggle output.
TM1
PC.11
MFP1
I/O
Timer1 event counter input / toggle output.
TM1_EXT
PD.3
MFP4
I
Timer1 external counter input.
TM1_EXT
PF.1
MFP5
I
Timer1 external counter input.
TM1_EXT
PE.3
MFP5
I
Timer1 external counter input.
TM2
PB.10
MFP1
I/O
Timer2 event counter input / toggle output.
TM2
PC.0
MFP5
I/O
Timer2 event counter input / toggle output.
TM2_EXT
PB.2
MFP2
I
Timer2 external counter input.
TM2_EXT
PB.4
MFP5
I
Timer2 external counter input.
TM3
PB.5
MFP5
I/O
Timer3 event counter input / toggle output.
TM3
PD.2
MFP4
I/O
Timer3 event counter input / toggle output.
TM3
PE.1
MFP5
I/O
Timer3 event counter input / toggle output.
TM3
PF.0
MFP5
I/O
Timer3 event counter input / toggle output.
TM2
TM3
Aug. 17, 2018
Page 75 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
TM1
Pin Name
NUC121/125
Group
Pin Name
GPIO
MFP*
Type
Description
TM3_EXT
PB.3
MFP2
I
Timer3 external counter input.
UART0_RXD
PA12
MFP3
I
Data receiver input pin for UART0.
UART0_RXD
PB.0
MFP1
I
Data receiver input pin for UART0.
UART0_RXD
PC.0
MFP6
I
Data receiver input pin for UART0.
UART0_RXD
PC.4
MFP2
I
Data receiver input pin for UART0.
UART0_RXD
PD.1
MFP5
I
Data receiver input pin for UART0.
UART0_RXD
PF.5
MFP3
I
Data receiver input pin for UART0.
UART0_TXD
PA.13
MFP3
O
Data transmitter output pin for UART0.
UART0_TXD
PB.1
MFP1
O
Data transmitter output pin for UART0.
UART0_TXD
PC.1
MFP6
O
Data transmitter output pin for UART0.
UART0_TXD
PC.5
MFP2
O
Data transmitter output pin for UART0.
UART0_TXD
PD.2
MFP5
O
Data transmitter output pin for UART0.
UART0_TXD
PF.4
MFP3
O
Data transmitter output pin for UART0.
UART0_nCTS
PA.14
MFP3
I
Clear to Send input pin for UART0.
UART0_nCTS
PB.3
MFP1
I
Clear to Send input pin for UART0.
UART0_nCTS
PC.2
MFP6
I
Clear to Send input pin for UART0.
UART0_nCTS
PD.3
MFP5
I
Clear to Send input pin for UART0.
UART0_nRTS
PA.15
MFP5
O
Request to Send output pin for UART0.
UART0_nRTS
PB.2
MFP1
O
Request to Send output pin for UART0.
UART0_nRTS
PB.14
MFP2
O
Request to Send output pin for UART0.
UART0_nRTS
PC.3
MFP6
O
Request to Send output pin for UART0.
UART0_nRTS
PD.0
MFP5
O
Request to Send output pin for UART0.
UART0_nRTS
PD.4
MFP5
O
Request to Send output pin for UART0.
USCI0_CLK
PC.0
MFP7
I/O
USCI0 clock pin.
USCI0_CLK
PC.9
MFP7
I/O
USCI0 clock pin.
USCI0_CLK
PD.1
MFP6
I/O
USCI0 clock pin.
USCI0_CTL0
PB.4
MFP6
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PB.7
MFP7
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PB.12
MFP6
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PC.1
MFP7
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PC.8
MFP7
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PD.0
MFP6
I/O
USCI0 CTL0 pin.
USCI0_CTL0
PD.4
MFP6
I/O
USCI0 CTL0 pin.
UART0
NUC121/125 SERIES DATASHEET
USCI0
Aug. 17, 2018
Page 76 of 148
Rev 1.02
NUC121/125
Group
GPIO
MFP*
Type
Description
USCI0_CTL1
PB6
MFP7
I/O
USCI0 CTL1 pin.
USCI0_CTL1
PB.13
MFP6
I/O
USCI0 CTL1 pin.
USCI0_CTL1
PC.12
MFP7
I/O
USCI0 CTL1 pin.
USCI0_CTL1
PE.2
MFP7
I/O
USCI0 CTL1 pin.
USCI0_DAT0
PA.11
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PB4
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PB.6
MFP6
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PC.3
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PC.5
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PC.11
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PD.3
MFP6
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PD.8
MFP6
I/O
USCI0 DAT0 pin.
USCI0_DAT0
PE.0
MFP7
I/O
USCI0 DAT0 pin.
USCI0_DAT1
PA.10
MFP6
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PB.5
MFP7
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PB.7
MFP6
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PC.2
MFP7
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PC.4
MFP7
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PC.10
MFP7
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PD.2
MFP6
I/O
USCI0 DAT1 pin.
USCI0_DAT1
PE.1
MFP7
I/O
USCI0 DAT1 pin.
XT_IN
PF.1
MFP1
I
External 4~24 MHz (high speed) or 32.768 kHz
(low speed) crystal input pin.
XT_OUT
PF.0
MFP1
O
External 4~24 MHz (high speed) or 32.768 kHz
(low speed) crystal output pin.
XT
Table 4.3-7 NUC121/125 GPIO Multi-function Table
Aug. 17, 2018
Page 77 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Pin Name
NUC121/125
5
BLOCK DIAGRAM
5.1 NuMicro® NUC121/125 Block Diagram
NUC121/125 SERIES DATASHEET
®
Figure 5.1-1 NuMicro NUC121/125 Block Diagram
Aug. 17, 2018
Page 78 of 148
Rev 1.02
NUC121/125
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
®
The Cortex -M0 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The
processor with optional hardware debug functionality can execute Thumb code and is compatible
with other Cortex-M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
®
®
an exception return. The Cortex -M0 is a processor with the same capability as the Cortex -M0
®
processor and includes floating point arithmetic functionality. The NuMicro NUC121/125 series is
®
®
embedded with Cortex -M0 processor. Throughout this document, the name Cortex -M0 refers to
®
®
both Cortex -M0 and Cortex -M0 processors. Figure 6.1-1 shows the functional controller of the
processor.
Cortex-M0 components
Cortex-M0 processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Wakeup
Interrupt
Controller
(WIC)
Debug
Cortex-M0
Processor
Core
Bus Matrix
Breakpoint
and
Watchpoint
Unit
Debugger
interface
Serial Wire or
JTAG debug port
®
Figure 6.1-1 Cortex -M0 Block Diagram
The implemented device provides:
Aug. 17, 2018
A low gate count processor:
ARMv6-M Thumb instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
®
Page 79 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
AHB-Lite
interface
Debug
Access
Port
(DAP)
NUC121/125
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug Support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 80 of 148
Rev 1.02
NUC121/125
6.2 System Manager
6.2.1
Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for
6.2.2
System Reset
Power Modes and Wake-up Sources
System Power Distribution
SRAM Memory Orginization
System Control Register for Part Number ID, Chip Reset and Multi-function Pin
Control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
Hardware Reset Sources
– Power-on Reset (POR)
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
–
–
–
Aug. 17, 2018
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
Page 81 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
NUC121/125
Glitch Filter
32 us
nRESET
~50k ohm
@5v
VDD
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
LVREN(SYS_BODCTL[7])
AVDD
Reset Pulse Width
3.2ms
Low Voltage
Reset
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
Reset Controller
System Reset
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Software Reset
Reset Pulse Width
2 system clocks
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 82 of 148
Rev 1.02
NUC121/125
®
There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset
Cortex-M0 only; the other reset sources will reset Cortex-M0 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
Register
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
SYS_RSTSTS
0x001
Bit 1 = 1
Bit 2 = 1
Bit 3 = 1
Bit 4 = 1
Bit 8 = 1
Bit 0 = 1
Bit 5 = 1
Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
Reload
from
CONFIG0
Reload
Reload
Reload
from
from
from
CONFIG0 CONFIG0 CONFIG0
(CLK_PWRCTL[0])
Reload
from
CONFIG0
Reload
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
LXTEN
0x0
-
-
-
-
-
-
-
-
0x1
-
0x1
-
-
-
0x1
-
-
(CLK_CLKSEL0[2:0])
Reload
from
CONFIG0
Reload
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
WDTSEL
0x3
0x3
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
0x0
-
-
-
-
-
-
-
Reload
from
CONFIG0
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
-
0x0700
0x0700
0x0700
-
-
(SYS_IPRST0[0])
BODEN
(SYS_BODCTL[0])
Reload
Reload
from
from
CONFIG0 CONFIG0
Reload
from
CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
(CLK_PWRCTL[1])
WDTCKEN
(CLK_APBCLK0[0])
HCLKSEL
HXTSTB
(CLK_STATUS[0])
LXTSTB
(CLK_STATUS[1])
PLLSTB
(CLK_STATUS[2])
HIRCSTB
(CLK_STATUS[4])
CLKSFAIL
(CLK_STATUS[7])
RSTEN
(WDT_CTL[1])
WDTEN
(WDT_CTL[7])
WDT_CTL
Aug. 17, 2018
0x0700
0x0700
0x0700
Page 83 of 148
-
Rev 1.02
NUC121/125 SERIES DATASHEET
(CLK_CLKSEL1[1:0])
NUC121/125
except bit 1 and bit 7.
WDT_ALTCTL
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_RLDCNT
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_CTL
0x3F0800
0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
0x3F0800
-
-
WWDT_STATUS
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_CNT
0x3F
0x3F
0x3F
0x3F
0x3F
-
0x3F
-
-
BS
Reload
from
CONFIG0
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
-
FMC_DFBA
Reload
from
CONFIG1
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG1 CONFIG1 CONFIG1 CONFIG1
Reload
from
CONFIG1
-
-
CBS
Reload
from
CONFIG0
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
from
CONFIG0
-
-
Reload
base on
CONFIG0
Reload
Reload
Reload
Reload
base on
base on
base on base on
CONFIG0 CONFIG0 CONFIG0 CONFIG0
Reload
base on
CONFIG0
-
-
(FMC_ISPCTL[1])
BL
(FMC_ISPCTL[16])
(FMC_ISPSTS[2:1))
VECMAP
(FMC_ISPSTS[23:9])
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
-
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
NUC121/125 SERIES DATASHEET
6.2.2.1
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
Aug. 17, 2018
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NUC121/125
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by
writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until
the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by
LVRDGSEL (SYS_BODCTL[14:12]). The LVRF(SYS_RSTSTS[3]) will be set to 1 if the previous
reset source is LVR reset. The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.
Aug. 17, 2018
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Rev 1.02
NUC121/125 SERIES DATASHEET
0.1V
VDD
NUC121/125
AVDD
VLVR
T1
( < LVRDGSEL)
T2
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
200 us
Delay for LVR stable
LVREN
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4
Brown-out Detector Reset (BOD Reset)
NUC121/125 SERIES DATASHEET
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD which is decided by BOD_EN (BODCR[0])
and BOD_VL (BODCR[2:1]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until
the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by
BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and
BODRSTEN(SYS_BODCTL[3]) is set by flash controller user configuration register CBODEN
(CONFIG0 [23]), CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can
determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the BrownOut Detector waveform.
Aug. 17, 2018
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NUC121/125
AVDD
VBODH
VBODL
Hysteresis
T1
(< BODDGSEL)
T2
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives
immediate indication of seriously errant kernel software. This is the result of the CPU being locked
because of an unrecoverable exception following the activation of the processor’s built in system
state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7
CPU Reset, CHIP Reset and MCU Reset
®
The CPU Reset means only Cortex -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
Aug. 17, 2018
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Rev 1.02
NUC121/125 SERIES DATASHEET
6.2.2.5
NUC121/125
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3
Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD,
GPIO, EINT, USCI and USBD.
Available Clocks
All
All except CPU clock
LXT and LIRC
After Wake-up
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-2 Power Mode Difference Table
NUC121/125 SERIES DATASHEET
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SCR(SCB[2]) = 1
2. PD_EN(PWRCTL[7]) = 1 and
PDWTCPU(PWRCTL[8]) = 1
3. CPU executes WFI
Idle Mode
Wake-up events
occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.2-6 Power Mode State Machine
Aug. 17, 2018
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NUC121/125
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If UART clock source is selected as LXT and LXT is on.
Idle Mode
Power-Down Mode
HXT (4~24 MHz XTL)
ON
ON
Halt
HIRC (48 MHz OSC)
ON
ON
Halt
LXT (32768 Hz XTL)
ON
ON
ON/OFF1
LIRC (10 kHz OSC)
ON
ON
ON/OFF2
PLL
ON
ON
Halt
LDO
ON
ON
ON
CPU
ON
Halt
Halt
HCLK/PCLK
ON
ON
Halt
SRAM retention
ON
ON
ON
FLASH
ON
ON
Halt
GPIO
ON
ON
Halt
PDMA
ON
ON
Halt
TIMER
ON
ON
ON/OFF3
BPWM
ON
ON
Halt
PWM
ON
ON
Halt
WDT
ON
ON
ON/OFF4
WWDT
ON
ON
Halt
USCI
ON
ON
Halt
UART
ON
ON
ON/OFF5
I2C
ON
ON
Halt
SPI/I S
ON
ON
Halt
USBD
ON
ON
Halt
ADC
ON
ON
Halt
2
NUC121/125 SERIES DATASHEET
Normal Mode
Table 6.2-3 Clocks in Power Modes
Wake-up Sources in Power-down Mode:
WDT, I²C, Timer, UART, BOD, GPIO, EINT, USCI and USBD
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
Aug. 17, 2018
Page 89 of 148
Rev 1.02
NUC121/125
*User needs to wait this condition before setting PD_EN(PWRCTL[6]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
Source
BOD
System Can Enter Power-Down Mode Again Condition*
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
After software write 1 to clear the INTSRC[n] bit.
Timer Interrupt
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
WDT Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
UART
RX Data wake-up
After software writes 1 to clear DATWKIF (UARTx_INTSTS[17]).
nCTS wake-up
After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).
TIMER
2
Falling edge in the I2C_SDA
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
or I2C_CLK
IC
USCI
USBD
Remote Wake-up
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
Table 6.2-4 Condition of Entering Power-down Mode Again
6.2.4
System Power Distribution
In this chip, power distribution is divided into four segments:
NUC121/125 SERIES DATASHEET
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB
transceiver.
A dedicated power from VDDIO supplies the power for PA.10, PA.11, PB.4 ~ PB.7,
PB.12 ~ PB.14 and PD.8 ~ 11 of NUC125.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
®
voltage level of the digital power (VDD). Figure 6.2-7 shows the power distribution of the NuMicro
NUC121 and NUC125.
Aug. 17, 2018
Page 90 of 148
Rev 1.02
VDDIO
PA.10, PA.11,
PB.4 ~ PB.7,
PB.12 ~ PB.14
and PD.8 ~ 11
of NUC125
NUC121/125
12-bit ADC
USB
Transceiver
IO Cell
Internal
Voltage
(Band-gap)
3.3V
AVDD
USB_D+
USB_DUSB_VDD33_CAP
1uF
AVSS
Brown-out
Detector
Low Voltage
Reset
5V à 3.3V
LDO
Temperature
Sensor
SRAM
Flash
USB_VBUS
Digital Logic
1.8V
LDO_CAP
1uF
PLL
XT1_OUT
HXT / LXT
48 MHz IRC
Oscillator
POR18
5V à 1.8V
LDO
POR50
XT1_IN
Power On
Control
10 kHz
IRC
Oscillator
IO Cell
5.0V
GPIO except
PA.10, PA.11,
PB.4 ~ PB.7,
PB.12 ~ PB.14
and PD.8 ~ 11
of NUC125
VSS
NUC121/125 SERIES DATASHEET
VDD
NUC121/125 power distribution
®
Figure 6.2-7 NuMicro NUC121/125 Power Distribution Diagram
Aug. 17, 2018
Page 91 of 148
Rev 1.02
NUC121/125
6.3 Clock Controller
6.3.1
Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
®
Cortex -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal
high speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-1
shows the clock generator and the overview of the clock source control.
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
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Rev 1.02
NUC121/125
HIRC/2
111
48 MHz
(HIRC)
PLL_FOUT/2
4~24 MHz
(HXT)
LIRC
HIRC
10 kHz
(LIRC)
CPU
HCLK
PDMA
PCLK 0
USCI
PCLK 1
I2C 1
GPIO
100
011
PLLFOUT
1/(HCLKDIV+1)
010
LXT
32.768 kHz
(LXT)
CPUCLK
101
001
HXT
000
I2C 0
CLK_CLKSEL0[2:0]
HIRC/2
1
LXT
LXT
HXT
000
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
FMC
101
HIRC/2
011
HCLK
010
001
BOD
HIRC/2
HCLK
010
HXT
LIRC
TMR 0
TMR 1
TMR 2
TMR 3
011
PCLK
0
CLK_PLLCTL[19]
HIRC
101
T0~T3
PLL FOUT
HXT
HIRC/2
111
LIRC
HIRC/2
Clock Output
HXT
001
1/2
111
1/2
011
1/2
010
LXT
CPUCLK
1
SysTick
0
001
000
HXT
SYST_CTRL[2]
000
CLK_CLKSEL2[4:2]
CLK_CLKSEL0[5:3]
PCLK 0
HIRC
PCLK 0
PLLFOUT
HXT
11
10
1
BPWM 0
PLLFOUT
0
PWM 0
SPI
CLK_CLKSEL1[28]
CLK_CLKSEL1[30]
01
00
1
BPWM 1
0
PWM 1
CLK_CLKSEL1[29]
CLK_CLKSEL1[31]
PLLFOUT
HIRC
LIRC
11
1/2048
10
LXT
01
1
0
1/(USBDIV+1)
USB
HCLK
WDT
CLK_CLKSEL3[8]
CLK_CLKSEL1[1:0]
HIRC/2
PCLK 0
PLLFOUT
HXT
LXT
11
10
01
00
PCLK 0
1/(ADCDIV+1)
ADC
11
WWDT
1/2048
10
CLK_CLKSEL1[31:30]
HIRC/2
CLK_CLKSEL1[3:2]
11
LXT
10
PLLFOUT
01
HXT
00
1/(UARTDIV+1)
UART
CLK_CLKSEL1[25:24]
Figure 6.3-1 Clock Generator Global View Diagram
Aug. 17, 2018
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Rev 1.02
NUC121/125 SERIES DATASHEET
PCLK 1
PLLFOUT
CLK_CLKSEL2[25:24]
NUC121/125
6.3.2
Clock Generator
The clock generator consists of 5 clock sources, which are listed below:
32.768 kHz external low-speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~24 MHz external high speed crystal (HXT) or 24 MHz (Internal high
speed oscillator, HIRC/2)
48 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable frequency.
When clock source is enabled, a stable counter start counting and correlated clock stable index
(HIRCSTB(CLK_STATUS[4]), LIRCSTB(CLK_STATUS[3]), PLLSTB(CLK_STATUS[2]),
HXTSTB(CLK_STATUS[0]) and LXTSTB(CLK_STATUS[1]) are set to 1 after stable counter value
reach a define value as shown in the following table.
System and peripheral can use the clock as its operating clock only when correlate clock stable index
is set to 1. The clock stable index will auto clear when user disables the clock source
(LIRCEN(CLK_PWRCTL[3]), HIRCEN(CLK_PWRCTL[2]),XTLEN(CLK_PWRCTL[1:0]) and
PD(CLK_PLLCTL[16]). Besides, the clock stable index of HXT, HIRC and PLL will auto clear when
chip enter power-down and clock stable counter will re-counting after chip wake-up if correlate clock is
enabled.
Clock Source
Clock Stable Count Value
Clock Stable Time
HXT
4096 HXT clocks
341.33 uS for 12 Mhz
PLL
It’s based on the value of STBSEL (CLK_PLLCTL[23])
STBSEL = 0
NUC121/125 SERIES DATASHEET
STBSEL = 0, stable count is 6144 PLL clocks.
122.88 uS for 50 Mhz
STBSEL = 1, stable count is 12288 PLL clocks.(Default)
STBSEL = 1:
245.76 uS for 50 Mhz
HIRC
512 HIRC clocks
10.667 uS for 48Mhz
LIRC
1 LIRC clock
100 uS for 10 kHz
LXT
8192 LXT clock
250 mS for 32 KHz
Table 6.3-1 Clock Stable Count Value Table
Aug. 17, 2018
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NUC121/125
XTLEN (CLK_PWRCTL[1:0]) = 10
External 32.768
kHz Crystal
(LXT)
LXT
XTLEN (CLK_PWRCTL[1:0]) = 01
HXT
PF.1
External 4~24
MHz Crystal
(HXT)
PF.0
PLLSRC (CLK_PLLCTL[19])
0
HIRCEN (CLK_PWRCTL[2])
PLL
PLL FOUT
1
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRCEN(CLK_PWRCTL[3])
Internal10 KHz
Oscillator
(LIRC)
LIRC
NUC121/125 SERIES DATASHEET
Figure 6.3-2 Clock Generator Block Diagram
Aug. 17, 2018
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Rev 1.02
NUC121/125
6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram
is shown in Figure 6.3-3
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC/2
PLL_FOUT/2
HIRC
LIRC
PLLFOUT
LXT
HXT
111
101
CPUCLK
100
1/(HCLK_N+1)
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
011
010
001
000
CPU in Power Down Mode
HCLK
PCLK0
PCLK1
CPU
AHB
APB0
APB1
:
Legend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source if stop and they have
individual enable and interrupt control. When HXT fail detector is enabled, the HIRC clock is
enabled automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
NUC121/125 SERIES DATASHEET
When HXT clock fail detector is enabled, the system clock will auto switch to HIRC/2 (24 MHz) if
HXT clock stop being detected on the following condition: system clock source comes from HXT
or system clock source comes from PLL with HXT as the input of PLL. If HXT clock stop condition
is detected, the HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE
(CLK_CLKDCTL[5]) is set to 1. User can trying to recover HXT by disable HXT and enable HXT
again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means
HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC/2 (24 MHz) procedure is shown in
Figure 6.3-4
Aug. 17, 2018
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
NO
System clock keep
original clock
YES
Switch system clock to
HIRC/2 (24 MHz)
Figure 6.3-4 HXT Stop Protect Procedure
If HXT clock frequency abnormally condition is detected, the HXTFQIF(CLK_CLKDSTS[8]) is set
to 1 and chip will enter interrupt if HXTFQIEN (CLK_CLKDCTL[17]) is set to 1. Different with HXT
fail(stop) detector, when HXT clock frequency abnormally condition is detected, the system clock
will NOT auto switch to HIRC/2 (24 MHz) even though system clock source comes from HXT or
system clock source comes from PLL with HXT as the input of PLL. The HXT frequency detector
just reminds user HXT clock frequency abnormally through to observe HXTFQIF
(CLK_CLKDSTS[8]).
®
The clock source of SysTick in Cortex -M0 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in Figure 6.3-5
Aug. 17, 2018
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NUC121/125 SERIES DATASHEET
Except HXT fail(stop) detector, HXT also has a frequency detector to observe HXT clock frequncy
if normally and it also has individual enable(HXTFQDEN=CLK_CLKDCTL[16]) and interrupt
control (HXTFQIEN=CLK_CLKDCTL[17]). When HXT frequency detector is enabled, the HIRC
clock is enabled automatically. Otherwise, before HXT frequency detector is enabled, we need set
the frequency detector upper boundary(UPERBD=CLK_CDUPB[9:0]) and lower boundary
(LOWERBD=CLK_CDLOWB[9:0]).
NUC121/125
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC/2
HCLK
HXT
1/2
111
1/2
011
1/2
010
LXT
STCLK
001
HXT
000
:
Legend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4
Peripherals Clock
The peripherals clock had different clock source switch setting, which depends on the different
peripheral.
6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources, and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
NUC121/125 SERIES DATASHEET
6.3.6
Clock Generator
10 kHz internal low-speed RC oscillator (LIRC) clock
32.768 kHz external low-speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
1
16
clocks with the frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock
divider.
(N+1)
The output formula is Fout = Fin/2
, where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
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CLKOSEL (CLK_CLKSEL2[4:2])
CLKOCKEN (CLK_APBCLK0[6])
HIRC
HIRC/2
HCLK
LXT
HXT
101
CLKO_CLK
011
010
001
000
:
Legend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-6 Clock Source of Clock Output
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
CLKO_CLK
1/2
16 chained
divide-by-2 counter
1/22
1/23
…...
1/215
1/216
:
:
1110
1111
16 to 1
MUX
CLKO
FREQSEL
(CLK_CLKOCTL[3:0])
Figure 6.3-7 Clock Output Block Diagram
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0000
0001
NUC121/125
6.4 Flash Memory Controller (FMC)
6.4.1
Overview
The NUC121/125 series is equipped with 32 K-bytes on-chip embedded flash for application and
Data Flash to store some application dependent data. A User Configuration block provides for
system initialization. A 4.5 K-bytes loader ROM (LDROM) is used for In-System-Programming
(ISP) function. A 512 bytes security protection ROM (SPROM) can conceal user program. This
chip also supports In-Application-Programming (IAP) function, user switches the code executing
without the chip reset after the embedded flash updated.
6.4.2
Features
Supports 32 K-bytes application ROM (APROM).
Supports 4.5 K-bytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports 512 bytes security protection ROM (SPROM) to conceal user program.
Supports 12 bytes User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded flash.
Supports CRC-32 checksum calculation function (must be 512 bytes page alignment).
Supports APROM, LDROM and embedded SRAM remap to system vector memory.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1
Overview
The NUC121/125 series has up to 52 General Purpose I/O pins to be shared with other function
pins depending on the chip configuration. These 52 pins are arranged in 6 ports named as PA,
PB, PC, PD, PE and PF.
PA has 6 pins on port (PA.10 ~ PA.15).
PB has 15 pins on port (PB.0 ~ PB.15, exclude PB.11).
PC has 12 pins on port (PC.0 ~ PC.13, exclude PC.6, PC.7).
PD has 10 pins on port (PD.0 ~ PD.11, exclude PD.6, PD.7).
PE has 3 pins on port (PE.0 ~ PE.2).
PF has 6 pins on port (PF.0 ~ PF.5).
Each of the 52 pins is independent and has the corresponding register bits to control the pin
mode function and data
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
Features
NUC121/125 SERIES DATASHEET
6.5.2
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Slew Rate I/O mode
Supports High Drive Strength mode for Port C
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in input mode after chip reset
CIOIN = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
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6.6 PDMA Controller (PDMA)
6.6.1
Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data
transfer. The PDMA controller can transfer data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controller has a total of 5 channels and each channel can
perform transfer between memory and peripherals or between memory and memory. The PDMA
supports time-out function for channel 0 and channel 1.
6.6.2
Features
Supports 5 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or no
increment
Supports software and SPI, UART, I S, I C, USCI, ADC, PWM and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function for channel 0 and channel 1
2
2
NUC121/125 SERIES DATASHEET
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6.7 Timer Controller (TMR)
6.7.1
Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.7.2
Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM,
BPWM, PDMA, ADC and DAC function
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6.8 Basic PWM Generator and Capture Timer (BPWM)
6.8.1
Overview
The NUC121/125 series provides two BPWM generators: BPWM0 and BPWM1. Each BPWM
supports 6 channels of BPWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit BPWM counter with 16-bit comparator. The BPWM counter supports
up, down and up-down counter types, all 6 channels share one counter. BPWM uses the
comparator compared with counter to generate events. These events are used to generate
BPWM pulse, interrupt and trigger signal for ADC to start conversion. For BPWM output control
unit, it supports polarity output, independent pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.8.2
6.8.2.1
Features
BPWM function features
Supports maximum clock frequency up to100 MHz
Supports up to two BPWM modules, each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution BPWM counter, each module provides 1 BPWM counter
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt on the following events:
NUC121/125 SERIES DATASHEET
Supports trigger ADC on the following events:
6.8.2.2
BPWM counter match zero, period value or compared value
BPWM counter match zero, period value or compared value
Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising edge or falling edge or both edges capture condition
Supports input rising/falling edge or both edges capture interrupt
Supports rising/falling or both edges capture with counter reload option
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6.9 PWM Generator and Capture Timer (PWM)
6.9.1
Overview
The NUC121/125 series provides two PWM generators － PWM0 and PWM1. Each PWM
supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up,
down and up-down counter types. PWM uses the comparator compared with counter to generate
events. These events are used to generate PWM pulse, interrupt and trigger signal for ADC to
start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, which have difference architecture. In Complementary mode, there are
two comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM
output control unit, it supports polarity output, independent pin mask, tri-state output enable and
brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.9.2
6.9.2.1
Features
PWM function features
Supports maximum clock frequency up to100 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter, each module provides 3 PWM counters
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out detection
and CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
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PWM counter match zero, period value or compared value
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6.9.2.2
Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.10
Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for WDT time-out interval.
Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63.
Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset
delay period.
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in
Config0 register.
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
4
18
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6.11
Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified
window period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter value CNTDAT(WWDT_CNT[5:0]) and maximum 6-bit compare value
CMPDAT(WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value PSCSEL(WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
WWDT counter only can be reloaded within in valid window period to prevent system reset
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6.12
USCI - Universal Serial Control Interface Controller
6.12.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
2
communication protocols. The user can configure this controller as UART, SPI, or I C functional
protocol.
6.12.2 Features
The controller can be individually configured to match the application needs. The following
protocols are supported:
UART
SPI
IC
2
To increase readability, the registers of USCI have different alias names that depending on the
selected protocol. For example, register USCI_CTL has alias name UUART_CTL for protocol
UART, has alias name USPI_CTL for protocol SPI, and has alias name UI2C_CTL for protocol
2
I C.
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6.13
USCI - UART Mode
6.13.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of
asynchronous data frames. It performs a serial-to-parallel conversion on data received from the
peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver
and transmitter are independent, frames can start at different points in time for transmission and
reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the
system by incoming data or nCTS.
6.13.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Supports 9-Bit Data Transfer (9-Bit RS-485)
Supports baud rate detection by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.14
USCI - SPI Mode
6.14.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows
full duplex transfer. It supports both master and slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received
from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral
device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as master or slave mode by setting the SLAVE
(USPI_PROTCTL[0]) to communicate with the off-chip SPI slave or master device. The
application block diagrams in master and slave mode are shown below.
USCI
USCI SPI
SPI Master
Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
(USCIx_DAT0)
SPI_MISO
Master Receive Data
(USCIx_DAT1)
SPI_CLK
Serial Bus Clock
(USCIx_CLK)
SPI_SS
Slave Select
(USCIx_CTL)
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0
Figure 6.14-1 SPI Master Mode Application Block Diagram
NUC121/125 SERIES DATASHEET
USCI
USCI SPI
SPI Slave
Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
(USCIx_DAT0)
SPI_MISO
Slave Transmit Data
(USCIx_DAT1)
SPI_CLK
Serial Bus Clock
(USCIx_CLK)
SPI_SS
Slave Select
(USCIx_CTL)
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0
Figure 6.14-2 SPI Slave Mode Application Block Diagram
6.14.2 Features
Supports master or slave mode operation (the maximum frequency for Master = fPCLK / 2, for
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
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Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports word suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.15
USCI - I2C Mode
6.15.1 Overview
2
On I C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
2
STOP). Please refer to Figure 6.15-1 for more detailed I C BUS Timing.
STOP
Repeated
START
START
STOP
SDA
(USCI_DAT0)
tBUF
tLOW
tr
SCL
(USCI_CLK)
tf
tHIGH
tHD_STA
tHD_DAT
tSU_DAT
tSU_STA
tSU_STO
2
Figure 6.15-1 I C Bus Timing
2
2
The device’s on-chip I C provides the serial interface that meets the I C bus standard mode
2
2
specification. The I C port handles byte transfers autonomously. The I C mode is selected by
2
FUNMODE (UI2C_CTL [2:0]) = 100b. When enable this port, the USCI interfaces to the I C bus
2
via two pins: SDA and SCL. When I/O pins are used as I C ports, user must set the pins function
2
to I C in advance.
2
6.15.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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Note: Pull-up resistor is needed for I C operation because the SDA and SCL are set to open2
drain pins when USCI is selected to I C operation mode .
NUC121/125
6.16
UART Interface Controller (UART)
6.16.1 Overview
The NUC121/125 series provides one channel of Universal Asynchronous Receiver/Transmitters
(UART). UART controller performs Normal Speed UART and supports flow control function. The
UART controller performs a serial-to-parallel conversion on data received from the peripheral and
a parallel-to-serial conversion on data transmitted from the CPU. Each UART controller channel
supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN and RS-485
function modes and auto-baud rate measuring function.
6.16.2 Features
NUC121/125 SERIES DATASHEET
Full-duplex asynchronous communications
Supports maximum clock frequency up to 10 Mbps
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
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I2C Serial Interface Controller (I2C)
6.17
6.17.1 Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
2
exchange between devices. The I C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
2
There are two sets of I C controllers which support Power-down wake-up function.
6.17.2 Features
2
The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to
2
the bus. The main features of the I C bus include:
2
Supports up to two I C ports
Supports speed up to 1Mbps
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timerout counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports two-level buffer function
Supports setup/hold time programmable
2
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2
NUC121/125
6.18
Serial Peripheral Interface (SPI)
6.18.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NUC121/125 series contains one SPI controller performing a serial-toparallel conversion on data received from a peripheral device, and a parallel-to-serial conversion
on data transmitted to a peripheral device. The SPI controller can be configured as a master or a
slave device.
This controller also supports the PDMA function to access the data buffer. The SPI controller also
2
supports I S mode to connect external audio CODEC.
6.18.2 Features
SPI Mode
One set of SPI controller
Supports Master or Slave mode operation
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports PDMA transfer
Supports one data channel half-duplex transfer
Support receive-only mode
2
I S Mode
NUC121/125 SERIES DATASHEET
Supports Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Provides separate 4-level depth transmit and receive FIFO buffers
Supports monaural and stereo audio data
Supports PCM mode A, PCM mode B, I S and MSB justified data format
Supports PDMA transfer
Aug. 17, 2018
2
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6.19
USB Device Controller (USBD)
6.19.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports
control/bulk/interrupt/isochronous transfer types. It implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 768 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGn, n=0~7).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are five different interrupt events in this controller. They are the SOF event, no-event-wakeup, device plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events,
like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the
related event flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of
interrupt occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB
controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.
After disable the SE0 bit, host will enumerate the USB device again.
6.19.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (NEVWK, VBUSDET, USB, BUS
and SOF)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and
maximum 768 bytes buffer size
Provides remote wake-up capability
Start of Frame (SOF) locked clock pulse generation
Supports USB 2.0 Link Power Management
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For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
NUC121/125
6.20
Analog-to-Digital Converter (ADC)
6.20.1 Overview
The NUC121/125 series contains one 12-bit successive approximation analog-to-digital converter
(SAR A/D converter) with 14 input channels. The A/D converter supports four operation modes:
Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D converter can be started
by software, external pin (STADC/PC.8), timer0~3 overflow pulse trigger and PWM trigger.
6.20.2 Features
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed
Up to 12 single-end analog input channels or 6 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Up to 800k SPS sampling rate
Configurable ADC internal sampling time
Four operation modes:
NUC121/125 SERIES DATASHEET
Single mode: A/D conversion is performed one time on a specified channel.
Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan
mode until software stops A/D conversion.
An A/D conversion can be started by:
Software Write 1 to ADST bit
External pin (STADC)
Timer 0~3 overflow pulse trigger
PWM trigger with optional start delay period
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Two internal channels which are band-gap voltage (VBG) and temperature sensor (VTEMP).
Supports PDMA transfer mode.
Note 1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note 2: If the internal channel (VTEMP) is selected to convert, the sampling rate needs to be less
than 300k SPS for accurate result.
Aug. 17, 2018
Page 118 of 148
Rev 1.02
NUC121/125
7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
AVDD
DVCC
Power
CS
CLK
MISO
MOSI
SPIx_SS
SPIx_CLK
SPIx_MISO
SPIx_MOSI
FB
VDD
VDD
SPI Device
VSS
0.1uF
0.1uF
VSS
DVCC
FB
DVCC
AVSS
4.7K
4.7K
CLK
I2Cx_SCL
VDD
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
I2Cx_SDA
NUC121
Series
DIO
RS232 Transceiver
DVCC
UARTx_RXD
ROUT
UARTx_TXD
TIN
VDD
I2C Device
VSS
PC COM Port
RIN
UART
TOUT
10K
Reset
Circuit
nRESET
10uF/25V
USB_VBUS
USB_DUSB_D+
USB_ID
USB_VDD33_CAP
33
33
USB FS Device
1uF
LDO
LDO_CAP
1uF
Aug. 17, 2018
Page 119 of 148
NUC121/125 SERIES DATASHEET
Note: For the SPI device, the chip supply voltage
must be equal to SPI device working voltage. For
example, when the SPI Flash working voltage is
3.3 V, the NUC121 chip supply voltage must also
be 3.3V.
Rev 1.02
NUC121/125
DVCC1
[1]
AVCC
AVDD
DVCC1
CS
CLK
MISO
MOSI
SPIx_SS
SPIx_CLK
SPIx_MISO
SPIx_MOSI
FB
VDD
VDD
SPI Device
VSS
0.1uF
0.1uF
VSS
DVCC2
FB
DVCC2
AVSS
Power
4.7K
4.7K
CLK
I2Cx_SCL
VDD
[2]
VDDIO
DVCC2
VDD
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
I2Cx_SDA
NUC125
Series
DIO
RS232 Transceiver
UARTx_RXD
ROUT
UARTx_TXD
TIN
I2C Device
VSS
PC COM Port
RIN
DVCC
UART
TOUT
10K
Reset
Circuit
nRESET
10uF/25V
USB_VBUS
USB_DUSB_D+
USB_ID
USB_VDD33_CAP
33
33
USB FS Device
1uF
LDO
LDO_CAP
1uF
NUC121/125 SERIES DATASHEET
Note1: For the SPI device, the chip supply
voltage must be equal to SPI device working
voltage if SPIx_SS, SPIx_CLK, SPIx_MISO and
SPIx_MOSI are not in VDDIO domain. For
example, when the SPI Flash working voltage is
3.3 V, the NUC125 chip supply voltage must also
be 3.3V.
Note2: DVCC2 can be 1.8V ~ 5.5V.
Aug. 17, 2018
Page 120 of 148
Rev 1.02
NUC121/125
8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNIT
VDD-VSS
-0.3
+7.0
V
VIN
VSS – 0.3
VDD + 0.3
V
Input Voltage on VDDIO
VDDIO
+1.8
+5.5
V
Oscillator Frequency
1/tCLCL
4
24
MHz
Operating Temperature
TA
-40
+105
C
Storage Temperature
TST
-55
+150
C
Maximum Current into VDD
IDD
-
120
mA
Maximum Current out of VSS
ISS
-
120
mA
-
35
mA
-
35
mA
Maximum Current Sunk by Total I/O Pins
-
100
mA
Maximum Current Sourced by Total I/O Pins
-
100
mA
DC Power Supply
Input Voltage
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
IIO
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the
device.
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 121 of 148
Rev 1.02
NUC121/125
8.2 DC Electrical Characteristics
(VDD-VSS = 2.5 ~ 5.5V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
2.5
-
5.5
V
1.8
-
5.5
V
VSS AVSS
-0.05
-
+0.05
V
VLDO
1.62
1.8
1.98
V
MCU operating in Run, Idle or Power-down
mode
CLDO
1
-
1
uF
Connect to LDO_CAP pin
Band-gap Voltage
VBG
-
1.21
-
V
VDD = 2.5 V ~ 5.5 V, TA = -40 ~ 105C
Allowed voltage
difference for VDD and
AVDD
VDD AVDD
-0.3
-
+0.3
V
IDD1
-
20.4
-
mA
Operation Voltage
VDD VSS
Power supply for
VDDIO PB.14, PA.11, PA.10,
VSS
PB.4 and PB.5
Power Ground
MAX. UNIT
LDO Output Voltage
NUC121/125 SERIES DATASHEET
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}executed
from flash
VDD = 2.5 ~ 5.5V up to 50 MHz
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
12 MHz
X
V
V
IDD2
-
9.5
-
mA
5.5 V
12 MHz
X
V
X
IDD3
-
20.0
-
mA
3.0 V
12 MHz
X
V
V
IDD4
-
9.3
-
mA
3.0 V
12 MHz
X
V
X
VDD
HXT
HIRC
PLL
IDD5
-
24.6
-
mA
All digital
module
5.5 V
X
48 MHz
V
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Aug. 17, 2018
IDD6
-
11.5
-
mA
5.5 V
X
48 MHz
V
X
IDD7
-
24.1
-
mA
3.0 V
X
48 MHz
V
V
IDD8
-
11.4
-
mA
3.0 V
X
48 MHz
V
X
mA
VDD
HXT
HIRC
PLL
IDD9
-
20.0
-
All digital
module
mA
5.5 V
12 MHz
X
V
V
IDD10
-
9.1
-
mA
5.5 V
12 MHz
X
V
X
IDD11
-
19.5
-
mA
3.0 V
12 MHz
X
V
V
IDD12
-
8.8
-
mA
3.0 V
12 MHz
X
V
X
IDD13
-
20.0
-
mA
VDD
HXT
HIRC
PLL
All digital
module
Page 122 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
TYP.
MAX. UNIT
5.5 V
X
48 MHz
X
V
IDD14
-
8.5
-
mA
5.5 V
X
48 MHz
X
X
IDD15
-
19.5
-
mA
3.0 V
X
48 MHz
X
V
IDD16
-
8.4
-
mA
3.0 V
X
48 MHz
X
X
IDD17
-
9.7
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
24 MHz
X
X
V
IDD18
-
4.4
-
mA
5.5 V
24 MHz
X
X
X
IDD19
-
9.5
-
mA
3.0 V
24 MHz
X
X
V
IDD20
-
4.2
-
mA
3.0 V
24 MHz
X
X
X
IDD21
-
11.1
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
X
48/2 MHz
X
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
IDD22
-
5.2
-
mA
5.5 V
X
48/2 MHz
X
X
IDD23
-
10.9
-
mA
3.0 V
X
48/2 MHz
X
V
IDD24
-
5.1
-
mA
3.0 V
X
48/2 MHz
X
X
VDD
HXT
HIRC
PLL
IDD25
-
6.4
-
mA
All digital
module
5.5 V
16 MHz
X
X
V
VLDO=1.8 V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD26
-
3.1
-
mA
5.5 V
16 MHz
X
X
X
IDD27
-
6.3
-
mA
3.0 V
16 MHz
X
X
V
IDD28
-
3.0
-
mA
3.0 V
16 MHz
X
X
X
VDD
HXT
HIRC
PLL
IDD29
-
8.3
-
mA
All digital
module
5.5 V
X
48/3 MHz
X
V
IDD30
-
4.2
-
mA
5.5 V
X
48/3 MHz
X
X
IDD31
-
8.1
-
mA
3.0 V
X
48/3 MHz
X
V
IDD32
-
4.1
-
mA
3.0 V
X
48/3 MHz
X
X
IDD33
-
4.9
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
12 MHz
X
X
V
IDD34
-
2.2
-
mA
5.5 V
12 MHz
X
X
X
IDD35
-
4.7
-
mA
3.0 V
12 MHz
X
X
V
IDD36
-
2.1
-
mA
3.0 V
12 MHz
X
X
X
VDD
HXT
HIRC
PLL
IDD37
-
6.8
-
mA
All digital
module
5.5 V
X
48/4 MHz
X
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =12 MHz
Aug. 17, 2018
Page 123 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
while(1){}executed
from flash
IDD38
-
3.7
-
mA
5.5 V
X
48/4 MHz
X
X
VLDO=1.8 V
IDD39
-
6.6
-
mA
3.0 V
X
48/4 MHz
X
V
IDD40
-
3.6
-
mA
3.0 V
X
48/4 MHz
X
X
IDD41
-
1.8
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
4 MHz
X
X
V
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
IDD42
-
0.9
-
mA
5.5 V
4 MHz
X
X
X
IDD43
-
1.7
-
mA
3.0 V
4 MHz
X
X
V
IDD44
-
0.8
-
mA
3.0 V
4 MHz
X
X
X
VDD
HXT
HIRC
PLL
IDD45
-
3.9
-
mA
All digital
module
5.5 V
X
48/12 MHz
X
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IDD46
-
2.5
-
mA
5.5 V
X
48/12 MHz
X
X
IDD47
-
3.9
-
mA
3.0 V
X
48/12 MHz
X
V
IDD48
-
2.5
-
mA
3.0 V
X
48/12 MHz
X
X
IDD49
-
120
-
uA
VDD
LXT
LIRC
PLL
All digital
module
5.5 V 32.768 kHz
X
X
V
NUC121/125 SERIES DATASHEET
IDD50
-
113
-
uA
5.5 V 32.768 kHz
X
X
X
IDD51
-
105
-
uA
3.0 V 32.768 kHz
X
X
V
IDD52
-
98
-
uA
3.0 V 32.768 kHz
X
X
X
IDD53
-
111
-
uA
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =10 kHz
while(1){}executed
from flash
VDD
LXT
LIRC
PLL
All digital
module
5.5 V
X
10 kHz
X
V
IDD54
-
109
-
uA
5.5 V
X
10 kHz
X
X
IDD55
-
96
-
uA
3.0 V
X
10 kHz
X
V
IDD56
-
94
-
uA
3.0 V
X
10 kHz
X
X
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
12 MHz
X
V
V
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =50 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =50 MHz
Aug. 17, 2018
IIDLE1
-
15.2
-
mA
IIDLE2
-
4.4
-
mA
5.5 V
12 MHz
X
V
X
IIDLE3
-
14.9
-
mA
3.0 V
12 MHz
X
V
V
IIDLE4
-
4.3
-
mA
3.0 V
12 MHz
X
V
X
VDD
HXT
HIRC
PLL
IIDLE5
-
19.3
-
mA
All digital
module
5.5 V
X
48 MHz
V
V
Page 124 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
while(1){}executed
from flash
IIDLE6
-
6.8
-
mA
5.5 V
X
48 MHz
V
X
VLDO=1.8 V
IIDLE7
-
19.1
-
mA
3.0 V
X
48 MHz
V
V
IIDLE8
-
6.8
-
mA
3.0 V
X
48 MHz
V
X
IIDLE9
-
14.7
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
12 MHz
X
V
V
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
IIDLE10
-
4.3
-
mA
5.5 V
12 MHz
X
V
X
IIDLE11
-
14.3
-
mA
3.0 V
12 MHz
X
V
V
IIDLE12
-
4.1
-
mA
3.0 V
12 MHz
X
V
X
IIDLE13
-
14.5
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
X
48 MHz
X
V
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
IIDLE14
-
3.7
-
mA
5.5 V
X
48 MHz
X
X
IIDLE15
-
14.2
-
mA
3.0 V
X
48 MHz
X
V
IIDLE16
-
3.6
-
mA
3.0 V
X
48 MHz
X
X
IIDLE17
-
7.2
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
24 MHz
X
X
V
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =24 MHz
while(1){}executed
from flash
IIDLE18
-
2.0
-
mA
5.5 V
24 MHz
X
X
X
IIDLE19
-
7.0
-
mA
3.0 V
24 MHz
X
X
V
IIDLE20
-
1.8
-
mA
3.0 V
24 MHz
X
X
X
IIDLE21
-
8.3
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
X
48/2 MHz
X
V
VLDO=1.8 V
IIDLE22
-
2.8
-
mA
5.5 V
X
48/2 MHz
X
X
IIDLE23
-
8.1
-
mA
3.0 V
X
48/2 MHz
X
V
IIDLE24
-
2.75
-
mA
3.0 V
X
48/2 MHz
X
X
VDD
HXT
HIRC
PLL
IIDLE25
-
4.7
-
mA
All digital
module
5.5 V
16 MHz
X
X
V
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =16 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =16 MHz
while(1){}executed
from flash
Aug. 17, 2018
IIDLE26
-
1.3
-
mA
5.5 V
16 MHz
X
X
X
IIDLE27
-
4.6
-
mA
3.0 V
16 MHz
X
X
V
IIDLE28
-
1.2
-
mA
3.0 V
16 MHz
X
X
X
VDD
HXT
HIRC
PLL
IIDLE29
-
6.3
-
mA
All digital
module
5.5 V
X
48/3 MHz
X
V
5.5 V
X
48/3 MHz
X
X
IIDLE30
-
2.6
-
mA
Page 125 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Operating Current
Idle Mode
HCLK =24 MHz
while(1){}executed
from flash
NUC121/125
SPECIFICATIONS
PARAMETER
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =12 MHz
while(1){}executed
from flash
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
IIDLE31
-
6.1
-
mA
3.0 V
X
48/3 MHz
X
V
IIDLE32
-
2.5
-
mA
3.0 V
X
48/3 MHz
X
X
IIDLE33
-
3.6
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
12 MHz
X
X
V
IIDLE34
-
1.0
-
mA
5.5 V
12 MHz
X
X
X
IIDLE35
-
3.5
-
mA
3.0 V
12 MHz
X
X
V
IIDLE36
-
0.9
-
mA
3.0 V
12 MHz
X
X
X
VDD
HXT
HIRC
PLL
IIDLE37
-
5.2
-
mA
All digital
module
5.5 V
X
48/4 MHz
X
V
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =12 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =4 MHz
while(1){}executed
from flash
IIDLE38
-
2.4
-
mA
5.5 V
X
48/4 MHz
X
X
IIDLE39
-
5.1
-
mA
3.0 V
X
48/4 MHz
X
V
IIDLE40
-
2.4
-
mA
3.0 V
X
48/4 MHz
X
X
IIDLE41
-
1.35
-
mA
VDD
HXT
HIRC
PLL
All digital
module
5.5 V
4 MHz
X
X
V
IIDLE42
-
0.48
-
mA
5.5 V
4 MHz
X
X
X
IIDLE43
-
1.28
-
mA
3.0 V
4 MHz
X
X
V
IIDLE44
-
0.43
-
mA
3.0 V
4 MHz
X
X
X
VDD
HXT
HIRC
PLL
IIDLE45
-
3.2
-
mA
All digital
module
5.5 V
X
48/12 MHz
X
V
VLDO=1.8 V
NUC121/125 SERIES DATASHEET
Operating Current
Idle Mode
HCLK =4 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IIDLE46
-
2.2
-
mA
5.5 V
X
48/12 MHz
X
X
IIDLE47
-
3.1
-
mA
3.0 V
X
48/12 MHz
X
V
IIDLE48
-
2.1
-
mA
3.0 V
X
48/12 MHz
X
X
IIDLE49
-
116
-
uA
VDD
LXT
LIRC
PLL
All digital
module
5.5 V 32.768 kHz
X
X
V
IIDLE50
-
110
-
uA
5.5 V 32.768 kHz
X
X
X
IIDLE51
-
101
-
uA
3.0 V 32.768 kHz
X
X
V
IIDLE52
-
95
-
uA
3.0 V 32.768 kHz
X
X
X
IIDLE53
-
109
-
uA
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =10 kHz
while(1){}executed
from flash
VLDO=1.8 V
Aug. 17, 2018
VDD
LXT
LIRC
PLL
All digital
module
5.5 V
X
10 kHz
X
V
IIDLE54
-
107
-
uA
5.5 V
X
10 kHz
X
X
IIDLE55
-
95
-
uA
3.0 V
X
10 kHz
X
V
Page 126 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
Standby Current
Power-down Mode
VLDO=1.8 V
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
IIDLE56
-
93
-
uA
IPWD1
-
6.7
-
uA
3.0 V
X
10 kHz
X
X
VDD
HXT/HIRC
LXT/LIRC
PLL
RAM
retention
5.5 V
X
LXT
X
V
IPWD2
-
6.8
-
uA
5.5 V
X
LIRC
X
V
IPWD3
-
7.4
-
uA
5.5 V
X
LXT & LIRC
X
V
IPWD4
-
6.1
uA
5.5 V
X
X
X
V
IPWD5
-
5.7
-
uA
3.0 V
X
LXT
X
V
IPWD6
-
5.8
-
uA
3.0 V
X
LIRC
X
V
IPWD7
-
6.3
-
uA
3.0 V
X
LXT & LIRC
X
V
IPWD8
-
5.1
-
uA
3.0 V
X
X
X
V
IIN
-
TBD
-
uA
VDD = 3.3V, VIN = 0.45V
Logic 0 Input Current
(Quasi-bidirectional
mode)
IIL
-
-68
-
uA
VDD = VDDIO = 5.5V, VIN = 0V
Logic 1 to 0 Transition
Current (Quasi[3]
bidirectional mode)
ITL
-
-600
-
uA
VDD = VDDIO = 5.5V, VIN = 2.0V
-
79
-
KΩ
VDD = VDDIO = 5.5V
-
143
-
KΩ
VDD = VDDIO = 3.3V
-
428
-
KΩ
VDD = VDDIO = 1.8V
-
0
-
A
-0.3
-
0.8
V
VDD = VDDIO = 4.5 V
-0.3
-
0.6
V
VDD = VDDIO = 2.5 V
-
0.58
-
V
2.0
-
VDD +
0.3
V
VDD = VDDIO = 5.5V
1.5
-
VDD +
0.3
V
VDD = VDDIO = 2.5V
Input Pull Up Resistor
RIN
Input Leakage Current
ILK
Input Low Voltage
(TTL input)
VIL1
Input Low Voltage
(TTL input for VDDIO
domain)
VIL2
Input High Voltage
(TTL input)
Aug. 17, 2018
VDD = VDDIO = 5.5V, 0 < VIN < VDD
Open-drain or input only mode
VDD = 2.5 ~ 5.5 V
VDDIO = 1.8 V
VIH1
Page 127 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Input Current at
[1]
nRESET
NUC121/125
NUC121/125 SERIES DATASHEET
Input High Voltage
(TTL input for VDDIO
domain)
VIH2
-
0.64
-
V
Input Low Voltage
(Schmitt input)
VIL3
-0.3
-
0.3VDD
V
VDD = VDDIO = 2.5 ~ 5.5 V
Input Low Voltage
(Schmitt input for VDDIO
domain)
VIL4
-0.3
-
0.3VDD
V
VDDIO = 1.8 ~ 5.5V
Input High Voltage
(Schmitt input)
VIH3
0.7VDD
-
VDD +
0.3
V
VDD = VDDIO = 2.5 ~ 5.5V
Input Low Voltage
(Schmitt input for VDDIO
domain)
VIH4
0.7VDDIO
-
VDDIO +
0.3
V
VDDIO = 1.8 ~ 5.5V
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
-
0.2VDD
-
V
Negative going
threshold
(Schmitt input),
nRESET
VIL5
-0.3
-
0.2VDD
V
Positive going
threshold
(Schmitt Input),
nRESET
VIH5
0.8VDD
-
VDD +
0.3
V
Internal nRESET pin
pull up resistor
RRST
-
17
-
KΩ
ISR1
-
-390
-
uA
VDD = VDDIO = 4.5V, VS = 2.4V
ISR2
-
-78
-
uA
VDD = VDDIO = 2.7V, VS = 2.2V
ISR3
-
-71
-
uA
VDD = VDDIO = 2.5V, VS = 2.0V
ISR4
-
21.2
-
uA
ISR5
-
-25
ISR6
-
-5
ISR7
-
(Push-pull Mode for
VDDIO domain)
ISR8
Sink Current
(Quasi-bidirectional,
Open-Drain and Push-
Source Current
(Quasi-bidirectional
Mode)
VDD = 2.5 ~ 5.5 V
VDDIO = 1.8 V
Source Current
(Quasi-bidirectional
Mode for VDDIO
domain)
Source Current
(Push-pull Mode)
VDDIO = 1.8V, VS = 1.6V
mA
VDD = VDDIO = 4.5V, VS = 2.4V
-
mA
VDD = VDDIO = 2.7V, VS = 2.2V
-4
-
mA
VDD = VDDIO = 2.5V, VS = 2.0V
-
1.51
-
mA
ISK1
-
15
-
mA
VDD = VDDIO = 4.5V, VS = 0.45V
ISK2
-
10
-
mA
VDD = VDDIO = 2.7V, VS = 0.45V
Source Current
Aug. 17, 2018
VDD = 2.5 ~ 5.5V
Page 128 of 148
VDD = 2.5 ~ 5.5V
VDDIO = 1.8V, VS = 1.6V
Rev 1.02
NUC121/125
pull Mode)
ISK3
-
9
-
mA
ISK4
-
6.51
-
mA
Higher GPIO Rising
Rate
HIORR1
-
1.76
-
ns
VDD = VDDIO = 5.5V, without capacitor
Basic GPIO Rising
Rate
BIORR1
-
3.12
-
ns
VDD = VDDIO = 5.5V, without capacitor
Higher GPIO Rising
Rate
HIORR2
-
3.73
-
ns
VDD = VDDIO = 3.3V, without capacitor
Basic GPIO Rising
Rate
BIORR2
-
5.97
-
ns
VDD = VDDIO = 3.3V, without capacitor
HIORR3
-
25
-
ns
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
BIORR3
-
27
-
ns
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
Higher GPIO Falling
Rate
HIOFR1
-
1.53
-
ns
VDD = VDDIO = 5.5V, without capacitor
Basic GPIO Falling
Rate
BIOFR1
-
3.02
-
ns
VDD = VDDIO = 5.5V, without capacitor
Higher GPIO Falling
Rate
HIOFR2
-
2.84
-
ns
VDD = VDDIO = 3.3V, without capacitor
Basic GPIO Falling
Rate
BIOFR2
-
6.08
-
ns
VDD = VDDIO = 3.3V, without capacitor
HIOFR3
-
8.69
-
ns
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
BIOFR3
-
20.28
-
ns
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
VDD = VDDIO = 2.5V, VS = 0.45V
Sink Current
(Quasi-bidirectional,
Open-Drain and Pushpull Mode for VDDIO
domain)
Higher GPIO Rising
Rate
(for VDDIO domain)
Basic GPIO Rising
Rate
(for VDDIO domain)
(for VDDIO domain)
Basic GPIO Falling
Rate
(for VDDIO domain)
VDDIO = 1.8V, VS = 1.6V
Note:
1. nRESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. All pins can source a transition current when they are externally driven from 1 to 0. In the condition of VDD = 5.5V, the
transition current reaches its maximum value when VIN approximates to 2V.
4. For ensuring power stability, a 1uF must be connected between LDO pin and the closest VSS pin of the device. Also
a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
Aug. 17, 2018
Page 129 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Higher GPIO Falling
Rate
VDD = 2.5 ~ 5.5V
NUC121/125
8.3 AC Electrical Characteristics
8.3.1
External 4~24 MHz High Speed Crystal (HXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Clock High Time
tCHCX
10
-
-
nS
Clock Low Time
tCLCX
10
-
-
nS
Clock Rise Time
tCLCH
2
-
15
nS
Clock Fall Time
tCHCL
2
-
15
nS
Input High Voltage
VIH
0.7VDD
-
VDD
V
Input Low Voltage
VIL
0
-
0.3VDD
V
tCLCL
tCLCH
VIH
90%
tCLCX
10%
VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
NUC121/125 SERIES DATASHEET
8.3.2
External 4~24 MHz High Speed Crystal (HXT) Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Oscillator frequency
fHXT
4
-
24
MHz
Temperature
THXT
-40
-
+105
C
-
0.74
-
mA
VDD = 5.5V @ 12MHz
Operating current
IHXT
-
0.61
-
mA
VDD = 3.3V @ 12MHz
8.3.2.1
VDD = 2.5 ~ 5.5V
Typical Crystal Application Circuits
CRYSTAL
4MHz ~ 24 MHz
Aug. 17, 2018
C1
C2
R1
20pF
20pF
without
Page 130 of 148
Rev 1.02
NUC121/125
XT_OUT
XT_IN
R1
C2
C1
Figure 8.3-1 Typical Crystal Application Circuit
8.3.3
External 32.768 kHz Low Speed Crystal (LXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
tCHCX
TBD
-
-
nS
Clock Low Time
tCLCX
TBD
-
-
nS
Clock Rise Time
tCLCH
TBD
-
TBD
nS
Clock Fall Time
tCHCL
TBD
-
TBD
nS
0.7VDD
-
VDD
V
0
-
0.3VDD
V
LXT Input Pin Input High
Voltage
Xin_VIH
LXT Input Pin Input Low
Voltage
Xin_VIL
NUC121/125 SERIES DATASHEET
Clock High Time
tCLCL
tCLCH
90%
Xin_VIH
tCLCX
Xin_VIL
10%
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.3.4
External 32.768 kHz Low Speed Crystal (LXT) Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Aug. 17, 2018
TYP.
MAX. UNIT
Page 131 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Oscillator frequency
fLXT
-
32.768
-
kHz
Temperature
TLXT
-40
-
+105
C
Operating current
ILXT
1.15
-
8.3.4.1
0.58
-
VDD = 2.5 ~ 5.5V
A
VDD = 5.5V
A
VDD = 3.3V
Typical Crystal Application Circuits
CRYSTAL
32.768 kHz
C3
C4
R2
20pF
20pF
without
XT_OUT
XT_IN
R2
C4
C3
NUC121/125 SERIES DATASHEET
Figure 8.3-2 Typical Crystal Application Circuit
8.3.4.2
Internal 48 MHz High Speed RC Oscillator (HIRC)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Supply voltage
[1]
VHRC
Center Frequency
Calibrated Internal
Oscillator Frequency
1.62
1.8
1.98
V
-
48
-
MHz
TA = 25C, VDD = 3.3V
-2
-
+2
%
-40C ~ +105C,
VDD = 2.5 ~ 5.5V
-40C ~ +105 C,
VDD = 2.5 ~ 5.5V
fHRC
-0.25
Aug. 17, 2018
TYP. MAX. UNIT
-
+0.25
Page 132 of 148
%
Enable 32.768K crystal
oscillator or internal USB
synchronous mode, and set
SYS_IRCTCTL[1:0]=”10”
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Operating current
8.3.4.3
TYP. MAX. UNIT
-
431
-
A
VDD = 5.5 V
-
430
-
A
VDD = 3.3 V
IHRC
Internal 10 kHz Low Speed RC Oscillator (LIRC)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Supply voltage
[1]
VLRC
Center Frequency
Calibrated Internal
Oscillator Frequency
Operating current
FLRC
TYP. MAX. UNIT
1.62
1.8
1.98
V
-
10
-
kHz
25C, VDD = 3.3V
-30
-
+30
%
25 C,
VDD = 2.5 ~ 5.5V
-50
-
+50
%
-40C ~+105 C,
VDD = 2.5 ~ 5.5V
-
0.74
-
A
VDD = 5.5V
A
VDD = 3.3V
ILRC
0.66
Note: Internal oscillator operation voltage comes from LDO.
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 133 of 148
Rev 1.02
NUC121/125
8.4 Analog Characteristics
8.4.1
12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Operating voltage
AVDD
3.0
-
5.5
V
Operating current (AVDD
current)
IADC1
-
2.72
-
mA
AVDD = VDD = 4.5V
ADC Clock Rate = 16 MHz
(Enable ADC and disable all
other analog modules)
IADC2
A
AVDD = VDD = 2.5V
ADC Clock Rate = 6 MHz
Resolution
RADC
-
-
12
Bit
Reference voltage
VREF
-
AVDD
-
V
ADC input voltage
VIN
0
-
AVDD
V
-
-
16
MHz
AVDD = 5 V
-
-
8
MHz
AVDD = 3 V
ADC Clock frequency
AVDD = VDD
AVDD = 5V
FADC
Acquisition Time (Sample
Stage)
TACQ
2
7
21
1/FADC Default: 7 (1/FADC)
Conversion time
TCONV
15
20
34
1/FADC
TCONV = TACQ + 13
Default: 20 (1/FADC)
AVDD = 5V
NUC121/125 SERIES DATASHEET
-
-
800
kSPS
FADC = 16 MHz
Conversion Rate
(FADC/TCONV)
TCONV = 20 clock
FSPS
AVDD = 3V
-
-
300
kSPS
TCONV = 20 clock
FADC = 6 MHz
Integral Non-Linearity Error
INL
+1.6
-
+2.1
LSB
Differential Non-Linearity
DNL
-1
-
-1.5
LSB
Gain error
EG
-3.4
-
-4.7
LSB
Offset error
EOFFSET
+2.2
-
+3.6
LSB
EABS
+3.1
-
+4.7
LSB
Internal Capacitance
CIN
-
3.2
-
pF
Input Load
RIN
-
6
-
kΩ
Monotonic
-
Absolute error
Aug. 17, 2018
Guaranteed
Page 134 of 148
-
Rev 1.02
NUC121/125
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Typical connection diagram using the ADC
VDD
(1)
AINx
RIN
12-bit
Converter
(1)
CIN
Note: GND < AINX < VDD
Aug. 17, 2018
Page 135 of 148
Rev 1.02
NUC121/125 SERIES DATASHEET
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
NUC121/125
8.4.2
LDO
Symbol
Parameter
Min
Typ
Max
Unit
VDD
DC Power Supply
2.5
-
5.5
V
VLDO
Output Voltage
1.62
1.8
1.98
V
TA
Temperature
-40
25
+105
℃
Test Condition
Note 1: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS
pin of the device.
Note 2: For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin
and the closest VSS pin of the device.
8.4.3
Low-Voltage Reset
Symbol
Parameter
Min
Typ
Max
Unit
AVDD
Supply Voltage
0
-
5.5
V
TA
Temperature
-40
-
+105
℃
-
ILVR
Quiescent Current
-
1.1
-
uA
AVDD = 5.5V
2.1
2.2
2.3
V
TA = 85℃
2.0
2.1
2.2
V
TA = 25℃
1.9
2.0
2.1
V
TA = -40℃
-
129
-
uS
VPOR
NUC121/125 SERIES DATASHEET
TLVR_Start
8.4.4
Threshold Voltage
Start-up Time
Test Condition
Brown-out Detector
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AVDD
Supply Voltage
0
-
5.5
V
-
TA
Temperature
-40
-
+105
℃
-
IBOD
Quiescent Current
-
81
-
μA
AVDD = 5.5V
4.3
4.5
4.7
V
BODVL [1:0] = 11
Brown-out Voltage
3.5
3.7
3.9
V
BODVL [1:0] = 10
(Falling edge)
2.55
2.7
2.85
V
BODVL [1:0] = 01
2.05
2.2
2.35
V
BODVL [1:0] = 00
4.3
4.6
.4.7
V
BODVL [1:0] = 11
VBOD
VBOD
Aug. 17, 2018
Brown-out Voltage
Page 136 of 148
Rev 1.02
NUC121/125
(Rising edge)
TBOD_Start
8.4.5
Start-up Time
3.6
3.8
4.0
V
BODVL [1:0] = 10
2.6
2.75
2.9
V
BODVL [1:0] = 01
2.1
2.25
2.4
V
BODVL [1:0] = 00
-
1060
-
uS
Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
-
+105
℃
-
VPOR
Threshold Voltage
1.5
2
2.2
V
-
VHYS
Power Drop Detect Voltage
1.78
V
VPOR
VHYS
t (don’t care)
Figure 8.4-1 Power-up Ramp Condition
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 137 of 148
Rev 1.02
NUC121/125
8.4.6
Temperature Sensor
SPECIFICATIONS
PARAMETER
TEST CONDITION
(supply voltage = 3V)
SYM.
MIN.
TYP.
MAX. UNIT
Detection Temperature
TDET
-40
-
+105
o
Operating current
ITEMP
6.4
-
10.5
A
Gain
VTG
-1.8
-1.76
-1.73
mV/ C
Offset
VTO
-
725
-
mV
C
o
o
Temperature at 0 C
Note 1: Internal operation voltage comes from LDO.
Note 2: The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃ ) x Temperature (℃) + Offset (mV)
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 138 of 148
Rev 1.02
NUC121/125
8.4.7
USB PHY
8.4.7.1
Low-full-Speed DC Electrical Specifications
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
2.0
-
-
V
-
-
-
0.8
V
-
0.2
-
-
V
|PADP-PADM|
0.8
-
2.5
V
Includes VDI range
0.8
-
2.0
V
-
Receiver Hysteresis
-
200
-
mV
-
VOL
Output Low (driven)
0
-
0.3
V
-
VOH
Output High (driven)
2.8
-
3.6
V
-
VCRS
Output Signal Cross Voltage
1.3
-
2.0
V
-
RPU
Pull-up Resistor
1.425
-
1.575
kΩ
-
RPD
Pull-down Resistor
14.25
-
15.75
kΩ
VTRM
TERMINATION Voltage for
Uptream port pull up (RPU)
3.0
-
3.6
V
ZDRV
Driver Output Resistance
-
10
-
Ω
Steady state drive*
CIN
Transceiver Capacitance
-
-
20
pF
Pin to GND
VIH
Input High (driven)
VIL
Input Low
VDI
Differential Input Sensitivity
VCM
VSE
Differential
Common-mode Range
Single-ended Receiver
Threshold
8.4.7.2
USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
TFR
Rise Time
4
-
20
ns
CL=50p
TFF
Fall Time
4
-
20
ns
CL=50p
Rise and Fall Time Matching
90
-
111.11
%
TFRFF=TFR/TFF
Min.
Typ.
Max.
Unit
Test Conditions
TFRFF
8.4.7.3
USB LDO Specification
Symbol
Parameter
VBUS
VBUS Pin Input Voltage
4.0
5.0
5.5
V
-
VDD33
LDO Output Voltage
3.0
3.3
3.6
V
-
-
1.0
-
uF
-
Cbp
External Bypass Capacitor
Aug. 17, 2018
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NUC121/125 SERIES DATASHEET
*Driver output resistance doesn’t include series resistor resistance.
NUC121/125
8.5 Flash DC Electrical Characteris
Symbol
Parameter
Min
Typ
Max
Unit
Supply Voltage
1.62
1.8
1.98
V
NENDUR
Endurance
20,000
-
-
cycles
TRET
Data Retention
100
-
-
year
TERASE
Page Erase Time
20
-
40
mS
TMER
Mass Erase Time
20
-
40
mS
TPROG
Program Time
20
-
40
uS
IDD1
Read Current
-
-
TBD
mA
IDD2
Program Current
-
-
TBD
mA
IDD3
Erase Current
-
-
TBD
uA
[1]
VFLA
Test Condition
[2]
TA = 25℃
Note 1: VFLA is source from chip LDO output voltage.
Note 2: Number of program/erase cycles.
Note 3: This table is guaranteed by design, not test in production.
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
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NUC121/125
8.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Symbol
Fast Mode[1][2]
Unit
Parameter
Min.
Max.
Min.
Max.
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH
SCL high period
4
-
0.6
-
uS
4.7
-
1.2
-
uS
tSU; STA
Repeated START condition setup time
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
STOP condition setup time
4
-
0.6
-
uS
Bus free time
4.7[3]
-
1.2[3]
-
uS
tSU;DAT
Data setup time
250
-
100
-
nS
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
tBUF
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Notes:
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
2
Figure 8.6-1 I C Timing Diagram
Aug. 17, 2018
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Rev 1.02
NUC121/125 SERIES DATASHEET
1. Guaranteed by design, not tested in production.
2
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I C frequency. It must
2
be higher than 8 MHz to achieve the maximum fast mode I C frequency.
2
3. I C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch
the low period of SCL signal.
NUC121/125
8.7 SPI Dynamic Characteristics
8.7.1
Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
Data setup time
4
2
-
ns
tDH
Data hold time
0
-
-
ns
tV
Data output valid time
-
7
11
ns
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tDS
Data setup time
5
3
-
ns
tDH
Data hold time
0
-
-
ns
tV
Data output valid time
-
13
18
ns
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
Data Valid
tDS
NUC121/125 SERIES DATASHEET
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDH
Data Valid
tV
Data Valid
MOSI
tDS
MISO
Data Valid
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDH
Data Valid
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2*PCLK+4
-
-
ns
tV
Data output valid time
-
2*PCLK+11
2*PCLK+19
ns
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
Aug. 17, 2018
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Rev 1.02
NUC121/125
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2*PCLK+6
-
-
ns
tV
Data output valid time
-
2*PCLK+19
2*PCLK+25
ns
CLKP=0
SPICLK
CLKP=1
tDS
MOSI
Data Valid
tDH
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
MISO
Data Valid
tDS
MOSI
Data Valid
tDH
Data Valid
Data Valid
Data Valid
Data Valid
tv
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
Figure 8.7-2 SPI Slave Mode Timing Diagram
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 143 of 148
Rev 1.02
NUC121/125
9
PACKAGE DIMENSIONS
9.1 LQFP 64S (7x7x1.4 mm)
NUC121/125 SERIES DATASHEET
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Page 144 of 148
Rev 1.02
NUC121/125
9.2 LQFP 48L (7x7x1.4 mm)
H
36
25
37
24
48
13
H
12
1
NUC121/125 SERIES DATASHEET
Controlling dimension : Millimeters
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Y
0
Aug. 17, 2018
Dimension in inch
Dimension in mm
Min Nom Max
Min Nom Max
0.002 0.004
0.006
0.05
0.055
0.057
1.35
1.40
1.45
0.006 0.008
0.010
0.15
0.20
0.25
0.004 0.006
0.008
0.10
0.15
0.20
0.272 0.276
0.280
6.90
7.00
7.10
0.272 0.276
0.280
6.90
7.00
7.10
0.020
0.026
0.35
0.50
0.65
0.053
0.014
0.10
0.15
0.350
0.354
0.358
8.90
9.00
9.10
0.350
0.354
0.358
8.90
9.00
9.10
0.018
0.024
0.030
0.45
0.60
0.75
1.00
0.039
0.004
0
7
Page 145 of 148
0.10
0
7
Rev 1.02
NUC121/125
9.3 QFN 33Z (5x5x0.8 mm)
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
Page 146 of 148
Rev 1.02
NUC121/125
10 REVISION HISTORY
Revision
Date
Description
1.00
2017.02.15
Preliminary version
1.01
1.02
2017.12.14
2018.08.17
1.
Fixed the typo of Operating Current Normal Run Mode HCLK = 50
MHz in section 8.2 DC Electrical Characteristics.
2.
Fixed the number of ADC channel in Table 4.1-2.
3.
Fixed Internal Reference Voltage to Internal Voltage (Band-gap) in
Figure 6.2-7.
1.
Removed the ICE_DAT and ICE_CLK description from PF.2 and
PF.3 in section 4.2 and 4.3.
NUC121/125 SERIES DATASHEET
Aug. 17, 2018
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Rev 1.02
NUC121/125
NUC121/125 SERIES DATASHEET
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Aug. 17, 2018
Page 148 of 148
Rev 1.02
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