T8 Data Sheet
DST8-v3.8
November 2021
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Copyright © 2021. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.
T8 Data Sheet
Contents
Introduction..................................................................................................................................... 4
Features............................................................................................................................................4
Available Package Options...................................................................................................................... 5
Device Core Functional Description................................................................................................6
XLR Cell.......................................................................................................................................................6
Logic Cell....................................................................................................................................................7
Embedded Memory..................................................................................................................................7
Multipliers................................................................................................................................................... 8
Global Clock Network.............................................................................................................................. 8
Clock and Control Distribution Network....................................................................................9
Global Clock Location (QFP144)................................................................................................. 9
Device Interface Functional Description....................................................................................... 11
Interface Block Connectivity.................................................................................................................. 11
General-Purpose I/O Logic and Buffer................................................................................................ 12
I/O Banks.................................................................................................................................................. 13
T8 BGA49 and BGA81 Interface Description..................................................................................... 14
Simple I/O Buffer......................................................................................................................... 14
Simple PLL.....................................................................................................................................15
Oscillator....................................................................................................................................... 16
T8 QFP144 Interface Description......................................................................................................... 17
Complex I/O Buffer..................................................................................................................... 17
Advanced PLL............................................................................................................................... 19
LVDS............................................................................................................................................. 22
Power Up Sequence...................................................................................................................... 26
Power Supply Current Transient............................................................................................................26
Configuration.................................................................................................................................27
Supported Configuration Modes..........................................................................................................28
Mask-Programmable Memory Option..................................................................................................28
DC and Switching Characteristics (BGA49 and BGA81)............................................................... 29
DC and Switching Characteristics (QFP144).................................................................................32
LVDS I/O Electrical and Timing Specifications (QFP144)............................................................. 36
ESD Performance........................................................................................................................... 36
Configuration Timing.................................................................................................................... 37
Maximum tUSER for SPI Active and Passive Modes............................................................................. 39
PLL Timing and AC Characteristics (BGA49 and BGA81)..............................................................40
PLL Timing and AC Characteristics (QFP144)............................................................................... 41
Internal Oscillator (BGA49 and BGA81)........................................................................................41
Pinout Description.........................................................................................................................42
Efinity Software Support............................................................................................................... 45
T8 Interface Floorplan...................................................................................................................45
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T8 Data Sheet
Ordering Codes............................................................................................................................. 46
Revision History.............................................................................................................................47
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T8 Data Sheet
Introduction
The T8 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped
with an I/O interface in a small footprint package for easy integration. T8 FPGAs support
mobile, consumer, and IoT edge markets that need low power, low cost, and a small form
factor. With ultra-low power T8 FPGAs, designers can build products that are always on,
providing enhanced capabilities for applications such as embedded vision, voice and gesture
recognition, intelligent sensor hubs, and power management.
Features
• High-density, low-power Quantum™ architecture
• Built on SMIC 40 nm process
• Less than 150 μA typical core leakage current at 1.1 V(1)
• Ultra-small footprint package options
• FPGA interface blocks
— GPIO
— PLL
— LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs(2)
— Oscillator
• Programmable high-performance I/O
— Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces(3)
• Flexible on-chip clocking
— 12 low-skew global clock signals can be driven from off-chip external clock signals or
PLL synthesized clock signals
— PLL support
• Flexible device configuration
— Standard SPI interface (active, passive, and daisy chain)
— JTAG interface
— Optional Mask Programmable Memory (MPM) capability
• Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1: T8 FPGA Resources
(1)
(2)
(3)
(4)
LEs(4)
Dedicated
Global Clocks
Dedicated
Global Controls
Embedded
Memory (kbits)
Embedded
Memory Blocks
(5 Kbits)
Embedded
Multipliers
7,384
Up to 16
Up to 8
122.88
24
8
BGA49 and BGA81 packages only.
LVDS pins are only available in QFP144 packages.
LVDS pins used as GPIO only support 3.3 V.
Logic capacity in equivalent LE counts.
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T8 Data Sheet
Table 2: T8 FPGA Package-Dependent Resources
Resource
BGA49
BGA81
QFP144
Available GPIO(5)
33
55
97
Global clocks from
GPIO pins
4
8
6
Global controls from
GPIO pins
5
8
8
PLL (simple)
1
1
–
PLL (advanced)
–
–
5
Oscillator
1
1
–
MPM
1 (optional)
1 (optional)
1 (optional)
LVDS
–
–
6 TX pairs
6 RX pairs
Learn more: Refer to the Trion Packaging User Guide for the package outlines and markings.
Available Package Options
Table 3: Available Packages
Package
(5)
(6)
Dimensions (mm x mm)
Pitch (mm)
49-ball FBGA(6)
3x3
0.4
81-ball FBGA
5x5
0.5
144-pin QFP
20 x 20
0.5
The LVDS I/O pins are dual-purpose. The full number of GPIO are available when all LVDS I/O pins are in GPIO mode.
GPIO and LVDS as GPIO supports different features. See Table 9: Supported Features for GPIO and LVDS as GPIO on
page 13.
This package does not have dedicated JTAG pins (TDI, TDO, TCK, TMS).
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T8 Data Sheet
Device Core Functional Description
T8 FPGAs feature an eXchangeable Logic and Routing (XLR) cell that Efinix has optimized
for a variety of applications. Trion® FPGAs contain three building blocks constructed from
XLR cells: logic elements, embedded memory blocks, and multipliers. Each FPGA in the
Trion® family has a custom number of building blocks to fit specific application needs. As
shown in the following figure, the FPGA includes I/O ports on all four sides, as well as
columns of XLR cells, memory, and multipliers. A control block within the FPGA handles
configuration.
Figure 1: T8 FPGA Block Diagram
Device Interface
Some Packages Have Interfaces
on Top and Bottom
Quantum Fabric
Device Interface
XLR Cells and Routing
Multiplier
Embedded Memory
Device Interface
I/O Ports from Core to Device Interface
Each Device Contains Unique
Interface Blocks such as GPIO
and PLL
Note: The number and locations of rows and
columns are shown for illustration purposes
only. The actual number and position depends
on the core.
Device Interface
XLR Cell
The eXchangeable Logic and Routing (XLR) cell is the basic building block of the Quantum™
architecture. The Efinix XLR cell combines logic and routing and supports both functions
interchangeably. This unique innovation greatly enhances the transistor flexibility and
utilization rate, thereby reducing transistor counts and silicon area significantly.
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T8 Data Sheet
Logic Cell
The logic cell comprises a 4-input LUT or a full adder plus a register (flipflop). You can
program each LUT as any combinational logic function with four inputs. You can configure
multiple logic cells to implement arithmetic functions such as adders, subtractors, and
counters.
Figure 2: Logic Cell Block Diagram
I[3:0]
Clock
4-Input LUT
LUT Out
Flipflop
Clock Enable
Preset/Reset
Register Out
Adder
Carry Out
Carry In
Embedded Memory
The core has 5-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory
blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, FIFOs,
or ROM. You can initialize the memory content during configuration. The Efinity® software
includes a memory cascading feature to connect multiple blocks automatically to form a
larger array. This feature enables you to instantiate deeper or wider memory modules.
The memory read and write ports have the following modes for addressing the memory
(depth x width):
256 x 16
1024 x 4
4096 x 1
512 x 10
512 x 8
2048 x 2
256 x 20
1024 x 5
The read and write ports support independently configured data widths.
Figure 3: Embedded Memory Block Diagram (True Dual-Port Mode)
Write Data A [9:0]
Address A [11:0]
Write Enable A
Clock A
Clock Enable A
Read Data A [9:0]
Embedded
Memory
Write Data B [9:0]
Address B [11:0]
Write Enable B
Clock B
Clock Enable B
Read Data B [9:0]
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T8 Data Sheet
Multipliers
The FPGA has high-performance multipliers that support 18 x 18 fixed-point multiplication.
Each multiplier takes two signed 18-bit input operands and generates a signed 36-bit output
product. The multiplier has optional registers on the input and output ports.
Figure 4: Multiplier Block Diagram
Operand A [17:0]
Multiplier
Operand B [17:0]
Clock
Multiplier Output [35:0]
Clock Enable Output
Set/Reset Output
Clock Enable A
Set/Reset A
Clock Enable B
Set/Reset B
Global Clock Network
The Quantum™ core fabric supports up to 16 global clock (GCLK) signals feeding 16 prebuilt global clock networks. Global clock pins (GPIO), PLL outputs, oscillator output, and
core-generated clocks can drive the global clock network.
The global clock networks are balanced clock trees that feed all FPGA modules. Each
network has dedicated clock-enable logic to save power by disabling the clock tree at the
root. The logic dynamically enables/disables the network and guarantees no glitches at the
output.
Figure 5: Global Clock Network
Binary Clock Tree
Distribution
GCLK [0:7]
GCLK [8:15]
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T8 Data Sheet
Clock and Control Distribution Network
The global clock network is distributed through the device to provide clocking for the core's
LEs, memory, multipliers, and I/O blocks. Designers can access the T8 global clock network
using the global clock GPIO pins, PLL outputs, oscillator output, and core-generated clocks.
Similarly, the T8 has GPIO pins (the number varies by package) that the designer can
configure as control inputs to access the high-fanout network connected to the LE's set, reset,
and clock enable signals.
Learn more: Refer to the T8 pinout for information on the location and names of these pins.
Global Clock Location (QFP144)
The following tables describe the location of the global clock signals in T8
FPGAs QFP144 package.
Table 4: Left Clock Input from GPIO Pins
Function
Name
Resource
Name
GCLK[0]
GCLK[1]
GCLK[2]
GCLK[3]
GCLK[4]
GCLK[5]
GCLK[6]
GCLK[7]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CLK0
GPIOL_24
CLK1
GPIOL_25
–
CLK2
GPIOL_26
–
–
CLK3
GPIOL_27
–
–
–
CLK4
GPIOL_28
–
–
–
CLK5
GPIOL_29
–
–
–
–
CLK6
GPIOL_30
–
–
–
–
–
CLK7
GPIOL_31
–
–
–
–
–
GCLK[6]
–
–
–
Table 5: Left Clock from PLL OUTCLK Signal
PLL
Reference
PLL_TL0
PLL_TL1
CLKOUT
GCLK[0]
CLKOUT0
GCLK[1]
GCLK[2]
GCLK[3]
GCLK[4]
GCLK[5]
–
–
–
–
–
GCLK[7]
–
CLKOUT1
–
–
–
–
–
–
CLKOUT2
–
–
–
–
–
–
CLKOUT0
–
–
–
–
–
–
CLKOUT1
–
–
–
–
–
–
CLKOUT2
–
–
–
–
–
–
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T8 Data Sheet
Table 6: Right Clock Input from GPIO Pins
Function
Name
Resource
Name
GCLK[8]
GCLK[9] GCLK[10] GCLK[11] GCLK[12] GCLK[13] GCLK[14] GCLK[15]
CLK0
GPIOR_127
–
–
–
CLK1
GPIOR_126
–
–
–
–
CLK2
GPIOR_125
–
–
–
–
–
CLK3
GPIOR_124
–
–
–
–
–
–
CLK4
GPIOR_123
–
–
–
–
–
–
CLK5
GPIOR_122
–
–
–
–
–
–
CLK6
GPIOR_121
–
–
–
–
–
CLK7
GPIOR_120
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 7: Right Clock from PLL OUTCLK Signal
PLL
Reference
PLL_TR0
PLL_TR1
PLL_BR0
CLKOUT
GCLK[8]
CLKOUT0
GCLK[9] GCLK[10] GCLK[11] GCLK[12] GCLK[13] GCLK[14] GCLK[15]
–
–
–
–
–
–
CLKOUT1
–
–
–
–
–
–
CLKOUT2
–
–
–
–
–
–
CLKOUT0
–
–
–
–
–
–
CLKOUT1
–
–
–
–
–
–
CLKOUT2
–
–
–
–
–
–
–
–
–
–
–
–
CLKOUT0
CLKOUT1
–
–
–
–
–
–
CLKOUT2
–
–
–
–
–
–
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T8 Data Sheet
Device Interface Functional Description
The device interface wraps the core and routes signals between the core and the device
I/O pads through a signal interface. Because they use the flexible Quantum™ architecture,
devices in the Trion® family support a variety of interfaces to meet the needs of different
applications.
Learn more: The following sections describe the available device interface features in T8 FPGAs. Refer to
the Trion® Interfaces User Guide for details on the Efinity® Interface Designer settings.
Interface Block Connectivity
The FPGA core fabric connects to the interface blocks through a signal interface. The
interface blocks then connect to the package pins. The core connects to the interface blocks
using three types of signals:
• Input—Input data or clock to the FPGA core
• Output—Output from the FPGA core
• Clock output—Clock signal from the core clock tree
Figure 6: Interface Block and Core Connectivity
FPGA
Interface
Block
Interface
Block
Signal
Interface
Input
Output
Core
Input
Output
Clock Output
Clock Output
Input
Output
Input
Output
Clock Output
Clock Output
Interface
Block
Interface
Block
GPIO
GPIO blocks are a special case because they can operate in several modes. For example, in
alternate mode the GPIO signal can bypass the signal interface and directly feed another
interface block. So a GPIO configured as an alternate input can be used as a PLL reference
clock without going through the signal interface to the core.
When designing for Trion® FPGAs, you create an RTL design for the core and also configure
the interface blocks. From the perspective of the core, outputs from the core are inputs to the
interface block and inputs to the core are outputs from the interface block.
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T8 Data Sheet
The Efinity netlist always shows signals from the perspective of the core, so some signals do
not appear in the netlist:
• GPIO used as reference clocks are not present in the RTL design, they are only visible in
the interface block configuration of the Efinity® Interface Designer.
• The FPGA clock tree is connected to the interface blocks directly. Therefore, clock
outputs from the core to the interface are not present in the RTL design, they are only
part of the interface configuration (this includes GPIO configured as output clocks).
The following sections describe the different types of interface blocks in the T8. Signals and
block diagrams are shown from the perspective of the interface, not the core.
General-Purpose I/O Logic and Buffer
The GPIO support the 3.3 V LVTTL and 1.8 V, 2.5 V, and 3.3 V LVCMOS I/O standards.
The GPIOs are grouped into banks. Each bank has its own VCCIO that sets the bank voltage
for the I/O standard.
Each GPIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the
I/O buffers. I/O buffers are located at the periphery of the device.
The I/O logic comprises three register types:
• Input—Capture interface signals from the I/O before being transferred to the core logic
• Output—Register signals from the core logic before being transferred to the I/O buffers
• Output enable—Enable and disable the I/O buffers when I/O used as output
Table 8: GPIO Modes
GPIO Mode
Input
Description
Only the input path is enabled; optionally registered. If registered, the input path uses the input
clock to control the registers (positively or negatively triggered).
Select the alternate input path to drive the alternate function of the GPIO. The alternate path
cannot be registered.
QFP144 packages: In DDIO mode, two registers sample the data on the positive and negative
edges of the input clock, creating two data streams.
Output
Only the output path is enabled; optionally registered. If registered, the output path uses the
output clock to control the registers (positively or negatively triggered).
The output register can be inverted.
QFP144 packages: In DDIO mode, two registers capture the data on the positive and negative
edges of the output clock, multiplexing them into one data stream.
Bidirectional
The input, output, and OE paths are enabled; optionally registered. If registered, the input clock
controls the input register, the output clock controls the output and OE registers. All registers can
be positively or negatively triggered. Additionally, the input and output paths can be registered
independently.
The output register can be inverted.
Clock output
Clock output path is enabled.
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T8 Data Sheet
Table 9: Supported Features for GPIO and LVDS as GPIO
LVDS as GPIO are LVDS pins that act as GPIOs instead of the LVDS function.
Package
BGA49
GPIO
Schmitt Trigger
BGA81
Variable Drive Strength
LVDS as GPIO
–
Pull-up
Pull-down
Slew Rate
QFP144
DDIO
Schmitt Trigger
Pull-up
Variable Drive Strength
Pull-up
Pull-down
Slew Rate
Important: Efinix® recommends that you limit the number of LVDS as GPIO set as output and
bidirectional to 16 per bank to avoid switching noise. The Efinity software issues a warning if you exceed
the recommended limit.
During configuration, all GPIO pins excluding LVDS as GPIO are configured in weak pullup mode.
During user mode, unused GPIO pins are tri-stated and configured in weak pull-up mode.
You can change the default mode to weak pull-down in the Interface Designer.
Note: Refer to Table 35: Single-Ended I/O Buffer Drive Strength Characteristics on page 30 and Table
47: Single-Ended I/O Buffer Drive Strength Characteristics on page 34 for more information.
I/O Banks
Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has
independent power pins. The number and voltages supported vary by FPGA and package.
The number of banks and the voltages they support vary by package.
Some I/O banks are merged at the package level by sharing VCCIO pins. Merged banks have
underscores (_) between banks in the name (e.g., 1B_1C means 1B and 1C are connected).
Table 10: I/O Banks by Package
Package
I/O Banks
Voltage (V)
Banks with
DDIO Support
Merged Banks
BGA49, BGA81
1A - 1C, 2A, 2B
1.8, 2.5, 3.3
–
–
QFP144
1A - 1E, 3A - 3E
1.8, 2.5, 3.3
1B, 1C, 1D,
3B, 3C, 3D, 3E
1C_1D, 3B_3C
4A, 4B
3.3
–
–
Learn more: Refer to the T8 pinout for information on the I/O bank assignments.
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T8 Data Sheet
T8 BGA49 and BGA81 Interface Description
T8 FPGAs in BGA49 and BGA81 packages have simple general-purpose I/O logic and
buffers, I/O banks, a simple PLL, and an oscillator.
Simple I/O Buffer
Figure 7: I/O Interface Block
Table 11: GPIO Signals
Signal
Direction
Description
IN
Output
Input data from the GPIO pad to the core fabric.
ALT
Output
Alternative input connection (in the Interface Designer, the input
Register Option is none). Alternative connections are GCLK, GCTRL, and
PLL_CLKIN.
OUT
Input
Output data to GPIO pad from the core fabric.
OE
Input
Output enable from core fabric to the I/O block. Can be registered.
OUTCLK
Input
Core clock that controls the output and OE register. This clock is not
visible in the user netlist.
INCLK
Input
Core clock that controls the input register. This clock is not visible in the
user netlist.
Table 12: GPIO Pads
Signal
IO
Direction
Bidirectional
Description
GPIO pad.
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T8 Data Sheet
Simple PLL
T8 FPGAs in BGA49 and BGA81 packages have a simple PLL.
The T8 has 1 PLL to synthesize clock frequencies. The PLL's reference clock input comes
from a dedicated GPIO's alternate input pin. The PLL consists of a pre-divider counter (N
counter), a feedback multiplier counter (M counter), post-divider counter (O counter), and an
output divider per clock output.
Figure 8: T8 PLL Block Diagram
PLL
CLKIN
FIN
N
Counter
FPFD
Phase
Frequency
Detector
Charge
Pump
Voltage
Control
Oscillator
Loop
Filter
FVCO
M
Counter
RSTN
FOUT
O
Counter
Output
Divider
The counter settings define the PLL output frequency:
LOCKED
CLKOUT0
CLKOUT1
CLKOUT2
where:
FPFD = FIN / N
FVCO is the voltage control oscillator frequency
FOUT = FVCO / (O x Output divider)
FIN is the reference clock frequency
FVCO = FPFD x M
FOUT is the output clock frequency
FPFD is the phase frequency detector input frequency
Note: The reference clock must be between 10 and 50 MHz.
The PFD input must be between 10 and 50 MHz.
The VCO frequency must be between 500 and 1,500 MHz.
Unlike other Trion® FPGAs, the T8 simple PLL output locks on the negative clock edge
(not the positive edge). When you are using two or more clock outputs, they are aligned
on the falling edge. If the core register receiving the clock is positive edge triggered, Efinix
recommends inverting the clock outputs so they are correctly edge aligned.
Figure 9: Simple PLL Output Aligned with Negative Edge
PLL Output (Negative Edge)
Inverted PLL Output (Positive Edge)
CLKOUT0
CLKOUT0
CLKOUT1
CLKOUT1
CLKOUT2
CLKOUT2
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T8 Data Sheet
Table 13: PLL Pins
Port
Direction
Description
CLKIN
Input
Reference clock. This port is also a GPIO pin; the GPIO pins' alternate
function is configured as a reference clock.
RSTN
Input
Active-low PLL reset signal. When asserted, this signal resets the PLL;
when de-asserted, it enables the PLL. Connect this signal in your design to
power up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10
ns to reset the PLL.
CLKOUT0
CLKOUT1
Output
PLL output. The designer can route these signals as input clocks to the
core's GCLK network.
Output
Goes high when PLL achieves lock; goes low when a loss of lock is
detected. Connect this signal in your design to monitor the lock status.
This signal is analog asynchronous.
CLKOUT2
LOCKED
Table 14: PLL Settings
Configure these settings in the Efinity® Interface Designer.
Setting
Allowed Values
Notes
N counter
1 - 15 (integer)
Pre-divider
M counter
1 - 255 (integer)
Multiplier
O counter
1, 2, 4, 8
Post-divider
Output divider
2, 4, 8, 16, 32, 64, 128, 256
Output divider per output
Oscillator
T8 FPGAs in BGA49 and BGA81 packages have an oscillator.
The T8 has 1 low-frequency oscillator tailored for low-power operation. The oscillator runs
at nominal frequency of 10 kHz. Designers can use the oscillator to perform always-on
functions with the lowest power possible. Its output clock is available to the GCLK network.
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T8 Data Sheet
T8 QFP144 Interface Description
T8 FPGAs in QFP144 packages have an advanced general-purpose I/O logic and buffers, I/O
banks, an advanced PLL, and an LVDS interface.
Complex I/O Buffer
Table 15: GPIO Signals (Interface to FPGA Fabric)
Signal
Direction
Description
IN[1:0]
Output
Input data from the GPIO pad to the core fabric.
ALT
Output
Alternative input connection (in the Interface Designer, Register Option is none).
Alternative connections are GCLK, GCTRL, PLL_CLKIN and PLL_EXTFB.
IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured on
the positive clock edge (HI pin name in the Interface Designer) and IN1 is the data
captured on the negative clock edge (LO pin name in the Interface Designer).
OUT[1:0]
Input
Output data to GPIO pad from the core fabric.
OE
Input
Output enable from core fabric to the I/O block. Can be registered.
OUTCLK
Input
Core clock that controls the output and OE registers. This clock is not visible in the
user netlist.
INCLK
Input
Core clock that controls the input registers. This clock is not visible in the user netlist.
OUT0 is the normal output from the core. In DDIO mode, OUT0 is the data captured
on the positive clock edge (HI pin name in the Interface Designer) and OUT1 is the
data captured on the negative clock edge (LO pin name in the Interface Designer).
Table 16: GPIO Pads
Signal
IO
Direction
Bidirectional
Description
GPIO pad.
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T8 Data Sheet
Double-Data I/O
T8 FPGAs support double data I/O (DDIO) on input and output registers. In this mode, the
DDIO register captures data on both positive and negative clock edges. The core receives 2
bit wide data from the interface.
In normal mode, the interface receives or sends data directly to or from the core on the
positive and negative clock edges. In resync mode, the interface resynchronizes the data to
pass both signals on the positive clock edge only.
Not all GPIO support DDIO; additionally, LVDS as GPIO (that is, single ended I/O) do not
support DDIO functionality.
Note: The Resource Assigner in the Efinity® Interface Designer shows which GPIO support DDIO.
Figure 10: DDIO Input Timing Waveform
GPIO Input
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
Clock
Normal Mode
IN0
DATA1
IN1
DATA3
DATA5
DATA2
DATA4
DATA7
DATA6
DATA8
Resync Mode
IN0
DATA1
IN1
DATA3
DATA5
DATA2
DATA4
DATA7
DATA6
DATA8
In resync mode, the IN1 data captured on the falling clock edge is delayed one half clock cycle.
In the Interface Designer, IN0 is the HI pin name and IN1 is the LO pin name.
Figure 11: DDIO Output Timing Waveform
Normal Mode
Clock
OUT0
DATA1
OUT1
GPIO Output
DATA3
DATA2
DATA1
DATA5
DATA4
DATA2
DATA3
DATA7
DATA6
DATA4
DATA5
DATA8
DATA6
DATA7
DATA8
Resync Mode
Clock
OUT0
DATA1
DATA3
DATA5
DATA7
OUT1
DATA2
DATA4
DATA6
DATA8
GPIO Output
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
In the Interface Designer, OUT0 is the HI pin name and OUT1 is the LO pin name.
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18
T8 Data Sheet
Advanced PLL
T8 FPGAs in QFP144 packages have an advanced I/O logic and buffer.
You can use the PLL to compensate for clock skew/delay via external or internal feedback to
meet timing requirements in advanced application. The PLL reference clock has up to four
sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold
the PLL in reset when dynamically selecting the reference clock source.)
One of the PLLs can use an LVDS RX buffer to input it’s reference clock.
The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M
counter), a post-divider counter (O counter), and output divider.
Note: Refer to T8 Interface Floorplan on page 45 for the location of the PLLs on the die. Refer to Table
69: General Pinouts on page 42 for the PLL reference clock resource assignment.
Figure 12: PLL Block Diagram
CLKIN[3]
CLKIN[2]
CLKIN[1]
CLKIN[0]
FIN
PLL
N
Counter
CLKSEL[1]
CLKSEL[0]
Local feedback
M
Counter
COREFBK
FPFD
Phase
Frequency
Detector
Charge
Pump
Voltage
Control
Oscillator
FVCO
Internal feedback
RSTN
Loop
Filter
O
Counter
Output
Divider (C)
Phase
Shift
Output
Divider (C)
Phase
Shift
Output
Divider (C)
Phase
Shift
LOCKED
CLKOUT0
FOUT
CLKOUT1
CLKOUT2
The counter settings define the PLL output frequency:
Internal Feedback Mode Local and Core Feedback Mode
FPFD = FIN / N
FVCO = FPFD x M
FOUT = (FIN x M) / (N x O
x C)
FPFD = FIN / N
FVCO = (FPFD x M x O x CFBK )
FOUT = (FIN x M x CFBK) / (N x
C)
(7)
Where:
FVCO is the voltage control oscillator frequency
FOUT is the output clock frequency
FIN is the reference clock frequency
FPFD is the phase frequency detector input frequency
C is the output divider
Note: FIN must be within the values stated in PLL Timing and AC Characteristics (QFP144) on page
41.
(7)
(M x O x CFBK) must be ≤ 255.
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19
T8 Data Sheet
Figure 13: PLL Interface Block Diagram
Trion FPGA
PLL
Block
Core
PLL Signals
Reference
Clock
GPIO
Block(s)
Table 17: PLL Signals (Interface to FPGA Fabric)
Signal
Direction
Description
CLKIN[3:0]
Input
Reference clocks driven by I/O pads or core clock tree.
CLKSEL[1:0]
Input
You can dynamically select the reference clock from one of the clock in pins.
RSTN
Input
Active-low PLL reset signal. When asserted, this signal resets the PLL; when deasserted, it enables the PLL. Connect this signal in your design to power up or reset
the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL.
Assert RSTN when dynamically changing the selected PLL reference clock.
COREFBK
Input
Connect to a clock out interface pin when the the PLL feedback mode is set to core.
CLKOUT0
Output
PLL output. The designer can route these signals as input clocks to the core's GCLK
network.
Output
Goes high when PLL achieves lock; goes low when a loss of lock is detected.
Connect this signal in your design to monitor the lock status.
CLKOUT1
CLKOUT2
LOCKED
Table 18: PLL Interface Designer Settings - Properties Tab
Parameter
Instance Name
Choices
User defined
PLL Resource
Clock Source
Automated
Clock
Calculation
Notes
The resource listing depends on the FPGA you choose.
External
PLL reference clock comes from an external pin.
Dynamic
PLL reference clock comes from an external pin or the core, and is
controlled by the clock select bus.
Core
PLL reference clock comes from the core.
Pressing this button launches the PLL Clock Caclulation window. The
calculator helps you define PLL settings in an easy-to-use graphical
interface.
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20
T8 Data Sheet
Table 19: PLL Interface Designer Settings - Manual Configuration Tab
Parameter
Reset Pin Name
Choices
Notes
User defined
Locked Pin Name User defined
Feedback Mode
Internal
PLL feedback is internal to the PLL resulting in no known phase
relationship between clock in and clock out.
Local
PLL feedback is local to the PLL. Aligns the clock out phase with clock in.
Core
PLL feedback is from the core. The feedback clock is defined by the
COREFBK connection, and must be one of the three PLL output clocks.
Aligns the clock out phase with clock in and removes the core clock delay.
Reference clock User defined
Frequency (MHz)
Multiplier (M)
1 - 255 (integer)
M counter.
Pre Divider (N)
1 - 15 (integer)
N counter.
Post Divider (O)
1, 2, 4, 8
O counter.
Clock 0, Clock 1,
Clock 2
On, off
Use these checkboxes to enable or disable clock 0, 1, and 2.
Pin Name
User defined
Specify the pin name for clock 0, 1, or 2.
Divider (C)
1 to 256
Output divider.
Phase Shift
(Degree)
0, 45, 90, 135,
180, or 270
Phase shift CLKOUT by 0, 45, 90, 135, 180, or 270 degrees.
180, and 270 require the C divider to be 2.
45 and 135 require the C divider to be 4.
90 requires the C divider to be 2 or 4.
To phase shift 225 degrees, select 45 and invert the clock at the
destination.
To phase shift 315 degrees, select 135 and invert the clock at the
destination.
Use as Feedback On, off
Table 20: PLL Reference Clock Resource Assignments (QFP144)
PLL
REFCLK1
REFCLK2
PLL_BR0
Differential: GPIOB_CLKP0, GPIOB_CLKN0
GPIOR_157_PLLIN
PLL_TR0
GPIOR_76_PLLIN0
GPIOR_77_PLLIN1
PLL_TR1
GPIOR_76_PLLIN0
GPIOR_77_PLLIN1
PLL_TL0
GPIOL_74_PLLIN0
GPIOL_75_PLLIN1
PLL_TL1
GPIOL_74_PLLIN0
GPIOL_75_PLLIN1
Single Ended: GPIOB_CLKP0
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21
T8 Data Sheet
LVDS
T8 FPGAs in QFP144 packages have an LVDS interface.
The LVDS hard IP transmitters and receivers operate independently.
• LVDS TX consists of LVDS transmitter and serializer logic.
• LVDS RX consists of LVDS receiver, on-die termination, and de-serializer logic.
The T8 has one PLL for use with the LVDS receiver.
Note: You can use the LVDS TX and LVDS RX channels as 3.3 V single-ended GPIO pins, which support a
weak pull-up but do not support a Schmitt trigger or variable drive strength. When using LVDS as GPIO,
make sure to leave at least 2 pairs of unassigned LVDS pins between any GPIO and LVDS pins in the same
bank. This separation reduces noise. The Efinity software issues an error if you do not leave this separation.
The LVDS hard IP has these features:
• Dedicated LVDS TX and RX channels (the number of channels is package dependent),
and one dedicated LVDS RX clock
• Up to 600 Mbps for LVDS data transmit or receive
• Supports serialization and deserialization factors: 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1
• Ability to disable serialization and deserialization
• Source synchronous clock output edge-aligned with data for LVDS transmitter and
receiver
• 100 Ω on-die termination resistor for the LVDS receiver
LVDS TX
Figure 14: LVDS TX Interface Block Diagram
Trion FPGA
Core
OUT[n:0]
Serializer
LVDS TX
Transmitter
TXP
TXN
PLL
SLOWCLK
FASTCLK
Table 21: LVDS TX Signals (Interface to FPGA Fabric)
Signal
Direction
Notes
OUT[n-1:0]
Input
Parallel output data where n is the serialization factor.
FASTCLK
Input
Fast clock to serialize the data to the LVDS pads.
SLOWCLK
Input
Slow clock to latch the incoming data from the core.
A width of 1 bypasses the serializer.
Table 22: LVDS TX Pads
Pad
Direction
Description
TXP
Output
Differential P pad.
TXN
Output
Differential N pad.
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T8 Data Sheet
The following waveform shows the relationship between the fast clock, slow clock, TX data
going to the pad, and byte-aligned data from the core.
Figure 15: LVDS Timing Example Serialization Width of 8
A
0
TX Pad
A A
1 2
A A
3 4
A A
5 6
A B
7 0
B B
1 2
B B
3 4
B B
5 6
B C
7 0
C C
1 2
C C
3 4
C C
5 6
C
7
FASTCLK
SLOWCLK
OUT[7:0]
A[7:0]
B[7:0]
C[7:0]
OUT is byte-aligned data passed from the core on the rising edge of SLOWCLK.
Figure 16: LVDS Timing Data and Clock Relationship Width of 8 (Parallel Clock Division=1)
TX Data
A
0
A A
1 2
A A
3 4
A A
5 6
A B
7 0
B B
1 2
B B
3 4
B B
5 6
B C
7 0
C C
1 2
C C
3 4
C C
5 6
C
7
TX Clock
Figure 17: LVDS Timing Data and Clock Relationship Width of 7 (Parallel Clock Division=1)
TX Data
A
0
A A
1 2
A A
3 4
A A
5 6
B
0
B B
1 2
B B
3 4
B B
5 6
C
0
C C
1 2
C C
3 4
C C
5 6
TX Clock
Table 23: LVDS TX Settings in Efinity® Interface Designer
Parameters
Mode
Parallel Clock
Division
Choices
serial data output
or reference
clock output
1, 2
Enable Serialization
On or off
Serialization Width
2, 3, 4, 5, 6, 7, or 8
Reduce VOD Swing
On or off
Output Load
Notes
serial data output—Simple output buffer or serialized output.
reference clock output—Use the transmitter as a clock output. When
choosing this mode, the Serialization Width you choose should
match the serialization for the rest of the LVDS bus.
1—The output clock from the LVDS TX lane is parallel clock frequency.
2—The output clock from the TX lane is half of the parallel clock
frequency.
When off, the serializer is bypassed and the LVDS buffer is used as a
normal output.
Supports 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1.
When true, enables reduced output swing (similar to slow slew rate).
5, 7 (default), or 10 Output load in pF. Use an output load of 7 pF or higher to achieve
the maximum throughput of 600 Mbps.
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23
T8 Data Sheet
LVDS RX
Figure 18: LVDS RX Interface Block Diagram
Trion FPGA
Core
Deserializer
IN[n:0]
LVDS RX
Receiver RXP1
RXN1
ALT 2
PLL
SLOWCLK
FASTCLK
PLL
1. There is a ~30k Ω internal weak pull-up to VCCIO (3.3V).
2. Only available for an LVDS RX resource in bypass mode
(deserialization width is 1).
Table 24: LVDS RX Signals (Interface to FPGA Fabric)
Signal
Direction
Notes
IN[n-1:0]
Output
Parallel input data where n is the de-serialization factor.
ALT
Output
Alternative input, only available for an LVDS RX resource in bypass
mode (deserialization width is 1; alternate connection type). Alternative
connections are PLL_CLKIN and PLL_EXTFB.
A width of 1 bypasses the deserializer.
FASTCLK
Input
Fast clock to de-serialize the data from the LVDS pads.
SLOWCLK
Input
Slow clock to latch the incoming data to the core.
Table 25: LVDS RX Pads
Pad
Direction
Description
RXP
Input
Differential P pad.
RXN
Input
Differential N pad.
The following waveform shows the relationship between the fast clock, slow clock, RX data
coming in from the pad, and byte-aligned data to the core.
Figure 19: LVDS RX Timing Example Serialization Width of 8
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T8 Data Sheet
Table 26: LVDS RX Settings in Efinity® Interface Designer
Parameter
Connection Type
Choices
normal, pll_clkin,
pll_extfb
Notes
normal—Regular RX function.
pll_clkin—Use the PLL CLKIN alternate function of the LVDS RX
resource.
pll_extfb—Use the PLL external feedback alternate function of the
LVDS RX resource.
Enable
Deserialization
On or off
Deserialization
Width
2, 3, 4, 5, 6, 7, or 8
Enable On-Die
Termination
On or off
When off, the de-serializer is bypassed and the LVDS buffer is used
as a normal input.
Supports 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1.
When on, enables an on-die 100-ohm resistor.
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T8 Data Sheet
Power Up Sequence
Efinix® recommends the following power up sequence when powering Trion® FPGAs:
1. Power up VCC and VCCA_xx first.
2. When VCC and VCCA_xx are stable, power up all VCCIO pins. There is no specific
timing delay between the VCCIO pins.
3. After all power supplies are stable, hold CRESET_N low for a duration of tCRESET_N
before asserting CRESET_N from low to high to trigger active SPI programming (the
FPGA loads the configuration data from an external flash device).
When you are not using the GPIO or PLL resources, connect the pins as shown in the
following table.
Table 27: Connection Requirements for Unused Resources
Unused Resource
Pin
Note
GPIO Bank
VCCIOxx
Connect to either 1.8 V, 2.5 V, or 3.3 V.
PLL
VCCA_PLL
Connect to VCC.
Note: Refer to Configuration Timing on page 37 for timing information.
Figure 20: Trion® FPGAs Power Up Sequence
VCC
VCCA_xx
All VCCIO
CRESET_N
tCRESET_vN
Power Supply Current Transient
You may observe an inrush current on the dedicated power rail during power-up. You must
ensure that the power supplies selected in your board meets the current requirement during
power-up and the estimated current during user mode. Use the Power Estimator to calculate
the estimated current during user mode.
Table 28: Maximum Power Supply Current Transient
Power Supply
VCC
(8)
(9)
Device Package
Maximum Power Supply
Current Transient(8)(9)
Unit
BGA49, BGA81
18
mA
QFP144
35
mA
Inrush current for other power rails are not significant in Trion® FPGAs.
Measured at room temperature.
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26
T8 Data Sheet
Configuration
The T8 FPGA contains volatile Configuration RAM (CRAM). The user must configure the
CRAM for the desired logic function upon power-up and before the FPGA enters normal
operation. The FPGA's control block manages the configuration process and uses a bitstream
to program the CRAM. The Efinity® software generates the bitstream, which is design
dependent. You can configure the T8 FPGA(s) in active, passive, or JTAG mode.
Learn more: Refer to AN 006: Configuring Trion FPGAs for details on the dedicated configuration pins
and how to configure FPGA(s).
Figure 21: High-Level Configuration Options
Board
JTAG
Interface
SPI Flash
Processor
Microcontroller
Trion FPGA
JTAG
SPI Data
JTAG Mode
Controller
SPI Active Mode
Controller
Control Block
Configuration
Manager
User
Logic
SPI Passive Mode
Controller
In active mode, the FPGA controls the configuration process. An oscillator circuit within the
FPGA provides the configuration clock. The bitstream is typically stored in an external serial
flash device, which provides the bitstream when the FPGA requests it.
The control block sends out the instruction and address to read the configuration data. First,
it issues a release from power-down instruction to wake up the external SPI flash. Then, it
waits for at least 30 μs before issuing a fast read command to read the content of SPI flash
from address 24h’000000.
In passive mode, the FPGA is the slave and relies on an external master to provide the
control, bitstream, and clock for configuration. Typically the master is a microcontroller or
another FPGA in active mode.
In JTAG mode, you configure the FPGA via the JTAG interface.
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T8 Data Sheet
Supported Configuration Modes
Table 29: T8 Configuration Modes by Package
Configuration
Mode
Active
Width
BGA49
BGA81
QFP144
X1
X2
X4
Passive
X1
X2
X4
X8
JTAG
X1
Mask-Programmable Memory Option
The T8 FPGA is equipped with one-time programmable MPM. With this feature, you use
on-chip MPM instead of an external serial flash device to configure the FPGA. This option
is for systems that require an ultra-small factor and the lowest cost structure such that an
external serial flash device is undesirable and/or not required at volume production. MPM is
a one-time factory programmable option that requires a Non-Recurring Engineering (NRE)
payment. To enable MPM, submit your design to our factory; our Applications Engineers
(AEs) convert your design into a single configuration mask to be specially fabricated.
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28
T8 Data Sheet
DC and Switching Characteristics
(BGA49 and BGA81)
Table 30: Absolute Maximum Ratings (10)
Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute
maximum ratings for extended periods of time has adverse effects on the device.
Symbol
Description
Min
Max
Units
VCC
Core power supply
-0.5
1.42
V
VCCIO
I/O bank power supply
-0.5
4.6
V
VCCA_PLL
PLL analog power supply
-0.5
1.42
V
VIN
I/O input voltage
-0.5
4.6
V
TJ
Operating junction temperature
-40
125
°C
TSTG
Storage temperature, ambient
-55
150
°C
Table 31: Recommended Operating Conditions (10)
Symbol
Description
Min
Typ
Max
Units
VCC
Core power supply
1.05
1.1
1.15
V
VCCIO
1.8 V I/O bank power supply
1.71
1.8
1.89
V
2.5 V I/O bank power supply
2.38
2.5
2.63
V
3.3 V I/O bank power supply
3.14
3.3
3.47
V
VCCA_PLL
PLL analog power supply
1.05
1.1
1.15
V
VIN
I/O input voltage(11)
-0.3
–
VCCIO
+ 0.3
V
TJCOM
Operating junction temperature, commercial
0
–
85
°C
TJIND
Operating junction temperature, industrial
-40
–
100
°C
Table 32: Power Supply Ramp Rates
Symbol
tRAMP
(10)
(11)
Description
Power supply ramp rate for all supplies.
Min
Max
Units
VCCIO/0.01
10
V/ms
Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply.
Values applicable to both input and tri-stated output configuration.
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T8 Data Sheet
Table 33: Single-Ended I/O DC Electrical Characteristics
I/O Standard
VIL (V)
VIH (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
3.3 V LVCMOS
-0.3
0.8
2
VCCIO + 0.3
0.2
VCCIO - 0.2
3.3 V LVTTL
-0.3
0.8
2
VCCIO + 0.3
0.4
2.4
2.5 V LVCMOS
-0.3
0.7
1.7
VCCIO + 0.3
0.5
1.8
1.8 V LVCMOS
-0.3
VCCIO + 0.3
0.45
VCCIO - 0.45
0.35 * VCCIO 0.65 * VCCIO
Table 34: Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic
Voltage
VT+ (V) Schmitt
Trigger Low-toHigh Threshold
VT- (V) Schmitt
Trigger High-toLow Threshold
Input Leakage
Current (μA)
Tristate Output
Leakage
Current (μA)
3.3
1.73
1.32
±10
±10
2.5
1.37
1.01
±10
±10
1.8
1.05
0.71
±10
±10
Table 35: Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage, device in nominal process (TT).
CDONE and CRESET_N have a drive strength of 1.
I/O Standard
3.3 V
2.5 V
1.8 V
Drive Strength
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
1
14.4
8.0
9.1
8.0
4.4
5.1
2
19.1
10.5
12.2
10.5
5.8
6.8
3
23.9
13.3
15.2
13.4
7.3
8.6
4
28.7
15.8
18.2
15.9
8.6
10.3
Table 36: Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance
CDONE and CRESET_N also have an internal weak pull-up with these values.
I/O Standard
Internal Pull-Up
Internal Pull-Down
Units
Min
Typ
Max
Min
Typ
Max
3.3 V LVTTL/LVCMOS
27
40
65
30
47
83
kΩ
2.5 V LVCMOS
35
55
95
37
62
118
kΩ
1.8 V LVCMOS
53
90
167
54
99
202
kΩ
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T8 Data Sheet
Table 37: Single-Ended I/O Rise and Fall Time
Data are based on the following IBIS simulation setup:
• Weakest drive strength model
• Typical simulation corner setting
• RLC circuit with 6.6 pF capacitance, 16.6 nH inductance, 0.095 ohm resistance, and 25 °C temperature
Note: For a more accurate data, you need to perform the simulation with your own circuit.
I/O Standard
Rise Time (TR)
Fall Time (TF)
Units
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
3.3 V LVTTL/LVCMOS
1.13
1.02
1.24
1.17
ns
2.5 V LVCMOS
1.4
1.3
1.44
1.31
ns
1.8 V LVCMOS
2.14
2.01
2.05
1.85
ns
Table 38: Maximum Toggle Rate
I/O Standard
Test Condition Load (pF)
Max Toggle Rate (Mbps)
3.3 V LVTTL/LVCMOS
10
400
2.5 V LVCMOS
10
400
1.8 V LVCMOS
10
400
Table 39: Block RAM Characteristics
Symbol
fMAX
Description
Block RAM maximum frequency.
C2, I2 Speed Grade
Units
275
MHz
C2, I2 Speed Grade
Units
275
MHz
Table 40: Multiplier Block Characteristics
Symbol
fMAX
Description
Multiplier block maximum frequency.
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T8 Data Sheet
DC and Switching Characteristics (QFP144)
T8 FPGAs in QFP144 packages have the following DC and switching characteristics.
Table 41: Absolute Maximum Ratings
Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute
maximum ratings for extended periods of time has adverse effects on the device.
Symbol
Description
Min
Max
Units
VCC
Core power supply
-0.5
1.42
V
VCCIO
I/O bank power supply
-0.5
4.6
V
VCCA_PLL
PLL analog power supply
-0.5
1.42
V
VIN
I/O input voltage
-0.5
4.6
V
TJ
Operating junction temperature
-40
125
°C
TSTG
Storage temperature, ambient
-55
150
°C
Table 42: Recommended Operating Conditions (C3, C4, and I4 Speed Grades) (12)
Symbol
Description
Min
Typ
Max
Units
VCC
Core power supply
1.15
1.2
1.25
V
VCCIO
1.8 V I/O bank power supply
1.71
1.8
1.89
V
2.5 V I/O bank power supply
2.38
2.5
2.63
V
3.3 V I/O bank power supply
3.14
3.3
3.47
V
VCCA_PLL
PLL analog power supply
1.15
1.2
1.25
V
VIN
I/O input voltage(13)
-0.3
–
VCCIO
+ 0.3
V
TJCOM
Operating junction temperature, commercial
0
–
85
°C
TJIND
Operating junction temperature, industrial
-40
–
100
°C
(12)
(13)
Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply.
Values applicable to both input and tri-stated output configuration.
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T8 Data Sheet
Table 43: Recommended Operating Conditions (C4L and I4L Speed Grades) (12)
Symbol
Description
Min
Typ
Max
Units
VCC
Core power supply
1.05
1.1
1.15
V
VCCIO
1.8 V I/O bank power supply
1.71
1.8
1.89
V
2.5 V I/O bank power supply
2.38
2.5
2.63
V
3.3 V I/O bank power supply
3.14
3.3
3.47
V
PLL analog power supply
1.05
1.1
1.15
V
-0.3
–
VCCIO
+ 0.3
V
0
–
85
°C
-40
–
100
°C
VCCA_PLL
VIN
I/O input voltage
TJCOM
Operating junction temperature, commercial
TJIND
Operating junction temperature, industrial
(14)
Table 44: Power Supply Ramp Rates
Symbol
tRAMP
Description
Power supply ramp rate for all supplies.
Min
Max
Units
VCCIO/0.01
10
V/ms
VOL (V)
VOH (V)
Table 45: Single-Ended I/O DC Electrical Characteristics
I/O Standard
VIL (V)
VIH (V)
Min
Max
Min
Max
Max
Min
3.3 V LVCMOS
-0.3
0.8
2
VCCIO + 0.3
0.2
VCCIO - 0.2
3.3 V LVTTL
-0.3
0.8
2
VCCIO + 0.3
0.4
2.4
2.5 V LVCMOS
-0.3
0.7
1.7
VCCIO + 0.3
0.5
1.8
1.8 V LVCMOS
-0.3
VCCIO + 0.3
0.45
VCCIO - 0.45
0.35 * VCCIO 0.65 * VCCIO
Table 46: Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic
(14)
Voltage (V)
VT+ (V) Schmitt
Trigger Low-toHigh Threshold
VT- (V) Schmitt
Trigger High-toLow Threshold
Input Leakage
Current (μA)
Tri-State Output
Leakage
Current (μA)
3.3
1.73
1.32
±10
±10
2.5
1.37
1.01
±10
±10
1.8
1.05
0.71
±10
±10
Values applicable to both input and tri-stated output configuration.
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T8 Data Sheet
Table 47: Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage.
CDONE and CRESET_N have a drive strength of 1.
I/O Standard
3.3 V
2.5 V
1.8 V
Drive Strength
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
1
14.4
8.0
9.1
8.0
4.4
5.1
2
19.1
10.5
12.2
10.5
5.8
6.8
3
23.9
13.3
15.2
13.4
7.3
8.6
4
28.7
15.8
18.2
15.9
8.6
10.3
Table 48: Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance
CDONE and CRESET_N also have an internal weak pull-up with these values.
I/O Standard
Internal Pull-Up
Internal Pull-Down
Units
Min
Typ
Max
Min
Typ
Max
3.3 V LVTTL/LVCMOS
27
40
65
30
47
83
kΩ
2.5 V LVCMOS
35
55
95
37
62
118
kΩ
1.8 V LVCMOS
53
90
167
54
99
202
kΩ
Table 49: LVDS Pins Configured as Single-Ended I/O DC Electrical Characteristics
I/O Standard
VIL (V)
VIH (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
3.3 V LVCMOS
-0.3
0.8
2
VCCIO + 0.3
0.2
VCCIO - 0.2
3.3 V LVTTL
-0.3
0.8
2
VCCIO + 0.3
0.4
2.4
Table 50: LVDS Pins Configured as Single-Ended I/O DC Electrical Characteristics
Voltage (V)
Input Leakage Current (μA)
Tri-State Output Leakage Current (μA)
3.3
±10
±10
Table 51: LVDS Pins Configured as Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage.
I/O Standard
3.3 V
2.5 V
1.8 V
Drive Strength
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
IOH (mA)
IOL (mA)
1
14.4
8.0
9.1
8.0
4.4
5.1
2
19.1
10.5
12.2
10.5
5.8
6.8
3
23.9
13.3
15.2
13.4
7.3
8.6
4
28.7
15.8
18.2
15.9
8.6
10.3
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T8 Data Sheet
Table 52: LVDS Pins Configured as Single-Ended I/O Internal Weak Pull-Up Resistance
I/O Standard
Internal Pull-Up
Units
Min
Typ
Max
27
40
65
3.3 V LVTTL/LVCMOS
kΩ
Table 53: Maximum Toggle Rate
I/O Standard
Test Condition Load (pF)
Max Toggle Rate (Mbps)
3.3 V LVTTL/LVCMOS
10
400
2.5 V LVCMOS
10
400
1.8 V LVCMOS
10
400
LVDS
10
800
Table 54: Single-Ended I/O and LVDS Pins Configured as Single-Ended I/O Rise and Fall Time
Data are based on the following IBIS simulation setup:
• Weakest drive strength model
• Typical simulation corner setting
• RLC circuit with 6.6 pF capacitance, 16.6 nH inductance, 0.095 ohm resistance, and 25 °C temperature
Note: For a more accurate data, you need to perform the simulation with your own circuit.
I/O Standard
Rise Time (TR)
Fall Time (TF)
Units
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
Slow Slew
Rate Enabled
Slow Slew
Rate Disabled
3.3 V LVTTL/LVCMOS
1.13
1.02
1.24
1.17
ns
2.5 V LVCMOS
1.4
1.3
1.44
1.31
ns
1.8 V LVCMOS
2.14
2.01
2.05
1.85
ns
LVDS pins configured as 3.3 V
LVTTL/LVCMOS
0.45
0.44
ns
Table 55: Block RAM Characteristics
Symbol
fMAX
Description
Block RAM maximum frequency.
Speed Grade
Units
C3, C4L, I4L
C4, I4
310
400
MHz
Table 56: Multiplier Block Characteristics
Symbol
fMAX
Description
Multiplier block maximum frequency.
Speed Grade
Units
C3, C4L, I4L
C4, I4
310
400
MHz
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T8 Data Sheet
LVDS I/O Electrical and Timing
Specifications (QFP144)
The LVDS pins comply with the EIA/TIA-644 electrical specifications.
Table 57: LVDS I/O Electrical Specifications
Parameter
Test Conditions
Min
Typ
Max
Unit
LVDS I/O Supply Voltage
–
2.97
3.3
3.63
V
VOD
Output Differential Voltage
–
250
–
450
mV
Δ VOD
Change in VOD
–
–
–
50
mV
VOCM
Output Common Mode Voltage
RT = 100 Ω
1,125
1,250
1,375
mV
Δ VOCM
Change in VOCM
–
–
–
50
mV
VOH
Output High Voltage
RT = 100 Ω
–
–
1475
mV
VOL
Output Low Voltage
RT = 100 Ω
925
–
–
mV
ISAB
Output Short Circuit Current
–
–
–
24
mA
VID
Input Differential Voltage
–
100
–
600
mV
VICM
Input Common Mode Voltage
–
100
–
2,000
mV
VTH
Differential Input Threshold
–
-100
–
100
mV
IIL
Input Leakage Current
–
–
–
20
μA
VCCIO
Description
LVDS TX
LVDS RX
Figure 22: LVDS RX I/O Electrical Specification Waveform
+ve
-ve
VID
VICM
0V
Table 58: LVDS Timing Specifications
Parameter
Description
tLVDS_DT
LVDS TX reference clock output duty cycle
tLVDS_skew
LVDS TX lane-to-lane skew
Min
Typ
Max
Unit
45
50
55
%
–
200
–
ps
ESD Performance
Refer to the Trion Reliability Report for ESD performance data.
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T8 Data Sheet
Configuration Timing
The T8 FPGA has the following configuration timing specifications. Refer to AN 006:
Configuring Trion FPGAs for detailed configuration information.
Timing Waveforms
Figure 23: SPI Active Mode (x1) Timing Sequence
CCK
tCRESET_N
CRESET_N
SS_N
VCC
CDI0
Read
24 bit Start Address
Dummy Byte
tH
CDI1
Data
tSU
Figure 24: SPI Passive Mode (x1) Timing Sequence
CCK
tCRESET_N
CRESET_N
SS_N
tDMIN
tCLK
GND
tCLKL
tH
CDI
Header and Data
tSU
CDONE
tUSER
The FPGA enters user mode; configuration
I/O pins are released for user functions
Figure 25: Boundary-Scan Timing Waveform
TMS
TDI
tTMSSU
tTDISU
tTMSH
TCK
tTDIH
TDO
tTCKTDO
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T8 Data Sheet
Timing Parameters
Table 59: All Modes
Symbol
Parameter
Min
Typ
Max
Units
tCRESET_N
Minimum creset_n low pulse width required to
trigger re-configuration.
320
–
–
ns
tUSER
Minimum configuration duration after CDONE
goes high before entering user mode.(15)(16)
12
–
(17)
μs
Test condition at 10 kΩ pull-up resistance and
10 pF output loading on CDONE pin.
Table 60: Active Mode
Symbol
fMAX_M
Parameter
Active mode configuration clock
frequency(18).
Frequency
Min
Typ
Max
Units
DIV4
14
20
26
MHz
DIV8
7
10
13
MHz
tSU
Setup time. Test condition at 3.3 V I/O
standard and 0 pF output loading.
–
7.5
–
–
ns
tH
Hold time. Test condition at 3.3 V I/O
standard and 0 pF output loading.
–
1
–
–
ns
Min
Typ
Max
Units
Passive mode X1 configuration clock frequency.
–
–
25
MHz
Passive mode X2, X4 or X8 configuration clock frequency.
–
–
50
MHz
Table 61: Passive Mode
Symbol
fMAX_S
Parameter
tCLKH
Configuration clock pulse width high.
0.48*1/
fMAX_S
–
–
ns
tCLKL
Configuration clock pulse width low.
0.48*1/
fMAX_S
–
–
ns
tSU
Setup time. (BGA49 and BGA81)
4
–
–
ns
tSU
Setup time. (QFP144 packages)
6
–
–
ns
tH
Hold time.
1
–
–
ns
tDMIN
Minimum time between deassertion of CRESET_N to first
valid configuration data.
1.2
–
–
μs
(15)
(16)
(17)
(18)
The FPGA may go into user mode before tUSER has elapsed. However, Efinix recommends that you keep the system
interface to the FPGA in reset until tUSER has elapsed.
For JTAG programming, the min tUSER configuration time is required after CDONE goes high and FPGA receives the
ENTERUSER instruction from JTAG host (TAP controller in UPDATE_IR state).
See Maximum tUSER for SPI Active and Passive Modes on page 39
For parallel daisy chain x2 and x4, the active configuration clock frequency, fMAX_M, is required to set to DIV4.
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T8 Data Sheet
Table 62: JTAG Mode
Symbol
Parameter
Min
Typ
Max
Units
fTCK
TCK frequency.
–
–
25
MHz
tTDISU
TDI setup time.
3.5
–
–
ns
tTDIH
TDI hold time.
1
–
–
ns
tTMSSU
TMS setup time.
3
–
–
ns
tTMSH
TMS hold time.
1
–
–
ns
tTCKTDO
TCK falling edge to TDO output.
–
–
10.5(19)
ns
Maximum tUSER for SPI Active and Passive
Modes
The following waveform illustrates the minimum and maximum values for tUSER.
B
CDONE
A
FPGA
Configuration
Mode
User
Mode
tUSER_MIN
tUSER
• Point A—User-defined trigger point to start counter on tUSER
• Point B—VIH (with Schmitt Trigger) of Trion I/Os
The maximum tUSER value can be derived based on the following formula:
Table 63: tUSER Maximum
Configuration Setup
Single Trion FPGA
tUSER Maximum
tUSER = t(from A to B) + tUSER_MIN
Slave FPGA in a dual-Trion FPGA SPI chain
Master FPGA in a dual-Trion FPGA SPI chain tUSER = (1344 / SPI_WIDTH) * CCK period + tUSER_MIN + t(from A to B)
(19)
0 pf output loading.
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39
T8 Data Sheet
PLL Timing and AC Characteristics
(BGA49 and BGA81)
The following tables describe the PLL timing and AC characteristics for the simple PLL in
BGA49 and BGA81 packages.
Table 64: PLL Timing
Symbol
Parameter
Min
Typ
Max
Units
10
–
50
MHz
FPFD
Phase frequency detector input frequency.
FOUT
Output clock frequency.
0.25
–
400
MHz
FVCO
PLL VCO frequency.
500
–
1500
MHz
Min
Typ
Max
Units
40
50
60
%
tOPJIT (PK - PK) Output clock period jitter (PK-PK).
–
100
–
ps
tILJIT (PK - PK)
Input clock long-term jitter (PK-PK)
–
–
800
ps
tLOCK
PLL pull in plus lock-in time.
–
–
0.5
ms
Table 65: PLL AC Characteristics
Symbol
tDT
Parameter
Output clock duty cycle.
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T8 Data Sheet
PLL Timing and AC Characteristics (QFP144)
The following tables describe the PLL timing and AC characteristics for the advanced PLL in
QFP144 packages.
Table 66: PLL Timing
Symbol
FIN(20)
Parameter
Min
Typ
Max
Units
Input clock frequency from core.
10
–
330
MHz
Input clock frequency from GPIO.
10
–
200
MHz
Input clock frequency from LVDS.
10
–
400
MHz
FOUT
Output clock frequency.
0.24
–
500
MHz
FVCO
PLL VCO frequency.
500
–
1,600
MHz
FPFD
Phase frequency detector input frequency.
10
–
50
MHz
Min
Typ
Max
Units
40
50
60
%
Table 67: PLL AC Characteristics(21)
Symbol
Parameter
tDT
Output clock duty cycle.
tOPJIT (PK - PK)
Output clock period jitter (PK-PK).
–
–
200
ps
tILJIT (PK - PK)
Input clock long-term jitter (PK-PK)
–
–
800
ps
tLOCK
PLL lock-in time.
–
–
0.5
ms
(22)
Internal Oscillator (BGA49 and BGA81)
The internal oscillator has the following specifications.
Table 68: Internal Oscillator Specifications
Symbol
Parameter
FCLKOSC
Oscillator clock frequency.
DCHOSC
Duty cycle.
(20)
(21)
(22)
Min
Typ
Max
Units
–
10
–
kHz
45
50
55
%
When using the Dynamic clock source mode, the maximum input clock frequency is limited by the slowest clock
frequency of the assigned clock source. For example, the maximum input clock frequency of a Dynamic clock source
mode from core and GPIO is 200 MHz.
Test conditions at 3.3 V and room temperature.
The output jitter specification applies to the PLL jitter when an input jitter of 20 ps is applied.
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T8 Data Sheet
Pinout Description
The following tables describe the pinouts for power, ground, configuration, and interfaces.
Table 69: General Pinouts
Function
Group
Direction
Description
VCC
Power
–
Core power supply.
VCCIO
Power
–
I/O pin power supply.
VCCA_PLL
Power
–
PLL analog power supply.
VCCA_xx
Power
–
PLL analog power supply. xx indicates location:
VCCIOxx
Power
–
I/O pin power supply. xx indicates the bank location:
TL: Top left, TR: Top right, BR: bottom right
1A: Bank 1A, 3E: Bank 3E
4A: Bank 4A (only for 3.3 V) , 4B: Bank 4B (only for 3.3 V)
VCCIOxx_yy_zz
Power
–
Power for I/O banks that are shorted together. xx, yy, and zz are
the bank locations. For example:
VCCIO1B_1C shorts banks 1B and 1C
VCCIO3C_TR_BR shorts banks 3C, TR, and BR
GND
Ground
–
Ground.
GNDA_PLL
Ground
–
PLL ground pin.
CLKn
Alternate
Input
Global clock network input. n is the number. The number of
inputs is package dependent.
CTRLn
Alternate
Input
Global network input used for high fanout and global reset. n is
the number. The number of inputs is package dependent.
PLLIN
Alternate
Input
PLL reference clock resource. There are 5 PLL reference clock
resource assignments (depending on the package). Assign the
reference clock resource based on the PLL you are using.
MREFCLK
Alternate
Input
MIPI PLL reference clock source.
GPIOx_n
GPIO
I/O
General-purpose I/O for user function. User I/O pins are singleended.
x: Indicates the bank (L or R)
n: Indicates the GPIO number.
GPIOx_n_yyy
GPIOx_n_yyy_zzz
GPIOx_zzzn
GPIO
MultiFunction
I/O
Multi-function, general-purpose I/O. These pins are single
ended. If these pins are not used for their alternate function, you
can use them as user I/O pins.
x: Indicates the bank; left (L), right (R), or bottom (B).
n: Indicates the GPIO number.
yyy, yyy_zzz: Indicates the alternate function.
zzzn: Indicates LVDS TX or RX and number.
TXNn, TXPn
LVDS
I/O
LVDS transmitter (TX). n: Indicates the number.
RXNn, RXPn
LVDS
I/O
LVDS receiver (RX). n: Indicates the number.
CLKNn, CLKPn
LVDS
I/O
Dedicated LVDS receiver clock input. n: Indicates the number.
RXNn_EXTFBn
LVDS
I/O
LVDS PLL external feedback. n: Indicates the number.
RXPn_EXTFBn
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T8 Data Sheet
Function
Group
Direction
–
–
REF_RES
Description
REF_RES is a reference resistor to generate constant current for
LVDS TX. Connect a 12 kΩ resistor with a tolerance of ±1% to
the REF_RES pin with respect to ground. If none of the pins in a
bank are used for LVDS, leave this pin floating.
Table 70: Dedicated Configuration Pins
These pins cannot be used as general-purpose I/O after configuration.
Pins
Direction
Description
Output
Configuration done status pin. CDONE is an open drain output;
connect it to an external pull-up resistor to VCCIO. When CDONE
= 1, configuration is complete. If you hold CDONE low, the device
will not enter user mode.
CRESET_N
Input
Initiates FPGA re-configuration (active low). Pulse CRESET_N low
for a duration of tcreset_N before asserting CRESET_N from low to
high to initiate FPGA re-configuration. This pin does not perform a
system reset.
TCK
Input
JTAG test clock input (TCK). The rising edge loads signals applied
at the TAP input pins (TMS and TDI). The falling edge clocks out
signals through the TAP TDO pin.
TMS
Input
JTAG test mode select input (TMS). The I/O sequence on this
input controls the test logic operation . The signal value typically
changes on the falling edge of TCK. TMS is typically a weak pullup; when it is not driven by an external source, the test logic
perceives a logic 1.
TDI
Input
JTAG test data input (TDI). Data applied at this serial input is fed
into the instruction register or into a test data register depending
on the sequence previously applied at TMS. Typically, the signal
applied at TDI changes state following the falling edge of TCK
while the registers shift in the value received on the rising edge.
Like TMS, TDI is typically a weak pull-up; when it is not driven from
an external source, the test logic perceives a logic 1.
TDO
Output
JTAG test data output (TDO). This serial output from the test logic
is fed from the instruction register or from a test data register
depending on the sequence previously applied at TMS. During
shifting, data applied at TDI appears at TDO after a number of
cycles of TCK determined by the length of the register included
in the serial path. The signal driven through TDO changes state
following the falling edge of TCK. When data is not being shifted
through the device, TDO is set to an inactive drive state (e.g., highimpedance).
CDONE
Use External
Weak Pull-Up
Note: All dedicated configuration pins have Schmitt Trigger buffer. See Table 34: Single-Ended I/O and
Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic on page 30 for the Schmitt Trigger
buffer specifications.
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T8 Data Sheet
Table 71: Dual-Purpose Configuration Pins
In user mode (after configuration), you can use these dual-purpose pins as general I/O.
Pins
Direction
Description
Use External
Weak Pull-Up
CBUS[2:0]
Input
Configuration bus width select. Connect to weak pull-up
resistors if using default mode (x1).
CBSEL[1:0]
Input
Optional multi-image selection input (if external multi-image
configuration mode is enabled).
N/A
CCK
I/O
Passive SPI input configuration clock or active SPI output
configuration clock (active low). Includes an internal weak
pull-up.
N/A
CDIn
I/O
n is a number from 0 to 31 depending on the SPI
configuration.
N/A
0: Passive serial data input or active serial output.
1: Passive serial data output or active serial input.
n: Parallel I/O.
In multi-bit daisy chain connection, the CDIn (31:0) connects
to the data bus in parallel.
CSI
Input
Chip select.
0: The FPGA is not selected or enabled and will not be
configured.
1: Selects the FPGA for configuration (SPI and JTAG
configuration).
CSO
Output
Chip select output. Selects the next device for cascading
configuration.
N/A
NSTATUS
Output
T8 BGA49 and T8 BGA81:
N/A
Status (active low). Indicates a configuration error. When the
FPGA drives this pin low, it indicates an ID mismatch.
T8 QFP144:
Status (active low). Indicates a configuration error. When the
FPGA drives this pin low, it indicates an ID mismatch, the
bitstream CRC check has failed, or remote update has failed.
SS_N
Input
SPI slave select (active low). Includes an internal weak
pull-up resistor to VCCIO during configuration. During
configuration, the logic level samples on this pin determine
the configuration mode. This pin is an input when sampled
at the start of configuration (SS is low); an output in active SPI
flash configuration mode.
The FPGA senses the value of SS_N when it comes out of
reset (pulse CRESET_N low to high).
0: Passive mode
1: Active mode
TEST_N
Input
Active-low test mode enable signal. Set to 1 to disable test
mode.
During configuration, rely on the external weak pull-up or
drive this pin high.
RESERVED_OUT
Output
Reserved pin during user configuration. This pin drives high
during user configuration.
N/A
BGA49 and BGA81 packages only.
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T8 Data Sheet
Efinity Software Support
The Efinity® software provides a complete tool flow from RTL design to bitstream
generation, including synthesis, place-and-route, and timing analysis. The software has a
graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow,
and view results. The software also has a command-line flow and Tcl command console. The
Efinity® software supports simulation flows using the ModelSim, NCSim, or free iVerilog
simulators. An integrated hardware Debugger with Logic Analyzer and Virtual I/O debug
cores helps you probe signals in your design. The software-generated bitstream file configures
the T8 FPGA. The software supports the Verilog HDL and VHDL languages.
T8 Interface Floorplan
Note: The numbers in the floorplan figures indicate the GPIO and LVDS number ranges. Some packages
may not have all GPIO or LVDS pins in the range bonded out. Refer to the T8 pinout for information on
which pins are available in each package.
Figure 26: Floorplan Diagram for BGA49 and BGA81 Packages
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45
T8 Data Sheet
Figure 27: Floorplan Diagram for QFP144 Packages
Left
Right
PLL_TL1
TL
PLL_TL0
PLL_TR1
1E
3A
62
75
76
TR
PLL_TR0
89
61
90
1D
3B
Quantum
Core Fabric
107
108
1C
3C
44
43
GPIO blocks
Dedicated blocks
PLL reference clock
28
27
LVDS block
LVDS clock
1B
3D
123
124
141
143
10
1A
3E
9
Dimensions not to scale
0
158
LVDS TX
BL
I/O bank
0
4B
LVDS RX
12
0
4A
12
Note:
1. PLL_BR0 has an LVDS
reference clock
PLL_BR0 (1)
BR
Ordering Codes
Refer to the Trion Selector Guide for the full listing of T8 ordering codes.
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46
T8 Data Sheet
Revision History
Table 72: Revision History
Date
Version
November 2021
3.8
Description
Added storage temperature, TSTG spec. (DOC-560)
Updated maximum JTAG mode TCK frequency, fTCK. (DOC-574)
Updated CSI pin description. (DOC-546)
Updated LVDS Pins Configured as Single-Ended I/O Buffer Drive Strength
specifications. (DOC-578)
Update LVDS standard compliance which is TIA/EIA-644. (DOC-592)
Updated tCLKH and tCLKL, and corrected SPI Passive Mode (x1) Timing
Sequence waveform. (DOC-590)
Updated REF_RES_xx description. (DOC-602, DOC-605)
Updated Maximum Toggle Rate table. (DOC-630)
Updated minimum Power Supply Ramp Rates. (DOC-631)
September 2021
3.7
Added Single-Ended I/O and LVDS Pins Configured as Single-Ended I/O
Rise and Fall Time specs. (DOC-522)
Added note to Active mode configuration clock frequency stating that for
parallel daisy chain x2 and x4 configuration, fMAX_M, must be set to DIV4.
(DOC-528)
Added Global Clock Location topic. (DOC-532)
Added Maximum tUSER for SPI Active and Passive Modes topic. (DOC-535)
August 2021
3.6
Removed Static Supply Current parameter. (DOC-456)
Added internal weak pull-up and pull-down resistor specs. (DOC-485)
Updated table title for Single-Ended I/O Schmitt Trigger Buffer
Characteristic. (DOC-507)
Added note in Pinout Description stating all dedicated configuration pins
have Schmitt Trigger buffer. (DOC-507)
June 2021
3.5
Updated CRESET_N pin description. (DOC-450)
April 2021
3.4
Updated PLL specs; tILJIT (PK - PK) and tDT. (DOC-403)
March 2021
3.3
Added LVDS TX reference clock output duty cycle and lane-to-lane skew
specs. (DOC-416)
March 2021
3.2
The simple PLL output is negative edge aligned. (DOC-400)
February 2021
3.1
Added I/O input voltage, VIN specification. (DOC-389)
Added note about limiting number of LVDS as GPIO output and
bidirectional per I/O bank to avoid switching noise. (DOC-411)
Added LVDS TX data and timing relationship waveform. (DOC-359)
Added LVDS RX I/O electrical specification waveform. (DOC-346)
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47
T8 Data Sheet
Date
Version
December 2020
3.0
Description
Updated NSTATUS pin description. (DOC-335)
Added data for C4L and I4L DC speed grades. (DOC-268)
Updated Advanced PLL reference clock input note by asking reader to
refer to PLL Timing and AC Characteristics (QFP144). (DOC-336)
Added other PLL input clock frequency sources in PLL Timing and AC
Characteristics (QFP144). (DOC-336)
Removed OE and RST from LVDS block as they are not supported in
software. (DOC-328)
Added a table to Power Up Sequence topic describing pin connection
when PLL or GPIO is not used. (DOC-325)
Updated fMAX_S for passive configuration modes. (DOC-350)
September 2020
2.9
Updated pinout links.
August 2020
2.8
Removed typical standby (low power [LP] option) from static supply
current table and updated typical standby value for BGA49 and BGA81
packages.
Updated tUSER timing parameter values and added a note about the
conditions for the values.
Updated description for GPIO pins state during configuration to exclude
LVDS as GPIO.
Added operating junction temperature for industrial speed grade for
BGA49 and BGA81 packages.
Updated block RAM and multiplier block maximum frequencies to include
I2 speed grade.
Added fMAX for single-ended I/O and LVDS configured as single-ended I/
O.
Added maximum power supply current transient during power-up.
July 2020
2.7
Removed preliminary note from FOUT, FVCO, tDT, and tOPJIT. These
specifications are final.
Updated timing parameter symbols in boundary scan timing waveform to
reflect JTAG mode parameter symbols.
Added supported GPIO features.
Updated the maximum FVCO for advanced PLL to 1,600 MHz.
Updated the C divider requirement for the 90 degrees phase shift in the
Advanced PLL Interface Designer Settings - Manual Configuration Tab.
Removed LVDS electrical specifications note about RX differential I/O
standard support. Added as a note in LVDS functional description topic.
Added note to LVDS RX interface block diagram.
Updated I/O bank names from TL_CORNER, BL_CORNER, TR_CORNER,
and BR_CORNER to TL, BL, TR, and BR respectively.
Updated the term DSP to multiplier.
Updated power up sequence description about holding CRESET_N low.
Updated PLLCLK pin name to PLL_CLKIN.
Added PLL_EXTFB as an alternative input in GPIO signals table for
complex I/O buffer.
Updated PLL names in PLL reference clock resource assignments.
April 2020
2.6
Removed preliminary note from LVDS I/O electrical specification. These
specifications are final.
www.efinixinc.com
48
T8 Data Sheet
Date
February 2020
Version
2.5
Description
Added fMAX for DSP blocks and RAM blocks.
Added Trion power-up sequence.
Updated number of global clocks and controls that can come from GPIO
pins in package resources table.
December 2019
2.4
Updated PLL settings in the Interface Designer.
Removed DIV1 and DIV2 active mode configuration frequencies; they are
not supported.
Added note to LVDS electrical specifications about RX differential I/O
standard support.
October 2019
2.3
Added explanation that 2 unassigned pairs of LVDS pins should be
located between and GPIO and LVDS pins in the same bank.
Updated the reference clock pin assignments for TL_PLL0 and TL_PLL1.
Added waveforms for configuration timing.
Clarified I/O bank information.
September 2019
2.2
Minor clarifications.
August 2019
2.1
Updated formatting for I/O bank information.
August 2019
2.0
Added information about T8 FPGAs in 144-pin QFP packages.
February 2019
1.7
Removed incorrect footnote about LVDS under Available Package
Options.
November 2018
1.6
Updated PLL interface description.
Added packaging and floorplan information.
Updated configuration timing and PLL timing information.
August 2018
1.5
Updated configuration pin table.
August 2018
1.4
Updated standby current specifications.
July 2018
1.3
Updated the PLL timing specification to add FPFD.
May 2018
1.2
Added ordering code information.
April 2018
1.1
Minor changes throughout.
December 2017
1.0
Initial release.
Renamed RST PLL pin as RSTN.
Updated ordering codes.
Clarified the slew rate description.
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