S-8243A/B Series
N
BATTERY PROTECTION IC
FOR 3-SERIAL OR 4-SERIAL CELL PACK
DE
SI
G
www.ablicinc.com
Rev.3.1_01
© ABLIC Inc., 2002-2016
The S-8243A/B Series is a protection IC for lithium-ion rechargeable battery. The S-8243A Series protects 3-series, the S-8243B
Series protects 4-series cell pack from the overcharge, overdischarge, overcurrent voltages. This IC has a high-accuracy battery
protection circuit and a battery monitor amplifier, and also a voltage regulator which operates the microcomputer or gas gauge IC.
Combining this IC and a microcomputer or a gas gauge IC allows to display the amount of charge remained in a battery.
W
Features
High-accuracy voltage detection for each cell
Overcharge detection voltage n (n = 1 to 4)
3.9 V to 4.4 V (50 mV step)
Accuracy 25 mV
Overcharge hysteresis voltage n (n = 1 to 4) of overcharge detection
0.10 V to 0.40 V (50 mV step) or 0 V
Accuracy 50 mV
(Overcharge release voltage n (= Overcharge detection voltage n Overcharge hysteresis voltage n) can be
selected within the range 3.8 V to 4.4 V.)
Overdischarge detection voltage n (n = 1 to 4)
2.0 V to 3.0 V (100 mV step)
Accuracy 80 mV
Overdischarge hysteresis voltage n (n = 1 to 4) of overdischarge detection
0.15 V to 0.70 V or 0 V (50 mV step)
Accuracy 100 mV
(Overdischarge release voltage n (= Overdischarge detection voltage n Overdischarge hysteresis voltage n)
can be selected within the range 2.0 V to 3.4 V.)
(2) Three-level overcurrent protection including protection for short-circuiting
Overcurrent detection voltage 1
0.05 V to 0.3 V (50 mV step)
Accuracy 25 mV
Overcurrent detection voltage 2
0.5 V
Accuracy 100 mV
Overcurrent detection voltage 3
VDD / 2
Accuracy 15 %
(3) Delay times for overcharge detection, overdischarge detection and overcurrent detection 1 can be set by external
capacitors. (Delay times for overcurrent detection 2 and 3 are fixed internally.)
(4) Charge/discharge operation can be controlled through the control pins.
(5) High-accuracy battery monitor amp
GAMP = VBATTERY 0.2 1.0%
(6) Voltage regulator
VOUT = 3.3 V 2.4 % (3 mA max.)
(7) High-withstand voltage
Absolute maximum rating: 26 V
(8) Wide operating voltage range
6 V to 18 V
(9) Wide operating temperature range:
40°C to 85C
(10) Low current consumption
Operation mode
120 A max.
Power down mode
0.1 A max.
(11) Lead-free, Sn 100%, halogen-free*1
RE
C
OM
M
EN
DE
D
FO
R
NE
(1)
*1. Refer to “ Product Name Structure” for details.
Applications
T
Lithium-ion rechargeable battery packs
Lithium polymer rechargeable battery packs
NO
Package
16-Pin TSSOP
1
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Block Diagrams
Rev.3.1_01
VDD
Battery protection
DOP
DE
SI
G
1. S-8243A Series
VREG
DOP,COP,
RVCM,RVSM
control
Voltage
regulator
W
COP
Delay
NE
200 nA
Delay
Delay
660 k
FO
VMP
660 k
VREG
1.4 M
R
Delay
440 k
CTL1
CTL2
1.4 M
VREG
1.4 M
Battery
selection
CTL3
D
1.4 M
EN
DE
VC1
VBATOUT
OM
1 M
CCT
CDT
T
Remark1. Diodes in the figure are parasitic diodes.
2. Numerical values are typical values.
NO
Battery monitor amp
5 M
VSS
2
CTL4
1.4 M
1 M
RE
C
VC3
1.4 M
5 M
M
VC2
VREG
Figure 1
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
VDD
Battery protection
DOP
DE
SI
G
N
2. S-8243B Series
VREG
DOP, COP,
RVCM, RVSM
control
Voltage
regulator
W
COP
Delay
200 nA
NE
Delay
Delay
660k
R
FO
660 k
VREG
1.4 M
Delay
440 k
VMP
CTL1
Battery
selection
CTL2
1.4 M
VREG
1.4 M
CTL3
1.4 M
VREG
DE
D
VC1
EN
VC2
1.4 M
CTL4
1.4 M
Battery monitor amp
1 M
5 M
VBATOUT
5 M
M
1 M
OM
VC3
RE
C
CCT
CDT
VSS
NO
T
Remark1. Diodes in the figure are parasitic diodes.
2. Numerical values are typical values.
Figure 2
3
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Product Name Structure
x
xx
FT
-
TB
x
DE
SI
G
1. Product Name
S-8243
Rev.3.1_01
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office
IC direction in tape specifications*1
W
Package name (abbreviation)
FT:
16-Pin TSSOP
NE
Serial code*2
Sequentially set from AA to ZZ
R
Product series name
A:
3-cell
B:
4-cell
FO
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
D
2. Package
Drawing Code
Tape
Reel
Environmental code = G
Environmental code = U
FT016-A-P-SD
FT016-A-P-SD
FT016-A-C-SD
FT016-A-C-SD
FT016-A-R-SD
FT016-A-R-S1
EN
16-Pin TSSOP
Package
DE
Package Name
3. Product Name List
Overcharge
hysteresis voltage
[VHC]
Overdischarge
detection voltage
[VDL]
Overdischarge
hysteresis voltage
[VHD]
4.350 0.025 V
4.350 0.025 V
0.15 0.05 V
0.35 0.05 V
2.40 0.08 V
2.40 0.08 V
0.20 0.10 V
0V
RE
C
S-8243AACFT-TB-x
S-8243AADFT-TB-x
Overcharge
detection voltage
[VCU]
OM
Product name / Item
M
Table 1 S-8243A Series (For 3-Serial Cell)
Product name / Item
NO
T
S-8243BADFT-TB-x
S-8243BAEFT-TB-x
S-8243BAFFT-TB-x
S-8243BAHFT-TB-x
Overcharge
detection voltage
Overcurrent
0 V battery
detection voltage1 charging
[VIOV1]
function
0.20 0.025 V
0.20 0.025 V
Available
Available
Table 2 S-8243B Series (For 4-Serial Cell)
[VCU]
Overcharge
hysteresis voltage
[VHC]
Overdischarge
detection voltage
[VDL]
Overdischarge
hysteresis voltage
[VHD]
4.350 0.025 V
4.350 0.025 V
4.250 0.025 V
4.315 0.025 V
0.25 0.05 V
0.15 0.05 V
0.25 0.05 V
0.20 0.05 V
2.40 0.08 V
2.40 0.08 V
2.40 0.08 V
2.00 0.08 V
0V
0.20 0.10 V
0V
0.15 0.10 V
Overcurrent
0 V battery
detection voltage1 charging
[VIOV1]
function
0.25 0.025 V
0.20 0.025 V
0.20 0.025 V
0.20 0.025 V
Available
Available
Available
Available
Remark 1. Change in the detection voltage is available in products other than listed above. Contact our sales office.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
4
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
N
Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREG
CTL1
CTL2
CTL3
CTL4
VBATOUT
CCT
CDT
W
VDD
DOP
COP
VMP
VC1
VC2
VC3
VSS
DE
SI
G
16-Pin TSSOP
Top view
NE
Figure 3
Table 3 Pin description (S-8243A Series)
Description
EN
DE
D
FO
R
Input pin for positive power supply, Connection pin for battery 1’s positive voltage
Connection pin for discharge control FET gate (CMOS output)
Connection pin for charge control FET gate (Nch open drain output)
Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)
No connection
Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage
Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage
Input pin for negative power supply, Connection pin for battery 3’s negative voltage
Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1
Connection pin to capacitor for overcharge detection delay
Output pin for battery voltage and offset voltage
Pin for selecting output from VBATOUT pin
Pin for selecting output from VBATOUT pin
Control pin for charge / discharge FET
Control pin for charge / discharge FET
Output pin for voltage regulator (3.3 V)
M
Symbol
VDD
DOP
COP
VMP
VC1
VC2
VC3
VSS
CDT
CCT
VBATOUT
CTL4
CTL3
CTL2
CTL1
VREG
OM
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
DOP
COP
VMP
VC1
VC2
VC3
VSS
CDT
CCT
VBATOUT
CTL4
CTL3
CTL2
CTL1
VREG
Description
Input pin for positive power supply, Connection pin for battery 1’s positive voltage
Connection pin for discharge control FET gate (CMOS output)
Connection pin for charge control FET gate (Nch open drain output)
Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)
Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage
Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage
Connection pin for battery 3’s negative voltage, for battery 4’s positive voltage
Input pin for negative power supply, Connection pin for battery 4’s negative voltage
Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1
Connection pin to capacitor for overcharge detection delay
Output pin for battery voltage and offset voltage
Pin for selecting output from VBATOUT pin
Pin for selecting output from VBATOUT pin
Control pin for charge / discharge FET
Control pin for charge / discharge FET
Output pin for voltage regulator (3.3 V)
NO
T
RE
C
Pin No.
Table 4 Pin description (S-8243B Series)
5
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Absolute Maximum Ratings
VMP pin Input voltage
DOP pin output voltage
COP pin output voltage
VREG pin output voltage
CTL1 pin input voltage
CTL2 to CTL4 pin input voltage
Cell voltage output voltage
VMP
VDOP
VCOP
VOUT
VCTL1
VCTLn
VBATOUT
Power dissipation
PD
V
VSS0.3 to VSS26
VSS0.3 to VDD0.3
VSS0.3 to VSS26
VSS0.3 to VDD0.3
VSS0.3 to VDD0.3
VSS0.3 to VOUT0.3
VSS0.3 to VOUT0.3
300 (When not mounted on board)
1100*1
40 to 85
40 to 125
V
V
V
V
V
V
V
mW
mW
C
C
FO
Operation ambient temperature
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size:
114.3 mm 76.2 mm t1.6 mm
(2) Board name:
JEDEC STANDARD51-7
VSS0.3 to VDD0.3
W
VIN
NE
Input voltage
Applied Pins
VC1, VC2, VC3, CCT,
CDT
VMP
DOP
COP
VREG
CTL1
CTL2, CTL3, CTL4
VBATOUT
(Ta = 25C unless otherwise specified)
Absolute Maximum Ratings
Unit
VSS0.3 to VSS26
V
R
Symbol
VDS
DE
SI
G
Table 5
Item
Input voltage VDD
Rev.3.1_01
DE
D
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
1000
EN
Power Dissipation (PD) [mW]
1200
800
RE
C
OM
M
600
400
200
0
0
50
100
150
Ambient Temperature (Ta) [C]
NO
T
Figure 4 Power Dissipation of Package (When Mounted on Board)
6
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Electrical Characteristics
Symbol
Conditions
VCUn
3.9 V to 4.4 V, 50 mV Step
VHCn
0.10 V to 0.40 V, and 0 V
VDLn
2.0 V to 3.0 V, 100 mV Step
VHDn
0.15 V to 0.70 V, and 0 V
Overcurrent detection voltage 1
VIOV1
0.05 V to 0.3 V, 50 mV Step
VM voltage based on VDD
VM voltage based on VDD
Min.
VCUn
0.025
VHCn
0.05
VDLn
0.08
VHDn
0.10
VIOV1
0.025
0.40
VDD0.425
VCUn
VHCn
VDLn
NE
Item
BATTERY PROTECTION
Overcharge detection voltage n
n=1, 2, 3
Overcharge hysteresis voltage n
n = 1, 2, 3
Overdischarge detection voltage
n = 1, 2, 3
Overdischarge hysteresis voltage
n = 1, 2, 3
(Ta = 25C unless otherwise specified)
Typ.
Max.
Unit
Test circuit
W
Table 6 (1 / 2)
DE
SI
G
1. S-8243A Series
VHDn
VIOV1
VCUn
0.025
VHCn
0.05
VDLn
0.08
VHDn
0.10
VIOV1
0.025
0.60
VDD0.575
V
4
V
4
V
4
V
4
V
4
NO
T
RE
C
OM
M
EN
DE
D
FO
R
Overcurrent detection voltage 2
VIOV2
0.50
V
4
Overcurrent detection voltage 3
VIOV3
VDD0.5
V
4
Temperature coefficient for
Ta = 5C to 55C*3
TCOE1
1.0
0
1.0
mV/C
4
*1
detection and release voltage
Temperature coefficient for
Ta = 5C to 55C*3
TCOE2
0.5
0
0.5
mV/C
4
*2
overcurrent detection voltage
0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited."
depending upon the product type.)
0 V battery charge starting charger
V0CHA
0 V battery charging available
0.8
1.5
V
7
voltage
0 V battery charge inhibition battery
V0INH
0 V battery charging unavailable
0.4
0.7
1.1
V
7
voltage
INTERNAL RESISTANCE
Internal resistance between
RVDM
V1 = V2 = V3 = 3.5 V
500
1100
2400
k
8
VMP and VDD
Internal resistance between
RVSM
V1 = V2 = V3 = 1.8 V
300
700
1500
k
8
VMP and VSS
VOLTAGE REGULATOR
Output voltage
VOUT
VDD = 14 V, IOUT = 3 mA
3.221
3.300
3.379
V
2
Line regulation
VOUT1 VDD = 6 V18 V, IOUT = 3 mA
5
15
mV
2
Load regulation
VOUT2 VDD = 14 V, IOUT = 5 A3 mA
15
30
mV
2
BATTERY MONITOR AMP
Input offset voltage n
VOFFn
V1 = V2 = V3 = 3.5 V
60
165
270
mV
3
n = 1, 2, 3
Voltage gain n
GAMPn V1 = V2 = V3 = 3.5 V
0.20.99
0.2
0.21.01
3
n = 1, 2, 3
INPUT VOLTAGE, OPERATING VOLTAGE
Operating voltage between
VDSOP
6
18
V
4
VDD and VSS
CTL1 input voltage for High
VCTL1H
VDD0.8
V
6
CTL1 input voltage for Low
VCTL1L
VDD0.2
V
6
CTLn input voltage for High
VCTLnH
VOUT0.9
VOUT
V
3, 6
n = 2, 3, 4
CTLn input voltage for Low
VCTLnL
VOUT0.1
V
3, 6
n = 2, 3, 4
7
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Table 6 (2 / 2)
Symbol
Remarks
Min.
Typ.
Max.
Unit
Test circuit
65
120
A
1
0.1
A
1
0
0.3
A
3
2.0
7.2
A
3
1.0
4.0
A
3
0.4
0.2
A
5
2.5
5
A
9
5
2.5
A
9
10
0.1
A
A
9
9
10
A
9
10
100
100
A
A
A
9
9
9
V1 = V2 = V3 = 3.5 V, VMP = VDD
IPDN
V1 = V2 = V3 = 1.5 V, VMP = VSS
IVCnN
V1 = V2 = V3 = 3.5 V
0.3
IVC2
V1 = V2 = V3 = 3.5 V
IVC3
V1 = V2 = V3 = 3.5 V
ICTL1L
V1 = V2 = V3 = 3.5 V, VCTL1 = 0 V
ICTLnH
VCTLn = VOUT
ICTLnL
VCTLn = 0 V
ICOH
ICOL
VCOP = 24 V
VCOP = VSS0.5 V
Source current DOP
IDOH
VDOP = VDD0.5 V
Sink current DOP
Source current VBATOUT
Sink current VBATOUT
IDOL
IVBATH
IVBATL
VDOP = VSS0.5 V
VBATOUT = VDD0.5 V
VBATOUT = VSS0.5 V
NE
R
FO
D
DE
Applied to S-8243AACFT and S-8243AADFT
W
IOPE
DE
SI
G
Item
INPUT CURRENT
Current consumption at not
monitoring VBATOUT
Current consumption at power down
Current for VCn at not monitoring
VBATOUT (n = 2, 3)
Current for VC2 at monitoring of
VBATOUT
Current for VC3 at monitoring of
VBATOUT
Current for CTL1 at Low
Current for CTLn at High
n = 2,3,4
Current for CTLn at Low
n = 2,3,4
OUTPUT CURRENT
Leak current COP
Sink current COP
N
Rev.3.1_01
NO
T
RE
C
OM
M
EN
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Test circuit
DELAY TIME
Overcharge detection delay time
tCU
CCT = 0.1 F
0.5
1.0
1.5
s
5
Overdischarge detection delay time tDL
CDT = 0.1 F
50
100
150
ms
5
Overcurrent detection delay time 1 tlOV1
CDT = 0.1 F
5
10
15
ms
5
Overcurrent detection delay time 2 tlOV2
1.5
2.5
4.0
ms
4
Overcurrent detection delay time 3 tlOV3
100
300
600
s
4
*1. Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n, overdischarge
detection voltage n, and overdischarge release voltage n.
*2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in
production.
8
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Symbol
Conditions
VCUn
3.9 V to 4.4 V, 50 mV Step
VHCn
0.10 V to 0.40 V, and 0 V
VDLn
2.0 V to 3.0 V, 100 mV Step
VHDn
0.15 V to 0.70 V, and 0 V
VIOV1
Overcurrent detection voltage 2
VIOV2
0.05 V to 0.3 V, 50 mV Step
VM voltage based on VDD
VM voltage based on VDD
Overcurrent detection voltage 3
VIOV3
VCUn
0.025
VHCn
0.05
VDLn
0.08
VHDn
0.10
VIOV1
0.025
0.40
VDD
0.425
R
Overcurrent detection voltage 1
Min.
(Ta = 25C unless otherwise specified)
Typ.
Max.
Unit
Test circuit
VCun
VHCn
VDLn
VHDn
NE
Item
DETECTION VOLTAGE
Overcharge detection voltage n
n = 1, 2, 3, 4
Overcharge hysteresis voltage n
n = 1, 2, 3, 4
Overdischarge detection voltage
n = 1, 2, 3, 4
Overdischarge hysteresis voltage
n = 1, 2, 3, 4
W
Table 7 (1 / 2)
DE
SI
G
N
2. S-8243B Series
VIOV1
0.50
VDD
0.5
VCUn
0.025
VHCn
0.05
VDLn
0.08
VHDn
0.10
VIOV1
0.025
0.60
VDD
0.575
V
4
V
4
V
4
V
4
V
4
V
4
V
4
NO
T
RE
C
OM
M
EN
DE
D
FO
Temperature coefficient for
Ta = 5C to 55C*3
TCOE1
1.0
0
1.0
mV/C
4
*1
detection and release voltage
Temperature coefficient for
Ta = 5C to 55C*3
TCOE2
0.5
0
0.5
mV/C
4
*2
overcurrent detection voltage
0 V BATTERY CHARGING FUNCTION (The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited."
depending upon the product type.)
0 V battery charge starting charger
V0CHA
0 V battery charging allowed
0.8
1.5
V
7
voltage
0 V battery charge inhibition battery
V0INH
0 V battery charging inhibited
0.4
0.7
1.1
V
7
voltage
INTERNAL RESISTANCE
Internal resistance between
RVDM
V1 = V2 = V3 = V4 = 3.5 V
500
1100
2400
k
8
VMP and VDD
Internal resistance between
RVSM
V1 = V2 = V3 = V4 = 1.8 V
300
700
1500
k
8
VMP and VSS
VOLTAGE REGULATOR
Output voltage
VOUT
VDD = 14V, IOUT = 3 mA
3.221
3.300
3.379
V
2
Line regulation
VOUT1 VDD = 6 V18 V, IOUT = 3 mA
5
15
mV
2
Load regulation
VOUT2 VDD = 14 V, IOUT = 5 A3 mA
15
30
mV
2
BATTERY MONITOR AMP
Input offset voltage n
VOFFn
V1 = V2 = V3 = V4 = 3.5 V
60
165
270
mV
3
n = 1, 2, 3, 4
Voltage gain n
GAMPn V1 = V2 = V3 = V4 = 3.5 V
0.20.99
0.2
0.21.01
3
n = 1, 2, 3, 4
INPUT VOLTAGE, OPERATING VOLTAGE
Operating voltage between
VDSOP
6
18
V
4
VDD and VSS
CTL1 input voltage for High
VCTL1H
VDD0.8
V
6
CTL1 input voltage for Low
VCTL1L
VDD0.2
V
6
CTLn input voltage for High
VCTLnH
VOUT0.9
VOUT
V
3, 6
n = 2, 3, 4
CTLn input voltage for Low
VCTLnL
VOUT0.1
V
3, 6
n = 2, 3, 4
9
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Remarks
Min.
Unit
Test circuit
120
A
1
0.1
A
1
0
0.3
A
3
3.2
10.4
A
3
2.0
7.2
A
3
1.0
4.0
A
3
0.4
0.2
A
5
2.5
5
A
9
5
2.5
A
9
10
10
10
100
100
0.1
A
A
A
A
A
A
9
9
9
9
9
9
Conditions
Min.
Typ.
Max.
Unit
Test circuit
0.5
50
5
1.5
100
1.0
100
10
2.5
300
1.5
150
15
4.0
600
s
ms
ms
ms
s
5
5
5
4
4
V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD
IPDN
V1 = V2 = V3 = V4 = 1.5 V, VMP = VSS
IVCnN
V1 = V2 = V3 = V4 = 3.5 V
0.3
IVC1
V1 = V2 = V3 = V4 = 3.5 V
IVC2
V1 = V2 = V3 = V4 = 3.5 V
IVC3
V1 = V2 = V3 = V4 = 3.5 V, VCTL1 = 0 V
ICTL1L
V1 = V2 = V3 = V4 = 3.5 V, VCTL1 = 0 V
ICTLnH
VCTLn = VOUT
ICTLnL
VCTLn = 0 V
ICOH
ICOL
IDOH
IDOL
IVBATH
VCOP = 24 V
VCOP = VSS0.5 V
VDOP = VDD0.5 V
VDOP = VSS0.5 V
VBATOUT = VDD0.5 V
IVBATL
VBATOUT = VSS0.5 V
65
NE
FO
D
Max.
W
IOPE
Typ.
DE
SI
G
Symbol
DE
Item
INPUT CURRENT
Current consumption at not
monitoring VBATOUT
Current consumption at power down
Current for VCn at not monitoring
VBATOUT (n = 2, 3)
Current for VC1 at monitoring of
VBATOUT
Current for VC2 at monitoring of
VBATOUT
Current for VC3 at monitoring of
VBATOUT
Current for CTL1 at Low
Current for CTLn at High
n = 2, 3, 4
Current for CTLn at Low
n = 2, 3, 4
OUTPUT CURRENT
Leak current COP
Sink current COP
Source current DOP
Sink current DOP
Source current VBATOUT
Sink current VBATOUT
R
Table 7 (2 / 2)
N
Rev.3.1_01
Symbol
CCT = 0.1 F
CDT = 0.1 F
CDT = 0.1 F
M
tCU
tDL
tlOV1
tlOV2
tlOV3
OM
Item
DELAY TIME
Overcharge detection delay time
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
EN
Applied to S-8243BAEFT, S-8243BAFFT, S-8243BAHFT
RE
C
Applied to S-8243BADFT
NO
T
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit Test circuit
DELAY TIME
Overcharge detection delay time
tCU
CCT = 0.1 F
0.5
1.0
1.5
s
5
Overdischarge detection delay time tDL
CDT = 0.1 F
55.5
111
222
ms
5
Overcurrent detection delay time 1 tlOV1
CDT = 0.1 F
3.31
6.62
13.2
ms
5
Overcurrent detection delay time 2 tlOV2
1.5
2.5
4.0
ms
4
Overcurrent detection delay time 3 tlOV3
100
300
600
s
4
*1. Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n, overdischarge
detection voltage n, and overdischarge release voltage n.
*2. Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in
production.
10
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Test Circuits
DE
SI
G
In this chapter test methods are explained for the case of S-8243B Series, which is designed for 4-serial cell pack. For the
case of S-8243A Series, which is designed for 3-serial cell, voltage source V2 should be shorted, V3 should be read as V2,
and V4 as V3.
1. Current consumption (Test circuit 1)
W
Current consumption at not monitoring VBATOUT, IOPE, is a current measured at the VSS pin when V1 = V2 = V3 = V4 =
3.5 V and VMP = VDD. Current consumption at power down, IPDN, is a current measured at the VSS pin when V1 = V2 =
V3 = V4 = 1.5 V and VMP = VSS.
2. Voltage regulator (Test circuit 2)
FO
R
NE
Output voltage of the regulator VOUT is a voltage measured at the VREG pin when VDD = VMP = 14 V and IOUT = 3 mA.
Line regulation of the voltage regulator VOUT1 is defined by the equation VOUT1 = VOUT2VOUT1 where VOUT1 is the
output voltage when VDD = VMP = 6 V and IOUT = 3 mA, and VOUT2 is the output voltage when VDD = VMP = 18 V and IOUT
= 3 mA.
Load regulation of the regulator is defined by the equation VOUT2 = VOUT3VOUT where VOUT3 is the output voltage when
VDD = VMP = 14 V and IOUT = 5 A.
3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3)
DE
D
Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the measurement result
provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin expressed by the following table at
the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to VC3, IVCn and IVCnN are at the same time
measured.
Table 8
CTL4 pin status
VCTL3H min.
VCTL3H min.
VCTL3H min.
Open
Open
Open
VCTL3L max.
VCTL3L max.
VCTL4H min.
Open
VCTL4L max.
VCTL4H min.
Open
VCTL4L max.
VCTL4H min.
Open
VBATOUT pin output
OM
M
EN
CTL3 pin status
VOFF1
VBAT1
VOFF2
VBAT2
VOFF3
VBAT3
VOFF4
VBAT4
VCn (n = 1, 2, 3) pin current
IVC1 at VC1 pin
IVC2 at VC2 pin
IVC3 at VC3 pin
IVCnN at VCn pin (n = 1, 2, 3)
NO
T
RE
C
Voltage gain of the battery monitor amp for each cell is calculated by the equation
GAMPn = (VBATnVOFFn) / Vn (n = 1 to 4)
11
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
DE
SI
G
N
4. Overcharge detection voltages, overcharge hysteresis voltages, overdischarge detection voltages,
overdischarge hysteresis voltages, and overcurrent detection voltages (Test circuit 4)
4. 1 Overcharge detection voltages, overcharge hysteresis voltages, overdischarge detection voltages and
overdischarge hysteresis voltages
NE
W
In the following VMP = VDD and the CDT pin is open.
The COP pin and the DOP pin should provide “Low”, which is a voltage equal to VDD 0.1 V or lower, in the condition
that V1 = V2 = V3 = V4 = 3.5 V.
The overcharge detection voltage VCU1 is defined by the voltage at which COP pin voltage becomes “High”, which is
a voltage equal to VDD 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1 =
3.5 V. The overcharge release voltage VCL1 is defined by the voltage at which COP pin voltage becomes “Low” when
the voltage V1 is gradually decreased. The overcharge hysteresis voltage VHC1 is then defined by the difference
between the overcharge detection voltage VCU1 and the overcharge release voltage VCL1.
FO
R
The overdischarge detection voltage VDL1 is defined by the voltage at which DOP pin voltage becomes “High” when
the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage
VDU1 is defined by the voltage at which DOP pin voltage becomes “Low” when the voltage V1 is gradually increased.
The overdischarge hysteresis voltage VHD1 is then defined by the difference between the overdischarge release
voltage VDU1 and the overdischarge detection voltage VDL1.
Other overcharge detection voltage VCUn, overcharge hysteresis voltage VHCn, overdischarge detection voltage VDLn,
and overdischarge hysteresis voltage VHDn ( for n = 2 to 4) are defined in the same manner as in the case for n = 1.
4. 2 Overcurrent detection voltages
DE
D
Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. The DOP pin voltage thus
provides “Low”
The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD VMP at which the DOP pin
voltage becomes “High” when the voltage of VMP pin is decreased.
M
EN
Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD
and the CDT pin voltage VCDT = VSS . The DOP pin voltage thus provides “Low”.
The overcurrent detection voltage 2, VIOV2 is defined by the voltage difference VDDVMP at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased.
OM
The overcurrent detection delay time 2, tIOV2 is a time needed for the DOP pin to become “High” from “Low” when the
VMP pin voltage is changed quickly to VIOV2 min.0.2 V from the starting condition VMP = VDD.
The overcurrent detection voltage 3, VIOV3 is defined by the voltage of the VMP pin at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.
NO
T
RE
C
The overcurrent detection delay time 3, tIOV3 is a time needed for the DOP pin to become “High” from “Low” when the
VMP pin voltage is changed quickly to VIOV3 min.0.2 V from the starting condition VMP = VDD.
12
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Starting condition is V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.
Current that flows between the CTL1 pin and VSS is the CTL1 pin current ICTL1L.
DE
SI
G
N
5. CTL1 pin current, overcharge detection delay time, overdischarge detection delay time, and
overcurrent detection delay time 1 (Test circuit 5)
The overcharge detection delay time tCU is a time needed for the COP pin voltage to change from “Low” to “High” just
after the V1 voltage is rapidly increased from 3.5 V to 4.5 V.
The overdischarge detection delay time tDL is a time needed for the DOP pin voltage to change from “Low” to “High” just
after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V.
6. Input voltages for CTL1 and CTL2 (Test circuit 6)
NE
W
The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to “High” just after
the VMP pin voltage is decreased from VDD to VDD0.35 V when V1 = 3.5 V.
D
FO
R
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin voltages of the COP and the DOP should be “High” when VCTL1 = VCTL1H min. and CTL2 is OPEN.
Pin voltages of the COP and the DOP should be “Low” when VCTL1 = VCTL1L max. and CTL2 is OPEN.
Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2H
min.
Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2L
max.
DE
7. 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage (Test
circuit 7)
One of the 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage is applied to each
product according to the 0 V battery charging function.
EN
Starting condition is V1 = V2 = V3 = V4 = 0 V for a product in which 0 V battery charging is available.
The COP pin voltage should be lower than V0CHA max.1 V when the VMP pin voltage VMP = V0CHA max.
NO
T
RE
C
OM
M
Starting condition is V1 = V2 = V3 = V4 = V0INH for a product in which 0 V battery charging is inhibited.
The COP pin voltage should be higher than VMP1 V when the VMP pin voltage VMP = 24 V.
13
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
N
8. Internal resistance (Test circuit 8)
DE
SI
G
The resistance between VDD and VMP is RVDM and is calculated by the equation RVDM = VDD / IVDM where IVDM is a VMP
pin current after VMP is changed to VSS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.
The resistance between VSS and VMP is RVSM and is calculated by the equation RVSM = VDD / IVSM where IVSM is a VMP
pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and VMP = VDD.
9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9)
NE
W
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin current for CTL2 at “High” is ICTL2H and is obtained by setting VCTL2 = VOUT.
Pin current for CTL2 at “Low” is ICTL2L and is obtained by setting VCTL2 = VSS.
Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2.
R
Pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, VMP = VDD, and VCOP = VDD. And
pin current for COP at “Low” is ICOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VCOP = 0.5 V.
Pin current for DOP at “Low” is IDOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VDOP = 0.5 V.
And pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, VMP = VDD1 V, and VDOP
= VDD0.5 V.
V4
A
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT 9
DE
V3
CTL1 15
CTL2 14
EN
V2
2 DOP
3 COP
VREG 16
1 VDD
D
VREG 16
1 VDD
V1
FO
Pin current for VBATOUT at “High” is IVBATH and is obtained by setting CTL3 and CTL4 are open and VBATOUT =
VOFF30.5 V. And pin current for VBATOUT at “Low” is IVBATL and is obtained by setting VBATOUT = VOFF30.5 V.
2 DOP
CTL1 15
3 COP
CTL2 14
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT 9
V
C11 F
C11 F
M
Test circuit 1
2 DOP
3 COP
V2
V3
V4
4 VMP
CTL1 15
CTL3 13
5 VC1
CTL4 12
V2
6 VC2
VBATOUT 11
V3
T
NO
V1
A
A
7 VC3
1 VDD
VREG 16
2 DOP
CTL1 15
3 COP
CTL2 14
CTL2 14
A
8 VSS
14
R11 M
VREG 16
RE
C
V1
Test circuit 2
OM
1 VDD
CCT 10
CDT
V
9
IOUT
V4
V
V
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT
9
C11 F
C11 F
Test circuit 3
Test circuit 4
Figure 5 (1 / 2)
VREG 16
2 DOP
CTL1 15
3 COP
4 VMP
V1
5 VC1
V2
V3
V4
R11 M
A
CTL2 14
CTL3 13
V1
CTL4 12
6 VC2
VBATOUT 11
V2
7 VC3
CCT 10
V3
8 VSS
CDT
V
9
V4
V
V3
V
CTL1 15
3 COP
CTL2 14
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
V2
CCT 10
7 VC3
V4
V1
R
V2
8 VSS
CDT
9
D
C11 F
CTL1 15
A
3 COP
CTL2 14
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT
V1
V2
V3
A
VBATOUT 11
CCT 10
8 VSS
CDT
9
C11 F
V3
V4
A
VREG 16
2 DOP
CTL1 15
3 COP
CTL2 14
4 VMP
CTL3 13
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT
9
C11 F
Test circuit 8
A
A
A
9
OM
V4
6 VC2
7 VC3
EN
VREG 16
CTL4 12
M
1 VDD
2 DOP
CTL3 13
5 VC1
DE
Test circuit 7
A
CTL2 14
4 VMP
1 VDD
VREG 16
FO
V1
CTL1 15
3 COP
Test circuit 6
R11 M
2 DOP
VREG 16
NE
Test circuit 5
1 VDD
1 VDD
2 DOP
W
C30.1 F C20.1 F C11 F
DE
SI
G
1 VDD
N
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
C11 F
Test circuit 9
NO
T
RE
C
Figure 5 (2 / 2)
15
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Operation
Rev.3.1_01
DE
SI
G
1. Battery protection circuit
Remark Refer to “ Battery Protection IC Connection Example”.
Battery protection protects batteries from overcharge and overdischarge, and also protects external FETs from
overcurrent.
1. 1 Normal status
W
When the voltage of each of the batteries is in the range from VDLn to VCUn and the discharge current is lower than a
specified value (the VMP pin voltage is lower than VIOV1), the charging and discharging FETs are turned on.
NE
1. 2 Overcharge status
R
When the voltage of one of the batteries becomes higher than VCUn and the state continues for tCU or longer, the
COP pin becomes high impedance and is pulled up to EB pin voltage by an external resistor, and the charging FET
is turned off to stop charging. The overcharge status is released when one of the following two conditions holds.
(a) The voltage of each of the batteries becomes lower than VCUn VHCn.
(b) VDDVMPVIOV1 (A load is connected, and discharging starts.)
FO
1. 3 Overdischarge status
DE
1. 3. 1 Power-down function
D
When the voltage of one of the batteries becomes lower than VDLn and the state continues for tDL or longer, the DOP
pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is the overdischarge
status.
M
EN
In the overdischarge status, when the VMP pin voltage is VIOV3 or lower, the power-down function starts to
operate and almost every circuit in the S-8243A/B Series stops working. When the power-down function is
operating, the VMP pin is pulled down to VSS level by the internal resistor RVSM. The conditions of each output
pin are as follows.
(a) COP
High-Z
Charging FET is turned off
(b) DOP
VDD
Discharging FET is turned off
(c) VREG
VSS
Voltage regulator circuit is off
(d) VBATOUT
VSS
Battery voltage monitor amp circuit is off
OM
The power down function is released when the following condition holds.
(a) VMP>VIOV3 (A charger is connected, and charging starts.)
RE
C
The overdischarge status is released when the following condition holds.
(a) The voltage of each of the batteries is VDLn or higher, and the VMP pin voltage is VDD / 2 or higher. (A
charger is connected.)
1. 4 Overcurrent status
NO
T
The S-8243A/B Series has three overcurrent detection levels (VIOV1, VIOV2 and VIOV3) and three overcurrent detection
delay times (tIOV1, tIOV2 and tIOV3) corresponding to each overcurrent detection levels. When the discharging current
becomes higher than a specified value (the voltage between VDD and VMP is greater than VIOV1) and the state
continues for tIOV1 or longer, the S-8243A/B Series enters the overcurrent status in which the DOP pin voltage
becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is
pulled up to EB pin voltage by an external resistor to turn off the charging FET to stop charging, and the VMP pin is
pulled up to VDD voltage by the internal resistor RVDM. Operation of two other overcurrent detection levels (VIOV2 and
VIOV3) and overcurrent detection delay times (tIOV2 and tIOV3) is the same as that for VIOV1 and tIOV1.
The overcurrent status is released when the following condition holds.
(a) VMP> {VIOV3 / (1VIOV3) 3 / 52 / 5} RVDM (A load is released, and the impedance between the EB and
EB pin becomes higher. )
16
N
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
1. 5 0 V battery charging function
DE
SI
G
Regarding the charging of a self-discharged battery (0 V battery) the S-8243A/B Series has two functions from which
one should be selected.
(a) 0 V battery charging is allowed (0 V battery charging is available)
When a charger voltage is higher than V0CHA, 0 V battery can be charged.
(b) 0 V battery charging is forbidden (0 V battery charging is impossible)
When the voltage of one of the batteries is lower than V0INH, 0 V battery can not be charged.
W
Caution When the VDD pin voltage is lower than minimum of VDSOP, the operation of S-8243A/B Series is
not guaranteed.
1. 6 Delay time setting
NE
Overcharge detection delay times (tCU1 to tCU4) are determined by the external capacitor at the CCT pin.
Overdischarge detection delay times (tDL1 to tDL4) and overcurrent detection delay time 1 (tIOV1) are determined by the
external capacitor at CDT pin. Overcurrent detection delay time 2, 3 (tIOV2, tIOV3) are fixed internally.
FO
R
S-8243AAC, S-8243AAD, S-8243BAE, S-8243BAF, S-8243BAH
min.
typ. max.
tCU [s]
= Delay factor (
5
10
15 ) CCT [F]
tDL [ms]
= Delay factor (
500 1000 1500 ) CDT [F]
tIOV1 [ms] = Delay factor (
50
100
150 ) CDT [F]
= Delay factor (
= Delay factor (
= Delay factor (
typ.
10
1110
66.2
max.
15 ) CCT [F]
2220 ) CDT [F]
132 ) CDT [F]
EN
2. Voltage regulator circuit
min.
5
555
33.1
DE
tCU [s]
tDL [ms]
tIOV1 [ms]
D
S-8243BAD
Built-in voltage regulator can be used to drive a micro computer, etc. The voltage regulator supplies voltage of 3.3 V (3
mA maximum) and an external capacitor is needed.
M
Caution When the power-down function operates, the voltage regulator output is pulled down to the VSS level
by an internal resistor.
OM
3. Battery monitor amp circuit
Battery monitor amp sends information of the batteries to a microcomputer. The battery monitor amp output is
controlled and selected by CTL3 and CTL4 pins to give the following two voltages.
RE
C
(a) VBATn = GAMPn VBATTERYn VOFFn where GAMPn is the n-th voltage gain of the amp, VBATTERYn is the n-th
battery voltage, and VOFFn is the n-th offset voltage of the amp.
(b) N-th offset voltage VOFFn
Each battery voltage VBATTERYn (n = 1 to 4) is thus calculated by following equation.
VBATTERYn = (VBATn VOFFn) / GAMPn (n = 1, 2, 3, 4)
NO
T
After the state of CTL3 and CTL4 are changed, a time between 25 s and 250 s is needed for the battery monitor amp
to become stable.
Caution When the power-down function operates, the battery monitor amp output is pulled down to the VSS
level by an internal resistor.
17
Rev.3.1_01
N
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
4. CTL pins
DE
SI
G
The S-8243A/B Series has four control pins. The CTL1 and CTL2 pins are used to control the COP and DOP pin output
voltages. CTL1 takes precedence over CTL2. CTL2 takes precedence over the battery protection circuit. The CTL3
and CTL4 pins are used to control the VBATOUT pin output voltage.
Table 9 CTL1 and CTL2 Mode
Output
CTL1 pin
CTL2 pin
External discharging FET
External charging FET
High
High
OFF
OFF
High
Open
OFF
OFF
High
Low
OFF
OFF
Open
High
OFF
OFF
Open
Open
OFF
OFF
Open
Low
OFF
OFF
Normal*1
OFF*2
Low
High
Normal*1
Normal*1
Low
Open
Normal*1
Low
Low
OFF
*1. States are controlled by voltage detection circuit.
*2. Off state is brought after the overcharge detection delay time tCU.
FO
R
NE
W
Input
Table 10 CTL3 and CTL4 Mode
OM
M
EN
DE
D
Input
Output
CTL3 pin
CTL4 pin
VBATOUT (A series)
VBATOUT (B series)
High
High
V1 Offset
V1 Offset
High
Open
V1 0.2 V1 Offset
V1 0.2 V1 Offset
High
Low
Don’t use.
V2 Offset
Open
High
Don’t use.
V2 0.2 V2 Offset
Open*1
Open*1
V2 Offset
V3 Offset
Open
Low
V2 0.2 V2 Offset
V3 0.2 V3 Offset
Low
High
V3 Offset
V4 Offset
Low
Open
V3 0.2 V3 Offset
V4 0.2 V4 Offset
Low
Low
Don’t use.
Don’t use.
*1. CTL3 and CTL4 pins should be open when a microcomputer is not used.
NO
T
RE
C
Caution Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) aMSS is generated through the external filter (RVSS and CVSS) as a result of input
voltage fluctuations.
18
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
N
Timing Charts
DE
SI
G
1. Overcharge detection, Overdischarge detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
W
(n = 1 to 4)
VDD
NE
DOP pin voltage
VSS
High-Z
VSS
VIOV3
DE
VMP pin
voltage
M
VBATOUT pin
*1
voltage
EN
VSS
VOUT
VBAT
High-Z
D
VDD
VIOV1
FO
COP pin voltage
R
VEB+
OM
VSS
VDD
VOUT
RE
C
VREG pin voltage
VSS
Charger connected
T
Load connected
*2
Overdischarge detection
delay time (tDL)
NO
Status
Overcharge detection
delay time (tCU)
*1. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.
*2. : Normal status, : Overcharge status, : Overdischarge status, : Power down status
Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger.
Figure 6
19
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
VHC
VCU
VCL
DE
SI
G
Battery
voltage
N
2. Overcurrent detection
VDU
VDL
VHD
W
VDD
NE
DOP pin
voltage
VSS
COP pin
voltage
VBAT
VSS
VREG pin
voltage
D
OM
VDD
EN
VBATOUT
*2
pin voltage
*1
VRETURN
M
VOUT
High-Z
DE
VDD
VIOV1
VIOV2
VIOV3
VSS
High-Z
FO
High-Z
VSS
VMP pin
voltage
R
VEB+
VOUT
RE
C
VSS
Charger connected
Load connected
*3
T
Status
Overcurrent detection
delay time 1 ( tIOV1)
Overcurrent detection
delay time 2 ( tIOV2)
Overcurrent detection
delay time 3 ( tIOV3)
NO
*1. VRETURN = VDD / 6 (typ.)
*2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.
*3. : Normal status, : Overcurrent status
Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger.
Figure 7
20
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
DOP pin
Voltage
VDD
VDD
VDD
VDD
VDD
VDD
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
VSS
VEB+
COP pin
Voltage
VOUT
VDD
EN
VOUT
OPEN
M
VSS
RE
C
VSS
OM
VDD
OPEN
*1
DE
VDD
VOUT
Normal
D
VOUT
VSS
CTL2 pin
Voltage
*1
FO
VSS
CTL1 pin
Voltage
Normal
R
VBAT
VBATOUT
*2
pin Voltage
VREG pin
Voltage
High-Z
VDD
NE
VSS
Normal*1 Normal*1
W
VDD
DE
SI
G
N
3. CTL1, CTL2 pin voltage
*1. State depends on each battery voltage and the VMP pin voltage.
*2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.
NO
T
Figure 8
21
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
DE
SI
G
N
4. CTL3, TL4 pin voltage
VDD
DOP pin
*1
voltage
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
V1 0.2
Don’t
use
Don’t
use
(1)
VSS
VREG pin
voltage
VOUT
OPEN
V3 0.2
Don’t
use
NE
(1)
V2 offset
V2 offset
FO
D
V2 offset
V2 0.2
V1 0.2
V1 offset
V2 0.2
V2 offset
V3 offset
V3 offset
V3 0.2
V3 offset
V3 offset
V4 0.2
V4 offset
V4 offset
Don’t
use
RE
C
VSS
(1)
OM
VOUT
CTL3 pin
voltage
(1)
M
VSS
VDD
(1)
EN
VDD
V1 offset
DE
VOUT
S-8243B
(4-serial cell) VBAT
VBATOUT
VOFF
pin voltage
V1 offset
VSS
(1)
R
VSS
VOUT
S-8243A
(3-serial cell) VBAT
VBATOUT
VOFF
pin voltage
V1 offset
VSS
W
VEB+
COP pin
*1
voltage
Rev.3.1_01
VDD
CTL4 pin
voltage
VOUT
OPEN
T
VSS
NO
*1. State depends on CTL1 and CTL2 and each battery voltage and the VMP pin voltage. Refer to Figure 6 to 8.
22
Figure 9
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Battery Protection IC Connection Example
Discharging FET
DE
SI
G
1. S-8243A Series
Charging FET
EB+
RCOP
RVMP
CTL1
RDOP
1 VDD
VREG 16
2 DOP
CTL1 15
CVREG
3 COP
CTL2 14
4 VMP
CTL3 13
W
RCTL1
RCTL2
CVC2
RVC3
RCTL3
CTL4 12
RCTL4
6 VC2
VBATOUT 11
7 VC3
CCT 10
RVBAT
CVC3
CVSS
R
RVC2
S-8243A
NE
5 VC1
Microcomputer
8 VSS
9
FO
RVSS
CDT
CCCT
CCDT
EB-
DE
D
Figure 10
Table 11 Constants for External Components
Part
Typ.
Range
0.51 to 1*1
1
RVC2
1
0.51 to 1*1
2
RVC3
1
2.2 to 10*1
3
RVSS
10
4
RDOP
5.1
2 to 10
5
RCOP
1
0.1 to 1
6
RVMP
5.1
1 to 10
7
RCTL1
1
1 to 100
8
RCTL2
1
1 to 10
9
RCTL3
1
1 to 10
10
RCTL4
1
1 to 10
11
RVBAT
0
0 to 100
0.047 to 0.22*1
12
CVC2
0.047
0.047 to 0.22*1
13
CVC3
0.047
2.2 to 10*1
14
CVSS
4.7
15
CCCT
0.1
More than 0.01
16
CCDT
0.1
More than 0.02
17
CVREG
4.7
0.68 to 10
*1. Please set up a filter constant to be RVSS CVSS 22 F and to be
RVC2 CVC2 = RVC3 CVC3 = RVSS CVSS.
Unit
k
k
k
M
k
k
k
k
k
k
F
F
F
F
F
F
NO
T
RE
C
OM
M
EN
No.
Caution1. No resistance should be inserted in the power supply pin VDD.
2. The above constants are subject to change without prior notice.
3. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant will
not guarantee successful operation. Perform thorough evaluation using the actual application to set
the constant.
23
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Charging FET
DE
SI
G
Discharging FET
N
2. S-8243B Series
Rev.3.1_01
EB+
RCOP
RVMP
CTL1
RDOP
1 VDD
VREG 16
2 DOP
CTL1 15
CVREG
RCTL1
3 COP
CTL2 14
4 VMP
CTL3 13
RVC1
CVC2
RVC2
RCTL3
5 VC1
CTL4 12
6 VC2
VBATOUT 11
7 VC3
CCT 10
RCTL4
RVBAT
CVC3
CVSS
8 VSS
CDT
9
CCCT
R
RVC3
S-8243B
Microcomputer
NE
CVC1
W
RCTL2
RVSS
FO
CCDT
EB-
D
Figure 11
DE
Table 12 Constants for External Components
NO
T
RE
C
OM
M
EN
No.
Part
Typ.
Range
0.51 to 1*1
1
RVC1
1
0.51 to 1*1
2
RVC2
1
0.51 to 1*1
3
RVC3
1
2.2 to 10*1
4
RVSS
10
5
RDOP
5.1
2 to 10
6
RCOP
1
0.1 to 1
7
RVMP
5.1
1 to 10
8
RCTL1
1
1 to 100
9
RCTL2
1
1 to 10
10
RCTL3
1
1 to 10
11
RCTL4
1
1 to 10
12
RVBAT
0
0 to 100
0.047 to 0.22*1
13
CVC1
0.047
0.047 to 0.22*1
14
CVC2
0.047
0.047 to 0.22*1
15
CVC3
0.047
2.2 to 10*1
16
CVSS
4.7
17
CCCT
0.1
More than 0.01
18
CCDT
0.1
More than 0.02
19
CVREG
4.7
0.68 to 10
*1. Please set up a filter constant to be RVSS CVSS 22 F and to be
RVC1 CVC1 = RVC2 CVC2 = RVC3 CVC3 = RVSS CVSS.
Unit
k
k
k
k
M
k
k
k
k
k
k
F
F
F
F
F
F
F
Caution1. No resistance should be inserted in the power supply pin VDD.
2. The above constants are subject to change without prior notice.
3. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant will
not guarantee successful operation. Perform thorough evaluation using the actual application to set
the constant.
24
Rev.3.1_01
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
N
Precautions
DE
SI
G
Pay attention to the operating conditions for input/output voltage and load current so that the power loss in the IC does
not exceed the package power dissipation.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
NO
T
RE
C
OM
M
EN
DE
D
FO
R
NE
W
ABLIC Inc. shall not be responsible for any patent infringement by products including the S-8243A/B Series, the method
of using the S-8243A/B Series in such products, the product specifications or the country of destination thereof.
25
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
N
The Example of Application Circuit
DE
SI
G
1. S-8243A Series
EB
VREG
CTL1
REG
VREG 16
VCC
S-8243A
CTL1 15
3 COP
CTL2 14
CTL2
4 VMP
CTL3 13
CTL3
6 VC2
VBATOUT 11
7 VC3
CCT 10
8 VSS
CDT
VREG
CTL4
VREG
VCELL1
THON
9
LED5
DISP
VOUT
ESCL
NE
CTL4 12
LED3
Bq2063 LED4
2 DOP
5 VC1
LED2
W
1 VDD
LED1
ESCD
VCC
A0
SCL
A2
WP
GND
S-24C A1
SDA
SMBC
SMBus
SMBD
R
VT
FO
RB1
VSS
HDQ
SR2
SR1
SRC
D
EB
DE
Figure 12
EN
2. S-8243B Series
VREG
CTL1
REG
VCC
CTL1 15
3 COP
CTL2 14
CTL2
4 VMP
CTL3 13
CTL3
VOUT
VCC
A0
5 VC1
CTL4 12
CTL4
ESCL
SCL
6 VC2
VBATOUT 11
VCELL1
ESCD
SDA
A2
WP
GND
M
2 DOP
OM
26
LED2
VREG 16
7 VC3
CCT 10
8 VSS
CDT
LED3
VREG
Bq2063 LED4
VREG
THON
9
LED5
DISP
S-24C A1
SMBC
SMBD
SMBus
VT
HDQ
RB1
T
NO
Caution
LED1
1 VDD
S-8243B
RE
C
EB+
VSS
SR2
SR1
SRC
EB-
Figure 13
The above connection example will not guarantee successful operation. Perform thorough evaluation
using the actual application.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
N
Characteristics (Typical Data)
S-8243BAF
IOPEVDD
120
100
80
80
IOPE [A]
100
60
40
60
40
20
20
0
0
0
4
8
12
16
20
40 20 0
24
VDD [V]
S-8243BAF
S-8243BAF
IPDNVDD
IPDNTemp
0.10
0.08
IPDN [A]
0.08
FO
0.06
0.06
0.04
0.04
0.02
0.00
0.00
40 20
8
12
16 20
VDD [V]
24
0
20 40 60 80
Ta [°C]
DE
4
D
0.02
0
60 80
R
0.10
IPDN [A]
20 40
Ta [°C]
NE
IOPE [A]
IOPETemp
120
W
S-8243BAF
DE
SI
G
1. Current consumption
2. Overcharge detection/release voltage, overdischarge detection/release voltage, overcurrent
detection voltages, and delay times
EN
4.05
3.99
3.95
40 20
0
20 40 60 80
Ta [°C]
20 40 60 80
2.425
2.400
2.375
2.350
2.325
2.300
40 20
Ta [°C]
S-8243BAF
VIOV1VDD
0.225
0.220
0.215
0.210
0.205
0.200
0.195
0.190
0.185
0.180
0.175
10
12
0
20 40 60 80
Ta [°C]
S-8243BAF
VIOV1 [V]
VIOV1 [V]
VDLTemp
0
VDUTemp
2.500
2.475
2.450
3.97
20 40 60 80
T
VDL [V]
S-8243BAF
NO
S-8243BAF
VDU [V]
VCL [V]
M
0
4.01
Ta [°C]
2.48
2.46
2.44
2.42
2.40
2.38
2.36
2.34
2.32
40 20
VCLTemp
4.03
OM
4.275
4.270
4.265
4.260
4.255
4.250
4.245
4.240
4.235
4.230
4.225
40 20
S-8243BAF
VCU Temp
RE
C
VCU [V]
S-8243BAF
14
VDD [V]
16
0.225
0.220
0.215
0.210
0.205
0.200
0.195
0.190
0.185
0.180
0.175
40 20
VIOV1Temp
0
20 40 60 80
Ta [°C]
27
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
0.40
S-8243BAF
0.40
VIOV3VDD
0.575
0.55
VIOV3 / VDD
VIOV2 [V]
0.45
0.50
0.50
0.55
0.60
14
VDD [V]
S-8243BAF
0.575
12
14
S-8243BAF
tCUCCT
15
0.550
16
VDD [V]
tCU Temp
CCT = 0.1 F
NE
VIOV3Temp
10
20 40 60 80
Ta [°C]
S-8243BAF
0.475
0.425
40 20 0
16
0.500
W
12
0.525
0.450
0.60
10
2.5
0.475
R
tCU [s]
0.500
10
5
0.450
0.425
0
40 20 0
20 40 60 80
0
0.4
0.8
1.0
0.5
0.0
40 20
1.0
0
DE
CCT [F]
S-8243BAF
S-8243BAF
tDLCDT
250
tDL Temp
CDT = 0.1 F
EN
1500
0.6
1.5
D
Ta [°C]
0.2
tCU [s]
2.0
0.525
FO
VIOV3 / VDD
S-8243BAF
0.550
0.45
VIOV2 [V]
VIOV2 Temp
VDD Reference
N
VIOV2VDD
VDD Reference
DE
SI
G
S-8243BAF
Rev.3.1_01
20
40 60 80
Ta [°C]
S-8243BAF
tIOV1CDT
150
tDL [ms]
M
0
0
0.2
OM
tDL [ms]
500
0.4
0.6
0.8
tIOV1 [ms]
200
1000
150
100
0
0
40 20 0
1.0
NO
5
40 20 0
28
tIOV2 Temp
4.0
Ta [°C]
0.6
0.8
1.0
tIOV3 Temp
600
500
3.5
3.0
2.5
400
300
200
1.5
20 40 60 80
0.4
S-8243BAF
S-8243BAF
2.0
0
0.2
CDT [F]
tIOV3 [s]
10
0
20 40 60 80
Ta [°C]
tIOV2 [ms]
15
T
tIOV1 [ms]
20
RE
C
25
tIOV1 Temp
CDT = 0.1 F
50
50
CDT [F]
S-8243BAF
100
40 20
0
20 40 60 80
Ta [°C]
100
40 20
0
20 40 60 80
Ta [°C]
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
ICOHVCOP
0.10
ICOL [mA]
0.06
0.04
0.02
0.00
0
4
8
ICOLVCOP
40
35
30
25
20
15
10
5
0
0
12 16 20 24
3.5
S-8243BAF
3
25
20
15
10
5
0
4
5
3.6
5.4
R
2
7.2
FO
IDOL [mA]
IDOH [mA]
1
1.8
14.0
IDOLVDOP
40
35
30
D
0
0
3.5
7.0
10.5
14.0
VDOP [V]
DE
VDOP [V]
4. Voltage regulator
S-8243BAF
EN
S-8243BAF
VOUT Temp
3.6
3.5
3.8
3.3
3.2
3.1
3.0
0
20 40 60 80
RE
C
40 20
VOUT [V]
M
3.4
OM
VOUT [V]
10.5
S-8243BAF
IDOHVDOP
0
7.0
VCOP [V]
NE
VCOP [V]
VOUTVDD
VDD = 024 V, Ta = 25°C
4.0
VOUTIOUT
V1 = V2 = V3 = V4 = VBAT
IOUT = 5 A
3.0
3.3
100 A
2.8
10 mA
18 V
2.0
2.3
VDD = 6 V
0.0
0
4
8
12
16
20
24
10 V
14 V
1.0
3 mA
VDD [V]
Ta [°C]
S-8243BAF
VOUT [V]
ICOH [A]
0.08
DE
SI
G
S-8243BAF
W
S-8243BAF
N
3. COP / DOP pin current
0
20
40 60 80 100
IOUT [mA]
S-8243BAF
4.0
VOUTIOUT
2.0
NO
VOUT [V]
T
3.0
85°C
25°C
1.0
Ta = 40°C
0.0
0
20
40
60
80
100
IOUT [mA]
29
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series
Rev.3.1_01
VOFFVBAT
V1 = V2 = V3 = V4 = VBAT
180
S-8243BAF
180
175
160
VOFF3
170
VOFF2
165
160
VOFF3
155
VOFF4
150
150
1
2
3
4
5
VOFF1
40 20 0
VBAT [V]
20
R
GAMP4
FO
GAMP3
0.200
0.199
GAMP2 GAMP1
0.198
40 20 0
20 40 60 80
NO
T
RE
C
OM
M
EN
DE
Ta [°C]
0.200
NE
GAMP Temp
GAMP4
GAMP2
GAMP1
0.198
40 60 80
Ta [°C]
D
GAMP
0.201
GAMP3
0.199
VOFF4
S-8243BAF
0.202
GAMP
VOFF2
GAMPVBAT
V1 = V2 = V3 = V4 = VBAT
0.201
W
VOFF1
165
155
30
0.202
175
170
VOFF [mV]
VOFF [mV]
S-8243BAF
VOFF Temp
DE
SI
G
S-8243BAF
N
5. Battery monitor amp
1
2
3
4
VBAT [V]
5
N
9
1
8
R
NE
W
16
DE
SI
G
5.1±0.2
DE
D
FO
0.17±0.05
0.22±0.08
OM
M
EN
0.65
NO
T
RE
C
No. FT016-A-P-SD-1.2
TITLE
TSSOP16-A-PKG Dimensions
FT016-A-P-SD-1.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
N
4.0±0.1
ø1.5 -0
0.3±0.05
8.0±0.1
1.5±0.1
NE
ø1.6±0.1
W
DE
SI
G
2.0±0.1
(7.2)
+0.4
16
8
9
Feed direction
No. FT016-A-C-SD-1.1
NO
T
RE
C
OM
M
EN
1
DE
D
6.5 -0.2
FO
R
4.2±0.2
TITLE
TSSOP16-A-Carrier Tape
No.
FT016-A-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
NE
W
DE
SI
G
N
21.4±1.0
FO
R
17.4±1.0
D
2±0.5
ø13±0.2
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
+2.0
17.4 -1.5
NO
T
RE
C
No. FT016-A-R-SD-2.0
TITLE
TSSOP16-A- Reel
FT016-A-R-SD-2.0
No.
ANGLE
UNIT
QTY.
mm
ABLIC Inc.
2,000
NE
W
DE
SI
G
N
21.4±1.0
FO
R
17.4±1.0
D
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
+2.0
17.4 -1.5
No. FT016-A-R-S1-1.0
TITLE
TSSOP16-A- Reel
No.
FT016-A-R-S1-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
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10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
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11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
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13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
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14. For more details on the information described herein, contact our sales office.
NO
2.0-2018.01
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