S-8204B Series
www.ablic.com
www.ablicinc.com
BATTERY PROTECTION IC
FOR 3-SERIES OR 4-SERIES CELL PACK
© ABLIC Inc., 2008-2016
Rev.3.9_01
The S-8204B Series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it possible for
users to monitor the status of 3-series or 4-series cell lithium-ion rechargeable battery. By switching the voltage level which
is applied to the SEL pin, users are able to use the S-8204B Series either for 3-series or 4-series cell pack.
By cascade connection using the S-8204B Series, it is also possible to protect 6-series or more cells*1 lithium-ion
rechargeable battery pack.
*1. Refer to the application note for connection examples of protection circuit for 6-series or more cells.
In case of protecting 5-series cell lithium-ion rechargeable battery pack, contact our sales office.
Features
High-accuracy voltage detection function for each cell
Overcharge detection voltage n (n = 1 to 4)
3.65 V to 4.6 V (50 mV step)
Accuracy 25 mV
Overcharge release voltage n (n = 1 to 4)
3.5 V to 4.6 V*1
Accuracy 50 mV
Overdischarge detection voltage n (n = 1 to 4)
2.0 V to 3.0 V (100 mV step)
Accuracy 80 mV
*2
Accuracy 100 mV
Overdischarge release voltage n (n = 1 to 4)
2.0 V to 3.4 V
Discharge overcurrent detection in 3-step
Discharge overcurrent detection voltage 1
0.05 V to 0.30 V (50 mV step)
Accuracy 15 mV
Discharge overcurrent detection voltage 2
0.5 V (fixed)
Accuracy 100 mV
Load short-circuit detection voltage
1.0 V (fixed)
Accuracy 300 mV
Settable by external capacitor; overcharge detection delay time, overdischarge detection delay time, discharge
overcurrent detection delay time 1, discharge overcurrent detection delay time 2
(Load short-circuit detection delay time is internally fixed.)
Switchable between 3-series and 4-series cell by using the SEL pin
Independent charge and discharge control by the control pins
Power-down function "available" / "unavailable" is selectable
High-withstand voltage
Absolute maximum rating: 24 V
Wide operation voltage range
2 V to 22 V
Wide operation temperature range
Ta = 40C to 85C
Low current consumption
During operation
33 A max. (Ta = 25C)
During power-down
0.1 A max. (Ta = 25C)
*3
Lead-free, Sn 100%, halogen-free
*1. Overcharge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.1 V to 0.4 V in 50 mV step.
(Overcharge hysteresis voltage = Overcharge detection voltage Overcharge release voltage)
*2. Overdischarge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.2 V to 0.7 V in 100 mV step.
(Overdischarge hysteresis voltage = Overdischarge release voltage Overdischarge detection voltage)
*3. Refer to " Product Name Structure" for details.
Application
Rechargeable lithium-ion battery pack
Package
16-Pin TSSOP
1
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Block Diagram
Control circuit
COP
Delay circuit
Delay circuit
CTLC
Delay circuit
CTLD
RVMD
VMP
RVMS
VDD
Delay circuit
Delay circuit
Overcharge
1
Overdischarge 1
Overcharge
2
Overdischarge 2
DOP
VINI
VC1
VC2
Discharge
overcurrent 1
Discharge
overcurrent 2
Load short circuit
Overcharge
3
Overdischarge 3
VC3
Overcharge
4
VC4
Overdischarge 4
CDT
CCT
CIT
VSS
SEL
Remark Diodes in the figure are parasitic diodes.
Figure 1
2
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Product Name Structure
1. Product name
S-8204B
xx
-
xxxx
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
S:
Lead-free, halogen-free
Package name (abbreviation) and packing specifications*1
TCT1: 16-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name
16-Pin TSSOP
Environmental code = S
Environmental code = U
Dimension
Tape
Reel
FT016-A-P-SD
FT016-A-P-SD
FT016-A-C-SD
FT016-A-C-SD
FT016-A-R-SD
FT016-A-R-S1
3
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
3. Product name list
Table 2
Discharge
Overcharge Overdischarge Overdischarge
Overcurrent
Release
Detection
Release
Detection
Voltage
Voltage
Voltage
Voltage 1
[VCL]
[VDL]
[VDU]
[VDIOV1]
Product Name
Overcharge
Detection
Voltage
[VCU]
S-8204BAB-TCT1y
4.350 V
4.150 V
2.00 V
2.70 V
0.250 V
Available
Available
S-8204BAC-TCT1y
4.225 V
4.075 V
2.30 V
3.00 V
0.100 V
Available
Available
S-8204BAD-TCT1y
S-8204BAE-TCT1y
S-8204BAF-TCT1y
S-8204BAG-TCT1y
S-8204BAH-TCT1y
S-8204BAI-TCT1y
S-8204BAJ-TCT1y
S-8204BAK-TCT1y
S-8204BAL-TCT1y
S-8204BAM-TCT1y
S-8204BAN-TCT1y
S-8204BAO-TCT1y
S-8204BAP-TCT1y
S-8204BAQ-TCT1y
S-8204BAR-TCT1y
S-8204BAS-TCT1y
S-8204BAT-TCT1y
S-8204BAU-TCT1y
S-8204BAV-TCT1y
S-8204BAW-TCT1y
S-8204BAX-TCT1y
S-8204BAY-TCT1y
S-8204BAZ-TCT1y
S-8204BBA-TCT1y
S-8204BBB-TCT1y
S-8204BBC-TCT1y
S-8204BBD-TCT1y
S-8204BBE-TCT1y
S-8204BBF-TCT1y
S-8204BBG-TCT1y
S-8204BBH-TCT1y
S-8204BBI-TCT1U
S-8204BBJ-TCT1U
S-8204BBK-TCT1U
S-8204BBL-TCT1U
3.800 V
4.350 V
4.350 V
4.350 V
4.200 V
3.900 V
4.300 V
3.650 V
4.200 V
4.400 V
4.100 V
3.900 V
4.320 V
3.800 V
3.850 V
4.250 V
3.650 V
4.200 V
3.900 V
3.800 V
4.250 V
3.900 V
4.250 V
4.250 V
4.250 V
4.250 V
4.300 V
3.800 V
3.800 V
4.250 V
4.250 V
4.250 V
4.250 V
4.250 V
4.230 V
3.600 V
4.150 V
4.150 V
4.150 V
4.000 V
3.800 V
4.100 V
3.500 V
4.100 V
4.200 V
4.100 V
3.600 V
4.120 V
3.600 V
3.650 V
4.150 V
3.500 V
4.100 V
3.600 V
3.650 V
4.250 V
3.600 V
4.100 V
4.150 V
4.150 V
4.100 V
4.200 V
3.600 V
3.600 V
4.100 V
4.150 V
4.150 V
4.150 V
4.190 V
4.230 V
2.00 V
2.50 V
2.30 V
2.80 V
2.60 V
2.00 V
2.50 V
2.40 V
2.70 V
2.00 V
2.00 V
2.50 V
2.40 V
2.00 V
2.50 V
2.80 V
2.00 V
2.70 V
2.00 V
2.20 V
2.00 V
2.30 V
3.00 V
2.50 V
2.70 V
2.80 V
2.30 V
2.00 V
2.00 V
2.80 V
2.70 V
2.70 V
2.70 V
2.80 V
2.80 V
2.30 V
3.00 V
3.00 V
3.30 V
3.00 V
2.00 V
2.90 V
3.00 V
2.90 V
2.70 V
2.50 V
2.70 V
3.00 V
2.30 V
2.70 V
3.00 V
2.70 V
2.90 V
2.70 V
2.50 V
2.00 V
2.50 V
3.30 V
3.00 V
3.00 V
3.20 V
3.00 V
2.30 V
2.30 V
3.30 V
3.00 V
3.00 V
3.00 V
3.00 V
3.00 V
0.300 V
0.250 V
0.100 V
0.100 V
0.100 V
0.150 V
0.250 V
0.100 V
0.250 V
0.250 V
0.150 V
0.100 V
0.100 V
0.150 V
0.150 V
0.150 V
0.100 V
0.100 V
0.100 V
0.100 V
0.100 V
0.100 V
0.100 V
0.100 V
0.250 V
0.250 V
0.100 V
0.100 V
0.050 V
0.100 V
0.125 V
0.125 V
0.150 V
0.150 V
0.150 V
Available
Available
Available
Available
Available
Unavailable
Available
Available
Available
Available
Unavailable
Unavailable
Unavailable
Available
Available
Available
Available
Available
Available
Available
Unavailable
Available
Available
Available
Unavailable
Unavailable
Available
Available
Available
Unavailable
Unavailable
Unavailable
Unavailable
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Unavailable
Unavailable
Available
Available
S-8204BBU-TCT1U
S-8204BBV-TCT1U
4.350 V
4.450 V
4.150 V
4.300 V
2.30 V
2.70 V
3.00 V
3.00 V
0.100 V
0.100 V
Unavailable
Unavailable
Available
Available
0 V Battery
Charge
Function
Power-down
Function
Remark 1. Please contact our sales office for products with detection voltage values other than those specified above.
2. y: S or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
4
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Pin Configuration
1.
16-Pin TSSOP
Top view
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 2
Table 3
Pin No.
Symbol
Description
1
2
3
COP
VMP
DOP
Connection pin of charge control FET gate (Pch open-drain output)
Voltage detection pin between VDD pin and VMP pin
Connection pin of discharge control FET gate (CMOS output)
Voltage detection pin between VSS pin and VINI pin,
discharge overcurrent 1 / 2 detection pin, load short-circuit detection pin
4
VINI
5
CDT
Capacitor connection pin for delay for overdischarge detection
6
7
CCT
CIT
8
SEL
9
VSS
10
VC4
11
VC3
12
VC2
13
VC1
14
VDD
15
16
CTLD
CTLC
Capacitor connection pin for delay for overcharge detection
Capacitor connection pin for delay for discharge overcurrent 1 / 2
Pin for switching 3-series or 4-series cell
VSS level: 3-series cell
VDD level: 4-series cell
Input pin for negative power supply,
connection pin for negative voltage of battery 4
Connection pin for negative voltage of battery 3,
connection pin for positive voltage of battery 4
Connection pin for negative voltage of battery 2,
connection pin for positive voltage of battery 3
Connection pin for negative voltage of battery 1,
connection pin for positive voltage of battery 2
Connection pin for positive voltage of battery 1
Input pin for positive power supply,
connection pin for positive voltage of battery 1
Discharge FET control pin
Charge FET control pin
5
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Absolute Maximum Ratings
Table 4
Item
Input voltage between VDD pin and
VSS pin
Input pin voltage
Symbol
Applied Pin
(Ta = 25C unless otherwise specified)
Absolute Maximum Rating
Unit
VDS
VC1, VC2, VC3, VC4,
CTLC, CTLD, SEL, CCT,
CDT, CIT, VINI
VMP
DOP
COP
VIN
VMP pin input voltage
VVMP
DOP pin output voltage
VDOP
COP pin output voltage
VCOP
Power dissipation
PD
Operation ambient temperature
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size:
114.3 mm 76.2 mm t1.6 mm
(2) Board name: JEDEC STANDARD51-7
VSS 0.3 to VSS 24
V
VSS 0.3 to VDD 0.3
V
VSS 0.3 to VSS 24
VSS 0.3 to VDD 0.3
VDD 24 to VDD 0.3
1100*1
40 to 85
40 to 125
V
V
V
mW
C
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (PD) [mW]
1200
1000
800
600
400
200
0
0
50
100
150
Ambient Temperature (Ta) [C]
Figure 3 Power Dissipation of Package (When Mounted on Board)
6
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Electrical Characteristics
Table 5 (1 / 2)
Item
Detection Voltage
Overcharge detection voltage n
(n = 1, 2, 3, 4)
Overcharge release voltage n
(n = 1, 2, 3, 4)
Symbol
Condition
VCUn
3.65 V to 4.6 V, adjustable,
50 mV step
VCLn
3.5 V to 4.6 V,
adjustable,
50 mV step
VCL VCU
VCL = VCU
Overdischarge detection voltage n
VDLn
(n = 1, 2, 3, 4)
2.0 V to 3.0 V, adjustable,
100 mV step
Overdischarge release voltage n
(n = 1, 2, 3, 4)
2.0 V to 3.4 V,
adjustable,
100 mV step
Discharge overcurrent detection
voltage 1
Discharge overcurrent detection
voltage 2
Load short-circuit detection
voltage
Temperature coefficient 1*1
Temperature coefficient 2*2
Delay Time Function*4
VDUn
VDIOV1
VDL VDU
VDL = VDU
0.05 V to 0.30 V, adjustable
(Ta = 25C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
VCUn
0.025
VCLn
0.05
VCLn
0.025
VDLn
0.08
VDUn
0.10
VDUn
0.08
VDIOV1
0.015
VCUn
VCLn
VCLn
VDLn
VDUn
VDUn
VDIOV1
VCUn
0.025
VCLn
0.05
VCLn
0.025
VDLn
0.08
VDUn
0.10
VDUn
0.08
VDIOV1
0.015
V
2
V
2
V
2
V
2
V
2
V
2
V
2
VDIOV2
0.4
0.5
0.6
V
2
VSHORT
0.7
1.0
1.3
V
2
TCOE1
TCOE2
Ta = 0°C to 50°C*3
Ta = 0°C to 50°C*3
1.0
0.5
0
0
1.0
0.5
mV/°C
mV/°C
2
2
CCT pin internal resistance
RINC
V1 = 4.7 V, V2 = V3 = V4 = 3.5 V
6.15
8.31
10.2
M
3
CDT pin internal resistance
RIND
V1 = 1.5 V, V2 = V3 = V4 = 3.5 V
615
831
1020
k
3
CIT pin internal resistance 1
RINI1
V1 = V2 = V3 = V4 = 3.5 V
123
166
204
k
3
CIT pin internal resistance 2
RINI2
V1 = V2 = V3 = V4 = 3.5 V
12.3
16.6
20.4
k
3
CCT pin detection voltage
VCCT
VDS = 15.2 V,
V1 = 4.7 V, V2 = V3 = V4 = 3.5 V
VDS
0.68
VDS
0.70
VDS
0.72
V
3
CDT pin detection voltage
VCDT
VDS = 12.0 V,
V1 = 1.5 V, V2 = V3 = V4 = 3.5 V
VDS
0.68
VDS
0.70
VDS
0.72
V
3
CIT pin detection voltage
VCIT
VDS = 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
VDS
0.68
VDS
0.70
VDS
0.72
V
3
tSHORT
FET gate capacitance = 2000 pF
100
300
600
s
3
1.2
2.0
V
2
0.4
0.7
1.1
V
2
0.5
1
1.5
M
4
450
900
1800
k
4
Load short-circuit detection
delay time
0 V Battery Charge Function
0 V battery charge starting
voltage
0 V battery charge inhibition
battery voltage
Internal Resistance
Resistance between
VMP pin and VDD pin
Resistance between
VMP pin and VSS pin
V0CHA
V0INH
RVMD
RVMS
0 V battery charge function
"available"
0 V battery charge function
"unavailable"
With power-down function
7
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Table 5 (2 / 2)
(Ta = 25C unless otherwise specified)
Item
Input Voltage
Operation voltage between VDD
pin and VSS pin
CTLC pin input voltage "H"
CTLC pin input voltage "L"
CTLD pin input voltage "H"
CTLD pin input voltage "L"
Symbol
VDSOP
VCTLCH
VCTLCL
VCTLDH
VCTLDL
SEL pin input voltage "H"
VSELH
SEL pin input voltage "L"
VSELL
Input Current
Current consumption
during operation
Current consumption
during power-down
Current consumption
during overdischarge
VC1 pin current
VC2 pin current
VC3 pin current
VC4 pin current
IVC1
IVC2
IVC3
IVC4
CTLC pin current "H"
ICTLCH
CTLC pin current "L"
ICTLCL
CTLD pin current "H"
ICTLDH
CTLD pin current "L"
ICTLDL
SEL pin current "H"
ISELH
SEL pin current "L"
ISELL
IOPE
IPDN
IOPED
Condition
Fixed output voltage of DOP pin and
COP pin
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
VDS = 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
VDS = 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
With power-down function,
V1 = V2 = V3 = V4 = 1.5 V
Without power-down function,
V1 = V2 = V3 = V4 = 1.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V,
VCTLC = VDD
V1 = V2 = V3 = V4 = 3.5 V,
maximum current flowing from CTLC pin
V1 = V2 = V3 = V4 = 3.5 V,
VCTLD = VDD
V1 = V2 = V3 = V4 = 3.5 V,
maximum current flowing from CTLD pin
V1 = V2 = V3 = V4 = 3.5 V,
VSEL = VDD
V1 = V2 = V3 = V4 = 3.5 V,
VSEL = VSS
Min.
Typ.
Max.
Unit
Test
Circuit
2
22
V
2
10.1
10.1
VDS
0.8
13.2
13.2
V
V
V
V
2
2
2
2
V
2
VDS
0.2
V
2
15
33
A
1
0.1
A
1
14
32
A
1
0.5
0.3
0.3
0.3
1.5
0
0
0
3.0
0.3
0.3
0.3
A
A
A
A
4
4
4
4
0.4
0.6
0.8
A
4
20.0
10.0
3.0
A
4
0.4
0.6
0.8
A
4
20.0
10.0
3.0
A
4
0.1
A
4
0.1
A
4
Output Current
COP pin source current
ICOH
VCOP = VDD 0.5 V
10
A
4
COP pin leakage current
ICOL
VCOP = 0 V
0.1
A
4
DOP pin source current
IDOH
VDOP = VDD 0.5 V
10
A
4
DOP pin sink current
IDOL
VDOP = VSS 0.5 V
10
A
4
*1. Voltage temperature coefficient 1: Overcharge detection voltage
*2. Voltage temperature coefficient 2: Discharge overcurrent detection voltage 1
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*4. Details of delay time function is described in " Operation".
8
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Test Circuit
This chapter describes how to test the S-8204B Series. In case of selecting to use it for 4-series cell battery, set SEL pin
= VDD. For 3-series cell battery, set SEL pin = VSS and short between the VC4 pin and the VSS pin.
1.
Current consumption during operation and power-down
(Test circuit 1)
1. 1 Current consumption during operation (IOPE)
The current at the VSS pin when V1 = V2 = V3 = V4 = 3.5 V and VVMP = VDD is the current consumption during
operation (IOPE).
1. 2 Current Consumption during power-down (IPDN) (with power-down function)
The current at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VVMP = VSS is the current consumption during
power-down (IPDN).
1. 3 Current consumption during overdischarge (IOPED) (without power-down function)
The current at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VVMP = VSS is the current consumption during
overdischarge (IOPED).
2.
Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage,
overdischarge release voltage, discharge overcurrent detection voltage 1, discharge overcurrent
detection voltage 2, load short-circuit detection voltage, CTLC pin input voltage "H", CTLC pin
input voltage "L", CTLD pin input voltage "H", CTLD pin input voltage "L", SEL pin input voltage
"H", SEL pin input voltage "L"
(Test circuit 2)
Confirm both the COP pin and the DOP pin are in "H" (its voltage level is VDS 0.9 V or more) after setting VVMP =
VSEL = VCTLC = VCTLD = VDD, VVINI = VSS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2 = V3 = V4 =
3.5 V. (This status is referred to as initial status.)
2. 1 Overcharge detection voltage (VCU1), overcharge release voltage (VCL1)
The overcharge detection voltage (VCU1) is a voltage at V1; when the COP pin's voltage is set to "L" (its voltage
level is VDD 0.1 V or less) after increasing a voltage at V1 gradually from the initial status. After that, decreasing
a voltage at V1 gradually, a voltage at V1 when the COP pin's voltage is set to "H"; is the overcharge release
voltage (VCL1).
2. 2 Overdischarge detection voltage (VDL1), overdischarge release voltage (VDU1)
The overdischarge detection voltage (VDL1) is a voltage at V1; when the DOP pin's voltage is set to "L" after
decreasing a voltage at V1 gradually from the initial status. After that, increasing a voltage at V1 gradually, a
voltage at V1 when the DOP pin’s voltage is set to "H"; is the overdischarge release voltage (VDU1).
By changing the voltage at Vn (n = 2 to 4), users can define the overcharge detection voltage (VCUn), the
overcharge release voltage (VCLn), the overdischarge detection voltage (VDLn), the overdischarge release voltage
(VDUn) as well when n = 1.
2. 3 Discharge overcurrent detection voltage 1 (VDIOV1)
The discharge overcurrent detection voltage 1 (VDIOV1) is the VINI pin's voltage; when the DOP pin's voltage is set
to "L" after increasing the VINI pin’s voltage gradually from the initial status.
2. 4 Discharge overcurrent detection voltage 2 (VDIOV2)
The discharge overcurrent detection voltage 2 (VDIOV2) is a voltage at the VINI pin; when a flowing current from
the CIT pin reaches 500 A or more after increasing the VINI pin's voltage gradually from the initial status.
2. 5 Load short-circuit detection voltage (VSHORT)
The load short-circuit detection voltage (VSHORT) is the VINI pin's voltage; when the DOP pin's voltage is set to "L"
after increasing the VINI pin's voltage gradually after setting the CIT pin's voltage VSS level from the initial status.
9
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
2. 6 CTLC pin input voltage "H" (VCTLCH), CTLC pin input voltage "L" (VCTLCL)
The CTLC pin input voltage "L" (VCTLCL) is the CTLC pin's voltage; when the COP pin's voltage is set to "L" after
decreasing the CTLC pin's voltage gradually from the initial status. After that, increasing the CTLC pin's voltage
gradually, the CTLC pin's voltage when the COP pin's voltage is set to "H"; is the CTLC pin input voltage "H"
(VCTLCH).
2. 7 CTLD pin input voltage "H" (VCTLDH), CTLD pin input voltage "L" (VCTLDL)
The CTLD pin input voltage "L" (VCTLDL) is the CTLD pin's voltage; when the DOP pin's voltage is set to "L" after
decreasing the CTLD pin's voltage gradually from the initial status. After that, increasing the CTLD pin's voltage
gradually, the CTLD pin's voltage when the DOP pin's voltage is set to "H"; is the CTLD pin input voltage "H"
(VCTLDH).
2. 8 SEL pin input voltage "H" (VSELH), SEL pin input voltage "L" (VSELL)
Start from the initial status, set V4 = 0 V. Confirm the DOP pin is in "L". After that, decreasing the SEL pin's
voltage gradually, the SEL pin's voltage when the DOP pin's voltage is set to "H"; is the SEL pin input voltage "L"
(VSELL). After that, increasing the SEL pin's voltage gradually, the SEL pin's voltage when the DOP pin's voltage is
set to "L"; is the SEL pin input voltage "H" (VSELH).
3.
CCT pin internal resistance, CDT pin internal resistance, CIT pin internal resistance 1, CIT pin
internal resistance 2, CCT pin detection voltage, CDT pin detection voltage, CIT pin detection
voltage, load short-circuit detection delay time
(Test circuit 3)
Confirm both the COP pin and the DOP pin are in "H" (its voltage level is VDS 0.9 V or more) after setting VVMP =
VSEL = VCTLC = VCTLD = VDD, VVINI = CCT = CDT = CIT = VSS, V1 = V2 = V3 = V4 = 3.5 V. (This status is referred to
as initial status.)
3. 1 CCT pin internal resistance (RINC)
The CCT pin internal resistance (RINC) is RINC = VDS / ICCT, ICCT is the current which flows from the CCT pin when
setting V1 = 4.7 V from the initial status.
3. 2 CDT pin internal resistance (RIND)
The CDT pin internal resistance (RIND) is RIND = VDS / ICDT, ICDT is the current which flows from the CDT pin when
setting V1 = 1.5 V from the initial status.
3. 3 CIT pin internal resistance 1 (RINI1)
The CIT pin internal resistance 1 (RINI1) is RINI1 = VDS / ICIT1, ICIT1 is the current which flows from the CIT pin when
setting VVINI = VDIOV1 max.0.05 V from the initial status.
3. 4 CIT pin internal resistance 2 (RINI2)
The CIT pin internal resistance 2 (RINI2) is RINI2 = VDS / ICIT2, ICIT2 is the current which flows from the CIT pin when
setting VVINI = VDIOV2 max0.05 V from the initial status.
3. 5 CCT pin detection voltage (VCCT)
The CCT pin detection voltage (VCCT) is the voltage at the CCT pin when the COP pin's voltage is set to "L"
(voltage VDS 0.1 V or less) after increasing the CCT pin's voltage gradually, after setting V1 = 4.7 V from the
initial status.
3. 6 CDT pin detection voltage (VCDT)
The CDT pin detection voltage (VCDT) is the voltage at the CDT pin when the DOP pin's voltage is set to "L"
(voltage VDS 0.1 V or less) after increasing the CDT pin's voltage gradually, after setting V1 = 1.5 V from the
initial status.
10
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
3. 7 CIT pin detection voltage (VCIT)
The CIT pin detection voltage (VCIT) is the voltage at the CIT pin when the DOP pin's voltage is set to "L" (voltage
VDS 0.1 V or less) after increasing the CIT pin's voltage gradually, after setting VVINI = VDIOV1 max.0.05 V from
the initial status.
3. 8 Load short-circuit detection delay time (tSHORT)
Load short-circuit detection delay time (tSHORT) is a period in which the VINI pin's voltage changes from "H" to "L"
by changing the VINI pin's voltage instantaneously from the initial status to VSHORT max.0.05 V.
4.
0 V battery charge starting voltage (0 V battery charge function "available"), 0 V battery charge
inhibition battery voltage (0 V battery charge function "unavailable")
(Test circuit 2)
Confirm both COP pin and DOP pin are in "H" (its voltage level is VDS 0.9 V or more) after setting VVMP = VSEL =
VCTLC = VCTLD = VDD, VVINI = VSS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2 = V3 = V4 = 3.5 V.
(This status is referred to as initial status.)
According to user's selection of the function to charge 0 V battery, either function of voltage for start charging 0 V
battery or battery voltage for inhibit charging 0 V battery is applied to each product.
4. 1 0 V battery charge starting voltage (V0CHA) (0 V battery charge function "available")
0 V battery charge starting voltage (V0CHA) is a voltage at V1; when a voltage at the COP pin is set to "H" after
increasing a voltage at V1 gradually, after setting V1 = V2 = V3 = V4 = 0 V from the initial status.
4. 2 0 V battery charge inhibition battery voltage (V0INH) (0 V battery charge function "unavailable")
0 V battery charge inhibition battery voltage (V0INH) is a voltage at V1; when a voltage at the COP pin is set to "L"
after decreasing a voltage at V1 gradually from the initial status.
5.
Resistance between VMP pin and VDD pin, resistance between VMP pin and VSS pin, VC1 pin
current, VC2 pin current, VC3 pin current, VC4 pin current, CTLC pin current "H", CTLC pin
current "L", CTLD pin current "H", CTLD pin current "L", SEL pin current "H", SEL pin current
"L", COP pin source current, COP pin leakage current, DOP pin source current, DOP pin sink
current
(Test circuit 4)
Set VCTLC = VCTLD = VVMP = VSEL = VDD, VVINI = VSS, V1 = V2 = V3 = V4 = 3.5 V, set other pins open. (This status is
referred to as initial status.)
5. 1 Resistance between VMP pin and VDD pin (RVMD)
The value of resistance between VMP pin and VDD pin (RVMD) can be defined by RVMD = VDS / IVMD by using the
VMP pin's current (IVMD) when VVINI = 1.5 V and VVMP = VSS after the initial status.
5. 2 Resistance between VMP pin and VSS pin (RVMS)
The value of resistance between VMP pin and VSS pin (RVMS) can be defined by RVMS = VDS / IVMS by using the
VMP pin's current (IVMS) when V1 = V2 = V3 = V4 = 1.8 V after the initial status.
5. 3 VC1 pin current (IVC1), VC2 pin current (IVC2), VC3 pin current (IVC3), VC4 pin current (IVC4)
In the initial status, each current flows in the VC1 pin, VC2 pin, VC3 pin, VC4 pin is the VC1 pin current (IVC1), the
VC2 pin current (IVC2), the VC3 pin current (IVC3), the VC4 pin current (IVC4), respectively.
5. 4 CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL)
In the initial status, a current which flows in the CTLC pin is the CTLC pin current "H" (ICTLCH). After that,
decreasing a voltage at the CTLC pin gradually, the maximum current which flows in the CTLC pin is; the CTLC
pin current "L" (ICTLCL).
11
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
5. 5 CTLD pin current "H" (ICTLDH), CTLD pin current "L" (ICTLDL)
In the initial status, a current which flows in the CTLD pin is the CTLD pin current "H" (ICTLDH). After that,
decreasing a voltage at the CTLD pin gradually, the maximum current which flows in the CTLD pin is; the CTLD
pin current "L" (ICTLDL).
5. 6 SEL pin current "H" (ISELH), SEL pin current "L" (ISELL)
In the initial status, a current which flows in the SEL pin is the SEL pin current "H" (ISELH). After that, a current
which flows in the SEL pin when setting VSEL = VSS is; the SEL pin current "L" (ISELL).
5. 7 COP pin source current (ICOH), COP pin leakage current (ICOL)
Start from the initial status, set VCOP = VDD 0.5 V, a current which flows in the COP pin is the COP pin source
current (ICOH). After that, a current which flows in the COP pin when setting V1 = V2 = V3 = V4 = 5.5 V, VCOP =
VSS is; the COP pin leakage current (ICOL).
5. 8 DOP pin source current (IDOH), DOP pin sink current (IDOL)
Start from the initial status, set VDOP = VDD 0.5 V, a current which flows in the DOP pin is the DOP pin source
current (IDOH). After that, a current which flows in the DOP pin when setting V1 = V2 = V3 = V4 = 1.8 V, VDOP =
VSS0.5 V is; the DOP pin sink current (IDOL).
12
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
S-8204B
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
VC2 12
6 CCT
7 CIT
VC3 11
VC4 10
8 SEL
VSS
V1
V2
V3
9
A
V4
C1 =
0.1 F
Figure 4 Test Circuit 1
S-8204B
V
V
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
VC2 12
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS
V1
V2
V3
V4
9
C1 =
0.1 F
A
Figure 5 Test Circuit 2
S-8204B
A
V
V
A
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
VC2 12
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS
A
V1
V2
V3
V4
9
C1 =
0.1 F
Figure 6 Test Circuit 3
13
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
S-8204B
A
1 COP
CTLC 16
A
A
2 VMP
CTLD 15
A
A
3 DOP
VDD 14
4 VINI
VC1 13
A
5 CDT
VC2 12
A
6 CCT
VC3 11
A
7 CIT
VC4 10
A
8 SEL
VSS
A
V1
V2
V3
V4
9
C1 =
0.1 F
Figure 7 Test Circuit 4
14
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Operation
Remark Refer to " Connection Examples of Battery Protection IC".
1. Normal status
In the S-8204B Series, both of the COP pin and the DOP pin get the VDD level; when the voltage of each of the
batteries is in the range of overdischarge detection voltage (VDLn) to overcharge detection voltage (VCUn), and due to
the discharge current, the VINI pin's voltage is discharge overcurrent detection voltage (VDIOV1) or less. This is the
normal status. At this time, the charge FET and discharge FET are on.
2. Overcharge status
In the S-8204B Series, the voltage of one of the batteries increases to the level of more than VCUn, the COP pin is set
in high impedance. This is the overcharge status. The COP pin is pulled down to EB by an external resistor so that
the charge FET is turned off and it stops charging.
This overcharge status is released if either condition mentioned below is satisfied;
(1) In case that the VMP pin voltage is 39 / 40 VDS or more; the voltage of each of the batteries is in the level of
overcharge release voltage (VCLn) or less.
(2) In case that the VMP pin voltage is 39 / 40 VDS or less; the voltage of each of the batteries is in the level of
VCUn or less.
3. Overdischarge status
In the S-8204B Series, when the voltage of one of the batteries decreases to the level of less than VDLn, the DOP pin
voltage gets the VSS level. This is the overdischarge status. The discharge FET is turned off and it stops discharging.
This overcharge status is released if either condition mentioned below is satisfied;
(1) To release; the VMP pin voltage is in the level of more than VDD, the voltage of each of the batteries is in the
VDLn level or more.
(2) To release; the VMP pin voltage is VDS / 2 or more and the VMP pin voltage is in the level of less than VDD,
the voltage of each of the batteries is in the level of overdischarge release voltage (VDUn) or more.
3. 1 Power-down function
In the S-8204B Series, power-down function "available" / "unavailable" is selectable.
3. 1. 1 With power-down function
When the S-8204B Series reaches the overdischarge status, the VMP pin is pulled down to the VSS level by
a resistor between the VMP pin and the VSS pin (RVMS). If the VMP pin voltage decreases to the level of
VDS / 2 or less, the power-down function starts to operate and almost every circuit in the S-8204B Series
stops working.
The power-down function is released if the following condition is satisfied.
(1) The VMP pin voltage gets VDS / 2 or more.
3. 1. 2 Without power-down function
The VMP pin is not pulled down even when the S-8204B Series reaches the overdischarge status. The
overdischarge status is maintained even If the VMP pin voltage decreases to the level of VDS / 2 or less, and
the current consumption decreases to the level of current consumption during overdischarge (IOPED) or less.
15
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
4. Discharge overcurrent status
In the S-8204B Series, in batteries in the normal status, the discharging current increases more than a certain value.
As a result, if the status in which the VINI pin voltage increases to the level of VDIOV1 or more, the DOP pin gets the
VSS level. This is the discharge overcurrent status. At this time, the discharge control FET is turned off and it stops
discharging.
The S-8204B Series has three levels for discharge overcurrent detection (VDIOV1, VDIOV2, VSHORT). In the status of
discharge overcurrent, the COP pin is set in high impedance. The VMP pin is pulled up to the VDD level by a resistor
between the VMP pin and the VDD pin (RVMD).
The S-8204B Series' operations against discharge overcurrent detection voltage 2 (VDIOV2) and load short-circuit
detection voltage (VSHORT) are as well in VDIOV1.
The discharge overcurrent status is released if the following condition is satisfied.
(1) The VMP pin voltage gets VDS 1.2 V (typ.) or more.
5. 0 V battery charge function
In the S-8204B Series, regarding how to charge a discharged battery (0 V battery), users are able to select either
function mentioned below.
(1) Allow to charge a 0 V battery (enable to charge a 0 V battery)
A 0 V battery is charged when the voltage between the VDD pin and the VSS pin (VDS) is 0 V battery charge
starting voltage (V0CHA) or more.
(2) Inhibit charging a 0 V battery (unable to charge a 0 V battery)
A 0 V battery is not charged when the battery voltage is 0 V battery charge inhibition battery voltage (V0INH) or
less.
Caution
16
When the VDD pin voltage is less than the minimum value of operation voltage between the VDD
pin and the VSS pin (VDSOP), the operation of the S-8204B Series is not assured.
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
6. Delay time setting
In the S-8204B Series, users are able to set delay time for the period; from detecting the voltage of one of the
batteries or detecting changes in the voltage at the VINI pin, to the output to the COP pin and the DOP pin. Each
delay time is determined by a resistor in the S-8204B Series and an external capacitor.
In the overchage detection, when the voltage of one of the batteries gets VCUn or more, the S-8204B Series starts
charging to the CCT pin's capacitor (CCCT) via the CCT pin's internal resistor (RINC). After a certain period, the COP
pin is set in high impedance if the voltage at the CCT pin reaches the CCT pin detection voltage (VCCT). This period is
overcharge detection delay time (tCU).
tCU is calculated using the following equation (VDS = V1V2V3V4).
tCU [s] = ln (1VCCT / VDS ) CCCT [F] RINC [M]
= ln (10.7 (typ.)) CCCT [F] 8.31 [M] (typ.)
= 10.0 [M] (typ.) CCCT [F]
Overdischarge detection delay time (tDL), discharge overcurrent detection delay time 1 (tDIOV1), discharge overcurrent
detection delay time 2 (tDIOV2) are calculated using the following equations as well.
tDL [ms] = ln (1VCDT / VDS) CCDT [F] RIND [k]
tDIOV1 [ms] = ln (1VCIT / VDS) CCIT [F] RINI1 [k]
tDIOV2 [ms] = ln (1VCIT / VDS) CCIT [F] RINI2 [k]
In case CCCT = CCDT = CCIT = 0.1 [F], each delay time tCU, tDL, tDIOV1, tDIOV2 is calculated as follows.
tCU [s] = 10.0 [M] (typ.) 0.1 [F] = 1.0 [s] (typ.)
tDL [ms] = 1000 [k] (typ.) 0.1 [F] = 100 [ms] (typ.)
tDIOV1 [ms] = 200 [k] (typ.) 0.1 [F] = 20 [ms] (typ.)
tDIOV2 [ms] = 20 [k] (typ.) 0.1 [F] = 2.0 [ms] (typ.)
Load short-circuit detection delay time (tSHORT) is fixed internally.
17
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
7. CTLC pin and CTLD pin
The S-8204B Series has two pins to control.
The CTLC pin controls the output voltage from the COP pin, the CTLD pin controls the output voltage from the DOP
pin. Thus it is possible for users to control the output voltages from the COP pin and DOP pin independently. These
controls precede the battery protection circuit.
Table 6 Conditions Set by CTLC Pin
CTLC Pin
COP Pin
"H"*1
Normal status*4
Open*2
"High-Z"
"L"*3
"High-Z"
*1. "H"; CTLC VCTLCH
*2. Pulled down by ICTLCH
*3. "L"; CTLC VCTLCL
*4. The status is controlled by the voltage detection circuit.
Table 7 Conditions Set by CTLD Pin
CTLD Pin
DOP Pin
"H"*1
Normal status*4
Open*2
VSS level
"L"*3
VSS level
*1. "H"; CTLD VCTLDH
*2. Pulled down by ICTLDH
*3. "L"; CTLD VCTLDL
*4. The status is controlled by the voltage detection circuit.
Caution
18
Note that when the power supply fluctuates, unexpected behavior might occur if an electrical
potential is generated between the potentials of "H" level input to the CTLC pin / the CTLD pin and
IC's VDD by external filters RVDD1 and CVDD1.
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
8. SEL pin
The S-8204B Series has a pin to switch-control the protection for 3-cell or 4-cell battery.
The overdischarge detection for V4-cell is inhibited by setting the SEL pin "L", so that short-circuiting the V4 cell does
not allow the overdischarge detection. This setting makes it possible to use the S-8204B Series for 3-cell protection.
The control by this SEL pin precedes the battery protection circuit. Be sure to use the SEL pin in "H" or "L".
Table 8 Conditions Set by SEL Pin
SEL Pin
"H"*1
Open
"L"*2
*1. "H"; SEL VSELH
*2. "L"; SEL VSELL
Condition
4-cell protection
Indefinite
3-cell protection
In cascade connection, it is possible to use the S-8204B Series for protecting 6-cell, 7-cell or 8-cell battery by
combining the electrical level of the SEL pin.
Table 9 Conditions Set by SEL Pin in Cascade Connection
SEL pin in S-8204B (1)
"L"*1
"L"*1
"H"*2
*1. "L"; SEL VSELL
*2. "H"; SEL VSELH
SEL pin in S-8204B (2)
"L"*1
"H"*2
"H"*2
Condition
6-series cell protection
7-series cell protection
8-series cell protection
19
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Timing Chart (Circuit in Figure 11)
1. Overcharge detection and overdischarge detection (with power-down function)
VCUn
VCLn
Battery voltage
VDUn
VDLn
(n = 1 to 4)
VDD
DOP pin voltage
VSS
VDD
COP pin voltage
High-Z
High-Z
VEB-
VDD
39 / 40 VDD
VMP pin voltage 1 / 2 VDD
VSS
Charger connection
Load connection
Status
*1.
*1
Overcharge detection
delay time (tCU)
(1)
(2)
Overdischarge detection
delay time (tDL)
(1)
(3)
(4)
(3)
(1)
(1): Normal status
(2): Overcharge status
(3): Overdischarge status
(4): Power-down status
Remark The charger is assumed to charge with a constant current. VEB- indicates the open voltage of the charger.
Figure 8
20
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
2. Overcharge detection and overdischarge detection (without power-down function)
VCUn
VCLn
Battery voltage
VDUn
VDLn
(n = 1 to 4)
VDD
DOP pin voltage
VSS
VDD
COP pin voltage
High-Z
VEB-
VDD
39 / 40VDD
VMP pin voltage 1 / 2VDD
VSS
Charger connection
Load connection
Status
*1.
*1
Overcharge detection
delay time (tCU)
(1)
Overdischarge detection
delay time (tDL)
(2)
(1)
(3)
(1)
(1): Normal status
(2): Overcharge status
(3): Overdischarge status
Remark The charger is assumed to charge with a constant current. VEB- indicates the open voltage of the charger.
Figure 9
21
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
3. Discharge overcurrent detection
VHC
VCUn
VCLn
Battery voltage
VDUn
VDLn
VHD
(n = 1 to 4)
VDD
DOP pin voltage
VSS
VDD
High-Z
COP pin voltage
High-Z
High-Z
VEBVDD
VMP pin voltage
VSS
VDD
VSHORT
V
VINI pin voltage DIOV2
VDIOV1
VSS
Charger connection
Load connection
Status
*1.
*1
Discharge overcurrent
detecion delay time 1 (tDIOV1)
(1)
Discharge overcurrent
detecion delay time 2 (tDIOV2)
(2)
(1)
(2)
Load short-circuit detecion
delay time (tSHORT)
(1)
(2)
(1)
(1): Normal status
(2): Discharge overcurrent status
Remark The charger is assumed to charge with a constant current. VEB- indicates the open voltage of the charger.
Figure 10
22
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Connection Examples of Battery Protection IC
1. 4-series cell (with overcurrent protection function)
EB
M1
RVMP
RATL
M2
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
CCDT
CCCT
CCIT
S-8204B
RCTLC
RCTLD
RVDD
RVC1
CVC1
VC2 12
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS 9
CVC2
CVC3
RVC2
RVC3
RVC4
CVC4
CVDD
RSEL
ZD1
REB
RCOP
RDOP
RVINI
RSENSE
EB
Nch FET1
Nch FET2
(Charge FET) (Discharge FET)
Figure 11
23
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Table 10 Constants for External Components (Circuit in Figure 11)
Symbol
Min.
Typ.
Max.
Unit
RVC1*1
0.51
1
1
k
RVC2*1
0.51
1
1
k
RVC3*1
0.51
1
1
k
RVC4*1
0.51
1
1
k
RDOP
2
5.1
10
k
RCOP
0.1
1
1
M
RVMP
1
5.1
10
k
RCTLC
1
1
10
k
RCTLD
1
1
10
k
RVINI
1
1
10
k
RSEL
1
1
100
k
*1
RVDD
22
47
100
*1
CVC1
0
47
100
nF
*1
CVC2
0
47
100
nF
CVC3*1
0
47
100
nF
*1
CVC4
0
47
100
nF
CCCT
0.01
0.1
F
CCDT
0.01
0.1
F
CVDD*1
0
1
2.2
F
CCIT
0.1
F
RSENSE
M1
M2
ZD1
REB
1
M
RATL
20
M
Nch FET1
Nch FET2
*1. Set up a filter constant to be RVDD CVDD = 47 F or more, and to be RVC1 CVC1 = RVC2 CVC2 =
RVC3 CVC3 = RVC4 CVC4 = RVDD CVDD.
Caution 1.
2.
3.
24
The above constants may be changed without notice.
It is recommended that filter constants between the VDD pin and the VSS pin should be set to
approximately 47 F .
e.g., CVDD RVDD = 1.0 F 47 = 47 F
Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with
the actual application is needed to determine the proper constants. Contact our sales office in case
the constants should be set to other than 47 F .
It has not been confirmed whether the operation is normal in circuits other than the above example
of connection. In addition, the example of connection shown above and the constants do not
guarantee proper operation. Perform thorough evaluation using an actual application to set the
constant.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
2. 7-series cell (cascade connection without overcurrent protection function)
EB+
RVMP1
RVINI1
CCDT1
CCCT1
RIFC
RCIT1
RIFD
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
S-8204B
VC2 12
(1)
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS 9
RCTLC
RCTLD
RVDD1
RVC1
CVC1
CVC2
CVC3
RVC2
RVC3
RVC4
CVDD1
RSEL1
RVMP2
RVINI2
CCDT2
CCCT2
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
S-8204B
VC2 12
(2)
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS 9
RVDD2
RVC5
CVC5
CVC6
CVC7
RVC7
RVC8
CVC8
DCOP
RDOP
RVC6
CVDD2
RCIT2
RSEL2
RCOP
EB
Charge FET
Discharge FET
Figure 12
Caution 1.
2.
It is recommended that filter constants between the VDD pin and the VSS pin should be set to
approximately 47 F .
e.g., CVDD RVDD = 1.0 F 47 = 47 F
Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with
the actual application is needed to determine the proper constants. Contact our sales office in case
the constants should be set to other than 47 F .
It has not been confirmed whether the operation is normal in circuits other than the above example
of connection. In addition, the example of connection shown above and the constants do not
guarantee proper operation. Perform thorough evaluation using an actual application to set the
constant.
Remark Refer to the application note for constants of each external component.
25
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
3. 8-series cell (cascade connection with overcurrent protection function)
EB+
M4
R1
RIFC
RINV2
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
RCTLD
RVDD1
RVC1
VC1 13
S-8204B
5 CDT (1)
VC2 12
RVINI1
CCCT1
CCDT1
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS 9
CVC1
CVC2
CVC3
RVC2
RVC3
RVC4
CVC4
CVDD1
RCIT1
M3
RCTLC
4 VINI
RIFD
R2
1 COP
RSEL1
M1
RINV1
RATL
M2
CCDT2
CCCT2
CCIT2
1 COP
CTLC 16
2 VMP
CTLD 15
3 DOP
VDD 14
4 VINI
VC1 13
5 CDT
S-8204B
(2)
VC2 12
6 CCT
VC3 11
7 CIT
VC4 10
8 SEL
VSS 9
RVDD2
RVC5
CVC5
CVC6
CVC7
RVC6
RVC7
RVC8
CVC8
CVDD2
ZD1
RSEL2
DCOP
REB
EB
RCOP
RDOP
RVINI2
RSENSE
Charge FET Discharge FET
Figure 13
Caution 1.
2.
It is recommended that filter constants between the VDD pin and the VSS pin should be set to
approximately 47 F .
e.g., CVDD RVDD = 1.0 F 47 = 47 F
Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with
the actual application is needed to determine the proper constants. Contact our sales office in case
the constants should be set to other than 47 F .
It has not been confirmed whether the operation is normal in circuits other than the above example
of connection. In addition, the example of connection shown above and the constants do not
guarantee proper operation. Perform thorough evaluation using an actual application to set the
constant.
Remark Refer to the application note for constants of each external component.
26
Rev.3.9_01
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Batteries can be connected in any order; however, there may be cases when discharging cannot be performed when
a battery is connected. In such a case, short the VMP pin and the VDD pin to return the IC to the normal mode.
If both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is
set in overcharge status and overdischarge status. Therefore either charging or discharging is impossible.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
27
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
Characteristics (Typical Data)
1. Current consumption
1. 2 IOPE vs. Ta
40
35
30
25
20
15
10
5
0
IOPE [μA]
IOPE [μA]
1. 1 IOPE vs. VDS
0
5
10
VDS [V]
15
20 22
40 25
0
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
1. 4 IPDN vs. Ta
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
IPDN [μA]
IPDN [μA]
1. 3 IPDN vs. VDS
0
40
35
30
25
20
15
10
5
0
5
10
VDS [V]
15
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
20 22
40 25
2. Overcharge detection / release voltage, overdischarge detection / release voltage, overcurrent
detection voltage
4.375
4.370
4.365
4.360
4.355
4.350
4.345
4.340
4.335
4.330
4.325
2. 2 VCL vs. Ta
4.20
4.18
VCL [V]
VCU [V]
2. 1 VCU vs. Ta
40 25
4.10
0
25
Ta [C]
50
75 85
40 25
40 25
0
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
2. 4 VDL vs. Ta
VDL [V]
VDU [V]
28
4.14
4.12
2. 3 VDU vs. Ta
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
4.16
0
25
Ta [C]
50
75 85
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
1.92
40 25
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
2. 6 VDIOV1 vs. Ta
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
VDIOV1 [V]
VDIOV1 [V]
2. 5 VDIOV1 vs. VDS
10
11
12
13
VDS [V]
14
15
16
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
11
12
13
VDS [V]
14
15
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
16
2. 9 VSHORT vs. VDS
0
25
Ta [C]
50
75 85
40 25
0
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
2. 10 VSHORT vs. Ta
1.3
1.3
1.2
1.2
1.1
1.1
VSHORT [V]
VSHORT [V]
40 25
2. 8 VDIOV2 vs. Ta
VDIOV2 [V]
VDIOV2 [V]
2. 7 VDIOV2 vs. VDS
10
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
1.0
0.9
0.8
1.0
0.9
0.8
0.7
0.7
10
11
12
13
VDS [V]
14
15
16
40 25
29
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
3. CCT pin internal resistance / detection voltage, CDT pin internal resistance / detection voltage, CIT
pin internal resistance / detection voltage and load short-circuit detection delay time
3. 2 VCCT vs. Ta (VDS = 15.2 V)
12.0
10.9
11.0
10.8
10.0
VCCT [V]
RINC [M]
3. 1 RINC vs. Ta
9.0
8.0
40 25
10.4
0
25
Ta [C]
50
75 85
3. 3 RIND vs. Ta
VCDT [V]
RIND [k]
900
800
40 25
25
Ta [C]
50
75 85
40 25
0
25
Ta [C]
50
75 85
3. 6 VCIT vs. Ta (VDS = 14.0 V)
10.0
240
220
9.9
200
VCIT [V]
RINI1 [k]
75 85
8.4
8.2
0
3. 5 RINI1 vs. Ta
180
160
9.8
9.7
140
40 25
9.6
0
25
Ta [C]
50
75 85
3. 7 RINI2 vs. Ta
40 25
0
25
Ta [C]
50
75 85
0
25
Ta [C]
50
75 85
3. 8 tSHORT vs. Ta
24.0
600
22.0
500
20.0
400
tSHORT [μs]
RINI2 [k]
50
8.3
700
18.0
16.0
14.0
30
25
Ta [C]
8.5
1000
12.0
0
8.6
1100
120
40 25
3. 4 VCDT vs. Ta (VDS = 12.0 V)
1200
600
10.6
10.5
7.0
6.0
10.7
300
200
100
40 25
0
0
25
Ta [C]
50
75 85
40 25
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204B Series
Rev.3.9_01
4. COP pin / DOP pin
4. 1 ICOH vs. VCOP
4. 2 ICOL vs. VCOP
20
ICOL [μA]
ICOH [mA]
25
15
10
5
0
0
3.5
7
VCOP [V]
10.5
14
4. 3 IDOH vs. VDOP
IDOL [mA]
IDOH [mA]
20
15
10
5
0
0
5
20 22
10
15
VCOP [V]
4. 4 IDOL vs. VDOP
25
0
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
3.5
7
VDOP [V]
10.5
14
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1.8
3.6
VDOP [V]
5.4
7.2
31
5.1±0.2
0.65
16
9
1
8
0.17±0.05
0.22±0.08
No. FT016-A-P-SD-1.2
TITLE
TSSOP16-A-PKG Dimensions
FT016-A-P-SD-1.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
4.0±0.1
ø1.5 -0
0.3±0.05
2.0±0.1
8.0±0.1
1.5±0.1
ø1.6±0.1
(7.2)
4.2±0.2
+0.4
6.5 -0.2
1
16
8
9
Feed direction
No. FT016-A-C-SD-1.1
TITLE
TSSOP16-A-Carrier Tape
No.
FT016-A-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
21.4±1.0
17.4±1.0
+2.0
17.4 -1.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT016-A-R-SD-2.0
TITLE
TSSOP16-A- Reel
FT016-A-R-SD-2.0
No.
ANGLE
UNIT
QTY.
mm
ABLIC Inc.
2,000
21.4±1.0
17.4±1.0
+2.0
17.4 -1.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT016-A-R-S1-1.0
TITLE
TSSOP16-A- Reel
No.
FT016-A-R-S1-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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