S-8213 Series
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK
(SECONDARY PROTECTION)
N
www.ablicinc.com
Rev.1.4_01
DE
SI
G
© ABLIC Inc., 2012-2017
The S-8213 Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a high-accuracy
voltage detection circuit and a delay circuit. Short-circuits between VC3 to VSS accommodate serial connection of two cells or
three cells.
Features
High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n = 1 to 3)
4.100 V to 4.500 V (in 50 mV steps)
Accuracy: 25 mV (Ta = 25C)
Accuracy: 30 mV (Ta = 0C to 60C)
Overcharge hysteresis voltage n (n = 1 to 3)
0 V 25 mV, 0.05 V 25 mV, 0.40 V 80 mV
Delay times for overcharge detection can be set by an internal circuit only (external capacitors are unnecessary)
Output form is selectable:
CMOS output, Nch open-drain output
Output logic is selectable:
Active "H", Active "L"
High-withstand voltage:
Absolute maximum rating 26 V
Wide operation voltage range:
3.6 V to 24 V
Wide operation temperature range:
Ta = 40C to 85C
Low current consumption
At VCUn 1.0 V for each cell:
2.0 A max. (Ta = 25C)
At 2.0 V for each cell:
0.3 A max. (Ta = 25C)
Lead-free (Sn 100%), halogen-free
R
FO
D
DE
NE
W
MM
EN
Application
Lithium-ion rechargeable battery pack (for secondary protection)
Packages
RE
CO
SOT-23-6
SNT-6A
NO
T
1
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Block Diagram
N
1. CMOS output product
DE
SI
G
VDD
Overcharge
detection
comparator 1
VC1
W
NE
Reference voltage 1
Overcharge
detection
comparator 2
Oscillator
Control
logic
MM
EN
Reference voltage 3
DE
Overcharge
detection
comparator 3
D
Reference voltage 2
VC3
VSS
NO
T
RE
CO
Remark The diodes in the figure are parasitic diodes.
2
Overcharge
detection / release
delay circuit
FO
R
VC2
Figure 1
CO
Rev.1.4_01
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
2. Nch open-drain output product
DE
SI
G
N
VDD
Overcharge
detection
comparator 1
VC1
W
Reference voltage 1
Oscillator
Control
logic
MM
EN
VSS
DE
Reference voltage 3
D
Overcharge
detection
comparator 3
CO
FO
Reference voltage 2
Overcharge
detection / release
delay circuit
R
VC3
NE
Overcharge
detection
comparator 2
VC2
Remark The diodes in the figure are parasitic diodes.
NO
T
RE
CO
Figure 2
3
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Product Name Structure
xxx
-
xxxx
U
DE
SI
G
S-8213
N
1. Product name
Environmental code
U:
Lead-free (Sn 100%), halogen-free
W
Package abbreviation and IC packing specifications*1
M6T1: SOT-23-6, Tape
I6T1: SNT-6A, Tape
NE
Serial code*2
Sequentially set from AAA to AAZ
R
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Packages
SOT-23-6
SNT-6A
Dimension
Tape
Reel
Land
MP006-A-P-SD
PG006-A-P-SD
MP006-A-C-SD
PG006-A-C-SD
MP006-A-R-SD
PG006-A-R-SD
PG006-A-L-SD
DE
3. Product name list
D
Package Name
FO
Table 1 Package Drawing Codes
MM
EN
3. 1 SNT-6A
Table 2
Overcharge
Overcharge
Overcharge
Hysteresis
Detection
Detection
Output Form
Output Logic
Voltage [VHC]
Delay Time [tCU]
Voltage [VCU]
S-8213AAB-I6T1U
4.300 V
0.40 V
2.0 s
CMOS output
Active "H"
S-8213AAC-I6T1U
4.350 V
0.40 V
2.0 s
CMOS output
Active "H"
S-8213AAD-I6T1U
4.400 V
0.40 V
2.0 s
CMOS output
Active "H"
S-8213AAE-I6T1U
4.450 V
0.40 V
2.0 s
CMOS output
Active "H"
S-8213AAF-I6T1U
4.500 V
0.40 V
2.0 s
CMOS output
Active "H"
S-8213AAG-I6T1U
4.300 V
0.40 V
4.0 s
CMOS output
Active "H"
S-8213AAH-I6T1U
4.350 V
0.40 V
4.0 s
CMOS output
Active "H"
S-8213AAI-I6T1U
4.400 V
0.40 V
4.0 s
CMOS output
Active "H"
S-8213AAJ-I6T1U
4.450 V
0.40 V
4.0 s
CMOS output
Active "H"
S-8213AAK-I6T1U
4.500 V
0.40 V
4.0 s
CMOS output
Active "H"
S-8213AAL-I6T1U
4.300 V
0.40 V
8.0 s
CMOS output
Active "H"
S-8213AAM-I6T1U
4.350 V
0.40 V
8.0 s
CMOS output
Active "H"
S-8213AAN-I6T1U
4.400 V
0.40 V
8.0 s
CMOS output
Active "H"
S-8213AAO-I6T1U
4.450 V
0.40 V
8.0 s
CMOS output
Active "H"
S-8213AAP-I6T1U
4.500 V
0.40 V
8.0 s
CMOS output
Active "H"
S-8213AAQ-I6T1U
4.150 V
0.05 V
2.0 s
CMOS output
Active "L"
S-8213AAR-I6T1U
4.250 V
0.05 V
2.0 s
CMOS output
Active "L"
S-8213AAS-I6T1U
4.150 V
0.05 V
2.0 s
Nch open-drain output Active "H"
S-8213AAT-I6T1U
4.250 V
0.05 V
2.0 s
Nch open-drain output Active "H"
Remark Please contact our sales department for the products with detection voltage value other than those specified above.
NO
T
RE
CO
Product Name
4
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Pin Configurations
Table 3
Top view
6 5 4
Symbol
1
VSS
2
VC3
3
VC2
4
5
6
VC1
VDD
CO
NE
Figure 3
W
1 2 3
Description
Input pin for negative power supply,
connection pin for negative voltage of battery 3
Connection pin for negative voltage of battery 2,
connection pin for positive voltage of battery 3
Connection pin for negative voltage of battery 1,
connection pin for positive voltage of battery 2
Connection pin for positive voltage of battery 1
Input pin for positive power supply
Connection pin of charge control FET gate
DE
SI
G
Pin No.
N
1. SOT-23-6
Top view
Table 4
Description
Connection pin of charge control FET gate
Input pin for positive power supply
Connection pin for positive voltage of battery 1
Connection pin for negative voltage of battery 1,
connection pin for positive voltage of battery 2
Connection pin for negative voltage of battery 2,
connection pin for positive voltage of battery 3
Input pin for negative power supply,
connection pin for negative voltage of battery 3
Figure 4
4
5
VC2
VC3
VSS
NO
T
RE
CO
MM
EN
6
D
FO
Pin No. Symbol
1
CO
2
VDD
3
VC1
6
5
4
DE
1
2
3
R
2. SNT-6A
5
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Absolute Maximum Ratings
Table 5
Storage temperature
Tstg
N
Input voltage between VDD and VSS
Input pin voltage
CMOS output product
CO output pin voltage
Nch open-drain output product
SOT-23-6
Power dissipation
SNT-6A
Operation ambient temperature
(Ta = 25C unless otherwise specified)
Symbol
Applied Pin
Absolute Maximum Rating Unit
VDS
VDD
VSS 0.3 to VSS 26
V
VIN
VC1, VC2, VC3
VSS 0.3 to VDD 0.3
V
V
VSS 0.3 to VDD 0.3
VCO
CO
VSS 0.3 to VSS 26
V
*1
mW
650
PD
*1
400
mW
Topr
40 to 85
C
R
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
FO
Caution
40 to 125
NE
*1. When mounted on board
[Mounted board]
(1) Board size:
114.3 mm 76.2 mm t1.6 mm
(2) Name:
JEDEC STANDARD51-7
W
DE
SI
G
Item
D
SOT-23-6
600
DE
SNT-6A
400
MM
EN
Power Dissipation (PD) [mW]
800
200
0
0
150
100
50
Ambient Temperature (Ta) [C]
NO
T
RE
CO
Figure 5 Power Dissipation of Package (When Mounted on Board)
6
C
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Electrical Characteristics
Table 6
N
Symbol
Condition
DE
SI
G
Item
(Ta = 25C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
DETECTION VOLTAGE
VCU
0.025
VCU
0.030
VHC
0.080
VHC
0.025
Overcharge detection
voltage n (n = 1, 2, 3)
VCUn
Overcharge hysteresis
voltage n (n = 1, 2, 3)
VHCn
Ta = 0°C to 60°C*1
VHC = 0.40 V
VHC
VHC
VCU
0.025
VCU
0.030
VHC
0.080
VHC
0.025
V
1
V
1
V
1
V
1
3.6
24
V
V1 = V2 = V3 = VCU 1.0 V
2.0
A
3
IPDN
V1 = V2 = V3 = 2.0 V
0.3
A
3
0.3
0
0.3
0.3
A
A
4
4
0.4
mA
5
20
A
5
0.1
A
5
tCU 0.8
tCU
tCU 1.2
20
s
ms
1
2
R
IOPE
D
NE
VDSOP
FO
IVC1
V1 = V2 = V3 = VCU 1.0 V
IVC2, IVC3 V1 = V2 = V3 = VCU 1.0 V
ICOH
ICOLL
tCU
tTST
DE
ICOL
MM
EN
INPUT VOLTAGE
Operation voltage between VDD
and VSS
INPUT CURRENT
Current consumption during
operation
Current consumption during
overdischarge
VC1 pin current
VC2 pin, VC3 pin current
OUTPUT CURRENT
CO pin sink current
CO pin source current
(CMOS output product)
CO pin leakage current
(Nch open-drain output product)
DELAY TIME
Overcharge detection delay time
Transition time to test mode
VCU
W
VHC = 0 V, 0.05 V
VCU
NO
T
RE
CO
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
7
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Test Circuits
N
1. Overcharge detection voltage, overcharge hysteresis voltage
(Test circuit 1)
DE
SI
G
Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively.
1. 1 Overcharge detection voltage n (VCUn)
Set V1 = V2 = V3 = VCU 0.05 V. The Overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin’s
output changes after the voltage of V1 has been gradually increased.
Overcharge detection voltage VCUn (n = 2, 3) can be determined in the same way as when n = 1.
1. 2 Overcharge hysteresis voltage n (VHCn)
NE
W
Set V1 = VCU 0.05 V, V2 = V3 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference between V1
voltage and VCU1 when the CO pin’s output changes after the V1 voltage has been gradually decreased.
Overcharge hysteresis voltage VHCn (n = 2, 3) can be determined in the same way as when n = 1.
2. Output current
(Test circuit 5)
R
Set SW1 and SW2 to OFF.
FO
2. 1 Active "H"
2. 1. 1 CO pin source current (ICOH)
D
Set SW1 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that
time.
DE
2. 1. 2 CO pin sink current (ICOL)
Set SW2 to ON after setting V1 to V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time.
2. 1. 3 CO pin leakage current (ICOLL)
MM
EN
Set SW2 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V5 = 26 V. I2 is the CO pin leakage current (ICOLL) at
that time.
2. 2 Active "L"
2. 2. 1 CO pin source current (ICOH)
Set SW1 to ON after setting V1 to V3 = 3.5 V, V4 = 0.5 V. I1 is the CO pin source current (ICOH) at that time.
CO
2. 2. 2 CO pin sink current (ICOL)
RE
Set SW2 to ON after setting V1 = 5.0 V, V2 = V3 = 3.0 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that
time.
2. 2. 3 CO pin leakage current (ICOLL)
NO
T
Set SW2 to ON after setting V1 to V3 = 3.5 V, V5 = 26 V. I2 is the CO pin leakage current (ICOLL) at that time.
8
Rev.1.4_01
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
3. Overcharge detection delay time (tCU)
(Test circuit 1)
N
Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively.
DE
SI
G
Increase V1 up to 5.0 V after setting V1 = V2 = V3 = 3.5 V. The overcharge detection delay time (tCU) is the time period
until the CO pin output changes.
4. Transition time to test mode (tTST)
(Test circuit 2)
Set SW1 to OFF and ON in CMOS output product and Nch open-drain output product, respectively.
W
Increase V4 up to 4.0 V, and decrease V4 again to 0 V after setting V1 = V2 = V3 = 3.5 V, and V4 = 0 V.
When the period from when V4 was raised to when it has fallen is short, if an overcharge detection operation is
NE
performed subsequently, the delay time is tCU. However, when the period from when V4 is raised to when it has fallen is
gradually made longer, the delay time during the subsequent overcharge detection operation is shorter than tCU. The
NO
T
RE
CO
MM
EN
DE
D
FO
R
transition time to test mode (tTST) is the period from when V4 was raised to when it has fallen at that time.
9
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
100 k
SW1
S-8213 Series
VDD
CO
V4
V
VC1
VSS
V1
V3
VC2
CO
V
VSS
V3
V1
VC2
VC3
V2
VC3
NE
W
V2
DE
SI
G
VDD
N
100 k
S-8213 Series
VC1
Rev.1.4_01
Figure 7 Test Circuit 2
FO
R
Figure 6 Test Circuit 1
S-8213 Series
IOPE
IPDN
VDD
CO
VC1
D
A
VSS
V3
VC2
DE
V1
VC3
MM
EN
V2
CO
Figure 8 Test Circuit 3
A I1
SW1
RE
VDD
CO
VC1
VSS
NO
T
V1
VC2
SW2
V3
VC3
V
A I2
V2
Figure 10 Test Circuit 5
10
V5
A
V1
CO
VC1
VSS
IVC1
IVC2
IVC3
A
A
VC2
VC3
V2
Figure 9 Test Circuit 4
V4
S-8213 Series
S-8213 Series
VDD
V3
SW1
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Operation
N
Remark Refer to " Battery Protection IC Connection Examples".
DE
SI
G
1. Normal status
If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCUn) the overcharge hysteresis
voltage (VHCn)", CO pin output changes to "L" (Active "H") or "H" (Active "L"). This is called normal status.
2. Overcharge status
When the voltage of one of the batteries exceeds VCUn during charging under normal conditions and the status is
retained for the overcharge detection delay time (tCU) or longer, CO pin output changes. This is called overcharge
W
status. Connecting FET to the CO pin provides charge control and a second protection.
If the voltage of each of the batteries is lower than VCUn VHCn and the status is retained for 2.0 ms typ. or longer, the
NO
T
RE
CO
MM
EN
DE
D
FO
R
NE
S-8213 Series changes to normal status.
11
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
3. Test mode
The overcharge detection delay time (tCU) can be shortened by entering the test mode.
N
The test mode can be set by retaining the VDD pin voltage 4.0 V or more higher than the VC1 pin voltage for 20 ms or
longer. The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is
DE
SI
G
decreased to the same voltage as that of the VC1 pin voltage.
After that, the latch for retaining the test mode is reset and the S-8213 Series exits from test mode under the overcharge
status.
VDD pin voltage
VC1 pin voltage
4.0 V or
more
NE
W
Pin voltage
VHCn
VCUn
R
Battery voltage
DE
tTST = 20 ms max.
NO
T
RE
CO
MM
EN
CO pin
(Active "H")
CO pin
(Active "L")
12
D
Test mode
FO
(n = 1 to 3)
32 ms typ.
Figure 11
2.0 ms typ.
Rev.1.4_01
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Timing Charts
N
1. Overcharge detection operation
DE
SI
G
1. 1 CMOS output product
VHCn
VCUn
Battery voltage
CO pin
(Active "H")
NE
W
(n = 1 to 3)
FO
R
tCU or shorter
DE
D
CO pin
(Active "L")
2.0 ms typ.
Figure 12
NO
T
RE
CO
MM
EN
tCU
13
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
1. 2 Nch open-drain output product
N
VHCn
DE
SI
G
VCUn
Battery voltage
(n = 1 to 3)
CO pin
(Active "H")
tCU or shorter
CO pin
(Active "L")
R
NE
W
High-Z
FO
High-Z
D
tCU
NO
T
RE
CO
MM
EN
DE
Figure 13
14
High-Z
2.0 ms typ.
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Battery Protection IC Connection Examples
1. 3-serial cell (CMOS output product)
DE
SI
G
VDD
RVDD
CVDD
VC1
R1
C2
BAT2
S-8213
Series
NE
VC2
R2
VC3
R3
FET
R
C3
BAT3
CO
DP
MM
EN
DE
D
FO
VSS
EB
W
C1
BAT1
N
SCP
EB
Figure 14
Table 7 Constants for External Components
Min.
0.2
0.01
50
Typ.
1
0.1
100
Max.
2
1
500
Unit
k
F
1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1 to R3 and to C1 to C3 and CVDD.
4. Set RVDD, C1 to C3, and CVDD so that the condition (RVDD) (C1 to C3, CVDD) 5 106 is satisfied.
5. Set R1 to R3, C1 to C3, and CVDD so that the condition (R1 to R3) (C1 to C3, CVDD) 1 104 is
satisfied.
6. Since CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
NO
T
RE
Caution
Part
R1 to R3
C1 to C3, CVDD
RVDD
CO
No.
1
2
3
15
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
2. 2-serial cell (CMOS output product)
DE
SI
G
VDD
RVDD
CVDD
VC1
R1
C2
BAT2
S-8213
Series
NE
VC2
R2
FET
R
VC3
VSS
EB
W
C1
BAT1
N
SCP
CO
FO
DP
D
EB
DE
Figure 15
Table 8 Constants for External Components
RE
NO
T
16
Min.
0.2
0.01
50
Typ.
1
0.1
100
Max.
2
1
500
Unit
k
F
1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constant.
3. Set the same constants to R1, R2 and to C1, C2 and CVDD.
4. Set RVDD, C1, C2, and CVDD so that the condition (RVDD) (C1, C2, CVDD) 5 106 is satisfied.
5. Set R1, R2, C1, C2, and CVDD so that the condition (R1, R2) (C1, C2, CVDD) 1 104 is satisfied.
6. Since CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
CO
Caution
Part
R1, R2
C1, C2, CVDD
RVDD
MM
EN
No.
1
2
3
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
DE
SI
G
N
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL 81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
Precautions
Do not connect batteries charged with VCUn + VHCn or higher. If the connected batteries include a battery charged with
VCUn VHCn or more, the S-8213 series may become overcharge status after all pins are connected.
In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough
evaluation with the actual application circuit.
Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figure in " Battery
Protection IC Connection Examples".
The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
NO
T
RE
CO
MM
EN
DE
D
FO
R
NE
W
17
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Characteristics (Typical Data)
DE
SI
G
1. 2 VCU VHC vs. Ta
1. 1 VCU vs. Ta
VHC = 0.4 V
VCU = 4.3 V
4.00
VCU [V]
4.35
4.30
4.25
25
Ta [°C]
50
75 85
0
25
Ta [°C]
50
75 85
R
FO
VDD = 9.9 V
VDD = 6.0 V
D
IPDN [μA]
0.3
1.5
1.0
0.5
0
2. 3 IOPE vs. VDD
25
Ta [°C]
50
75 85
MM
EN
−40 −25
DE
IOPE [μA]
−40 −25
2. 2 IPDN vs. Ta
2.0
Ta = 25C
CO
60
40
RE
IOPE [μA]
3.85
NE
0
2. 1 IOPE vs. Ta
20
0
5
NO
T
0
18
3.90
3.80
−40 −25
2. Current consumption
0
3.95
W
VCU + VHC [V]
4.40
4.20
N
1. Detection voltage
10
15
20
VDD [V]
25
30
0.2
0.1
0
−40 −25
0
25
Ta [°C]
50
75 85
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
3. Delay time
N
3. 1 tCU vs. Ta
DE
SI
G
VDD = 12 V
3.0
tCU [s]
2.5
2.0
−40 −25
0
25
Ta [°C]
50
75 85
NE
1.0
W
1.5
4. Output current
4. 2 ICOH vs. VDD
R
4. 1 ICOL vs. VDD
D
1.5
ICOH [μA]
100
1.0
DE
ICOL [mA]
Ta = 25C
FO
Ta = 25C
2.0
0.5
0
5
10
4. 3 ICOLL vs. VDD
15
20
VDD [V]
25
30
MM
EN
0
75
50
25
0
0
5
10
15
20
VDD [V]
25
30
Ta = 25C
CO
0.075
0.025
0
0
RE
0.050
5
NO
T
ICOLL [A]
0.100
10
15
20
VDD [V]
25
30
19
BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8213 Series
Rev.1.4_01
Marking Specification
N
1. SNT-6A
6
5
DE
SI
G
Top view
Product code (Refer to Product name vs. Product code)
Lot number
(1) to (3):
(4) to (6):
4
(1) (2) (3)
(4) (5) (6)
2
3
W
1
CO
RE
NO
T
20
FO
D
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
DE
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
MM
EN
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
R
Product Code
(1)
(2)
(3)
Product Name
S-8213AAB-I6T1U
S-8213AAC-I6T1U
S-8213AAD-I6T1U
S-8213AAE-I6T1U
S-8213AAF-I6T1U
S-8213AAG-I6T1U
S-8213AAH-I6T1U
S-8213AAI-I6T1U
S-8213AAJ-I6T1U
S-8213AAK-I6T1U
S-8213AAL-I6T1U
S-8213AAM-I6T1U
S-8213AAN-I6T1U
S-8213AAO-I6T1U
S-8213AAP-I6T1U
S-8213AAQ-I6T1U
S-8213AAR-I6T1U
S-8213AAS-I6T1U
S-8213AAT-I6T1U
NE
Product name vs. Product code
N
2.9±0.2
1
2
3
0.95
+0.1
0.15 -0.05
DE
CO
MM
EN
0.35±0.15
D
FO
R
NE
0.95
4
5
W
6
DE
SI
G
1.9±0.2
NO
T
RE
No. MP006-A-P-SD-2.1
TITLE
SOT236-A-PKG Dimensions
No.
MP006-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
0.25±0.1
+0.2
ø1.0 -0
W
DE
SI
G
N
+0.1
ø1.5 -0
D
FO
3.2±0.2
MM
EN
DE
3 2 1
4 5 6
1.4±0.2
R
NE
4.0±0.1
CO
Feed direction
NO
T
RE
No. MP006-A-C-SD-3.1
TITLE
SOT236-A-Carrier Tape
No.
MP006-A-C-SD-3.1
ANGLE
UNIT
mm
ABLIC Inc.
9.0±0.3
DE
MM
EN
Enlarged drawing in the central part
D
FO
R
NE
W
DE
SI
G
N
12.5max.
(60°)
CO
(60°)
ø13±0.2
NO
T
RE
No. MP006-A-R-SD-2.1
TITLE
SOT236-A-Reel
No.
MP006-A-R-SD-2.1
ANGLE
QTY
UNIT
mm
ABLIC Inc.
3,000
5
4
2
3
+0.05
0.08 -0.02
NE
1
W
DE
SI
G
6
N
1.57±0.03
0.5
DE
D
FO
R
0.48±0.02
MM
EN
0.2±0.05
NO
T
RE
CO
No. PG006-A-P-SD-2.1
TITLE
SNT-6A-A-PKG Dimensions
No.
PG006-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
N
4.0±0.1
0.25±0.05
+0.1
4.0±0.1
0.65±0.05
4
MM
EN
3 2 1
DE
D
FO
R
1.85±0.05
ø0.5 -0
NE
W
2.0±0.05
DE
SI
G
+0.1
ø1.5 -0
5 6
CO
Feed direction
NO
T
RE
No. PG006-A-C-SD-2.0
TITLE
SNT-6A-A-Carrier Tape
No.
PG006-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
FO
R
NE
W
DE
SI
G
N
12.5max.
D
9.0±0.3
DE
Enlarged drawing in the central part
MM
EN
ø13±0.2
(60°)
No. PG006-A-R-SD-1.0
NO
T
RE
CO
(60°)
SNT-6A-A-Reel
TITLE
No.
PG006-A-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
5,000
1
R
0.2 0.3
NE
W
0.52
2
DE
SI
G
1.36
N
0.52
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
FO
1.
2.
D
0.03 mm
DE
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
MM
EN
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
NO
T
RE
CO
1.
2.
No. PG006-A-L-SD-4.1
TITLE
SNT-6A-A
-Land Recommendation
No.
PG006-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
MM
EN
DE
D
FO
R
NE
W
DE
SI
G
N
1.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
CO
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
RE
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
NO
T
14. For more details on the information described herein, contact our sales office.
2.0-2018.01
www.ablicinc.com
工商网监
湘ICP备2023018690号
