S-8244 Series
www.ablic.com
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK
(SECONDARY PROTECTION)
© ABLIC Inc., 2003-2020
Rev.7.1_00
The S-8244 Series is used for secondary protection of lithium-ion batteries with from one to four cells, and incorporates a
high-precision voltage detector circuit and a delay circuit. Short-circuiting between cells makes it possible for serial
connection of one to four cells.
Features
(1) Internal high-precision voltage detector circuit
• Overcharge detection voltage range: 3.700 V to 4.550 V: Accuracy of ± 25 mV (at +25°C)
(at a 5 mV/step)
Accuracy of ± 50 mV (at −40°C to +85°C)
• Hysteresis:
5 types
0.38 ± 0.1 V, 0.25 ± 0.07 V, 0.13 ± 0.04 V, 0.045 ± 0.02 V, None
(2) High-withstand voltage:
Absolute maximum rating: 26 V
(3) Wide operating voltage range:
3.6 V to 24 V (refers to the range in which the delay circuit can operate
normally after overvoltage is detected)
(4) Delay time during detection:
Can be set by an external capacitor.
(5) Low current consumption:
At 3.5 V for each cell: 3.0 μA max. (+25°C)
At 2.3 V for each cell: 2.4 μA max. (+25°C)
(6) Output logic and form:
5 types
CMOS output active “H”
CMOS output active “L”
Pch open drain output active “L”
Nch open drain output active “H”
Nch open drain output active “L”
(CMOS / Nch open drain output for 0.045 V hysteresis models)
(7) Lead-free (Sn 100%), halogen-free
Applications
• Lithium ion rechargeable battery packs (secondary protection)
Packages
• SNT-8A
• TMSOP-8
1
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
Block Diagram
VCC
SENSE
Overcharge detection
comparator 1
+
-
Reference voltage 1
VC1
Overcharge
detection
delay circuit
Overcharge detection
comparator 2
ICT
+
-
Control
logic
Reference voltage 2
VC2
Overcharge detection
comparator 3
+
-
CO
Reference voltage 3
VC3
Overcharge detection
comparator 4
+
-
Reference voltage 4
VSS
Remark In the case of Nch open-drain output, only the Nch transistor will be connected to the CO
pin.
In the case of Pch open-drain output, only the Pch transistor will be connected to the CO pin.
Figure 1
2
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Product Name Structure
1.
Product Name
S-8244A xx
xx
-
xxx
xx
U
Environmental code
U: Lead-free (Sn 100%), halogen-free
IC direction of tape specifications*1
TF: SNT-8A
T2: TMSOP-8
Product code*2
Package abbreviation
PH: SNT-8A
FM: TMSOP-8
Serial code
Sequentially set from AA to ZZ
*1.
*2.
Refer to the tape drawing.
Refer to “3. Product Name List”.
2. Packages
Package name
SNT-8A
TMSOP-8
Package
PH008-A-P-SD
FM008-A-P-SD
Drawing code
Tape
Reel
PH008-A-C-SD
PH008-A-R-SD
FM008-A-C-SD
FM008-A-R-SD
Land
PH008-A-L-SD
⎯
3
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
3.
Product Name List
(1) SNT-8A
Table 1
Product name
S-8244AAAPH-CEATFU
S-8244AABPH-CEBTFU
S-8244AADPH-CEDTFU
S-8244AAFPH-CEFTFU
S-8244AAGPH-CEGTFU
S-8244AAJPH-CEJTFU
S-8244AASPH-CESTFU
S-8244AATPH-CETTFU
S-8244AAVPH-CEVTFU
S-8244AAYPH-CEYTFU
S-8244AAZPH-CEZTFU
S-8244ABBPH-CFBTFU
S-8244ABDPH-CFDTFU
S-8244ABEPH-CFETFU
S-8244ABHPH-CFHTFU
S-8244ABMPH-CFMTFU
Overcharge detection voltage Overcharge hysteresis voltage
[VCU]
[VCD]
4.450 ± 0.025 V
0.38 ± 0.1 V
4.200 ± 0.025 V
0V
4.200 ± 0.025 V
0V
4.350 ± 0.025 V
0.045 ± 0.02 V
4.450 ± 0.025 V
0.045 ± 0.02 V
4.500 ± 0.025 V
0.38 ± 0.1 V
4.350 ± 0.025 V
0.38 ± 0.1 V
4.200 ± 0.025 V
0.25 ± 0.07 V
4.275 ± 0.025 V
4.300 ± 0.025 V
4.280 ± 0.025 V
4.380 ± 0.025 V
4.150 ± 0.025 V
4.215 ± 0.025 V
4.280 ± 0.025 V
4.100 ± 0.025 V
0.045 ± 0.02 V
0.25 ± 0.07 V
0.25 ± 0.07 V
0.25 ± 0.07 V
0.045 ± 0.02 V
0V
0.045 ± 0.02 V
0.25 ± 0.07 V
4.550 ± 0.025 V
0.38 ± 0.1 V
S-8244ABOPH-CFOTFU
Remark Please contact our sales representatives for products other than the above.
4
Output logic and form
CMOS output active “H”
Nch open drain output active “H”
Pch open drain output active “L”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “L”
Nch open drain output active “L”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
(2) TMSOP-8
Table 2
Product name
S-8244AAAFM-CEAT2U
S-8244AABFM-CEBT2U
S-8244AACFM-CECT2U
S-8244AAFFM-CEFT2U
S-8244AAGFM-CEGT2U
S-8244AAHFM-CEHT2U
S-8244AAIFM-CEIT2U
S-8244AAJFM-CEJT2U
S-8244AALFM-CELT2U
S-8244AANFM-CENT2U
S-8244AAOFM-CEOT2U
Overcharge detection voltage Overcharge hysteresis voltage
[VCU]
[VCD]
4.450 ± 0.025 V
0.38 ± 0.1 V
4.200 ± 0.025 V
0V
4.115 ± 0.025 V
0.13 ± 0.04 V
4.350 ± 0.025 V
0.045 ± 0.02 V
4.450 ± 0.025 V
0.045 ± 0.02 V
4.300 ± 0.025 V
0.25 ± 0.07 V
4.400 ± 0.025 V
0.045 ± 0.02 V
4.500 ± 0.025 V
0.38 ± 0.1 V
4.350 ± 0.025 V
0.25 ± 0.07 V
4.150 ± 0.025 V
0.25 ± 0.07 V
4.250 ± 0.025 V
0.25 ± 0.07 V
4.050 ± 0.025 V
0.25 ± 0.07 V
4.150 ± 0.025 V
0V
4.200 ± 0.025 V
0.25 ± 0.07 V
3.825 ± 0.025 V
0.25 ± 0.07 V
4.275 ± 0.025 V
0.045 ± 0.02 V
4.025 ± 0.025 V
0.25 ± 0.07 V
4.220 ± 0.025 V
0.045 ± 0.02 V
3.750 ± 0.025 V
0.25 ± 0.07 V
4.225 ± 0.025 V
0.045 ± 0.02 V
4.100 ± 0.025 V
0V
4.325 ± 0.025 V
0.045 ± 0.02 V
4.175 ± 0.025 V
0V
4.225 ± 0.025 V
0.38 ± 0.1 V
4.350 ± 0.025 V
0.38 ± 0.1 V
S-8244AAPFM-CEPT2U
S-8244AAQFM-CEQT2U
S-8244AATFM-CETT2U
S-8244AAUFM-CEUT2U
S-8244AAVFM-CEVT2U
S-8244AAXFM-CEXT2U
S-8244ABAFM-CFAT2U
S-8244ABCFM-CFCT2U
S-8244ABGFM-CFGT2U
S-8244ABIFM-CFIT2U
S-8244ABJFM-CFJT2U
S-8244ABKFM-CFKT2U
S-8244ABNFM-CFNT2U
S-8244ABPFM-CFPT2U
Remark Please contact our sales representatives for products other than the above.
Output logic and form
CMOS output active “H”
Nch open drain output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
Nch open drain output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
Nch open drain output active “L”
Nch open drain output active “L”
Nch open drain output active “L”
Nch open drain output active “L”
Nch open drain output active “L”
Nch open drain output active “L”
5
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
Pin Configurations
Table 3
Pin No.
1
SNT-8A
Top view
2
CO
1
8
VCC
ICT
2
7
SENSE
VSS
3
6
VC1
VC3
4
5
VC2
3
4
5
6
7
8
Figure 2
Pin No.
1
2
TMSOP-8
Top view
VCC
1
8
CO
SENSE
2
7
ICT
VC1
3
6
VSS
VC2
4
5
VC3
3
4
5
6
7
Figure 3
6
8
Symbol
Description
CO
FET gate connection pin for charge control
Capacitor connection pin for overcharge detection
ICT
delay
Input pin for negative power supply,
VSS
Connection pin for battery 4’s negative voltage
Connection pin for battery 3’s negative voltage,
VC3
Connection pin for battery 4’s positive voltage
Connection pin for battery 2’s negative voltage,
VC2
Connection pin for battery 3’s positive voltage
Connection pin for battery 1’s negative voltage,
VC1
Connection pin for battery 2’s positive voltage
SENSE Connection pin for battery 1’s positive voltage
VCC Input pin for positive power supply
Table 4
Symbol
Description
VCC Input pin for positive power supply
SENSE Connection pin for battery 1’s positive voltage
Connection pin for battery 1’s negative voltage,
VC1
Connection pin for battery 2’s positive voltage
Connection pin for battery 2’s negative voltage,
VC2
Connection pin for battery 3’s positive voltage
Connection pin for battery 3’s negative voltage,
VC3
Connection pin for battery 4’s positive voltage
Input pin for negative power supply,
VSS
Connection pin for battery 4’s negative voltage
Capacitor connection pin for overcharge detection
ICT
delay
CO
FET gate connection pin for charge control
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Absolute Maximum Ratings
Table 5
(Ta = 25°C unless otherwise specified)
Item
Input voltage between VCC and VSS
Delay capacitor connection pin voltage
Symbol
VDS
VICT
Input pin voltage
VIN
Applied pin
VCC
ICT
SENSE, VC1,
VC2, VC3
(CMOS output)
VCO
(Nch open drain output)
(Pch open drain output)
SNT-8A
Power
PD
dissipation
TMSOP-8
Operating ambient temperature
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Name :
JEDEC STANDARD51-7
CO output pin
voltage
Unit
V
V
VSS −0.3 to VCC +0.3
V
VSS −0.3 to VCC +0.3
VSS −0.3 to 26
VCC −26 to VCC +0.3
450*1
650*1
−40 to +85
−40 to +125
V
V
V
mW
mW
°C
°C
CO
⎯
⎯
⎯
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
700
Power Dissipation (PD) [mW]
Caution
Absolute maximum rating
VSS−0.3 to VSS +26
VSS −0.3 to VCC +0.3
600
TMSOP-8
500
400
300
200
SNT-8A
100
0
0
50
100
150
Ambient Temperature (Ta) [°C]
Figure 4
Power Dissipation of Package (When Mounted on Board)
7
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
Electrical Characteristics
Table 6
(Ta = 25 °C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Test circuit
condition
DETECTION VOLTAGE
Overcharge detection voltage 1 *1
VCU1
3.7 V to 4.55 V Adjustment
Overcharge detection voltage 2 *1
VCU2
3.7 V to 4.55 V Adjustment
Overcharge detection voltage 3 *1
VCU3
3.7 V to 4.55 V Adjustment
Overcharge detection voltage 4 *1
VCU4
3.7 V to 4.55 V Adjustment
Overcharge hysteresis voltage 1 *2
Overcharge hysteresis voltage 2 *2
Overcharge hysteresis voltage 3 *2
Overcharge hysteresis voltage 4 *2
Detection voltage
temperature coefficient *3
DELAY TIME
Overcharge detection delay time
OPERATING VOLTAGE
Operating voltage
between VCC and VSS *5
CURRENT CONSUMPTION
Current consumption
during normal operation
Current consumption at
power down
VC1 sink current
VC2 sink current
VC3 sink current
OUTPUT VOLTAGE*6
VCD1
VCD2
VCD3
VCD4
⎯
⎯
⎯
⎯
VCU1
−0.025
VCU2
−0.025
VCU3
−0.025
VCU4
−0.025
0.28
0.28
0.28
0.28
0.38
0.38
0.38
0.38
VCU1
+0.025
VCU2
+0.025
VCU3
+0.025
VCU4
+0.025
0.48
0.48
0.48
0.48
TCOE
Ta = −40°C to +85°C*4
−0.4
0.0
C = 0.1 μF
1.0
⎯
IOPE
CO “H” voltage
CO “L” voltage
V
1
1
V
2
1
V
3
1
V
4
1
V
V
V
V
1
2
3
4
1
1
1
1
+0.4
mV/°C
⎯
⎯
1.5
2.0
s
5
2
3.6
⎯
24
V
⎯
⎯
V1 = V2 = V3 = V4 = 3.5 V
⎯
1.5
3.0
μA
6
3
IPDN
V1 = V2 = V3 = V4 = 2.3 V
⎯
1.2
2.4
μA
6
3
IVC1
IVC2
IVC3
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
−0.3
−0.3
−0.3
⎯
⎯
⎯
0.3
0.3
0.3
μA
μA
μA
6
6
6
3
3
3
VCO(H)
at IOUT = 10 μA
VCC
−0.05
⎯
⎯
V
7
4
VCO(L)
at IOUT = 10 μA
⎯
⎯
VSS
+0.05
V
7
4
tCU
VDSOP
VCU1
VCU2
VCU3
VCU4
± 50 mV when Ta = −40°C to +85°C.
0.25 ± 0.07 V, 0.13 ± 0.04 V, 0.045 ± 0.02 V except for 0.38 V hysteresis models.
Overcharge detection voltage or overcharge hysteresis voltage.
Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*5. After detecting the overcharge, the delay circuit operates normally in the range of operating voltage.
*6. Output logic and CMOS or open drain output can be selected.
*1.
*2.
*3.
*4.
8
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Test Circuits
(1) Test Condition 1, Test Circuit 1
Set switches 1 and 2 to OFF for CMOS output product.
Set switch 1 to ON and switch 2 to OFF for Nch open drain product.
Set switch 1 to OFF and switch 2 to ON for Pch open drain product.
• Product with CMOS output active “H”, Nch open drain output active “H”
The overcharge detection voltage 1 (VCU1) is a voltage at V1; when the CO pin’s voltage is set to “H” by increasing
V1 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V1’s voltage to set CO = “L”,
and the difference of this V1’s voltage and VCU1 is the overcharge hysteresis voltage 1 (VCD1).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
The overcharge detection voltage 1 (VCU1) is a voltage at V1; when the CO pin’s voltage is set to “L” by increasing
V1 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V1’s voltage to set CO =
“H”, and the difference of this V1’s voltage and VCU1 is the overcharge hysteresis voltage 1 (VCD1).
(2) Test Condition 2, Test Circuit 1
Set switches 1 and 2 to OFF for CMOS output product.
Set switch 1 to ON and switch 2 to OFF for Nch open drain product.
Set switch 1 to OFF and switch 2 to ON for Pch open drain product.
• Product with CMOS output active “H”, Nch open drain output active “H”
The overcharge detection voltage 2 (VCU2) is a voltage at V2; when the CO pin’s voltage is set to “H” by increasing
V2 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V2’s voltage to set CO = “L”,
and the difference of this V2’s voltage and VCU2 is the overcharge hysteresis voltage 2 (VCD2).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
The overcharge detection voltage 2 (VCU2) is a voltage at V2; when the CO pin’s voltage is set to “L” by increasing
V2 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V2’s voltage to set CO =
“H”, and the difference of this V2’s voltage and VCU2 is the overcharge hysteresis voltage 2 (VCD2).
(3) Test Condition 3, Test Circuit 1
Set switches 1 and 2 to OFF for CMOS output product.
Set switch 1 to ON and switch 2 to OFF for Nch open drain product.
Set switch 1 to OFF and switch 2 to ON for Pch open drain product.
• Product with CMOS output active “H”, Nch open drain output active “H”
The overcharge detection voltage 3 (VCU3) is a voltage at V3; when the CO pin’s voltage is set to “H” by increasing
V3 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V3’s voltage to set CO = “L”,
and the difference of this V3’s voltage and VCU3 is the overcharge hysteresis voltage 3 (VCD3).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
The overcharge detection voltage 3 (VCU3) is a voltage at V3; when the CO pin’s voltage is set to “L” by increasing
V3 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V3’s voltage to set CO =
“H”, and the difference of this V3’s voltage and VCU3 is the overcharge hysteresis voltage 3 (VCD3).
9
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
(4) Test Condition 4, Test Circuit 1
Set switches 1 and 2 to OFF for CMOS output product.
Set switch 1 to ON and switch 2 to OFF for Nch open drain product.
Set switch 1 to OFF and switch 2 to ON for Pch open drain product.
• Product with CMOS output active “H”, Nch open drain output active “H”
The overcharge detection voltage 4 (VCU4) is a voltage at V4; when the CO pin’s voltage is set to “H” by increasing
V4 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V4’s voltage to set CO =
“L”, and the difference of this V4’s voltage and VCU4 is the overcharge hysteresis voltage 4 (VCD4).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
The overcharge detection voltage 4 (VCU4) is a voltage at V4; when the CO pin’s voltage is set to “L” by increasing
V4 gradually, after setting V1 = V2 = V3 = V4 = 3.5 V. After that, gradually decreasing V4’s voltage to set CO =
“H”, and the difference of this V4’s voltage and VCU4 is the overcharge hysteresis voltage 4 (VCD4).
(5) Test Condition 5, Test Circuit 2
Set switches 1 and 2 to OFF for CMOS output product.
Set switch 1 to ON and switch 2 to OFF for Nch open drain product.
Set switch 1 to OFF and switch 2 to ON for Pch open drain product.
• Product with CMOS output active “H”, Nch open drain output active “H”
Rise V1 to 4.7 V momentarily within 10 μs after setting V1 = V2 = V3 = V4 = 3.5 V. The period from V1 having
reached 4.7 V to CO = “H” is the overcharge detection delay time (tCU).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
Rise V1 to 4.7 V momentarily within 10 μs after setting V1 = V2 = V3 = V4 = 3.5 V. The period from V1 having
reached 4.7 V to CO = “L” is the overcharge detection delay time (tCU).
(6) Test Condition 6, Test Circuit 3
Measure current consumption (I1) setting V1 = V2 = V3 = V4 = 2.3 V. This I1 is current consumption at power-down
(IPDN).
Measure current consumption (I1) setting V1 = V2 = V3 = V4 = 3.5 V. This I1 is current consumption during normal
operation (IOPE), I2 is the VC1 sink current (IVC1), I3 is the VC2 sink current (IVC2), I4 is the VC3 sink current (IVC3).
10
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
(7) Test Condition 7, Test Circuit 4
Measure setting switch 1 to OFF and switch 2 to ON.
• Product with CMOS output active “H”
Decrease V6 from VCC gradually after setting V1 = V2 = V3 = V4 = 4.6 V, the V6’s voltage when flowing I2 = −10
μA is the VCO(H) voltage.
Increase V6 from 0 V gradually after setting V1 = V2 = V3 = V4 = 3.5 V, the V6’s voltage when flowing I2 = 10 μA
is the VCO(L) voltage.
• Product with CMOS output active “L”
Decrease V6 from VCC gradually after setting V1 = V2 = V3 = V4 = 3.5 V, the V6’s voltage when flowing I2 = −10
μA is the VCO(H) voltage.
Increase V6 from 0 V gradually after setting V1 = V2 = V3 = V4 = 4.6 V, the V6’s voltage when flowing I2 = 10 μA
is the VCO(L) voltage.
• Product with Pch open drain output active “L”
Decrease V6 from VCC gradually after setting V1 = V2 = V3 = V4 = 3.5 V, the V6’s voltage when flowing I2 = −10
μA is the VCO(H) voltage.
• Product with Nch open drain output active “H”
Increase V6 from 0 V gradually after setting V1 = V2 = V3 = V4 = 3.5 V, the V6’s voltage when flowing I2 = 10 μA
is the VCO(L) voltage.
• Product with Nch open drain output active “L”
Increase V6 from 0 V gradually after setting V1 = V2 = V3 = V4 = 4.6 V, the V6’s voltage when flowing I2 = 10 μA
is the VCO(L) voltage.
11
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
10 MΩ
10 MΩ
SW1
S-8244
S-8244
VCC
CO
SENSE
ICT
SW2
V1
VC1
V
VSS
V4
V2
VC2
SW1
VCC
CO
SENSE
ICT
V1
VC1
VSS
VC2
VC3
SW2
0.1 μF
V2
VC3
10 MΩ
V3
V
V4
10 MΩ
V3
Test Circuit 1
Test Circuit 2
I1
S-8244
I1
V1
V2
I2
I3
VCC
CO
SENSE
ICT
VC1
VC2
V5
S-8244
VSS
VC3
V3
I4
V4
VCC
CO
SENSE
ICT
SW2
V1
VC1
VSS
V2
VC2
VC3
V3
Test Circuit 3
Test Circuit 4
Figure 5
12
SW1
V
V4
I2
V6
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Operation
Remark Refer to “
Battery Protection IC Connection Example”.
1. Overcharge Detection
• Product with CMOS output active “H”, Nch open drain output active “H”
During charging in the normal status, the voltage of one of the batteries exceeds overcharge detection voltage
(VCU), and this status is maintained for overcharge detection delay time (tCU) or longer, CO gets “H”. This is
overcharge status. Connecting a FET to the CO pin enables charge-control and the second protect.
In this case, the IC maintains the overcharge status until the voltage of each of the batteries decreases, to the
overcharge hysteresis voltage (VCD) from the overcharge detection voltage (VCU).
• Product with CMOS output active “L”, Nch open drain output active “L”, Pch open drain output active “L”
During charging in the normal status, the voltage of one of the batteries exceeds overcharge detection voltage
(VCU), and this status is maintained for overcharge detection delay time (tCU) or longer, CO gets “L”. This is
overcharge status. Connecting a FET to the CO pin enables charge-control and the second protect.
In this case, the IC maintains the overcharge status until the voltage of each of the batteries decreases, to the
overcharge hysteresis voltage (VCD) from the overcharge detection voltage (VCU).
2. Delay Circuit
The delay circuit rapidly charges the capacitor connected to the delay capacitor connection pin up to a specified
voltage when the voltage of one of the batteries exceeds the overcharge detection voltage (VCU). Then, the delay
circuit gradually discharges the capacitor at 100 nA and inverts the CO output when the voltage at the delay
capacitor connection pin goes below a specified level. Overcharge detection delay time (tCU) varies depending
upon the external capacitor.
Each delay time is calculated using the following equation.
Min.
tCU[s] = Delay Coefficient (10,
Typ.
15,
Max.
20) × CICT [μF]
Because the delay capacitor is rapidly charged, the smaller the capacitance, the larger the difference between the
maximum voltage and the specified value of delay capacitor pin (ICT pin). This will cause a deviation between
the calculated delay time and the resultant delay time. Also, delay time is internally set in this IC to prevent the
CO output from inverting until the charge to delay capacitor pin is reached to the specified voltage. If large
capacitance is used, output may be enabled without delay time because charge is disabled within the internal
delay time.
Please note that the maximum capacitance connected to the delay capacitor pin (ICT pin) is 1 μF.
13
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
Timing Chart
VCD
V1 battery
V2 battery
VCU
Battery voltage
VSS
VCC
CO pin voltage
CMOS output active “H” and
Nch open drain output active “H” products
VSS
VCC
CO pin voltage
CMOS output active “L” ,
Pch open drain output active “L” and
Nch open drain output active “L” products
VSS
ICT pin voltage
VSS
Delay
Figure 6
14
V3 battery
V4 battery
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Battery Protection IC Connection Example
(1)
Connection Example 1
SCP
EB+
RVCC
SENSE
R1
BAT1
VCC
CVCC
C1
VC1
R2
BAT2
C2
VC2
R3
BAT3
ICT
CICT
C3
VC3
R4
BAT4
FET
C4
VSS
CO
EB−
Figure 7
Table 7 Constants for External Components 1
Symbol
R1 to R4
C1 to C4
RVCC
CVCC
CICT
Min.
0
0
0
0
0
Typ.
1k
0.1
100
0.1
0.1
Max.
10 k
1
1k
1
1
Unit
Ω
μF
Ω
μF
μF
Caution1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation.
Perform thorough evaluation using the actual application to set the constants.
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL +81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
15
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
(2) Connection Example 2 (for 3-cells)
SCP
EB+
RVCC
SENSE
R1
BAT1
VCC
CVCC
C1
VC1
R2
BAT2
C2
VC2
R3
BAT3
ICT
CICT
C3
VC3
FET
VSS
CO
EB−
Figure 8
Symbol
R1 to R3
C1 to C3
RVCC
CVCC
CICT
Table 8 Constants for External Components 2
Min.
Typ.
Max.
0
1k
10 k
0
0.1
1
0
100
1k
0
0.1
1
0
0.1
1
Unit
Ω
μF
Ω
μF
μF
Caution1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation.
Perform thorough evaluation using the actual application to set the constants.
16
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
(3) Connection Example 3 (for 2-cells)
SCP
EB+
RVCC
SENSE
R1
BAT1
VCC
CVCC
C1
VC1
R2
BAT2
C2
VC2
ICT
CICT
VC3
FET
VSS
CO
EB−
Figure 9
Symbol
R1, R2
C1, C2
RVCC
CVCC
CICT
Table 9 Constants for External Components 3
Min.
Typ.
Max.
0
1k
10 k
0
0.1
1
0
100
1k
0
0.1
1
0
0.1
1
Unit
Ω
μF
Ω
μF
μF
Caution1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation.
Perform thorough evaluation using the actual application to set the constants.
17
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
(4) Connection Example 4 (for 1-cell)
SCP
EB+
RVCC
SENSE
R1
BAT1
VCC
CVCC
C1
VC1
VC2
ICT
CICT
VC3
FET
VSS
CO
EB−
Figure 10
Table 10 Constants for External Components 4
Symbol
R1
C1
RVCC
CVCC
CICT
Min.
0
0
0
0
0
Typ.
1k
0.1
100
0.1
0.1
Max.
10 k
1
1k
1
1
Unit
Ω
μF
Ω
μF
μF
Caution1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation.
Perform thorough evaluation using the actual application to set the constants.
18
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
Rev.7.1_00
S-8244 Series
Precautions
• This IC charges the delay capacitor through the delay capacitor pin (ICT pin) immediately when the voltage of one of
batteries V1 to V4 reaches the overcharge voltage. Therefore, setting the resistor connected to the VCC pin to any
value greater than the recommended level causes a reduction in the IC power supply voltage because of charge
current of the delay capacitor. This may lead to a malfunction. Set up the resistor NOT to exceed the typical value.
If you change the resistance, please consult us.
• DO not connect any of overcharged batteries. Even if only one overcharged battery is connected to this IC, the IC
detects overcharge, then charge current flows to the delay capacitor through the parasitic diode between pins where
the battery is not connected yet. This may lead to a malfunction. Please perform sufficient evaluation in the case of
use. Depending on an application circuit, even when the fault charge battery is not contained, the connection turn of
a battery may be restricted in order to prevent the output of CO detection pulse at the time of battery connection.
CMOS output active “H” and Nch open drain output active “H” products
VCD
V1 battery
V2 battery
V3 battery
V4 battery
VCU
Battery voltage
VSS
VCC
CO pin voltage
CICT high
CICT low
VSS
CICT low
Setting voltage
ICT pin voltage
CICT high
VSS
Internal delay
Delay
• In this IC, the output logic of the CO pin is inverted after several milliseconds of internal delay if this IC is under the
overcharge condition even ICT pin is either “VSS−short circuit,” “VCC−short circuit” or “Open” status.
• Any position from V1 to V4 can be used when applying this IC for a one to three-cell battery. However, be sure to
short circuit between pins not in use (SENSE−VC1, VC1−VC2, VC2−VC3, or VC3−VSS).
• The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
19
BATTERY PROTECTION IC FOR 1-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8244 Series
Rev.7.1_00
Characteristics (Typical Data)
1. Detection Voltage vs. Temperature
Overcharge Detection Voltage vs. Temperature
VCU = 4.45 V
S-8244AAAFN
4.17
VCU−VCD [V]
S-8244AAAFN
4.55
VCU [V]
Overcharge Release Voltage vs. Temperature
4.45
VCD = 0.38 V
4.07
3.97
4.35
−40
−20
0
20
40
Ta [°C]
60
80
−40
100
−20
0
20
40
Ta [°C]
60
80
100
2. Current Consumption vs. Temperature
Current Consumption during Normal Operation vs. Temperature
S-8244AAAFN
VCC = 14.0 V
2
1
VCC = 9.2 V
S-8244AAAFN
3
IPDN [μA]
IOPE [μA]
3
Current Consumption at Power Down vs. Temperature
2
1
0
0
−40
−20
0
20
40
Ta [°C]
60
80
100
−40
−20
0
3. Delay Time vs. Temperature
Overcharge Detection Delay Time vs. Temperature
S-8244AAAFN
VCC = 15.2 V
tCU [s]
3
2
1
0
−40
Caution
20
−20
0
20
40
Ta [°C]
60
80
100
Please design all applications of the S-8244 Series with safety in mind.
20
40
Ta [°C]
60
80
100
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.25±0.05
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
4.00±0.1
4.00±0.1
1.00±0.1
+0.1
1.5 -0
1.05±0.05
0.30±0.05
3.25±0.05
4
1
5
8
Feed direction
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
16.5max.
13.0±0.3
Enlarged drawing in the central part
13±0.2
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
工商网监
湘ICP备2023018690号
