S-8239A Series
www.ablic.com
OVERCURRENT MONITORING IC
FOR MULTI-SERIAL-CELL PACK
© ABLIC Inc., 2013-2020
Rev.1.6_00
The S-8239A Series is an overcurrent monitoring IC for multi-serial-cell pack including high-accuracy voltage detection
circuits and delay circuits.
The S-8239A Series is suitable for protection of lithium-ion / lithium polymer rechargeable battery packs from overcurrent.
Features
• Built-in high-accuracy voltage detection circuit
Overcurrent 1 detection voltage*1
0.04 V to 0.30 V (10 mV step)
Accuracy ±15 mV
Overcurrent 2 detection voltage
0.1 V to 0.7 V (100 mV step)
Accuracy ±100 mV
Overcurrent 3 detection voltage
1.2 V (Fixed)
Accuracy ±300 mV
• Built-in three-step overcurrent detection circuit: Overcurrent 1, overcurrent 2, overcurrent 3
• Overcurrent 3 detection function:
Available, unavailable
• UVLO (under voltage lock out) function
UVLO detection voltage
2.0 V (Fixed)
Accuracy ±100 mV
• High-withstand voltage:
VM pin, DO pin: Absolute maximum rating 28 V
• Delay times are generated only by an internal circuit (External capacitors are unnecessary).
• Low current consumption
During normal operation:
7.0 μA max.
During UVLO operation:
6.0 μA max.
• Output logic:
Active "L", Active "H"
• Wide operation temperature range:
Ta = −40°C to +85°C
• Lead-free (Sn 100%), halogen-free
*1. Overcurrent 1 detection voltage ≤ 0.06 V should be satisfied in the case of overcurrent 2 detection voltage = 0.1 V.
Overcurrent 1 detection voltage ≤ 0.85 × overcurrent 2 detection voltage − 0.05 V should be satisfied in the case of
overcurrent 2 detection voltage ≥ 0.2 V.
Applications
• Lithium-ion rechargeable battery pack
• Lithium polymer rechargeable battery pack
Package
• SOT-23-6
1
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Block Diagram
DP
DO
+
VDD
−
Delay circuit
output control circuit
UVLO detection
comparator
+
−
VM
RVMS
Overcurrent latch
comparator
+
−
VINI
Overcurrent 1
detection comparator
+
−
Overcurrent 2
detection comparator
+
−
VSS
Remark All the diodes shown in the figure are parasitic diodes.
Figure 1
2
Overcurrent 3
detection comparator
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Product Name Structure
1. Product name
S-8239A xx
-
M6T1
U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M6T1: SOT-23-6, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name
SOT-23-6
Dimension
Tape
Reel
MP006-A-P-SD
MP006-A-C-SD
MP006-A-R-SD
3. Product name list
Table 2
Product Name
Overcurrent 1
Detection
Voltage
[VDIOV1]
Overcurrent 2
Detection
Voltage
[VDIOV2]
Overcurrent 1
Detection
Delay Time
[tDIOV1]
Overcurrent 2
Detection
Delay Time
[tDIOV2]
S-8239AAA-M6T1U
0.08 V
0.4 V
1150 ms
S-8239AAB-M6T1U
0.10 V
0.5 V
1150 ms
S-8239AAC-M6T1U
0.10 V
0.3 V
18.0 ms
S-8239AAD-M6T1U
0.10 V
0.2 V
290 ms
S-8239AAE-M6T1U
0.10 V
0.7 V
18.0 ms
S-8239AAF-M6T1U
0.04 V
0.3 V
4600 ms
S-8239AAG-M6T1U
0.10 V
0.2 V
1150 ms
S-8239AAH-M6T1U
0.06 V
0.1 V
290 ms
S-8239AAI-M6T1U
0.10 V
0.3 V
290 ms
S-8239AAJ-M6T1U
0.11 V
0.3 V
4600 ms
S-8239AAK-M6T1U
0.10 V
0.3 V
290 ms
S-8239AAL-M6T1U
0.06 V
0.2 V
290 ms
S-8239AAM-M6T1U
0.06 V
0.1 V
1150 ms
S-8239AAN-M6T1U
0.07 V
0.2 V
290 ms
S-8239AAO-M6T1U
0.30 V
0.6 V
4600 ms
S-8239AAP-M6T1U
0.10 V
0.2 V
36 ms
Remark Contact our sales representatives for products other than the above.
1.12 ms
0.28 ms
0.28 ms
0.56 ms
0.56 ms
0.28 ms
1.12 ms
0.56 ms
0.28 ms
2.24 ms
1.12 ms
1.12 ms
9.00 ms
0.56 ms
143 ms
0.56 ms
Overcurrent 3
Detection
Output Logic
Function
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Available
Unavailable
Unavailable
Available
Available
Unavailable
Available
Available
Available
Unavailable
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
3
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Pin Configuration
1. SOT-23-6
Table 3
Top view
6 5 4
1 2 3
Figure 2
*1. The DP pin should be open.
4
Pin No.
Symbol
1
VINI
2
3
4
5
6
VM
DO
DP*1
VDD
VSS
Description
Voltage detection pin between VINI pin and VSS pin
(Overcurrent detection pin)
Overcurrent latch pin
Connection pin of discharge control FET gate
Test pin for delay time measurement
Input pin for positive power supply
Input pin for negative power supply
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Absolute Maximum Ratings
Table 4
(Ta = +25°C unless otherwise specified)
Item
Input voltage between VDD pin and VSS pin
VM pin input voltage
VINI pin input voltage
DO pin output voltage
Power dissipation
Operation ambient temperature
Symbol
VDS
VVM
VVINI
VDO
PD
Topr
Storage temperature
Tstg
Applied pin
VDD
VM
VINI
DO
−
−
Absolute Maximum Rating
VSS − 0.3 to VSS +12
VDD − 28 to VDD + 0.3
VSS − 0.3 to VSS + 12
VSS − 0.3 to VSS + 28
650*1
−40 to +85
Unit
V
V
V
V
mW
°C
−
−55 to +125
°C
*1. When mounted on board
[Mounted board]
(1) Board size:
114.3 mm × 76.2 mm × t1.6 mm
(2) Board name:
JEDEC STANDARD51-7
1. The DP pin should be open.
2. The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
700
Power dissipation (PD) [mW]
Caution
600
500
400
300
200
100
0
0
100
150
50
Ambient temperature (Ta) [°C]
Figure 3 Power Dissipation of Package (When Mounted on Board)
5
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Electrical Characteristics
1. Ta = +25°C
Table 5
Item
Symbol
Condition
VDIOV1
−
Overcurrent 2 detection voltage*1 VDIOV2
−
Min.
(Ta = +25°C unless otherwise specified)
Test
Test
Typ. Max. Unit
Condition Circuit
Detection Voltage
Overcurrent 1 detection voltage
Overcurrent 3 detection voltage
VDIOV3
UVLO detection voltage
VUVLO
Release Voltage
Overcurrent release voltage
VRIOV
Input Voltage, Operation Voltage
Operation voltage between
VDSOP
VDD pin and VSS pin
Current Consumption
Current consumption during
IOPE
normal operation
Current consumption during
IUVLO
UVLO operation
Internal Resistance
Internal resistance between
RVMS
VM pin and VSS pin
Output Resistance (Active "L")
DO pin resistance "L"
RDOL
Output Resistance (Active "H")
DO pin resistance "L"
RDOL
With overcurrent 3 detection
function
−
VDIOV1
VDIOV1
− 0.015
VDIOV2
VDIOV2
− 0.100
VDIOV1
+ 0.015
VDIOV2
+ 0.100
V
1
1
V
1
1
0.90
1.20
1.50
V
1
1
1.90
2.00
2.10
V
1
1
VDD criteria, VDD = 3.5 V
0.7
1.2
1.5
V
1
1
Output logic is determined*2
1.5
−
8
V
−
−
VDD = 3.5 V, VVM = 0 V
1.0
3.5
7.0
μA
2
2
VDD = VVM = 1.5 V
0.7
3.0
6.0
μA
2
2
VDD = VVM = 3.5 V
210
300
390
kΩ
3
3
VDD = VVINI = 3.5 V, VDO = 0.5 V
2.5
5
10
kΩ
4
4
VDD = 3.5 V, VVINI = 0 V
VDO = 0.5 V
2.5
5
10
kΩ
4
4
tDIOV1
tDIOV1
× 1.4
ms
5
5
tDIOV2
tDIOV2
× 1.4
ms
5
5
280
392
μs
5
5
Delay Time
tDIOV1
Overcurrent 1 detection delay
−
tDlOV1
× 0.6
time
t
Overcurrent 2 detection delay
DIOV2
−
tDlOV2
× 0.6
time
With overcurrent 3 detection
Overcurrent 3 detection delay
168
tDlOV3 function
time
−
UVLO detection delay time
tUVLO
2.94
*1. Even if overcurrent 1 detection voltage and overcurrent 2 detection voltage are
VDIOV2.
*2. It indicates that DO pin output logic is determined.
6
4.90
6.86
s
5
5
in the same range, VDIOV1 is lower than
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
2. Ta = −40°C to +85°C*1
Table 6
Item
Symbol
Condition
(Ta = −40°C to +85°C*1 unless otherwise specified)
Test
Test
Min.
Typ. Max. Unit
Condition Circuit
Detection Voltage
VDIOV1
−
Overcurrent 2 detection voltage*2 VDIOV2
−
Overcurrent 1 detection voltage
Overcurrent 3 detection voltage
VDIOV3
UVLO detection voltage
VUVLO
Release Voltage
Overcurrent release voltage
VRIOV
Input Voltage, Operation Voltage
Operation voltage between
VDSOP
VDD pin and VSS pin
Current Consumption
Current consumption during
IOPE
normal operation
Current consumption during
IUVLO
UVLO operation
Internal Resistance
Internal resistance between
RVMS
VM pin and VSS pin
Output Resistance (Active "L")
DO pin resistance "L"
RDOL
Output Resistance (Active "H")
DO pin resistance "L"
RDOL
With overcurrent 3 detection
function
−
VDIOV1
VDIOV1
− 0.021
VDIOV2
VDIOV2
− 0.130
VDIOV1
+ 0.021
VDIOV2
+ 0.130
V
1
1
V
1
1
0.70
1.20
1.70
V
1
1
1.85
2.00
2.15
V
1
1
VDD criteria, VDD = 3.5 V
0.5
1.2
1.7
V
1
1
Output logic is determined*3
1.5
−
8
V
−
−
VDD = 3.5 V, VVM = 0 V
0.7
3.5
8.0
μA
2
2
VDD = VVM = 1.5 V
0.5
3.0
7.0
μA
2
2
VDD = VVM = 3.5 V
150
300
450
kΩ
3
3
VDD = VVINI = 3.5 V, VDO = 0.5 V
1.2
5
15
kΩ
4
4
VDD = 3.5 V, VVINI = 0 V
VDO = 0.5 V
1.2
5
15
kΩ
4
4
Delay Time
tDIOV1
tDIOV1
Overcurrent 1 detection delay
−
tDlOV1
tDIOV1
ms
5
5
× 0.2
× 1.8
time
tDIOV2
tDIOV2
Overcurrent 2 detection delay
−
tDlOV2
tDIOV2
ms
5
5
× 0.2
× 1.8
time
With overcurrent 3 detection
Overcurrent 3 detection delay
μs
56
280
504
tDlOV3
5
5
function
time
−
UVLO detection delay time
tUVLO
0.98
4.90
8.82
s
5
5
*1. Since products are not screened at high and low temperatures, the specification for this temperature range is
guaranteed by design, not tested in production.
*2. Even if overcurrent 1 detection voltage and overcurrent 2 detection voltage are in the same range, VDIOV1 is lower than
VDIOV2.
*3. It indicates that DO pin output logic is determined.
7
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Test Circuits
Caution
Unless otherwise specified, the output voltage levels "H" and "L" at the DO pin (VDO) are judged by
the threshold voltage (1.0 V) of the N-channel FET. Judge the DO pin level with respect to VSS.
1. Overcurrent 1 detection voltage, overcurrent 2 detection voltage, overcurrent release voltage,
UVLO detection voltage
(Test condition 1, test circuit 1)
1. 1 Active "L"
The overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V2 whose delay time for changing VDO from
"H" to "L" lies between the minimum and the maximum value of the overcurrent 1 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
The overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V2 whose delay time for changing VDO from
"H" to "L" lies between the minimum and the maximum value of the overcurrent 2 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
The overcurrent release voltage (VRIOV) is defined as the voltage V3 at which VDO goes from "L" to "H" after
decreasing V2 to 0 V and the voltage V3 is increased gradually from the set conditions of V1 = V2 = 3.5 V, V3 =
0 V.
The UVLO detection voltage (VUVLO) is defined as the voltage V1 at which VDO goes from "H" to "L" after the
voltages V1 and V3 are decreased gradually from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
1. 2 Active "H"
The overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V2 whose delay time for changing VDO from
"L" to "H" lies between the minimum and the maximum value of the overcurrent 1 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
The overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V2 whose delay time for changing VDO from
"L" to "H" lies between the minimum and the maximum value of the overcurrent 2 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
The overcurrent release voltage (VRIOV) is defined as the voltage V3 at which VDO goes from "H" to "L" after
decreasing V2 to 0 V and the voltage V3 is increased gradually from the set conditions of V1 = V2 = 3.5 V, V3 =
0 V.
The UVLO detection voltage (VUVLO) is defined as the voltage V1 at which VDO goes from "L" to "H" after the
voltages V1 and V3 are decreased gradually from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
2. Overcurrent 3 detection voltage (With overcurrent 3 detection function)
(Test condition 1, test circuit 1)
2. 1 Active "L"
The overcurrent 3 detection voltage (VDIOV3) is defined as the voltage V2 whose delay time for changing VDO from
"H" to "L" lies between the minimum and the maximum value of the overcurrent 3 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
2. 2 Active "H"
The overcurrent 3 detection voltage (VDIOV3) is defined as the voltage V2 whose delay time for changing VDO from
"L" to "H" lies between the minimum and the maximum value of the overcurrent 3 detection delay time after the
voltage V2 is increased instantaneously (within 10 μs) from the set conditions of V1 = V3 = 3.5 V, V2 = 0 V.
3. Current consumption during normal operation, current consumption during UVLO operation
(Test condition 2, test circuit 2)
The current consumption during normal operation (IOPE) is the current that flows through the VDD pin (IDD) under the
set conditions of V1 = 3.5 V, V2 = 0 V.
The current consumption during UVLO operation (IUVLO) is IDD under the set conditions of V1 = V2 = 1.5 V.
4. Internal resistance between VM pin and VSS pin
(Test condition 3, test circuit 3)
The internal resistance between the VM pin and the VSS pin (RVMS) is the resistance between the VM pin and the
VSS pin under the set condition of V1 = V2 = V3 = 3.5 V.
8
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
5. DO pin resistance "L"
(Test condition 4, test circuit 4)
5. 1 Active "L"
The DO pin resistance "L" (RDOL) is the DO pin resistance under the set conditions of V1 = V2 = 3.5 V, V3 = 0.5 V.
5. 2 Active "H"
The DO pin resistance "L" (RDOL) is the DO pin resistance under the set conditions of V1 = 3.5 V, V2 = 0 V, V3 =
0.5 V.
6. Overcurrent 1 detection delay time
(Test condition 5, test circuit 5)
6. 1 Active "L"
6. 1. 1 VDIOV2 = 0.1 V
The overcurrent 1 detection delay time (tDIOV1) is the time period from when the voltage V2 exceeds VDIOV1 to
when VDO goes to "L", after V2 is increased to 0.08V instantaneously (within 10 μs) under the set conditions of
V1 = 3.5 V, V2 = 0 V.
6. 1. 2 VDIOV2 ≥ 0.2 V
The overcurrent 1 detection delay time (tDIOV1) is the time period from when the voltage V2 exceeds VDIOV1 to
when VDO goes to "L", after V2 is increased to VDIOV1 max. + 0.01 V instantaneously (within 10 μs) under the set
conditions of V1 = 3.5 V, V2 = 0 V.
6. 2 Active "H"
6. 2. 1 VDIOV2 = 0.1 V
The overcurrent 1 detection delay time (tDIOV1) is the time period from when the voltage V2 exceeds VDIOV1 to
when VDO goes to "H", after V2 is increased to 0.08V instantaneously (within 10 μs) under the set conditions of
V1 = 3.5 V, V2 = 0 V.
6. 2. 2 VDIOV2 ≥ 0.2 V
The overcurrent 1 detection delay time (tDIOV1) is the time period from when the voltage V2 exceeds VDIOV1 to
when VDO goes to "H", after V2 is increased to VDIOV1 max. + 0.01 V instantaneously (within 10 μs) under the set
conditions of V1 = 3.5 V, V2 = 0 V.
7. Overcurrent 2 detection delay time, UVLO detection delay time
(Test condition 5, test circuit 5)
7. 1 Active "L"
The overcurrent 2 detection delay time (tDIOV2) is the time period from when the voltage V2 exceeds VDIOV2 to when
VDO goes to "L", after V2 is increased to 0.9 V instantaneously (within 10 μs) under the set conditions of V1 = 3.5 V,
V2 = 0 V.
The UVLO detection delay time (tUVLO) is the time period from when the voltage V1 falls below VUVLO to when VDO
goes to "L", after V1 is decreased to 1.8 V instantaneously (within 10 μs) under the set conditions of V1 = 3.5 V, V2
= 0 V.
7. 2 Active "H"
The overcurrent 2 detection delay time (tDIOV2) is the time period from when the voltage V2 exceeds VDIOV2 to when
VDO goes to "H", after V2 is increased to 0.9 V instantaneously (within 10 μs) under the set conditions of V1 = 3.5
V, V2 = 0 V.
The UVLO detection delay time (tUVLO) is the time period from when the voltage V1 falls below VUVLO to when VDO
goes to "H", after V1 is decreased to 1.8 V instantaneously (within 10 μs) under the set conditions of V1 = 3.5 V, V2
= 0 V.
9
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
8. Overcurrent 3 detection delay time (With overcurrent 3 detection function)
(Test condition 5, test circuit 5)
8. 1 Active "L"
The overcurrent 3 detection delay time (tDIOV3) is the time period from when the voltage V2 exceeds VDIOV3 to when
VDO goes to "L", after V2 is increased to 1.6 V instantaneously (within 10 μs) under the set conditions of V1 = 3.5 V,
V2 = 0 V.
8. 2 Active "H"
The overcurrent 3 detection delay time (tDIOV3) is the time period from when the voltage V2 exceeds VDIOV3 to when
VDO goes to "H", after V2 is increased to 1.6 V instantaneously (within 10 μs) under the set conditions of V1 =
3.5 V, V2 = 0 V.
10
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
IDD
A
DP
VDD
V1
V1
S-8239A Series
VSS
S-8239A Series
V3
VM
VSS
VM
DO
VINI
DO
VINI
DP
VDD
100 kΩ
V2
V2
V VDO
COM
COM
Figure 5 Test Circuit 2
Figure 4 Test Circuit 1
V1
S-8239A Series
V1
S-8239A Series
VINI
DO
VINI
VM
VSS
VM
VSS
DP
VDD
DP
VDD
A IVM
A IDO
V2
V3
V2
DO
V3
COM
COM
Figure 6 Test Circuit 3
DP
VDD
V1
Figure 7 Test Circuit 4
S-8239A Series
VSS
VM
DO
VINI
100 kΩ
V2
COM
Oscilloscope
Figure 8 Test Circuit 5
11
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Operation
1. Normal status
The S-8239A Series monitors the voltage between the VINI pin and the VSS pin to control discharging. When the
VINI pin voltage is equal to or lower than the overcurrent 1 detection voltage (VDIOV1), the DO pin becomes "High-Z"
(Active "L") or VSS potential (Active "H"). This status is called the normal status.
Caution
When a battery is connected for the first time, the S-8239A Series may not be in the normal status.
In this case, short the VM pin and VSS pin or connect the charger. The S-8239A Series then
becomes the normal status.
2. Overcurrent status (Overcurrent 1, overcurrent 2, overcurrent 3)
When a battery is in the normal status, if the VINI pin voltage is equal to or higher than the overcurrent detection
voltage because the discharge current is equal to or higher than the specified value and the status continues for the
overcurrent detection delay time or longer, the DO pin becomes VSS potential (Active "L") or "High-Z" (Active "H").
This status is called the overcurrent status. The overcurrent status is retained when the voltage between the VDD pin
and the VM pin is equal to or lower than the overcurrent release voltage (VRIOV).
In the overcurrent status, the VM pin and VSS pin are shorted by the internal resistor between the VM pin and the
VSS pin (RVMS) in the S-8239A Series. However, the VM pin is at VDD potential due to the external load as long as the
external load is connected. When the external load is disconnected completely, the VM pin returns to VSS potential.
The overcurrent status is released when the voltage between the VDD pin and the VM pin is equal to or higher than
VRIOV.
3. UVLO status
The S-8239A Series includes a UVLO (under voltage lock out) function to prevent the IC malfunction due to the
decrease of the battery voltage when detecting the overcurrent. When the battery voltage in the normal status is
equal to or lower than the UVLO detection voltage (VUVLO) and the status continues for the UVLO detection delay time
(tUVLO) or longer, the DO pin becomes VSS potential (Active "L") or "High-Z" (Active "H"). This status is called the
UVLO status.
In the UVLO status, the VM pin and VSS pin are shorted by RVMS between the VM pin and the VSS pin in the
S-8239A Series.
After that, the UVLO status is released if the battery voltage becomes equal to or higher than VUVLO.
12
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
4. Delay circuit
The detection delay times are determined by dividing a clock of approximately 3.5 kHz with the counter.
Remark The overcurrent 2 detection delay time (tDIOV2) starts when the overcurrent 1 detection voltage (VDIOV1) is
detected. When the overcurrent 2 detection voltage (VDIOV2) is detected over tDIOV2 after the detection of
VDIOV1, the S-8239A Series becomes the overcurrent status within tDIOV2 from the time of detecting VDIOV2.
DO pin
High-Z
0 ≤ tD ≤ tDIOV2
VSS
tDIOV2
tD
Time
VDIOV2
VINI pin
VDIOV1
VSS
Time
Figure 9
5. DP pin
The DP pin is a test pin for delay time measurement and it should be open in the actual application.
If a capacitor whose capacitance is 1000 pF or more or a resistor whose resistance is 1 MΩ or less is connected to
this pin, error may occur in the delay times or in the detection voltages.
13
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Timing Charts
1. Overcurrent detection
1. 1 Active "L"
1. 1. 1 With overcurrent 3 detection function
VINI pin
VDIOV3
VDIOV2
VDIOV1
VSS
VDD
VRIOV
VM pin
VSS
High-Z
DO pin
High-Z
High-Z
High-Z
VSS
External load connection
Overcurrent 1 detection
delay time (tDIOV1)
Overcurrent 2 detection
delay time (tDIOV2)
Status*1
(1)
(2)
(1)
(2)
*1. (1): Normal status
(2): Overcurrent status
Figure 10
14
Overcurrent 3 detection
delay time (tDIOV3)
(1)
(2)
(1)
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
1. 1. 2 Without overcurrent 3 detection function
VINI pin
VDIOV2
VDIOV1
VSS
VDD
VRIOV
VM pin
VSS
High-Z
DO pin
High-Z
High-Z
VSS
External load connection
Overcurrent 1 detection delay time (tDIOV1) Overcurrent 2 detection delay time (tDIOV2)
Status
*1
(1)
(2)
(1)
(2)
(1)
*1. (1): Normal status
(2): Overcurrent status
Figure 11
15
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
1. 2 Active "H"
1. 2. 1 With overcurrent 3 detection function
VINI pin
VDIOV3
VDIOV2
VDIOV1
VSS
VDD
VRIOV
VM pin
VSS
High-Z
DO pin
High-Z
High-Z
VSS
External load connection
Overcurrent 1 detection delay time (tDIOV1) Overcurrent 2 detection delay time (tDIOV2)
Overcurrent 3 detection delay time (tDIOV3)
Status*1
(1)
(2)
(1)
(2)
*1. (1): Normal status
(2): Overcurrent status
Figure 12
16
(1)
(2)
(1)
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
1. 2. 2 Without overcurrent 3 detection function
VINI pin
VDIOV2
VDIOV1
VSS
VDD
VRIOV
VM pin
VSS
High-Z
DO pin
High-Z
VSS
External load connection
Overcurrent 1 detection delay time (tDIOV1) Overcurrent 2 detection delay time (tDIOV2)
Status
*1
(1)
(2)
(1)
(2)
(1)
*1. (1): Normal status
(2): Overcurrent status
Figure 13
17
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
2. UVLO detection
2. 1 Active "L"
VUVLO
Battery voltage
VDD
VM pin
VSS
DO pin
High-Z
High-Z
VSS
Charger connection
External load connection
UVLO detection delay time (tUVLO)
Status
*1
(1)
(2)
(1)
*1. (1): Normal status
(2): UVLO status
Remark The charger is assumed to charge with a constant current.
Figure 14
18
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
2. 2 Active "H"
VUVLO
Battery voltage
VDD
VM pin
VSS
DO pin
High-Z
VSS
Charger connection
External load connection
UVLO detection delay time (tUVLO)
Status
*1
(1)
(2)
(1)
*1. (1): Normal status
(2): UVLO status
Remark The charger is assumed to charge with a constant current.
Figure 15
19
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
5-serial-cell Protection Circuit Examples
Figure 16 and Figure 17 show the 5-serial-cell protection circuit examples used by the S-8239A Series and the S-8225A
Series. Contact our sales representatives when using the circuit other than the following protection circuit examples.
1. Active "L"
EB+
100 Ω
1 MΩ
FET4
CTLD
VDD
CTLC
VC1
CO
VC2
1 kΩ
1 MΩ
0.1 μF 0.1 μF
1 kΩ
*2
FET2
FET3
RVM
330 kΩ
FET1*2
RDOP
VM
DP
S-8239A
Series
DO
VDD
RDO
VINI
1 kΩ
1 kΩ
RVDD
CVDD
1 μF
VSS
SEL2
VC5
CDT
VC6
1 kΩ
0.1 μF 0.1 μF
ZVINI
RVINI
1 MΩ
DO
VC3
S-8225A
Series*1
SEL1
VC4
CCT
100 Ω
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
VSS
CHA−
DIS−
RSENSE
DFET
CFET
Figure 16
2. Active "H"
EB+
100 Ω
1 MΩ
FET4
CTLD
VDD
CTLC
VC1
CO
VC2
1 kΩ
1 MΩ
1 kΩ
FET2
*2
FET3
RDOP
330 kΩ
1 MΩ
FET1*2
RVM
RDO
VM
DP
S-8239A
Series
DO
VDD
FET5
VINI
RVINI
1 MΩ
VSS
1 kΩ
CFET
DFET
CVDD
RSENSE
SEL2
VC5
CDT
VC6
CCT
VSS
1 kΩ
1 μF
0.1 μF 0.1 μF
ZVINI
Figure 17
20
1 kΩ
RVDD
CHA−
DIS−
DO
VC3
S-8225A
Series*1
SEL1
VC4
0.1 μF 0.1 μF
100 Ω
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
0.1 μF
1 kΩ
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Table 7 Constants for External Components
Symbol
RVDD
RVINI
RSENSE
RVM
RDO*3
RDOP
CVDD
Min.
300
1
0
1
−
330
0.022
Typ.
470
−
−
5.1
5.1
510
0.1
Max.
1000
−
−
51
−
2000
1
Unit
Ω
kΩ
mΩ
kΩ
kΩ
kΩ
μF
*1. Refer to the data sheet of the S-8225A Series for the recommended value for external components
of the S-8225A Series.
*2. Use the products with the same model number for FET1 and FET2.
*3. Set up the optimal constant according to the FET in use.
Caution 1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the connection
example. In addition, the connection example and the constants do not guarantee proper operation.
Perform thorough evaluation using the actual application to set the constants.
3. The DP pin should be open.
21
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Precautions
•
The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
•
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
•
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
22
Rev.1.6_00
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Characteristics (Typical Data)
1. Current consumption
1. 2 IOPE vs. VDD
8
8
6
6
IOPE [μA]
IOPE [μA]
1. 1 IOPE vs. Ta
4
2
0
−40 −25
0
+25
Ta [°C]
+50
+75 +85
0
+25
Ta [°C]
+50
+75 +85
4
2
0
0
2
4
VDD [V]
6
8
1. 3 IUVLO vs. Ta
IUVLO [μA]
8
6
4
2
0
−40 −25
2. Overcurrent detection / release voltage, UVLO function and delay times
2. 2 VDIOV2 vs. Ta
2. 1 VDIOV1 vs. Ta
VDIOV2 = 0.4 V
0.10
0.6
0.09
0.5
VDIOV2 [V]
VDIOV1 [V]
VDIOV1 = 0.08 V
0.08
0.07
0.06
−40 −25
0
25
Ta [°C]
50
0
25
Ta [°C]
50
+75 +85
0
+25
Ta [°C]
+50
+75 +85
1.8
1.4
1.5
1.3
VRIOV [V]
VDIOV3 [V]
−40 −25
2. 4 VRIOV vs. Ta
1.5
1.2
1.1
1.0
0.9
0.3
0.2
+75 +85
2. 3 VDIOV3 vs. Ta
0.4
−40 −25
0
25
Ta [°C]
50
+75 +85
1.2
0.9
0.6
−40 −25
23
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
2. 6 VDIOV2 vs. VDD
2. 5 VDIOV1 vs. VDD
VDIOV2 = 0.4 V
0.10
0.6
0.09
0.5
VDIOV2 [V]
VDIOV1 [V]
VDIOV1 = 0.08 V
0.08
0.07
0.06
0.4
0.3
0.2
2
3
4
5
6
7
2
8
3
4
5
VDD [V]
6
7
8
4
5
VDD [V]
6
7
8
VDD [V]
2. 7 VDIOV3 vs. VDD
2. 8 VRIOV vs. VDD
1.5
1.8
1.4
1.5
VRIOV [V]
VDIOV3 [V]
1.3
1.2
1.1
1.0
0.9
1.2
0.9
0.6
2
3
4
5
6
7
2
8
3
VDD [V]
2. 10 tDIOV2 vs. Ta
2. 9 tDIOV1 vs. Ta
tDIOV2 = 1.12 ms
1.6
1.4
1.4
tDIOV2 [ms]
tDIOV1 [s]
tDIOV1 = 1150 ms
1.6
1.2
1.0
0.8
−40 −25
+25
Ta [°C]
0
+50
+75 +85
2. 11 tDIOV3 vs. Ta
1.2
1.0
0.8
−40 −25
0
+25
Ta [°C]
+50
+75 +85
2. 12 tDIOV1 vs. VDD
400
1.6
340
1.4
280
220
160
24
tDIOV1 [s]
tDIOV3 [μs]
tDIOV1 = 1150 ms
−40 −25
0
+25
Ta [°C]
+50
+75 +85
1.2
1.0
0.8
2
3
4
5
VDD [V]
6
7
8
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
2. 14 tDIOV3 vs. VDD
2. 13 tDIOV2 vs. VDD
1.6
400
1.4
340
tDIOV3 [μs]
tDIOV2 [ms]
tDIOV2 = 1.12 ms
1.2
1.0
0.8
280
220
160
2
3
4
5
6
7
2
8
3
4
VDD [V]
2. 15 VUVLO vs. Ta
7
8
6.0
5.5
tUVLO [s]
2.1
VUVLO [V]
6
2. 16 tUVLO vs. VDD
2.2
2.0
1.9
1.8
5
VDD [V]
5.0
4.5
4.0
3.5
−40 −25
0
25
Ta [°C]
50
+75 +85
3.0
1.5
1.6
1.7
1.8
VDD [V]
1.9
2.0
3. Output Resistance
3. 1 RDOL vs. Ta
10.0
RDOL [kΩ]
8.0
6.0
4.0
2.0
0.0
−40 −25
0
+25
Ta [°C]
+50
+75 +85
25
OVERCURRENT MONITORING IC FOR MULTI-SERIAL-CELL PACK
S-8239A Series
Rev.1.6_00
Marking Specification
1. SOT-23-6
Top view
6
5
(1) to (3):
(4):
4
(1) (2) (3) (4)
1
2
3
Product name vs. Product code
Product Name
S-8239AAA-M6T1U
S-8239AAB-M6T1U
S-8239AAC-M6T1U
S-8239AAD-M6T1U
S-8239AAE-M6T1U
S-8239AAF-M6T1U
S-8239AAG-M6T1U
S-8239AAH-M6T1U
S-8239AAI-M6T1U
S-8239AAJ-M6T1U
S-8239AAK-M6T1U
S-8239AAL-M6T1U
S-8239AAM-M6T1U
S-8239AAN-M6T1U
S-8239AAO-M6T1U
S-8239AAP-M6T1U
26
Product Code
(1)
(2)
(3)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Product code (Refer to Product name vs. Product code)
Lot number
2.9±0.2
1.9±0.2
6
0.95
4
5
1
2
3
+0.1
0.15 -0.05
0.95
0.35±0.15
No. MP006-A-P-SD-2.1
TITLE
SOT236-A-PKG Dimensions
No.
MP006-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
ø1.5 -0
+0.2
ø1.0 -0
2.0±0.05
0.25±0.1
4.0±0.1
1.4±0.2
3.2±0.2
3 2 1
4 5 6
Feed direction
No. MP006-A-C-SD-3.1
TITLE
SOT236-A-Carrier Tape
No.
MP006-A-C-SD-3.1
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP006-A-R-SD-2.1
TITLE
SOT236-A-Reel
No.
MP006-A-R-SD-2.1
ANGLE
QTY
UNIT
mm
ABLIC Inc.
3,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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