TC58NVG1S3ETAI0

TC58NVG1S3ETAI0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 2 GBIT (256M × 8 BIT) CMOS NAND E PROM DESCRIPTION The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG1S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES • Organization Memory cell array Register Page size Block size x8 2112 × 128K × 8 2112 × 8 2112 bytes (128K + 4K) bytes • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read • Mode control Serial input/output Command control • Number of valid blocks Min 2008 blocks Max 2048 blocks • Power supply VCC = 2.7V to 3.6V • Access time Cell array to register Serial Read Cycle 25 μs max 25 ns min (CL=100pF) • Program/Erase time Auto Page Program Auto Block Erase 300 μs/page typ. 2.5 ms/block typ. Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 30 mA max. 30 mA max 30 mA max 50 μA max • • Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) 1 2012-09-01C TC58NVG1S3ETAI0 PIN ASSIGNMENT (TOP VIEW) TC58NVG1S3ETAI0 ×8 NC NC NC NC NC NC RY / BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC ×8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC PIN NAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY/BY Ready/Busy VCC Power supply VSS Ground 2 2012-09-01C TC58NVG1S3ETAI0 BLOCK DIAGRAM VCC VSS Status register Address register I/O1 Column buffer I/O Control circuit to Column decoder I/O8 Command register Data register Row address buffer decoder CE CLE ALE Logic control WE Control circuit RE WP Row address decoder Sense amp Memory cell array RY / BY RY / BY HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VCC Power Supply Voltage −0.6 to 4.6 V VIN Input Voltage −0.6 to 4.6 V VI/O Input /Output Voltage PD Power Dissipation 0.3 W TSOLDER Soldering Temperature (10 s) 260 °C TSTG Storage Temperature −55 to 150 °C TOPR Operating Temperature -40 to 85 °C −0.6 to VCC + 0.3 (≤ 4.6 V) V CAPACITANCE *(Ta = 25°C, f = 1 MHz) SYMB0L PARAMETER CONDITION MIN MAX UNIT CIN Input VIN = 0 V ⎯ 10 pF COUT Output VOUT = 0 V ⎯ 10 pF * This parameter is periodically sampled and is not tested for every device. 3 2012-09-01C TC58NVG1S3ETAI0 VALID BLOCKS SYMBOL NVB NOTE: PARAMETER Number of Valid Blocks MIN TYP. MAX UNIT 2008 ⎯ 2048 Blocks The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT 2.7 ⎯ 3.6 V VCC Power Supply Voltage VIH High Level input Voltage 2.7 V ≤ VCC ≤ 3.6 V Vcc x 0.8 ⎯ VCC + 0.3 V VIL Low Level Input Voltage 2.7 V ≤ VCC ≤ 3.6 V −0.3* ⎯ Vcc x 0.2 V −2 V (pulse width lower than 20 ns) * DC CHARACTERISTICS (Ta = -40 to 85℃, VCC = 2.7 to 3.6V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current VIN = 0 V to VCC ⎯ ⎯ ±10 μA ILO Output Leakage Current VOUT = 0 V to VCC ⎯ ⎯ ±10 μA ICCO1 Serial Read Current CE = VIL, IOUT = 0 mA, tcycle = 25 ns ⎯ ⎯ 30 mA ICCO2 Programming Current ⎯ ⎯ ⎯ 30 mA ICCO3 Erasing Current ⎯ ⎯ ⎯ 30 mA ICCS Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC ⎯ ⎯ 50 μA VOH High Level Output Voltage IOH = −0.1 mA Vcc – 0.2 ⎯ ⎯ V VOL Low Level Output Voltage IOL = 0.1 mA ⎯ ⎯ 0.2 V IOL ( RY / BY ) Output current of RY / BY VOL = 0.2 V pin ⎯ 4 ⎯ mA 4 2012-09-01C TC58NVG1S3ETAI0 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85℃, VCC = 2.7 to 3.6V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 12 ⎯ ns tCLH CLE Hold Time 5 ⎯ ns tCS CE Setup Time 20 ⎯ ns tCH CE Hold Time 5 ⎯ ns tWP Write Pulse Width 12 ⎯ ns tALS ALE Setup Time 12 ⎯ ns tALH ALE Hold Time 5 ⎯ ns tDS Data Setup Time 12 ⎯ ns tDH Data Hold Time 5 ⎯ ns tWC Write Cycle Time 25 ⎯ ns tWH WE High Hold Time 10 ⎯ ns tWW WP High to WE Low 100 ⎯ ns tRR Ready to RE Falling Edge 20 ⎯ ns tRW Ready to WE Falling Edge 20 ⎯ ns tRP Read Pulse Width 12 ⎯ ns tRC Read Cycle Time 25 ⎯ ns tREA RE Access Time ⎯ 20 ns tCEA CE Access Time ⎯ 25 ns tCLR CLE Low to RE Low 10 ⎯ ns tAR ALE Low to RE Low 10 ⎯ ns tRHOH RE High to Output Hold Time 22 ⎯ ns tRLOH RE Low to Output Hold Time 5 ⎯ ns tRHZ RE High to Output High Impedance ⎯ 60 ns tCHZ CE High to Output High Impedance ⎯ 20 ns tCSD CE High to ALE or CLE Don’t Care 0 ⎯ ns tREH RE High Hold Time 10 ⎯ ns tIR Output-High-impedance-to- RE Falling Edge 0 ⎯ ns tRHW RE High to WE Low 30 ⎯ ns tWHC WE High to CE Low 30 ⎯ ns tWHR WE High to RE Low 60 ⎯ ns tR Memory Cell Array to Starting Address ⎯ 25 μs tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) ⎯ 30 μs tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) ⎯ 35 μs tWB WE High to Busy ⎯ 100 ns tRST Device Reset Time (Ready/Read/Program/Erase) ⎯ 6/6/10/500 μs *1: tCLS and tALS can not be shorter than tWP *2: tCS should be longer than tWP + 8ns. 5 2012-09-01C TC58NVG1S3ETAI0 AC TEST CONDITIONS CONDITION PARAMETER VCC: 2.7 to 3.6V VCC − 0.2 V, 0.2 V Input level Input pulse rise and fall time 3 ns Input comparison level Vcc / 2 Output data comparison level Vcc / 2 CL (100 pF) + 1 TTL Output load Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin. (Refer to Application Note (9) toward the end of this document.) PROGRAMMING AND ERASING CHARACTERISTICS (Ta = -40 to 85℃, VCC = 2.7 to 3.6V) SYMBOL PARAMETER MIN TYP. MAX UNIT tPROG Average Programming Time ⎯ 300 700 μs tDCBSYW1 Data Cache Busy Time in Write Cache (following 11h) ⎯ ⎯ 10 μs tDCBSYW2 Data Cache Busy Time in Write Cache (following 15h) ⎯ ⎯ 700 μs N Number of Partial Program Cycles in the Same Page ⎯ ⎯ 4 tBERASE Block Erasing Time ⎯ 2.5 10 NOTES (2) (1) ms (1) Refer to Application Note (12) toward the end of this document. (2) tDCBSYW2 depends on the timing between internal programming time and data in time. Data Output When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH (22ns MIN). On this condition, waveforms look like normal serial read mode. When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling edge of /WE, and waveforms look like Extended Data Output Mode. 6 2012-09-01C TC58NVG1S3ETAI0 TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time Hold Time WE tDS tDH I/O : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCLH tCS tCH CE tWP WE tALS tALH ALE tDS tDH I/O : VIH or VIL 7 2012-09-01C TC58NVG1S3ETAI0 Address Input Cycle Timing Diagram tCLS tCLH CLE tCH tCS tWC tWC tCH tCS CE tWP tWH tWP tWH tWP tWH tWP tWH tWP WE tALS tALH ALE tDS I/O tDH tDS CA0 to 7 tDH tDS CA8 to 11 tDH tDS PA0 to 7 tDH tDS PA8 to 15 tDH PA16 : VIH or VIL Data Input Cycle Timing Diagram tCLS tCLH CLE tCH tCS tCS tCH CE tALS tALH tWC ALE tWP tWH tWP tWP WE tDS I/O tDH tDS DIN0 tDH DIN1 8 tDS tDH DIN2111 2012-09-01C TC58NVG1S3ETAI0 Serial Read Cycle Timing Diagram tRC CE tRP tREH tRP tCHZ tRP RE tRHZ tRHOH tREA tRHZ tRHZ tRHOH tREA tREA tCEA tRHOH tCEA I/O tRR RY / BY : VIH or VIL Status Read Cycle Timing Diagram tCLR CLE tCLS tCLH tCS CE tWP tCH WE tCEA tCHZ tWHC tWHR RE tRHOH tDS tDH tIR tREA I/O tRHZ Status output 70h* RY / BY : VIH or VIL *: 70h represents the hexadecimal number 9 2012-09-01C TC58NVG1S3ETAI0 Read Cycle Timing Diagram tCLR CLE tCLS tCLH tCS tCH tCLS tCS tCLH tCH CE tWC WE tALH tALS tALH tALS ALE tR tRC tWB RE tDS tDH I/O tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 to 7 00h CA8 to 11 PA0 to 7 PA8 to 15 tDS tDH PA16 tCEA tRR tREA D OUT 30h N DOUT N+1 Data out from Col. Add. N Col. Add. N RY / BY Read Cycle Timing Diagram: When Interrupted by CE tCLR CLE tCLS tCLH tCS tCH tCLS tCS tCLH tCH CE tCSD tWC WE tALH tALS tALH tALS ALE tR tCHZ tWB RE tRHZ tDS tDH I/O tRC 00h tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 Col. Add. N PA16 tDS tDH 30h tRR tCEA tREA D OUT N tRHOH DOUT N+1 Col. Add. N RY / BY 10 2012-09-01C TC58NVG1S3ETAI0 Read Cycle with Data Cache Timing Diagram (1/2) tCLR CLE tCLS tCLH tCLS tCLH tCH tCLS tCLH tCH tCS tCLR tCLS tCLH tCH tCS tCS tALH tALS tRW tCH tCS CE tWC WE tALH tALS tCEA tCEA ALE tR tWB RE tDS tDH I/O 00h tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 to 7 CA8 to 11 Column address N* PA0 to 7 PA8 to 15 PA16 tDCBSYR1 tRC tDCBSYR1 tWB tDS tDH tDS tDH 30h 31h Page address M tWB tRR tDS tDH tREA DOUT 0 DOUT 1 31h DOUT Col. Add. 0 * The column address will be reset to 0 by the 31h command input. tREA DOUT 0 Page address M+1 Page address M RY / BY tRR Col. Add. 0 1 Continues to 1 11 of next page 2012-09-01C TC58NVG1S3ETAI0 Read Cycle with Data Cache Timing Diagram (2/2) tCLR CLE tCLS tCLR tCLH tCLS tCH tCLR tCLH tCLS tCH tCS tCLH tCH tCS tCS CE WE tCEA tCEA tCEA ALE tDCBSYR1 tDCBSYR1 tRC tWB RE tDS tDH I/O DOUT tRC tDCBSYR1 tWB tRR 31h tDS tDH tREA DOUT 0 DOUT 1 DOUT tRC tWB tRR DOUT 0 31h tDS tDH tREA DOUT 1 Page address M+2 Page address M + 1 RY / BY Col. Add. 0 Col. Add. 0 1 DOUT 3Fh tRR tREA DOUT 0 DOUT 1 DOUT Page address M + x Col. Add. 0 Make sure to terminate the operation with 3Fh command. Continues from 1 of last page 12 2012-09-01C TC58NVG1S3ETAI0 Column Address Change in Read Cycle Timing Diagram (1/2) tCLR CLE tCLS tCLH tCS tCLS tCLH tCH tCH tCS CE tWC tCEA WE tALH tALS tALH tALS ALE tRC tR tWB RE I/O tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 00h CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 PA16 Page address P tDS tDH 30h tRR tREA DOUT DOUT A A+1 DOUT A+N Page address P RY / BY Column address A 1 Continues from 1 13 of next page 2012-09-01C TC58NVG1S3ETAI0 Column Address Change in Read Cycle Timing Diagram (2/2) tCLR CLE tCLS tCLH tCS tCH tCLS tCS tCLH tCH CE tRHW tWC tCEA WE tALH tALS tALH tALS ALE tWHR tRC RE tDS tDH tDS tDH tDS tDH tDS tDH tREA tIR DOUT A+N I/O 05h CA0 to 7 CA8 to 11 E0h Column address B DOUT B DOUT B+1 DOUT B + N’ Page address P RY / BY Column address B 1 Continues from 1 of last page 14 2012-09-01C TC58NVG1S3ETAI0 Data Output Timing Diagram CLE tCLS tCLH tCS tCH CE WE tALH ALE tRC tRP tCHZ tREH tRP tRP tRHZ RE tREA tCEA tREA I/O Dout tRR tREA tDS tDH tRLOH tRLOH Command Dout tRHOH tRHOH RY / BY 15 2012-09-01C TC58NVG1S3ETAI0 Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tALS tPROG tALS tWB ALE RE I/O tDS tDS tDS tDH tDS tDH 80h CA0 to 7 tDH tDH CA8 to 11 PA0 to 7 PA8 PA16 to 15 DINN DIN N+1 DINM 10h 70h Status output Column address N RY / BY : Do not input data while data is being output. : VIH or VIL *) M: up to 2111 (byte input data for ×8 device). 16 2012-09-01C TC58NVG1S3ETAI0 Auto-Program Operation with Data Cache Timing Diagram (1/3) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tDCBSYW2 tALS tWB tALS ALE RE I/O tDS tDS tDH tDS tDH 80h CA0 to 7 tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN tDH DIN N+1 15h 80h CA0 to 7 DIN2111 RY / BY : Do not input data while data is being output. : VIH or VIL 1 CA0 to CA11 is 0 in this diagram. Continues to 17 1 of next page 2012-09-01C TC58NVG1S3ETAI0 Auto-Program Operation with Data Cache Timing Diagram (2/3) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tALS tDCBSYW2 tALS tWB ALE RE tDS tDS tDH tDS tDH 80h CA0 to 7 I/O tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN tDH DIN N+1 15h 80h CA0 to 7 DIN2111 RY / BY Repeat a max of 62 times (in order to program pages 1 to 62 of a block). 1 Continued from 1 2 of last page : Do not input data while data is being output. : VIH or VIL 18 2012-09-01C TC58NVG1S3ETAI0 Auto-Program Operation with Data Cache Timing Diagram (3/3) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tPROG (*1) tALS tALS tWB ALE RE tDS tDS tDS tDH tDS tDH 80h CA0 to 7 I/O tDH tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN DIN N+1 10h 70h Status DIN2111 RY / BY : Do not input data while data is being output. : VIH or VIL 2 Continued from 2 of last page (*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following equation. tPROG = tPROG of the last page + tPROG of the previous page − A A = (command input cycle + address input cycle + data input cycle time of the last page) If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max. (Note) Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next operation. 19 2012-09-01C TC58NVG1S3ETAI0 Multi-Page Program Operation with Data Cache Timing Diagram (1/4) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tALS tDCBSYW1 tALS tWB ALE RE tDS tDS tDH I/O 80h tDS tDH CA0 to 7 tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN tDH DIN N+1 Page Address M District-0 RY / BY 11h 81h CA0 to 7 DIN2111 : Do not input data while data is being output. : VIH or VIL 1 Continues to 20 1 of next page 2012-09-01C TC58NVG1S3ETAI0 Multi-Page Program Operation with Data Cache Timing Diagram (2/4) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tDCBSYW2 tALS tWB tALS ALE RE tDS tDS tDH tDS tDH 81h CA0 to 7 I/O tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN tDH DIN N+1 Page Address M District-1 15h 80h CA0 to 7 DIN2111 RY / BY Repeat a max of 63 times (in order to program pages 0 to 62 of a block). 1 Continued from 1 2 of last page : Do not input data while data is being output. : VIH or VIL 21 2012-09-01C TC58NVG1S3ETAI0 Multi-Page Program Operation with Data Cache Timing Diagram (3/4) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tALS tDCBSYW1 tALS tWB ALE RE tDS I/O tDS tDH tDS tDH 80h CA0 to 7 tDS tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN tDH DIN N+1 Page Address M+n District-0 RY / BY 11h 81h CA0 to 7 DIN2111 : Do not input data while data is being output. : VIH or VIL 3 2 Continues to 22 3 of next page 2012-09-01C TC58NVG1S3ETAI0 Multi-Page Program Operation with Data Cache Timing Diagram (4/4) tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tALS tPROG (*1) tALS tWB ALE RE tDS tDS tDS tDH tDS tDH 81h CA0 to 7 I/O tDH tDH CA8 to 11 PA0 to 7 PA8 to 15 PA16 DINN DIN N+1 Page Address M+n District-1 RY / BY 10h 71h DIN2111 : Do not input data while data is being output. : VIH or VIL 3 Continued from 3 of last page (*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following equation. tPROG = tPROG of the last page + tPROG of the previous page − A A = (command input cycle + address input cycle + data input cycle time of the last page) If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max. (Note) Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next operation. 23 2012-09-01C Status TC58NVG1S3ETAI0 Auto Block Erase Timing Diagram CLE tCLS tCLH tCS tCLS CE WE tALH tALS tWB tBERASE ALE RE tDS tDH I/O RY / BY 60h Auto Block Erase Setup command : VIH or VIL PA0 to 7 PA8 to 15 PA16 D0h Erase Start command Status output 70h Busy Status Read command : Do not input data while data is being output. 24 2012-09-01C TC58NVG1S3ETAI0 Multi Block Erase Timing Diagram CLE tCLS tCLH tCS tCLS CE WE tALH tALS tWB tBERASE ALE RE tDS tDH I/O1 to 60h PA0 to 7 PA8 to 15 PA16 D0h 71h Status output RY/BY Auto Block Erase Setup command Busy Status Read command Repeat 2 times (District-0,1) : VIH or VIL : Do not input data while data is being output. 25 2012-09-01C TC58NVG1S3ETAI0 ID Read Operation Timing Diagram tCLS CLE tCLS tCS tCS tCH tCEA CE tCH WE tALS tALH tALH tAR ALE RE tDH tDS I/O tREA tREA tREA 90h 00h 98h DAh ID Read command Address 00 Maker code Device code tREA See Table 5 tREA See Table 5 See Table 5 : VIH or VIL 26 2012-09-01C TC58NVG1S3ETAI0 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading address information into the internal address register. Address information is latched into the address register from the I/O port on the rising edge of WE while ALE is High. Chip Enable: CE The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes High. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with an appropriate resister. If RY / BY signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee. 27 2012-09-01C TC58NVG1S3ETAI0 Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 Data Cache 2048 64 Page Buffer 2048 64 I/O8 A page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112 bytes 1 block = 2112 bytes × 64 pages = (128K + 4K) bytes Capacity = 2112 bytes × 64pages × 2048 blocks 64 Pages=1 block 131072 pages 2048 blocks 8I/O 2112 An address is read in via the I/O port over five consecutive clock cycles, as shown in Table 1. Table 1. Addressing I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 L L L L CA11 CA10 CA9 CA8 Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 L L L L L L L PA16 First cycle Second cycle Fifth cycle 28 CA0 to CA11: Column address PA0 to PA16: Page address PA6 to PA16: Block address PA0 to PA5: NAND address in block 2012-09-01C TC58NVG1S3ETAI0 Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic Table CLE ALE CE Command Input H L Data Input L Address input WE *1 RE WP L H * L L H H L H L H * Serial Data Output L L L H During Program (Busy) * * * * * H During Erase (Busy) * * * * * H * * H * * * * * L H (*2) H (*2) * Program, Erase Inhibit * * * * * L Standby * * H * * 0 V/VCC * During Read (Busy) H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit *2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or read to device. Reset or Status Read command can be input during Read Busy. 29 2012-09-01C TC58NVG1S3ETAI0 Table 3. Command table (HEX) First Cycle Second Cycle Serial Data Input 80 ⎯ Read 00 30 Column Address Change in Serial Data Output 05 E0 Read with Data Cache 31 ⎯ Read Start for Last Page in Read Cycle with Data Cache 3F ⎯ Auto Page Program 80 10 Column Address Change in Serial Data Input 85 ⎯ Auto Program with Data Cache 80 15 80 11 81 15 81 10 Read for Page Copy (2) with Data Out 00 3A Auto Program with Data Cache during Page Copy (2) 8C 15 Auto Program for last page during Page Copy (2) 8C 10 Auto Block Erase 60 D0 ID Read 90 ⎯ Status Read 70 ⎯ { Status Read for Multi-Page Program or Multi Block Erase 71 ⎯ { Reset FF ⎯ { Multi Page Program Acceptable while Busy HEX data bit assignment Serial Data Input: 80h (Example) 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 I/O1 Table 4. Read mode operation states CLE ALE CE WE RE I/O1 to I/O8 Power Output select L L L H L Data output Active Output Deselect L L L H H High impedance Active H: VIH, L: VIL 30 2012-09-01C TC58NVG1S3ETAI0 DEVICE OPERATION Read Mode Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and the block diagram (Refer to the detailed timing chart.). CLE CE WE ALE RE RY / BY Column Address M Busy Page Address N 00h I/O tR 30h M+1 M M+2 Page Address N Start-address input M m Data Cache Page Buffer Select page N Cell array I/O1 to 8: m = 2111 A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Random Column Address Change in Read Cycle CLE CE WE ALE RE RY / BY Busy tR Col. M I/O 30h 00h Col. M Page N M+1 M+2 M+3 Page N Start from Col. M Start-address input M M E0h 05h Col. M’ M’ M’+1 M’+2 M’+3 M’+4 Page N Start from Col. M’ During the serial data output from the Data Cache, the column address can be changed by inputting a new column address using the 05h and E0h commands. The data is read out in serial starting at the new column address. Random Column Address Change operation can be done multiple times within the same page. M’ Select page N 31 2012-09-01C TC58NVG1S3ETAI0 Read Operation with Read Cache The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be started from the beginning. CLE CE WE ALE RE RY / BY tR tDCBSYR1 1 I/O 00h 31h 30h Col. M Data Cache Page Buffer 2 Page N 0 Column 0 tDCBSYR1 3 4 1 2 31h 2111 3 6 1 2 Page N Page N 1 3 2111 3Fh 0 1 7 2 3 2111 Page Address N + 2 Page N + 2 Page N + 1 Page N 1 2 Page Address N + 1 Page Address N Page N + 1 3 4 Cell Array 0 tDCBSYR1 5 Page N + 2 5 7 6 Page N + 1 3 Page N + 2 5 3Fh & RE clock 30h 31h & RE clock 31h & RE clock If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory cell to data register) will be reduced. 1 Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max. 2 After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time period can be detected by Ready/Busy signal. 3 Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously. 4 The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time. 5 Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously 6 The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time. 7 Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately after the completion of serial data out. 32 2012-09-01C TC58NVG1S3ETAI0 Multi Page Read Operation The device has a Multi Page Read operation and Multi Page Read with Data Cache operation. (1) Multi Page Read without Data Cache The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each district has to be selected. Command input (3 cycle) 60 Address input (3 cycle) 60 Address input Page Address PA0 to PA16 (District 1) Page Address PA0 to PA16 (District 0) A 30 tR A RY/BY A Command input (5 cycle) 00 Address input (2 cycle) 05 Column + Page Address CA0 to CA11, PA0 to PA16 (District 0) RY/BY E0 Column Address CA0 to CA11 (District 0) Data output B (District 0) B A B Command input (5 cycle) 00 Address input 05 Column + Page Address CA0 to CA11, PA0 to PA16 (District 1) RY/BY Address input Address input E0 Column Address CA0 to CA11 (District 1) Data output (District 1) B District 0 District 1 Reading Selected page Selected page The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of WE in the 30h command input cycle (after the 2 Districts address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. 33 2012-09-01C TC58NVG1S3ETAI0 (2) Multi Page Read with Data Cache When the block address changes (increments) this sequenced has to be started from the beginning. The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each district has to be selected. Command input 60 Address input Address input 60 Page Address PA0 to PA16 (Page n0 ; District 1) Page Address PA0 to PA16 (Page m0 ; District 0) A 30 tR A RY/BY Command input A RY/BY A 31 Address input 00 05 Column + Page Address CA0 to CA11, PA0 to PA16 (Page m0 ; District 0) tDCBSYR1 Address input E0 Column Address CA0 to CA11 (District 0) Data output B (District 0) B Command input B Address input 00 05 Column + Page Address CA0 to CA11, PA0 to PA16 (Page n0 ; District 1) RY/BY Address input Data output C C C Return to A Repeat a max of 63 times 3F Address input 00 05 Column + Page Address CA0 to CA11, PA0 to PA16 (Page m63 ; District 0) tDCBSYR1 Address input E0 Column Address CA0 to CA11 (District 0) Data output D 00 Address input 05 Column + Page Address CA0 to CA11, PA0 to PA16 (Page n63 ; District 1) RY/BY D (District 0) Command input D C (District 1) B Command input RY/BY E0 Column Address CA0 to CA11 (District 1) Address input Column Address CA0 to CA11 (District 1) E0 Data output (District 1) D 34 2012-09-01C TC58NVG1S3ETAI0 (3) Notes (a) Internal addressing in relation with the Districts • • • To use Multi Page Read operation, the internal addressing should be considered in relation with the District. The device consists from 2 Districts. Each District consists from 1024 erase blocks. The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 (b) Address input restriction for the Multi Page Read operation There are following restrictions in using Multi Page Read; (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example; (60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30) (60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (60) [District 0] (60) [District 1] (30) (60) [District 1] (60) [District 0] (30) It requires no mutual address relation between the selected blocks from each District. (c) WP signal Make sure WP is held to High level when Multi Page Read operation is performed 35 2012-09-01C TC58NVG1S3ETAI0 Auto Page Program Operation The device carries out an Automatic Page Program operation when it receives a "10h" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) CLE CE WE ALE RE RY/BY Din Din Din 80h I/O Col. M Page P Din 70h 10h Status Out Data Data input Program The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the rising edge of WE following input of the “10h” command. After programming, the programmed data is transferred back to the Page Buffer to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Read& verification Selected page Random Column Address Change in Auto Page Program Operation The column address can be changed by the 85h command during the data input sequence of the Auto Page Program operation. Two address input cycles after the 85h command are recognized as a new column address for the data input. After the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. The Random Column Address Change operation can be repeated multiple times within the same page. 80h Din Col. M Din Din Din 85h Din Col. M’ Page N Col. M Din Din Din 10h 70h Status Busy Col. M’ Data input Program Reading & verification Selected page 36 2012-09-01C TC58NVG1S3ETAI0 Multi Page Program The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data input is shown bellow. (Refer to the detailed timing chart.) Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when any of the pages fails. Limitation in addressing with Multi Page Program is shown below. Multi Page Program tDCBSYW1 tPROG R/ B ”0” I/O0~7 80h Address & Data Input CA0~CA11 PA0~PA5 PA6 PA7~PA16 11h 81h Note : Valid : Valid’ : District0’ : Valid’ Address & Data Input CA0~CA11 PA0~PA5 PA6 PA7~PA16 10h 70h : Valid : Valid : District1 : Valid I/O0 Pass ”1” Fail NOTE: Any command between 11h and 81h is prohibited except 70h and FFh. 80h 11h 81h 10h Data Input Plane 0 (1024 Block) Plane 1 (1024 Block) Block 0 Block 1 Block 2 Block 3 Block 2044 Block 2045 Block 2046 Block 2047 37 2012-09-01C TC58NVG1S3ETAI0 Auto Page Program Operation with Data Cache The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this sequenced has to be started from the beginning. CLE CE WE ALE RE RY / BY tDCBSYW2 I/O 80h Add Add Add Add Add Din Din Page N Data for Page N Data Cache Page Buffer 1 Din 1 15h 70h Add Add Add Add Add 80h 2 Din Din Page N + 1 Status Output 2 tPROG (NOTE) tDCBSYW2 3 Din 15h 3 70h 4 80h 4 Page N + P Status Output 5 Data for Page N + 1 Add Add Add Add Add Din Din Din 5 10h 70h 6 Status Output Data for Page N + P Data for Page N + 1 Data for Page N 3 Cell Array Page N 5 6 Page N + 1 Page N + P − 1 Page N + P Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache 1 Data for Page N is input to Data Cache. 2 Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (tDCBSYW2). 3 Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache. 4 By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + 1 (tDCBSYW2). 5 Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed. 6 The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed. NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following; tPROG = tPROG for the last page + tPROG of the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page) 38 2012-09-01C TC58NVG1S3ETAI0 Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation. z I/O1 : Pass/fail of the current page program operation. z I/O2 : Pass/fail of the previous page program operation. The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions. z Status on I/O1: Page Buffer Ready/Busy is Ready State. The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command z Status on I/O2: Data Cache Read/Busy is Ready State. The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command. Example) I/O2 I/O1 80h…15h => => Invalid Invalid 70h Status Out Page 1 Page 1 Invalid 80h…15h 70h Status Out Page N − 2 Invalid Page 1 Page 2 70h Status Out 80h…15h 70h Status Out Page N − 1 Page 2 Page N − 1 Page N invalid invalid 80h…10h 70h Status Out 70h Status Out Page N RY/BY pin Data Cache Busy Page Buffer Busy Page 1 Page 2 Page N − 1 Page N If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2 39 2012-09-01C TC58NVG1S3ETAI0 Multi Page Program with Data Cache The device has a Multi Page Program with Data Cache operation, which enables even higher speed program operation compared to Auto Page Program with Data Cache as shown below. When the block address changes (increments) this sequenced has to be started from the beginning. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) Data input command Dummy for multi-page Program program command Data input command 80 11 Address Data input 0 to 2111 input (District 0) Program with Data Cache command 81 15 Address Data input 0 to 2111 input (District 1) Data input command 80 Dummy Program command 11 Address Data input 0 to 2111 input (District 0) Data input command for multi-page program Auto Page Program command 81 10 Address Data input 0 to 2111 input (District1) RY/BY After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”. District 0 Program District 1 Reading & verification Selected page The data is transferred (programmed) from the page buffer to the selected page on the rising edge of /WE following input of the “15h” or “10h” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. 40 2012-09-01C TC58NVG1S3ETAI0 Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation total 64 times with incrementing the page address in the blocks, and then input the last page data of the blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command sequence. In this full sequence, the command sequence is following. 80 11 81 15 80 11 81 15 63th 80 11 81 15 64th 80 11 81 10 1st After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read command. Pass 10 or15 71 I/O Status Read command Fail RY/BY The 71h command Status description is as below. STATUS OUTPUT I/O1 Chip Status1 : Pass/Fail Pass: 0 Fail: 1 I/O2 District 0 Chip Status1 : Pass/Fail Pass: 0 Fail: 1 I/O3 District 1 Chip Status1 : Pass/Fail Pass: 0 Fail: 1 I/O4 District 0 Chip Status2 : Pass/Fail Pass: 0 Fail: 1 I/O5 District 1 Chip Status2 : Pass/Fail Pass: 0 Fail: 1 I/O6 Ready/Busy Ready: 1 Busy: 0 I/O7 Data Cache Ready/Busy Ready: 1 Busy: 0 I/O8 Write Protect Protect: 0 I/O1 describes Pass/Fail condition of district 0 and 1(OR data of I/O2 and I/O3). If one of the districts fails during multi page program operation, it shows “Fail”. I/O2 to 5 shows the Pass/Fail condition of each district. For details on “Chip Status1” and “Chip Status2”, refer to section “Status Read”. Not Protect: 1 41 2012-09-01C TC58NVG1S3ETAI0 Internal addressing in relation with the Districts To use Multi Page Program operation, the internal addressing should be considered in relation with the District. • The device consists from 2 Districts. • Each District consists from 1024 erase blocks. • The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Page Program with Data Cache operation There are following restrictions in using Multi Page Program with Data Cache; (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example; (80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (15 or 10) (80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (15 or 10) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (80) [District 0] (11) (81) [District 1] (15 or 10) (80) [District 1] (11) (81) [District 0] (15 or 10) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Program with Data Cache operation (Restriction) The operation has to be terminated with “10h” command. Once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for Status Read command and reset command. 42 2012-09-01C TC58NVG1S3ETAI0 Page Copy (2) By using Page Copy (2), data in a page can be copied to another page after the data has been read out. When the block address changes (increments) this sequenced has to be started from the beginning. Command input 00 2 Address input 30 Address CA0 to CA11, PA0 to PA16 (Page N) Data output 3 8C Col = 0 start 1 Address input Data input Address CA0 to CA11, PA0 to PA16 (Page M) 15 00 When changing data, changed data is input. 4 Address input 3A Address CA0 to CA11, PA0 to PA16 (Page N+P1) Data output A Col = 0 start 5 A RY/BY tDCBSYW2 tR 1 Data for Page N 2 Data for Page N 3 Data for Page M tDCBSYR2 4 5 Data for Page N + P1 Data Cache Page Buffer Cell Array Page M Page N + P1 Page N Page Copy (2) operation is as following. 1 Data for Page N is transferred to the Data Cache. 2 Data for Page N is read out. 3 Copy Page address M is input and if the data needs to be changed, changed data is input. 4 Data Cache for Page M is transferred to the Page Buffer. 5 After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is being programmed. 43 2012-09-01C TC58NVG1S3ETAI0 Command input A 6 Address input 8C Address CA0 to CA11, PA0 to PA16 (Page M+R1) Data input 15 Address input 00 3A Address CA0 to CA11, PA0 to PA16 (Page N+P2) When changing data, changed data is input. 7 RY / BY Data output 00 Address input 8 Data output 3A Address CA0 to CA11, PA0 to PA16 (Page N+Pn) Col = 0 start B Col = 0 start 9 A B tDCBSYW2 6 Data for Page M + R1 7 Data for Page M + R1 tDCBSYR2 8 tDCBSYR2 9 Data for Page N + P2 Data for Page N + Pn Data Cache Page Buffer Page M + Rn − 1 Page M + R1 Cell Array Page M + Rn − 1 Page M Page N + Pn Page N + P1 6 7 8 9 Page N + P2 Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input. After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer. By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache. The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache. 44 2012-09-01C TC58NVG1S3ETAI0 Command input B 10 Address input 8C Data input 10 70 Status output Address CA0 to CA11, PA0 to PA16 (Page M+Rn) 11 RY / BY B tPROG (*1) 10 Data for Page M + Rn 11 Data for Page M + Rn Data Cache Page Buffer Page M + Rn Page M + Rn − 1 Cell Array 10 11 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input. By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn. (*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following, tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page) NOTE) This operation needs to be executed within District-0 or District-1. Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High level when Page Copy (2) operation is performed. Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence 45 2012-09-01C TC58NVG1S3ETAI0 Multi Page Copy (2) By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out. When the each block address changes (increments) this sequenced has to be started from the beginning. Same page address (PA0 to PA5) within two districts has to be selected. Command input Address input 60 Address input 60 Address PA0 to PA16 (Page m0 ; District 0) 30 E0 A Data output Address CA0 to CA11 (Col = 0) A 00 Address input 05 Address input E0 Data output Address input 8C Address CA0 to CA11 (Col = 0) Address CA0 to CA11, PA0 to PA16 (Page n0) Data input B tDCBSYW1 8C Address input Data input 15 60 Address CA0 to CA11, PA0 to PA16 (Page N0 ; District 1) Address input 60 Address PA0 to PA16 (Page m1 ; District 0) B Address input 00 Address input Address CA0 to CA11, PA0 to PA16 (Page m1) 05 Address input E0 C 3A Address PA0 to PA16 (Page n1 ; District 1) C tDCBSYR2 tDCBSYW2 C B 11 Address CA0 to CA11, PA0 to PA16 (Page M0 ; District 0) A B RY/BY Address input tR A RY/BY 05 Address CA0 to CA11, PA0 to PA16 (Page m0) Address PA0 to PA16 (Page n0 ; District 1) RY/BY RY/BY Address input 00 Data output 00 Address CA0 to CA11 (Col = 0) Address input Address CA0 to CA11, PA0 to PA16 (Page n1) C 46 05 Address input Address CA0 to CA11 (Col = 0) E0 Data output D D 2012-09-01C TC58NVG1S3ETAI0 D 8C Address input Data input 11 8C Address CA0 to CA11, PA0 to PA16 (Page M1 ; District 0) RY/BY E tDCBSYW2 tDCBSYW1 60 Address input Address input 60 3A Address input 00 05 Address CA0 to CA11, PA0 to PA16 (Page m63) Address PA0 to PA16 (Page n63 ; District 1) Address input E0 Data output F Address CA0 to CA11 (Col = 0) E F tDCBSYR2 F 00 Address input 05 Address CA0 to CA11, PA0 to PA16 (Page n63) Address input E0 Data output 8C Address CA0 to CA11 (Col = 0) Address input Data input G 11 Address CA0 to CA11, PA0 to PA16 (Page M63 ; District 0) F G tDCBSYW1 8C Address input Data input G 10 Note) This operation needs to be executed within each District. Address CA0 to CA11, PA0 to PA16 (Page N63 ; District 1) RY/BY E 15 Address CA0 to CA11, PA0 to PA16 (Page N1 ; District 1) Address PA0 to PA16 (Page m63 ; District 0) RY/BY Data input D E RY/BY Address input G Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. tPROG (*1) (*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache program, the tPROG* during cache programming is given by the following equation. Make sure WP is held to High level when Multi Page Copy (2) operation is performed. Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence tPROG = tPROG of the last page + tPROG of the previous page-A A = (command input cycle + address input cycle + data output/input cycle time of the last page) If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max. 47 2012-09-01C TC58NVG1S3ETAI0 Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 Block Address input: 3 cycles 70 I/O Status Read command Erase Start command RY / BY Pass Fail Busy Multi Block Erase The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by checking the status by 71h status read command. For details on 71h status read command, refer to section “Multi Page Program with Data Cache”. 60 Block Address input: 3 cycles District 0 60 D0 71 Status Read command Block Address Erase Start input: 3 cycles command District 1 RY / BY I/O Pass Fail Busy Internal addressing in relation with the Districts • • • To use Multi Block Erase operation, the internal addressing should be considered in relation with the District. The device consists from 2 Districts. Each District consists from 1024 erase blocks. The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Block Erase There are following restrictions in using Multi Block Erase (Restriction) Maximum one block should be selected from each District. For example; (60) [District 0] (60) [District 1] (D0) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (60) [District 1] (60) [District 0] (D0) It requires no mutual address relation between the selected blocks from each District. Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h command input, input the FFh reset command to terminate the operation. 48 2012-09-01C TC58NVG1S3ETAI0 ID Read The device contains ID codes which can be used to identify the device type, the manufacturer, and features of the device. The ID codes can be read out under the following timing conditions: CLE tCEA CE WE tAR ALE RE tREA I/O See table 5 See table 5 See table 5 90h 00h 98h DAh ID Read command Address 00 Maker code Device code Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data 1 0 0 1 1 0 0 0 98h Table 5. Code table 1st Data Maker Code 2nd Data Device Code 1 1 0 1 1 0 1 0 DAh 3rd Data Chip Number, Cell Type ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table 4th Data Page Size, Block Size, ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table 5th Data Plane Number ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ See table 3rd Data Description Internal Chip Number Cell Type I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 1 2 4 8 0 0 1 1 2 level cell 4 level cell 8 level cell 16 level cell 49 I/O2 I/O1 0 0 1 1 0 1 0 1 0 1 0 1 2012-09-01C TC58NVG1S3ETAI0 4th Data Description Page Size (without redundant area) 1 KB 2 KB 4 KB 8 KB Block Size (without redundant area) 64 KB 128 KB 256 KB 512 KB I/O8 I/O7 I/O6 I/O5 0 0 1 1 0 1 0 1 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 0 0 1 1 0 1 0 1 I/O2 I/O1 5th Data Description Plane Number I/O8 1 Plane 2 Plane 4 Plane 8 Plane 50 I/O7 I/O4 I/O3 0 0 1 1 0 1 0 1 2012-09-01C TC58NVG1S3ETAI0 Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a Read operation to find out the Ready/Busy status. The resulting information is outlined in Table 6. Table 6. Status output table Page Program Block Erase Definition I/O1 Chip Status1 Pass: 0 Fail: 1 I/O2 Chip Status 2 Pass: 0 Fail: 1 I/O3 Read Cache Read Cache Program Pass/Fail Pass/Fail Invalid Invalid Pass/Fail Invalid Not Used 0 0 0 I/O4 Not Used 0 0 0 I/O5 Not Used 0 0 0 I/O6 Page Buffer Ready/Busy Ready: 1 Busy: 0 Ready/Busy Ready/Busy Ready/Busy I/O7 Data Cache Ready/Busy Ready: 1 Busy: 0 Ready/Busy Ready/Busy Ready/Busy I/O8 Write Protect Not Protected :1 Write Protect Write Protect Write Protect Protected: 0 The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state. Chip Status 1: During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result. During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state. Chip Status 2: This bit shows the pass/fail result of the previous page program operation during Auto Page Programming with Data Cache. This status is valid when I/O7 shows the Ready State. The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not 15h or 31h. 51 2012-09-01C TC58NVG1S3ETAI0 An application example with multiple devices is shown in the figure below. CE1 CE2 CE3 CEN CEN + 1 CLE ALE Device 1 WE Device 2 Device 3 Device N Device N+1 RE I/O1 to I/O8 RY / BY RY / BY Busy CLE ALE WE CE1 CEN RE 70h I/O 70h Status on Device 1 Status on Device N System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. Reset The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally generated voltage is discharged to 0 volt and the device enters the Wait state. Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also stop the previous program to a page depending on when the FF reset is input. The response to a “FFh” Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during programming 80 10 FF 00 Internal VPP RY / BY tRST (max 10 μs) 52 2012-09-01C TC58NVG1S3ETAI0 When a Reset (FFh) command is input during erasing D0 FF 00 Internal erase voltage RY / BY tRST (max 500 μs) When a Reset (FFh) command is input during Read operation 00 30 FF 00 RY / BY tRST (max 6 μs) When a Reset (FFh) command is input during Ready FF 00 RY / BY tRST (max 6 μs) When a Status Read command (70h) is input after a Reset FF 70 I/O status: Pass/Fail → Pass : Ready/Busy → Ready RY / BY When two or more Reset commands are input in succession 10 (1) (2) (3) FF FF FF RY / BY The second FF command is invalid, but the third 53 FF command is valid. 2012-09-01C TC58NVG1S3ETAI0 APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off. 2.7 V 2.5V 0 V VCC Don’t care Don’t care CE , WE , RE CLE, ALE WP VIH VIL VIL 1 ms max Operation 100 μs max Don’t care Invalid Ready/Busy (2) Power-on Reset The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of commands while in the Busy state During the Busy state, do not input any command except 70h(71h) and FFh. 54 2012-09-01C TC58NVG1S3ETAI0 (5) Acceptable commands after Serial Input command “80h” Once the Serial Input command “80h” has been input, do not input any command other than the Column Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page Program command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”. 80 FF WE Address input RY / BY If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not performed and the device operation is set to the mode which the input command specifies. 80 XX 10 Mode specified by the command. Programming cannot be executed. Command other than “85h”, “10h”, “11h”, “15h” or “FFh” (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) Data register Data (64) Data register (32) (3) Page 0 Page 1 Page 2 Page 31 (32) Page 31 (1) Page 63 (64) Page 63 (64) Page 0 Page 1 Page 2 (1) (2) 55 (2) (3) 2012-09-01C TC58NVG1S3ETAI0 (7) Status Read during a Read operation 00 Command 00 30 [A] 70 CE WE RY/BY RE Address N Status Read command input Status output Status Read . The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read mode unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A], Status Read mode is reset, and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary (8) Auto programming failure Fail 80 10 70 I/O 80 Address Data M input 10 Address Data N input 80 If the programming result for page address M is Fail, do not try to program the page to address N in another block without the data input sequence. Because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 M N (9) RY / BY : termination for the Ready/Busy pin ( RY / BY ) A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit. VCC Ready VCC VCC R Busy Device RY / BY tr tf CL VCC = 3.3 V Ta = 25°C CL = 100 pF VSS 1.5 μs tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. 1.0 μs 10 ns tf tr 0.5 μs 0 15 ns tf 5 ns 1 KΩ 2 KΩ 3 KΩ 4 KΩ R 56 2012-09-01C TC58NVG1S3ETAI0 (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN 80 10 WP RY / BY tWW (100 ns MIN) Disable Programming WE DIN 80 10 WP RY / BY tWW (100 ns MIN) Enable Erasing WE DIN 60 D0 WP RY / BY tWW (100 ns MIN) Disable Erasing WE DIN 60 D0 WP RY / BY tWW (100 ns MIN) 57 2012-09-01C TC58NVG1S3ETAI0 (11) When six address cycles are input Although the device may read in a sixth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 00h 30h Ignored Address input RY / BY Program operation CLE CE WE ALE I/O 80h Ignored Address input 58 Data input 2012-09-01C TC58NVG1S3ETAI0 (12) Several programming cycles on the same page (Partial Page Program) Each segment can be programmed individually as follows: 1st programming 2nd programming All 1 s 4th programming Result All 1 s Data Pattern 1 Data Pattern 2 All 1 s Data Pattern 1 Data Pattern 2 59 All 1 s Data Pattern 4 Data Pattern 4 2012-09-01C TC58NVG1S3ETAI0 (13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: Please do not perform an erase operation to bad blocks. It may be impossible to recover the bad block information if the information is erased. Bad Block Bad Block Check if the device has any bad blocks after installation into the system. Refer to the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. The number of valid blocks over the device lifetime is as follows: Valid (Good) Block Number MIN TYP. MAX UNIT 2008 ⎯ 2048 Block Bad Block Test Flow Regarding invalid blocks, bad block mark is in either the 1st or the 2nd page. Read Check : Read either column 0 or 2048 of the 1st page or the 2nd page of each block. If the data of the column is not FF (Hex), define the block as a bad block. Start Block No = 1 Fail Read Check Pass Block No. = Block No. + 1 Bad Block *1 No Last Block Yes End *1: No erase operation is allowed to detected bad blocks 60 2012-09-01C TC58NVG1S3ETAI0 (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase → Block Replacement Page Programming Failure Status Read after Program → Block Replacement Single Bit Programming Failure “1 to 0” ECC • ECC: Error Correction Code. 1 bit correction per 512 Bytes is necessary. • Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A ( by creating a bad block table or by using another appropriate scheme). Block B Erase When an error occurs during an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. (16) The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. 61 2012-09-01C TC58NVG1S3ETAI0 (17) Reliability Guidance This reliability guidance is intended to notify some guidance related to using NAND flash with 1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note. Although random bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad when a program status failure or erase status failure is detected. The other failure modes may be recovered by a block erase. ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures. • Write/Erase Endurance Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto program or auto block erase operation. The cumulative bad block count will increase along with the number of write/erase cycles. • Data Retention The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After block erasure and reprogramming, the block may become usable again. Here is the combined characteristics image of Write/Erase Endurance and Data Retention. Data Retention [Years] Write/Erase Endurance [Cycles] • Read Disturb A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors occur on other pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become usable again. 62 2012-09-01C TC58NVG1S3ETAI0 Package Dimensions Weight: 0.53g (typ.) 63 2012-09-01C TC58NVG1S3ETAI0 Revision History Date 2008-11-20 2009-01-07 2009-03-09 Rev. 1.00 1.01 1.02 2009-07-09 1.03 2010-01-25 1.04 2010-05-21 2010-07-13 2011-03-01 2011-11-01 2012-09-01 1.05 1.06 1.07 1.08 1.09 Description Original version Description for PSL is added. Description for PSL is eliminated. Descriptions of APPLICATION NOTES AND COMMENTS (5) and (7) are changed. tRST is changed. tRHOH is changed from 25ns to 22ns. Modified “FEATURES” Revised “APPLICATION NOTES AND COMMENTS” (14). Deleted an invalid description at Page 30. Deleted Confidential notation. Changed “RESTRICTIONS ON PRODUCT USE”. Corrected TIMING DIAGRAM of ID Read. Deleted TENTATIVE notation. tR is changed. Corrected typo. Changed “RESTRICTIONS ON PRODUCT USE”. 64 2012-09-01C TC58NVG1S3ETAI0 RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. • PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. • Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. • Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. • ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. • Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. • Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 65 2012-09-01C