S-35740C01I-K8T2U

S-35740 INTERVAL TIMER IC www.ablic.com © ABLIC Inc., 2019 PROGRAMMABLE INTERVAL TIMER IC Rev.1.0_00 The interval timer IC allows for intermittent system operation by inputting a signal to the system at fixed periods of time. The S-35740 outputs an interval signal (fixed-cycle interrupt signal). The frequency and duty ratio of the interval signal (fixed-cycle interrupt signal) can be set freely by users via a 2-wire serial interface. The S-35740 has a 24-bit timer. For example, users can obtain the cumulative energization time of the system since the timer performs a count-up action every second.  Features • Interval signal output function: Settable interval signal frequency and duty ratio, with an output control pin (Fixed-cycle interrupt signal output function) • Low current consumption: 0.2 μA typ. (Quartz crystal: CL = 6.0 pF, VDD = 3.0 V, ENBL pin = "H", Ta = +25°C) • Wide range of operation voltage: 1.8 V to 5.5 V • 2-wire (I2C-bus) CPU interface • Built-in 32.768 kHz crystal oscillation circuit • Operation temperature range: Ta = −40°C to +85°C • Lead-free (Sn 100%), halogen-free  Applications • • • • • IoT communications device Monitoring device Security device Battery system Energy harvesting system  Package • TMSOP-8 1 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Block Diagram ENBL XIN Oscillation circuit XOUT Divider, Timing generator INT pin controller INT Timer (24-bit) Time register Fixed-cycle interrupt signal setting register VDD Power-on detection circuit Constant voltage circuit SDA Serial interface VSS SCL Figure 1 2 INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Product Name Structure 1. Product name S-35740 C 01 I - K8T2 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specification*1 K8T2: TMSOP-8, Tape Operation temperature I: Ta = −40°C to +85°C Fixed value Fixed value C: Quartz crystal CL = 6.0 pF Product name *1. Refer to the tape drawing. 2. Package Table 1 Package Name TMSOP-8 Package Drawing Codes Dimension Tape Reel FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD 3. Product name list Table 2 Product Name S-35740C01I-K8T2U INT Pin Output Form CMOS output 3 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Pin Configuration 1. TMSOP-8 Table 3 Pin No. Symbol Top view 1 2 3 4 8 7 6 5 Figure 2 4 1 ENBL 2 3 4 XOUT XIN VSS 5 INT 6 SDA 7 SCL 8 VDD Description Input pin for fixed-cycle interrupt signal output control Connection pins for quartz crystal GND pin Output pin for fixed-cycle interrupt signal I/O pin for serial data Input pin for serial clock Pin for positive power supply List of Pins I/O Input Configuration CMOS input − − − − Output CMOS output Bi-directional Nch open-drain output, CMOS input Input CMOS input − − INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Pin Functions 1. SDA (I/O for serial data) pin This is a data input / output pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with a clock pulse from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, the SDA pin is pulled up to VDD potential via a resistor, and is used with wired-OR connection of other device of Nch open-drain output or open collector output. 2. SCL (Input for serial clock) pin This is a clock input pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with this clock 3. ENBL (Input for fixed-cycle interrupt signal output control) pin This pin controls the clock pulse output from the INT pin. The INT pin outputs the fixed-cycle interrupt signal when the ENBL pin is "H". The INT pin is fixed when the ENBL pin is "L". 4. INT (Output for fixed-cycle interrupt signal) pin This pin outputs a fixed-cycle interrupt signal. The fixed-cycle interrupt signal of the frequency and duty ratio, which is set to the fixed-cycle interrupt signal setting register, is output. Regarding the operation of the fixed-cycle interrupt signal output, refer to " INT Pin Fixed-cycle Interrupt Signal Output". Besides, the INT pin output form is CMOS output. 5. XIN, XOUT (Connection for quartz crystal) pins Connect a quartz crystal between the XIN pin and the XOUT pin. 6. VDD (Positive power supply) pin Connect this pin with a positive power supply. Regarding the values of voltage to be applied, refer to " Recommended Operation Conditions". 7. VSS pin Connect this pin to GND. 5 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Equivalent Circuits of Pins SCL SDA Figure 3 SCL pin Figure 4 SDA pin INT ENBL Figure 5 6 ENBL Pin Figure 6 INT Pin INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Absolute Maximum Ratings Table 4 Item Power supply voltage Symbol VDD Input voltage VIN Output voltage VOUT Applied Pin − Absolute Maximum Rating VSS − 0.3 to VSS + 6.5 Unit SDA, SCL, ENBL VSS − 0.3 to VSS + 6.5 V SDA INT VSS − 0.3 to VSS + 6.5 V V V VSS − 0.3 to VDD + 0.3 ≤ VSS + 6.5 − −40 to +85 °C Operation ambient temperature*1 Topr − −55 to +150 °C Storage temperature Tstg *1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a malfunction. Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Recommended Operation Conditions Table 5 Item Operation power supply voltage Symbol VDD Condition Ta = −40°C to +85°C Min. Typ. Max. (VSS = 0 V) Unit 1.8 − 5.5 V  Oscillation Characteristics Table 6 (Ta = +25°C, VDD = 3.0 V, VSS = 0 V unless otherwise specified) (Quartz crystal (NX3215SD, CL = 6.0 pF) manufactured by Nihon Dempa Kogyo Co., Ltd.) Item Symbol Condition Min. Typ. Max. Unit − Oscillation start voltage VSTA Within 10 seconds 1.8 5.5 V − − − Oscillation start time tSTA 1 s δIC − −20 − +20 IC-to-IC frequency deviation*1 ppm *1. Reference value 7 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  DC Electrical Characteristics Table 7 Item Symbol Current consumption 1 IDD1 Current consumption 2 IDD2 Current consumption 3 IDD3 High level input leakage current Low level input leakage current High level output leakage current Low level output leakage current High level input voltage Low level input voltage High level output voltage Low level output voltage 8 (Ta = −40°C to +85°C, VSS = 0 V unless otherwise specified) (Quartz crystal (NX3215SD, CL = 6.0 pF) manufactured by Nihon Dempa Kogyo Co., Ltd.) Applied Pin Condition Min. Typ. Max. Unit VDD = 3.0 V, Out of communication, − − 1.7 3.0 μA ENBL pin = VSS, INT pin = no load VDD = 3.0 V, Out of communication, − μA 0.35 0.55 ENBL pin = VDD, − INT pin output = 1.024 kHz, INT pin = no load VDD = 3.0 V, fSCL = 1 MHz, During communication, − 170 300 μA − ENBL pin = VDD, INT pin = no load IIZH SDA, SCL, ENBL VIN = VDD −0.5 − 0.5 μA IIZL SDA, SCL, ENBL VIN = VSS −0.5 − 0.5 μA IOZH SDA VOUT = VDD −0.5 − 0.5 μA IOZL SDA VOUT = VSS −0.5 − 0.5 μA VIH SDA, SCL, ENBL − 0.7 × VDD − VSS + 5.5 V VIL SDA, SCL, ENBL − VSS − 0.3 − 0.3 × VDD V VOH INT IOH = −0.4 mA 0.8 × VDD − − V VOL SDA, INT IOL = 2.0 mA − − 0.4 V INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  AC Electrical Characteristics Table 8 Measurement Conditions Input pulse voltage Input pulse rise / fall time Output reference voltage Output load VIH = 0.8 × VDD, VIL = 0.2 × VDD 20 ns VOH = 0.7 × VDD, VOL = 0.3 × VDD 100 pF Input pulse voltage 0.8 × VDD 0.7 × VDD 0.3 × VDD 0.2 × VDD Figure 7 Table 9 Output reference voltage Input / Output Waveform during AC Measurement AC Electrical Characteristics (Ta = −40°C to +85°C) VDD = 1.8 V to 2.5 V VDD = 2.5 V to 5.5 V Item Symbol Unit Min. Max. Min. Max. SCL clock frequency fSCL 0 400 0 1000 kHz − − μs SCL clock "L" time tLOW 1.3 0.4 − − μs SCL clock "H" time tHIGH 0.6 0.3 − − μs SDA output delay time*1 tAA 0.9 0.5 − − μs Start condition set-up time tSU.STA 0.6 0.25 − − μs Start condition hold time tHD.STA 0.6 0.25 − − Data input set-up time tSU.DAT 100 80 ns − − Data input hold time tHD.DAT 0 0 ns − − μs Stop condition set-up time tSU.STO 0.6 0.25 − − μs SCL, SDA rise time tR 0.3 0.3 − − μs SCL, SDA fall time tF 0.3 0.3 − − μs Bus release time tBUF 1.3 0.5 − − Noise suppression time tl 50 50 ns *1. Since the output form of the SDA pin is Nch open-drain output, the SDA output delay time is determined by the values of the load resistance and load capacitance outside the IC. Figure 9 shows the relationship between the output load values. 9 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 tF tHIGH tR tLOW SCL tHD.DAT tHD.STA tSU.STA tSU.STO tSU.DAT SDA (S-35740 input) tBUF tAA SDA (S-35740 output) Figure 8 Bus Timing Maximum pull-up resistance [kΩ] 15 13 11 9 fSCL = 400 kHz 7 5 3 fSCL = 1.0 MHz 1 100 10 Load capacitance [pF] Figure 9 10 Output Load 1000 INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  INT Pin Fixed-cycle Interrupt Signal Output 1. Frequency and duty ratio The frequency and duty ratio of the fixed-cycle interrupt signal output is set in the fixed-cycle interrupt signal setting register. By setting "1" to each bit of the fixed-cycle interrupt signal setting register, the frequency corresponding to each bit (1 Hz to 1.024 kHz) is output depending on AND logic, and the frequency and the duty ratio are changed. The example of the fixed-cycle Interrupt signal output when 512 Hz = "1", 256 Hz = "1", 128 Hz = "1", 64 Hz = "1" and others = "0" is shown below. When all bits of the fixed-cycle interrupt signal setting register are "0", the INT pin outputs are fixed to "L". 1.024 kHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz INT 0.98 ms Figure 10 15.6 ms Example of Fixed-cycle Interrupt Signal Output 2. ENBL pin and INT pin clock pulse output The INT pin outputs the fixed-cycle interrupt signal when the ENBL pin is "H". The INT pin is fixed to "H" when the ENBL pin is "L". Duty ratio of the INT pin may change when the "H" and "L" of the ENBL pin changes. The example of the INT pin output timing is shown below. ENBL Internal signal reset Internal signal reset Internal signal INT Figure 11 INT Pin Output Timing Example 1 11 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 3. Write operation of fixed-cycle interrupt signal setting register and INT pin clock pulse output Even if the write operation of the fixed-cycle interrupt signal setting register is performed when the INT pin does not output the fixed-cycle interrupt signal, the INT pin maintains "H". Therefore, when the ENBL pin is set to "H", the INT pin outputs the fixed-cycle interrupt signal according to the value written to the fixed-cycle interrupt signal setting register immediately before the setting. The divider is reset if the write operation of the fixed-cycle interrupt signal setting register is performed when the INT pin outputs the fixed-cycle interrupt signal. Therefore, the duty ratio of the INT pin may change. The example of the INT pin output timing is shown below. ENBL Write operation of fixed-cycle interrput setting register Internal signal reset Internal signal reset Internal signal INT Figure 12 INT Pin Output Timing Example 2 Moreover, since the crystal oscillation circuit is unstable immediately after power-on, regardless of the status of the ENBL pin, the INT pin is fixed to "L" for about 0.5 seconds after power-on. The write operation of the fixed-cycle interrupt signal setting register is possible even during this time. When the ENBL pin is set to "H" without the write operation of the fixed-cycle interrupt signal setting register after power-on, the INT pin is fixed to "L". Therefore, the write operation of the fixed-cycle interrupt signal setting register should be performed after power-on. 12 INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Timer The S-35740 has a 24-bit timer. The timer performs a count-up action every second and stops at "FFFFFF h". Even if the timer stops, the clock pulse output of INT pin is not affected. Input a timer reset command to the S-35740 in order to reset the timer. Thereby, the timer restarts the operation. Refer to "Figure 17 Acknowledge Output Timing" and "Figure 18 Data Transmission Format of Serial Interface" regarding the timer reset command. As shown in "Figure 11 INT Pin Output Timing Example 1" and "Figure 12 INT Pin Output Timing Example 2", the S-35740 resets the internal signal when the write operation of the fixed-cycle interrpt signal setting register is performed. The internal signal generates a count-up signal of the timer every second. Therefore, the count-up action of the timer will be delayed for up to 1 second when the write operation of the fixed-cycle interrupt signal setting register is performed. Figure 13 shows the operation outline. 1 Hz (n − 1) seconds (n) seconds 1 second 1 second (n + 1) seconds 1 second 1 Hz (n − 1) seconds 1 second (n) seconds (n + 1) seconds 1 second 1 second 1 Hz Figure 13 (n − 1) seconds (n) second (n + 1) seconds 1 second 1 second 1 second Timer Count-up Action and Internal Signal Reset 13 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Configuration of Registers 1. Time register The time register is a 3-byte register that stores the timer value in the binary code. The time register is read-only. Perform the read operation of the time register in 3-byte unit from TM23 to TM0. Example: 3 seconds (0000_0000_0000_0000_0000_0011) 45 minutes (0000_0000_0000_1010_1000_1100) 5 hours 30 minutes (0000_0000_0100_1101_0101_1000) TM23 TM22 TM21 TM20 TM19 TM18 TM17 TM16 B7 B0 TM15 TM14 TM13 TM12 TM11 TM10 TM9 B7 TM7 TM8 B0 TM6 TM5 TM4 TM3 B7 TM2 TM1 TM0 B0 Figure 14 2. Fixed-cycle interrupt signal setting register The fixed-cycle interrupt signal setting register is a 2-byte register that sets the fixed-cycle interrupt signal at the upper 10 bits. By setting "1" to each bit, the frequency corresponding to each bit is output from the INT pin depending on AND logic. Refer to " INT Pin Fixed-cycle Interrupt Signal Output" for details. The lower 3 bits, RST2 to RST0 are used as a register to input the timer reset command. The timer is reset by writing RST2 = "0", RST1 = "1" and RST0 = "0". The fixed-cycle interrupt signal setting register is not reset even if the timer reset command is input. Therefore, it is unnecessary to write to the fixed-cycle interrupt signal setting register again. Moreover, when only a fixed-cycle interrupt signal is set without resetting the timer, write the data except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the fixed-cycle interrupt signal setting register. Set DM1 and DM0 to "0" or "1" since they are dummy data. The fixed-cycle interrupt signal setting register is possible for write and read. Perform the write and read operation of the fixed-cycle interrput signal setting register in 2-byte unit. When performing the read operation of fixed-cycle interrupt signal setting register, set the ENBL pin to "H". If the ENBL pin is set to "L", the time register data is read. 1Hz B7 2Hz 4Hz 16Hz DM1 DM0 RST2 RST1 RST0                    B0 Figure 15 14 32Hz 64Hz 128Hz                    B0 256Hz 512Hz 1kHz B7 8Hz INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Serial Interface The S-35740 transmits and receives various commands via I2C-bus serial interface to read / write data. 1. Start condition When SDA changes from "H" to "L" with SCL at "H", the S-35740 recognizes start condition and the access operation is started. 2. Stop condition When SDA changes from "L" to "H" with SCL at "H", the S-35740 recognizes stop condition and the access operation is completed. The S-35740 enters standby mode, consequently. tSU.STA tHD.STA tSU.STO SCL SDA Start condition Stop condition Figure 16 Start / Stop Condition 3. Data transmission and acknowledge The data transmission is performed at every one byte after the start condition detection. Pay attention to the specification of tSU.DAT and tHD.DAT when changing SDA, and perform the operation when SCL is "L". If SDA changes when SCL is "H", the start / stop condition is recognized even during the data transmission, and the access operation will be interrupted. Whenever a one-byte data is received during data transimmion, the receiving device returns an acknowledge. For example, as shown in Figure 17, assume that the S-35740 is a receiving device, and the master device is a transmitting device. If the clock pulse at the 8th bit falls, the master device releases SDA. Consequently, the S-35740, as an acknowledge, sets SDA to "L" during the 9th bit pulse. The access operation is not performed properly when the S-35740 does not output an acknowledge. SCL (S-35740 input) 1 tSU.DAT 8 9 tHD.DAT SDA (Master device output) Release SDA High-Z Acknowledge output (Active "L") SDA (S-35740 output) High-Z Start condition Figure 17 tAA Acknowledge Output Timing 15 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 4. Data transmission format After the start condition transmission, the 1st byte is a slave address and a command (read / write bit) that shows the transmission direction at the 2nd byte or subsequent bytes. The slave address of the S-35740 is specified to "0110010". The data can be written to the fixed-cycle interrupt signal setting register when read / write bit is "0", and the data of the fixed-cycle interrupt signal setting register or the time register can be read when read / write bit is "1". When the data can be written to fixed-cycle interrupt signal setting register, input the data from the master device in order of B7 to B0. The acknowledge ("L") is output from the S-35740 whenever a one-byte data is input. When the data of the fixed-cycle interrupt signal setting register or the timer register can be read, the data from the S-35740 is output in order of B7 to B0 in byte unit. Input the acknowledge ("L") from the master device whenever a one-byte data is input. However, do not input the acknowledge for the last byte (NO_ACK). By this, the end of the data read is informed. After the master device receives / transmits the acknowledge for the last byte data, input the stop condition to the S-35740 to finish the access operation. When the master device inputs start condition instead of stop condition, the S-35740 becomes restart condition, and can transmit / receive the data if the master device inputs the slave address continuously. 9 1 18 27 36 SCL Data write format SDA ST Slave address 0 A Data read format SDA ST Slave address 1 A B7 B7 B7 : S-35740 output data 16 B0 B0 B0 B0 A SP B0 A Data B7 Data Transmission Format of Serial Interface A A Data A : Acknowledge SP B0 B7 A Data B7 Data A Data A B0 B7 : Start condition ST A B0 B7 Data B7 A Data A Data B0 B7 A Data B1 R/W B7 : Master device input data Figure 18 B0 A Data B7 A Data B1 R/W B7 ST Slave address 1 A B7 B0 B1 R/W B7 Restart format SDA ST Slave address 0 A A Data B1 R/W B7 SP B0 SP : Stop condition INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740 5. Read operation of time register Transmit the start condition and slave address from the master device. The slave address of the S-35740 is specified to "0110010". The data of the time register can be read when the read / write bit is "1". The 2nd byte to the 4th byte are used as the time register. Each byte from B7 is transmitted. When the read operation of the time register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output from the master device, and then transmit the stop condition. The time register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of the time register. Regarding the time register, refer to " Configuration of Registers". 1 9 18 27 36 SCL B1 R/W B7 B7 B0 Slave address (0110010) B7 B0 B7 STOP 0 1 1 0 0 1 0 1 NO_ACK TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 ACK TM8 TM9 TM10 TM11 TM12 TM13 TM14 TM15 ACK TM16 TM17 TM18 TM19 TM20 TM21 TM22 TM23 ACK START SDA B0 Time register (3-byte) Take in the counter value at this timing and transmit it as a serial data. : Master device input data Input NO_ACK after the 3rd byte data is transmitted. : S-35740 output data Figure 19 Read Timing of Time Register 6. Write operation of fixed-cycle interrupt signal setting register Transmit the start condition and slave address from the master device. The slave address of the S-35740 is specified to "0110010". Next, transmit "0" to the the read / write bit. Transmit dummy data to the 2nd byte. However, make sure to set B0 to "1" since it is a test bit. B7 to B0 in the 3rd byte and B7 to B5 in the 4th byte are used as the fixed-cycle interrupt signal setting register. Set B6 to B1 in the 2nd byte and B4 to B3 in the 4th byte to "0" or "1" since they are dummy data. B2 to B0 (RST2 to RST0) in the 4th byte are used as a register to input the timer reset command. The timer is reset when transmitting RST2 = "0", RST1 = "1" and RST0 = "0". When not resetting the timer, transmit the data except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the fixed-cycle interrupt signal setting register. Transmit the stop condition from the master device to finish the access operation. Regarding the fixed-cycle interrupt signal setting register, refer to " Configuration of Registers". Write operation of the fixed-cycle interrupt signal setting register is performed each byte, so transmit the data in 2-byte unit. Note that the S-35740 may not operate as desired if the data is not transmitted in 2-byte unit. 1 9 18 27 36 SCL 1 Hz to 128 Hz 256 Hz to 1 kHz, RST[2:0] Write timing Write timing B7 1 1 B1 R/W B7 Slave address (0110010) Dummy data B0 *1 B7 B0 B7 STOP 1 1 00 1 00 ACK RST0 RST1 RST2 DM0*1 DM1*1 1kHz 512Hz 256Hz ACK 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz ACK 0 ACK START SDA B0 Fixed-cycle interrupt signal setting register (2byte) Make sure to set B0 to "1" since it is a test bit. Set B7 as an address pointer : Master device input data : S-35740 output data *1. Set "0" or "1" since they are dummy data. Figure 20 Write Timing of Fixed-cycle Interrupt Signal Setting Register 17 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 7. Read operation of fixed-cycle interrupt signal setting register Perform the read operation of fixed-cycle interrupt signal setting register with the restart format. Regarding the restart format, refer to "4. Data transmission format". When performing the read operation of fixed-cycle interrupt signal setting register, set the ENBL pin to "H". If the ENBL pin is set to "L", the time register data is read. Transmit the start condition and the slave address from the master device. The slave address of the S-35740 is specified to "0110010". Next, transmit "0" to the read / write bit. B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the fixed-cycle interrupt signal setting register. Next, transmit the dummy data to B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called "dummy write". Then transmit the start condition, the slave address and the read / write bit. The data of the fixed-cycle interrupt setting register can be read when the read / write bit is set to "1". Consequently, the fixed-cycle interrupt signal setting register is output from the S-35740. Each byte from B7 is transmitted. When the read operation of the fixed-cycle interrupt signal setting register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 output from the master device, and then transmit the stop condition. The fixed-cycle interrupt signal setting register is a 2-byte register. "1" is read if the read operation is performed continuously after reading 2 bytes of the fixed-cycle interrupt signal setting register. Regarding the fixed-cycle interrput signal setting register, refer to " Configuration of Registers". Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop condition after dummy write operation. The time register is read if performing the read operation of the register after transmitting the stop condition. 1 9 18 1 9 18 27 SCL B7 B0 Dummy data*1 Slave address (0110010) 01100101 B7 B1R/W Slave address (0110010) B7 B7 B0 Input NO_ACK after the 2nd byte transmission Dummy write : Master device input data : S-35740 output data *1. Set "0" or "1" since they are dummy data. Figure 21 18 B7 Fixed-cycle interrupt signal setting register (2byte) Make sure to set B0 to "1" since it is a test bit. Set B7 as an address pointer B0 STOP 1 NO_ACK RST0 RST1 RST2 DM0 *1 DM1 *1 1 kHz 512 Hz 256 Hz ACK 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 kz 2 Hz 1 Hz ACK B1 R/W 0 START B7 ACK 01100100 ACK START SDA Read Timing of Fixed-cycle Interrpt Signal Setting Register PROGRAMMABLE INTERVAL TIMER IC S-35740 INTERVAL TIMER IC Rev.1.0_00  Release of SDA The ENBL pin of the S-35740 does not perform the reset operation of the communication interface. Therefore, the stop condition is input to reset the internal interface circuit usually. However, the S-35740 does not accept the stop condition from the master device when in the status that SDA outputs "L" (at the time of acknowledge outputting or reading). Consequently, it is necessary to finish the acknowledge output or read operation. Figure 22 shows the SDA release method. First, input the start condition from the master device (since SDA of the S-35740 outputs "L", the S-35740 can not detect the start condition). Next, input the clocks for 1-byte data access (9 clocks) from SCL. During the time, release SDA of the master device. By this, the SDA input / output before communication interrupt is completed, and SDA of the S-35740 becomes release status. Continuously, if the stop condition is input, the internal circuit resets and the communication returns to normal status. It is strongly recommended that the SDA release method is performed at the time of system initialization after the power supply voltage of the master device rises. Start condition Clocks for 1-byte data access 1 SCL 2 8 Stop condition 9 SDA (Master device output) SDA (S-35740 output) SDA "L" "L" Figure 22 "L" or High-Z High-Z "L" or High-Z SDA Release Method 19 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Power-on Detection Circuit In order for the power-on detection circuit to operate normally, raise the power supply voltage of the IC from 0.2 V or lower so that it reaches 1.8 V of the operation power supply voltage minimum value within 10 ms, as shown in Figure 23. Within 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0V *1. *1 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35740. Figure 23 How to Raise the Power Supply Voltage If the power supply voltage of the S-35740 cannot be raised under the above conditions, the power-on detection circuit may not operate normally and an oscillation may not start. In such case, perform the operations shown in "1. When power supply voltage is raised at ENBL pin = "L" " and "2. When power supply voltage is raised at ENBL pin = "H" ". 1. When power supply voltage is raised at ENBL pin = "L" Set the ENBL pin to "L" until the power supply voltage reaches 1.8 V or higher. While the ENBL pin is set to "L", the oscillation start signal becomes "H", and the crystal oscillation circuit normally oscillates. If the ENBL pin is set to "H" after the power supply voltage reaches 1.8 V, the oscillation start signal becomes "L" within 500 ms, and the oscillation status is maintained. The current consumption increases by 1.7 μA typ. while the ENBL pin is set to "L". 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0 V*1 ENBL pin input Oscillation start signal Crystal oscillation circuit output *1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35740. Figure 24 20 When Power Supply Voltage is Raised at ENBL Pin = "L" INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740 2. When power supply voltage is raised at ENBL pin = "H" Set the ENBL pin to "L" after the power supply voltage reaches 1.8 V or higher. If the ENBL pin is set to "L" for 500 ms or longer, the oscillation start signal becomes "H", and the crystal oscillation circuit normally oscillates. After that, if the ENBL pin is set to "H", the oscillation start signal becomes "L" within 500 ms, and the oscillation status is maintained. The current consumption increases by 1.7 μA typ. while the ENBL pin is set to "L". 10 ms 1.8 V (Operation power supply voltage min.) 0.2 V or lower 0 V*1 ENBL pin input Oscillation start signal Crystal oscillation circuit output *1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35740. Figure 25 When Power Supply Voltage is Raised at ENBL Pin = "H" 21 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 VOUT VR 10 kΩ SCL VDD 1 kΩ S-35740 S-1xxx VIN 1 kΩ  Example of Application Circuit VCC SDA ENBL VSS VSS CPU INT XIN XOUT VSS Figure 26 Caution 1. 2. 22 Start communication under stable condition after turning on the the system power supply. The above connection diagram does not guarantee operation. Set the constants after performing sufficient evaluation using the actual application. INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Configuration of Crystal Oscillation Circuit Since the S-35740 has built-in capacitors (Cg and Cd), adjustment of oscillation frequency is unnecessary. However, the crystal oscillation circuit is sensitive to external noise and parasitic capacitance (CP), these effects may become a factor to worsen the clock accuracy. Therefore, the following steps are recommended for optimizing the configuration of the crystal oscillation circuit. • Locate the bypass capacitor adjacent to the power supply pin of the S-35740. • Place the S-35740 and the quartz crystal as close to each other as possible, and shorten the wiring. • Increase the insulation resistance between pins and the board wiring patterns of XIN and XOUT. • Do not place any signal or power lines close to the crystal oscillation circuit. • Locate the GND layer immediately below the crystal oscillation circuit. (In the case of a multi-layer board, only the layer farthest from the oscillation circuit should be located as the GND layer. Do not locate a circuit pattern on the intermediate layers.) Quartz crystal: 32.768 kHz CL = 6.0 pF S-35740 XIN Cg Rf Cd Parasitic capacitance (CP) XOUT Rd Rf = 100 MΩ Rd = 100 kΩ Figure 27 Configuration of Crystal Oscillation Circuit Locate the GND layer in the layer immediately below (In the case of a multi-layer board, only the layer farthest from the oscillation circuit should be located as the GND layer. Do not locate a circuit pattern on the intermediate layers.) XOUT XIN VSS Quartz crystal S-35740 Top view Shield the perimeter with GND Figure 28 Example of Recommended Connection Pattern Diagram Caution Oscillation characteristics are subject to the variation of each component such as board parasitic capacitance, parasitic resistance, quartz crystal and external capacitor. When configuring the crystal oscillation circuit, pay sufficient attention for them. 23 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00  Cautions When Using Quartz Crystal Request a matching evaluation between the IC and a quartz crystal to the quartz crystal maker.  Precautions • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 24 INTERVAL TIMER IC Rev.1.0_00 PROGRAMMABLE INTERVAL TIMER IC S-35740  Characteristics (Typical Data) 1. Current consumption 1 vs. Power supply voltage characteristics 2. Current consumption 2 vs. Power supply voltage characteristics Ta = +25°C, CL = 6.0 pF 2.0 0.8 IDD2 [μA] IDD1 [μA] 1.5 1.0 0.5 0 Ta = +25°C, CL = 6.0 pF 1.0 0.6 0.4 0.2 0 2 4 0 6 0 2 VDD [V] 3. Current consumption 3 vs. SCL frequency characteristics CL = 6.0 pF 3.0 2.5 VDD = 5.0 V 400 IDD1 [μA] IDD3 [μA] 500 300 VDD = 3.0 V 200 VDD = 5.0 V 2.0 1.5 VDD = 3.0 V 1.0 0.5 100 0 0 500 1000 SCL frequency [kHz] 0 −40 −25 1500 5. Current consumption 2 vs. Temperature characteristics 0 0.8 0.5 IDD2 [μA] IDD2 [μA] 0.6 VDD = 5.0 V 0.4 0.2 0 −40 −25 25 Ta [°C] 50 0.3 VDD = 3.0 V 0.2 0 5 10 15 20 INT pin load capacitance [pF] 25 8. Oscillation frequency vs. Temperature characteristics Ta = +25°C, CL = 6.0 pF CL = 6.0 pF 50 0 Δf/f [ppm] 10 0 −10 −20 VDD = 5.0 V 0.4 0 75 85 7. Oscillation frequency vs. Power supply voltage characteristics 20 75 85 0.1 VDD = 3.0 V 0 50 Ta = +25°C, CL = 6.0 pF, INT pin output = 1.024 kHz 1.0 0.6 25 Ta [°C] 6. Current consumption 2 vs. INT pin load capacitance characteristics CL = 6.0 pF, INT pin output = 1.024 kHz, INT pin = no load Δf/f [ppm] 6 4. Current consumption 1 vs. Temperature characteristics Ta = +25°C, CL = 6.0 pF 600 4 VDD [V] −50 −100 −150 0 2 4 VDD [V] 6 −200 −40 −25 0 25 Ta [°C] 50 75 85 25 INTERVAL TIMER IC PROGRAMMABLE INTERVAL TIMER IC S-35740 Rev.1.0_00 70 60 50 40 30 20 10 0 4 VOUT [V] VDD = 3.0 V −10 −15 VDD = 5.0 V −20 VDD = 3.0 V 2 INT pin, Ta = +25°C 0 −5 VDD = 5.0 V 0 26 10. High level output current vs. VDD − VOUT characteristics INT pin, SDA pin, Ta = +25°C IOH [mA] IOL [mA] 9. Low level output current vs. Output voltage characteristics 6 −25 0 2 4 VDD − VOUT [V] 6 2.90±0.2 8 5 1 4 0.13±0.1 0.2±0.1 0.65±0.1 No. FM008-A-P-SD-1.2 TITLE TMSOP8-A-PKG Dimensions No. FM008-A-P-SD-1.2 ANGLE UNIT mm ABLIC Inc. 2.00±0.05 4.00±0.1 4.00±0.1 1.00±0.1 +0.1 1.5 -0 1.05±0.05 0.30±0.05 3.25±0.05 4 1 5 8 Feed direction No. FM008-A-C-SD-2.0 TITLE TMSOP8-A-Carrier Tape FM008-A-C-SD-2.0 No. ANGLE UNIT mm ABLIC Inc. 16.5max. 13.0±0.3 Enlarged drawing in the central part 13±0.2 (60°) (60°) No. FM008-A-R-SD-1.0 TITLE TMSOP8-A-Reel No. FM008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 4,000 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. 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