S-8264A/B/C Series
www.ablic.com
BATTERY PROTECTION IC FOR 2-SERIAL
TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
© ABLIC Inc., 2005-2021
Rev.4.6_00
The S-8264A/B/C Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a
high-accuracy voltage detection circuit and a delay circuit.
Short-circuiting between cells makes it possible for serial connection of two cells to four cells.
Features
(1)
High-accuracy voltage detection circuit for each cell
• Overcharge detection voltage n (n = 1 to 4)
4.200 V to 4.800 V (in 50 mV steps) Accuracy : ±25 mV (+25°C), Accuracy : ±30 mV (−5°C to +55°C)
• Overcharge hysteresis voltage n (n = 1 to 4)
−0.520 ±0.210 V, −0.390 ±0.160 V, −0.260 ±0.110 V, −0.130 ±0.06 V, None
(2) Delay times for overcharge detection can be set by an internal circuit only (external capacitors are unnecessary)
(3) Output control function via CTL pin (CTL pin is pulled down internally) (S-8264A Series)
Output control function via CTL pin (CTL pin is pulled up internally) (S-8264C Series)
(4) Output latch function after overcharge detection (S-8264B Series)
(5) Output form and logic
CMOS output active “H”
(6) High withstand voltage
Absolute maximum rating 26 V
(7) Wide operation voltage range
3.6 V to 24 V
(8) Wide operation temperature range
−40°C to +85°C
(9) Low current consumption
• At 3.5 V for each cell
5.0 μA max. (+25°C)
• At 2.3 V for each cell
4.0 μA max. (+25°C)
(10) Lead-free, Sn 100%, halogen-free*1
*1. Refer to “ Product Name Structure” for details.
Application
• Lithium-ion rechargeable battery packs (for secondary protection)
Packages
• SNT-8A
• 8-Pin TSSOP
1
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Block Diagrams
(1) S-8264A Series
VDD
Overcharge
detection
comparator 1
SENSE
+
−
Reference voltage 1
VC1
Overcharge
detection
comparator 2
Oscillator
+
Overcharge
detection/release
delay circuit
−
Reference voltage 2
VC2
Overcharge
detection
comparator 3
Control
logic
+
−
CO
Reference voltage 3
VC3
Overcharge
detection
comparator 4
+
−
Reference voltage 4
VSS
CTL
Remark
The diodes in the figure are parasitic diodes.
Figure 1
2
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
(2) S-8264B Series
VDD
Overcharge
detection
comparator 1
SENSE
+
−
Reference voltage 1
Overcharge
detection
comparator 2
VC1
Oscillator
+
Overcharge
detection/release
delay circuit
−
Reference voltage 2
VC2
Overcharge
detection
comparator 3
Control
logic
+
−
SR
latch
Reference voltage 3
VC3
CO
Overcharge
detection
comparator 4
+
−
Reference voltage 4
VSS
CTL
UVLO
Remark
The diodes in the figure are parasitic diodes.
Figure 2
3
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
（3）S-8264C Series
VDD
Overcharge
detection
comparator 1
SENSE
＋
－
Reference voltage 1
VC1
Overcharge
detection
comparator 2
Oscillator
＋
Overcharge
detection/release
delay circuit
－
Reference voltage 2
VC2
Control
Overcharge
detection
comparator 3
logic
＋
－
CO
Reference voltage 3
VC3
Overcharge
detection
comparator 4
＋
－
Reference voltage 4
VSS
CTL
Remark
The diodes in the figure are parasitic diodes.
Figure 3
4
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Product Name Structure
1. Product Name
(1) SNT-8A
S-8264
x
xx
-
I8T1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
*1
Package abbreviation and IC packing specification
I8T1: SNT-8A, Tape
*2
Serial code
Sequentially set from AA to AZ
Product type
A:
Without CO pin output latch function (CTL pin is pulled down internally)
B:
With CO pin output latch function
C:
Without CO pin output latch function (CTL pin is pulled up internally)
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
(2) 8-Pin TSSOP
S-8264 x
xx - T8T1
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales representatives)
Package abbreviation and IC packing specification*1
T8T1: 8-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to AZ
Product type
A:
Without CO pin output latch function (CTL pin is pulled down internally)
B:
With CO pin output latch function
C:
Without CO pin output latch function (CTL pin is pulled up internally)
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
2. Packages
Package Name
SNT-8A
8-Pin TSSOP
Environmental code = G
Environmental code = U
Package
PH008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
Drawing Code
Tape
Reel
PH008-A-C-SD
PH008-A-R-SD
FT008-E-C-SD
FT008-E-R-SD
FT008-E-C-SD
FT008-E-R-S1
Land
PH008-A-L-SD
⎯
5
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
3. Product Name List
(1) S-8264A Series
Table 1 SNT-8A
Product Name
S-8264AAA-I8T1U
S-8264AAB-I8T1U
S-8264AAC-I8T1U
S-8264AAD-I8T1U
S-8264AAE-I8T1U
S-8264AAF-I8T1U
S-8264AAG-I8T1U
S-8264AAH-I8T1U
S-8264AAI-I8T1U
S-8264AAJ-I8T1U
S-8264AAK-I8T1U
S-8264AAO-I8T1U
S-8264AAS-I8T1U
S-8264AAT-I8T1U
S-8264AAV-I8T1U
S-8264AAW-I8T1U
Overcharge Detection
Voltage [VCU]
4.450 ±0.025 V
4.350 ±0.025 V
4.500 ±0.025 V
4.350 ±0.025 V
4.300 ±0.025 V
4.450 ±0.025 V
4.300 ±0.025 V
4.400 ±0.025 V
4.400 ±0.025 V
4.450 ±0.025 V
4.350 ±0.025 V
4.400 ±0.025 V
4.500 ±0.025 V
4.550 ±0.025 V
4.600 ±0.025 V
4.220 ±0.025 V
Overcharge Hysteresis
Voltage [VHC]
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
Overcharge Detection
Delay Time [tCU]
4.0 ±0.8 s
4.0 ±0.8 s
4.0 ±0.8 s
2.0 ±0.4 s
4.0 ±0.8 s
2.0 ±0.4 s
2.0 ±0.4 s
4.0 ±0.8 s
2.0 ±0.4 s
5.65 ±1.15 s
5.65 ±1.15 s
5.65 ±1.15 s
5.65 ±1.15 s
5.65 ±1.15 s
5.65 ±1.15 s
2.0 ±0.4 s
Output Form
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
Table 2 8-Pin TSSOP
Product Name
S-8264AAA-T8T1x
S-8264AAB-T8T1x
S-8264AAK-T8T1U
Overcharge Detection
Voltage [VCU]
4.450 ±0.025 V
4.350 ±0.025 V
4.350 ±0.025 V
Overcharge Hysteresis
Voltage [VHC]
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
Overcharge Detection
Delay Time [tCU]
4.0 ±0.8 s
4.0 ±0.8 s
5.65 ±1.15 s
Output Form
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
(2) S-8264B Series
Table 3 SNT-8A
Product Name
S-8264BAA-I8T1U
S-8264BAB-I8T1U
S-8264BAC-I8T1U
Overcharge Detection
Voltage [VCU]
4.450 ±0.025 V
4.350 ±0.025 V
4.550 ±0.025 V
Overcharge Hysteresis
Voltage [VHC]
−0.390 ±0.160 V
−0.390 ±0.160 V
−0.390 ±0.160 V
Overcharge Detection
Delay Time [tCU]
4.0 ±0.8 s
4.0 ±0.8 s
4.0 ±0.8 s
Output Form
CMOS output active “H”
CMOS output active “H”
CMOS output active “H”
Table 4 8-Pin TSSOP
Product Name
S-8264BAB-T8T1x
6
Overcharge Detection
Voltage [VCU]
4.350 ±0.025 V
Overcharge Hysteresis
Voltage [VHC]
−0.390 ±0.160 V
Overcharge Detection
Delay Time [tCU]
4.0 ±0.8 s
Output Form
CMOS output active “H”
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
(3) S-8264C Series
Table 5 SNT-8A
Product Name
S-8264CAA-I8T1U
S-8264CAB-I8T1U
Overcharge Detection
Voltage [VCU]
4.450 ±0.025 V
4.220 ±0.025 V
Overcharge Hysteresis
Voltage [VHC]
−0.390 ±0.160 V
−0.260 ±0.110 V
Overcharge Detection
Delay Time [tCU]
2.0 ±0.4 s
2.0 ±0.4 s
Output Form
CMOS output active “H”
CMOS output active “H”
Remark 1. Please contact our sales representatives for products other than the above.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
7
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Pin Configurations
Table 6
SNT-8A
Top view
VDD 1
8 CO
SENSE 2
7 CTL
VC1 3
VC2 4
6 VSS
5 VC3
Pin No.
Symbol
1
2
VDD
SENSE
3
VC1
4
VC2
5
VC3
6
VSS
7
CTL
8
CO
Pin No.
1
2
Symbol
VDD
SENSE
3
VC1
4
VC2
5
VC3
6
VSS
7
CTL
8
CO
Description
Positive power input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power input pin
Negative voltage connection pin of battery 4
CO output control pin (S-8264A/C Series)
Overcharge detection latch reset pin (S-8264B Series)
FET gate connection pin for charge control
Figure 4
Table 7
8-Pin TSSOP
Top view
VDD
SENSE
VC1
VC2
8
7
6
5
1
2
3
4
Figure 5
8
CO
CTL
VSS
VC3
Description
Positive power input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power input pin
Negative voltage connection pin of battery 4
CO output control pin (S-8264A/C Series)
Overcharge detection latch reset pin (S-8264B Series)
FET gate connection pin for charge control
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Absolute Maximum Ratings
Table 8
(Ta = 25°C unless otherwise specified)
Item
Symbol
VDS
VIN
VCO
Applied Pin
VDD
SENSE, VC1, VC2, VC3, CTL
CO
Unit
⎯
Rating
VSS − 0.3 to VSS + 26
VSS − 0.3 to VDD + 0.3
VSS − 0.3 to VDD + 0.3
450*1
700*1
−40 to +85
⎯
−40 to +125
°C
Input voltage between VDD and VSS
Input pin voltage
CO output pin voltage
SNT-8A
Power dissipation
8-Pin TSSOP
Operation ambient temperature
PD
⎯
Topr
Storage temperature
Tstg
V
V
V
mW
mW
°C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Name :
JEDEC STANDARD51-7
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
800
Power Dissipation (PD) [mW]
Caution
8-Pin TSSOP
600
SNT-8A
400
200
0
0
150
100
50
Ambient Temperature (Ta) [°C]
Figure 6 Power Dissipation of Package (When Mounted on Board)
9
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Electrical Characteristics
1. Except Detection Delay Time
Table 9
Item
Symbol
Condition
(Ta = 25°C unless otherwise specified)
Test
Test
Max.
Unit
Condition Circuit
Min.
Typ.
VCUn−0.025
VCUn
VCUn+0.025
V
1
1
VCUn−0.030
VCUn
VCUn+0.030
V
1
1
DETECTION VOLTAGE
Overcharge detection
voltage n
(n = 1, 2, 3, 4)
Overcharge hysteresis
voltage n*2
(n = 1, 2, 3, 4)
INPUT VOLTAGE
Operation voltage between
VDD and VSS
CTL input “H” voltage
CTL input “L” voltage
INPUT CURRENT
Current consumption during
operation
Current consumption during
overdischarge
SENSE pin current
VC1 pin current
VC2 pin current
VC3 pin current
CTL pin “H” current
CTL pin “L” current
OUTPUT CURRENT
CO pin sink current
CO pin source current
VCUn
4.200 V to 4.800 V,
adjustable,
Ta = 25°C
4.200 V to 4.800 V,
adjustable,
Ta = −5°C to +55°C*1
VHCn
⎯
VHCn−0.210
−0.520
VHCn+0.210
V
1
1
VDSOP
⎯
3.6
⎯
24
V
⎯
⎯
VCTLH
VCTLL
⎯
⎯
VDD×0.95
⎯
⎯
⎯
⎯
VDD×0.4
V
V
6
6
2
2
IOPE
V1 = V2 = V3 = V4 = 3.5 V
⎯
2.5
5.0
μA
7
4
IOPED
V1 = V2 = V3 = V4 = 2.3 V
⎯
2.0
4.0
μA
7
4
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
V1 = V2 = V3 = V4 = 3.5 V
A/B Series
V1 = V2 = V3 = V4 = 3.5 V,
VCTL = VDD
C Series
V1 = V2 = V3 = V4 = 3.5 V
VCTL = VDD
A/B Series
V1 = V2 = V3 = V4 = 3.5 V,
VCTL = 0 V
C Series
V1 = V2 = V3 = V4 = 3.5 V
VCTL = 0 V
⎯
−0.3
−0.3
−0.3
1.5
0
0
0
3.2
0.3
0.3
0.3
μA
μA
μA
μA
8
8
8
8
5
5
5
5
1.1
1.5
1.8
μA
8
5
⎯
⎯
0.15
μA
8
5
−0.15
⎯
⎯
μA
8
5
−150
−50
−10
μA
8
5
0.4
20
⎯
⎯
⎯
⎯
mA
μA
9
9
6
6
ISENSE
IVC1
IVC2
IVC3
ICTLH
ICTLL
ICOL
ICOH
VCOP = VSS+0.5 V
VCOP = VDD−0.5 V
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*2. −0.390 ±0.160 V, −0.260 ±0.110 V, −0.130 ±0.060 V, or none, except for −0.520 V hysteresis product circuits. The
overcharge release voltage is the total of the overcharge detection voltage (VCUn) and the overcharge hysteresis voltage
(VHCn).
10
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
2. Detection Delay Time
(1) S-8264AAA, S-8264AAB, S-8264AAC, S-8264AAE, S-8264AAH, S-8264BAA, S-8264BAB, S-8264BAC
Table 10
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
Condition Circuit
Symbol
Condition
Min.
DELAY TIME
Overcharge detection delay time
Overcharge timer reset delay time
Overcharge release delay time
CTL pin response time
tCU
tTR
tCL
tCTL
3.2
6
51
⎯
4.0
12
64
⎯
4.8
20
77
2.5
s
ms
ms
ms
2
3
2
4
1
1
1
2
Transition time to Test mode
tTST
⎯
⎯
⎯
⎯
V1 = V2 = V3 = V4 = 3.5 V,
VDD ≥ VSENSE + 8.5 V
⎯
⎯
80
ms
5
3
Item
(2) S-8264AAD, S-8264AAF, S-8264AAG, S-8264AAI, S-8264CAA, S-8264CAB
Table 11
Item
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
Condition Circuit
Symbol
Condition
Min.
DELAY TIME
Overcharge detection delay time
Overcharge timer reset delay time
Overcharge release delay time
CTL pin response time
tCU
tTR
tCL
tCTL
1.6
6
1.6
⎯
2.0
12
2.0
⎯
2.4
20
3.0
2.5
s
ms
ms
ms
2
3
2
4
1
1
1
2
Transition time to Test mode
tTST
⎯
⎯
⎯
⎯
V1 = V2 = V3 = V4 = 3.5 V,
VDD ≥ VSENSE + 8.5 V
⎯
⎯
80
ms
5
3
(3) S-8264AAJ, S-8264AAK, S-8264AAO, S-8264AAS, S-8264AAT, S-8264AAV
Table 12
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
Condition Circuit
Symbol
Condition
Min.
DELAY TIME
Overcharge detection delay time
Overcharge timer reset delay time
Overcharge release delay time
CTL pin response time
tCU
tTR
tCL
tCTL
4.5
8
70
⎯
5.65
17
88
⎯
6.8
28
110
2.5
s
ms
ms
ms
2
3
2
4
1
1
1
2
Transition time to Test mode
tTST
⎯
⎯
⎯
⎯
V1 = V2 = V3 = V4 = 3.5 V,
VDD ≥ VSENSE + 8.5 V
⎯
⎯
80
ms
5
3
Item
(4) S-8264AAW
Table 13
Item
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
Condition Circuit
Symbol
Condition
Min.
DELAY TIME
Overcharge detection delay time
Overcharge timer reset delay time
Overcharge release delay time
CTL pin response time
tCU
tTR
tCL
tCTL
1.6
6
51
⎯
2.0
12
64
⎯
2.4
20
77
2.5
s
ms
ms
ms
2
3
2
4
1
1
1
2
Transition time to Test mode
tTST
⎯
⎯
⎯
⎯
V1 = V2 = V3 = V4 = 3.5 V,
VDD ≥ VSENSE + 8.5 V
⎯
⎯
80
ms
5
3
11
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Test Circuits
(1) Test Condition 1, Test Circuit 1
Set V1, V2, V3, and V4 to 3.5 V. Overcharge detection voltage 1 (VCU1) is the V1 voltage when CO is “H” after the
voltage of V1 has been gradually increased. The overcharge hysteresis voltage (VHC1) is the difference between V1
and VCU1 when CO is “L” after the voltage of V1 has been gradually decreased.
Overcharge detection voltage VCUn (n = 2 to 4) and overcharge hysteresis VHCn (n = 2 to 4) can be determined in the
same way as when n = 1.
(2) Test Condition 2, Test Circuit 1
Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 μs) increase V1 up to 5.0 V. The overcharge
detection delay time (tCU) is the period from when V1 reached 5.0 V to when CO becomes “H”. After that, in a moment
of time (within 10 μs) decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the period from when V1
has reached 3.5 V to when CO becomes “L”.
(3) Test Condition 3, Test Circuit 1
Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 μs) increase V1 up to 5.0 V. This is defined as the
first rise. Within tCU − 20 ms after the first rise, in a moment of time (within 10 μs) decrease V1 down to 3.5 V and then
in a moment of time (within 10 μs) restore up to 5.0 V. This is defined as the second rise. When the period from when
V1 was fallen to the second rise is short, CO becomes “H” after tCU has elapsed since the first rise. If the period from
when V1 falls to the second rise is gradually made longer, CO becomes “H” when tCU has elapsed since the second rise.
The overcharge timer reset delay time (tTR) is the period from V1 fall till the second rise at that time.
(4) Test Condition 4, Test Circuit 2
In the S-8264A/C Series, set V1, V2, V3, and V4 to 3.5 V and V5 to 14 V. The CTL pin response time (tCTL) is the period
from when V5 reaches 0 V after V5 is in a moment of time (within 10 μs) decreased down to 0 V to when CO becomes
“H”.
In the S-8264B Series, set V1, V2, V3, and V4 to 3.5 V and V5 to 14 V after an overvoltage is detected and CO becomes
“H”. In a moment of time (within 10 μs) raise V5 from 0 V to 14 V. The CTL pin response time (tCTL) is the period from
when V5 becomes 14 V to when CO becomes “L”.
(5) Test Condition 5, Test Circuit 3
After setting V1, V2, V3, and V4 to 3.5 V and V5 to 0 V, in a moment of time (within 10 μs) increase V5 up to 8.5 V and
decrease V5 again down to 0 V. When the period from when V5 was raised to when it has fallen is short, if an
overcharge detection operation is performed subsequently, the overcharge detection time is tCU. However, when the
period from when V5 is raised to when it is fallen is gradually made longer, the overcharge detection time during the
subsequent overcharge detection operation is shorter than tCU. The transition time to test mode (tTST) is the period from
when V5 was raised to when it has fallen at that time.
12
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
(6) Test Condition 6, Test Circuit 2
Set V1, V2, V3, and V4 to 3.5 V and V5 to 0 V. The CTL input “H” voltage (VCTLH) is the maximum voltage of V5 when
CO is “L” after V5 has been gradually increased. Next, set V5 to 14 V. The CTL input “L” voltage (VCTLL) is the minimum
voltage of V5 when CO is “H” after V5 has been gradually decreased.
(7) Test Condition 7, Test Circuit 4
The current consumption during operation (IOPE) is the total of the currents that flow in the VDD pin and SENSE pin
when V1, V2, V3, and V4 are set to 3.5 V.
The current consumption during overdischarge (IOPED) is the total of the currents that flow in the VDD pin and SENSE
pin when V1, V2, V3, and V4 are set to 2.3 V.
(8) Test Condition 8, Test Circuit 5
The SENSE pin current (ISENSE) is I1, the VC1 pin current (IVC1) is I2, the VC2 pin current (IVC2) is I3, the VC3 pin current
(IVC3) is I4, and the CTL pin “H” current (ICTLH) is I5 when V1, V2, V3, and V4 are set to 3.5 V, and V5 to 14 V.
The CTL pin “L” current (ICTLL) is I5 when V1, V2, V3, and V4 are set to 3.5 V and V5 to 0 V.
(9) Test Condition 9, Test Circuit 6
Set SW1 to OFF and SW2 to ON. The CO pin sink current (ICOL) is I2 when V1, V2, V3, and V4 are set to 3.5 V and V6
to 0.5 V.
Set SW1 and SW2 to OFF. Set V1 to V5, set V2, V3, and V4 to 3.0 V, and set V5 to 0.5 V. After tCU has elapsed, set
SW1 to ON and SW2 to OFF. I1 is the CO pin source current (ICOH).
13
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
S-8264A/B/C Series
S-8264A/B/C Series
VDD
CO
VDD
SENSE
CTL
V
V1
VSS
VC1
V4
V2
CO
SENSE
CTL
V1
VC1
VSS
VC2
VC3
V5
V
V4
V2
VC3
VC2
Rev.4.6_00
V3
V3
Test Circuit 1
Test Circuit 2
S-8264A/B/C Series
S-8264A/B/C Series
VDD
VDD
CO
CO
A
V5
SENSE
CTL
V
V1
VC1
VSS
V4
V2
VC2
SENSE
CTL
VC1
VSS
VC2
VC3
V1
V4
V2
VC3
V3
V3
Test Circuit 3
Test Circuit 4
V5
A I1
S-8264A/B/C Series
I1
A
V1
V2
VDD
CO
SENSE
CTL
VC1
VSS
A
A
V5
I4
I3
VC2
VC3
V3
VDD
I5
I2
A
V4
CO
SENSE
CTL
VC1
VSS
VC2
VC3
SW2
V1
V2
A
V3
Test Circuit 5
Test Circuit 6
Figure 7
14
SW1
S-8264A/B/C Series
V4
A I2
V6
V
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Operation
Remark Refer to “ Battery Protection IC Connection Example”.
1. Overcharge Detection
When the voltage of one of the batteries exceeds the overcharge detection voltage (VCU) during charging under normal
conditions and the state is retained for the overcharge detection delay time (tCU) or longer, CO becomes “H”. This state
is called overcharge. Connecting FET to the CO pin provides charge control and a second protection.
In the S-8264A/C Series, if the voltage of each of the batteries is lower than VCU + the overcharge hysteresis voltage
(VHC) and the state is retained for the overcharge release delay time (tCL) or longer, CO becomes “L”.
In the S-8264B Series, if the voltage of each of the batteries is lower than VCU + VHC and the state is retained for tCL or
longer, the overcharge state is released; however, CO stays at “H”. When the CTL pin is switched from “L” to “H”, CO
becomes “L”.
2. Overcharge Timer Reset Operation
When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during
tCU from when VCU is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge
release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time
the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCU has been
exceeded, counting tCU resumes.
15
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
3. CTL Pin
The S-8264A/B/C Series has a control pin. The CTL pin is used to control the output voltage of the CO pin.
In the S-8264A/C Series, the CTL pin takes precedence over the overcharge detection circuit.
In the S-8264B Series, when the CTL pin is switched from “L” to “H”, a reset signal is output to the overcharge detection
latch and CO becomes “L”.
Table 14 Control via CTL Pin
CTL Pin
“H”
Open
“L”
“L”→“H”
“H”→“L”
S-8264A Series
Normal state*1
“H”
“H”
−
−
CO Pin
S-8264B Series
Without latch
Normal state*1
Normal state*1
Latch reset*2
−
S-8264C Series
Normal state*1
Normal state*1
“H”
−
−
*1. The state is controlled by the overcharge detection circuit.
*2. Latch reset becomes effective when the voltage of each of the batteries is lower than the overcharge detection
voltage (VCU) + the overcharge hysteresis voltage (VHC) and the overcharge release delay time (tCL) has
elapsed.
–
CTL
*1
+
–
CTL
*1
+
Pull-up resistor
Pull-down resistor
S-8264A/B Series
S-8264C Series
*1. The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage − 2.8 V (Typ.), does not have the
hysteresis.
Figure 8 Internal Equivalent Circuit of CTL Pin
Caution
1. In the S-8264A/B Series, since the CTL pin implements high resistance of 8 MΩ to 12 MΩ for
pull down, be careful of external noise application. If an external noise is applied, CO may
become “H”. Perform thorough evaluation using the actual application.
2. In the S-8264B Series, when the CTL pin is open or “L”, CO latches “H”. When the VDD pin
voltage is decreased to the UVLO voltage of 2 V (Typ.) or lower, the latch is reset.
16
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
4. Test Mode
In the S-8264A/B/C Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at least
80 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = 25°C). The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin.
When CO becomes “H” when the delay time has elapsed after overcharge detection, the latch for retaining the test
mode is reset and the S-8264A/B Series exits from the test mode.
VDD pin voltage
SENSE pin voltage
8.5 V or
more
Pin voltage
VCUn
VHCn
Battery voltage
(n = 1 to 4)
Test mode
tTST = 80 ms max.
CO pin
*1
tCL
*1. In the product tCU = 4 s Typ. during normal mode, tCU = 64 ms Typ.
In the product tCU = 2 s Typ. during normal mode, tCU = 32 ms Typ.
In the product tCU = 5.65 s Typ. during normal mode, tCU = 88 ms Typ.
Figure 9
Caution
1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the
S-8264A/B/C Series returns to the normal mode.
2. Set the test mode when no batteries are overcharged.
3. The overcharge release delay time (tCL) is not shortened in the test mode.
4. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
17
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Timing Charts
1. Overcharge Detection Operation
(1) S-8264A/C Series
VHCn
VCUn
Battery voltage
(n = 1 to 4)
CTL pin
tTR or
longer
CO pin
tCU or shorter
tTR or shorter
tCU
tCL
Figure 10
(2) S-8264B Series
VHCn
VCUn
Battery voltage
(n = 1 to 4)
Reset operation disabled
Reset operation enabled
CTL pin
CO pin
tTR or
longer
tCU or shorter
tTR or shorter
tCU
Figure 11
18
tCL
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
2. Overcharge Timer Reset Operation
VHCn
tTR or
shorter
tTR or
longer
tTR or shorter
VCUn
Battery voltage
(n = 1 to 4)
tTR
CO pin
tCU or
shorter
tCU
Timer reset
Figure 12
19
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Battery Protection IC Connection Example
(1) 4-serial cell
SCP
EB+
VDD
RVDD
CVDD
SENSE
BAT1
BAT2
R1
R2
C1
C2
VC1
S-8264A/B/C
VC2
BAT3
R3
Series
C3
VC3
BAT4
R4
FET
CO
DP
C4
VSS
CTL
External
input*1
RCTL
EB−
Figure 13
*1.
Refer to Table 14 for setting on external input.
Table 15 Constants for External Components
No.
1
2
3
4
Caution
20
Part
R1 to R4
C1 to C4, CVDD
RVDD
RCTL
Min.
0.1
0.01
50
0
Typ.
1
0.1
100
100
Max.
10
1
500
500
Unit
kΩ
μF
Ω
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. Set the same constants to R1 to R4 and to C1 to C4 and CVDD.
4. Set RVDD, C1 to C4, and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied.
5. Set R1 to R4, C1 to C4, and CVDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is
satisfied.
6. Since “H” may be output at CO transiently when the battery is being connected, connect the
positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
(2) 3-serial cell
SCP
EB+
VDD
RVDD
CVDD
SENSE
BAT1
BAT2
R1
R2
C1
C2
VC1
S-8264A/B/C
VC2
BAT3
R3
Series
FET
C3
VC3
CO
DP
VSS
CTL
External R
CTL
input*1
EB−
Figure 14
*1.
Refer to Table 14 for setting on external input.
Table 16 Constants for External Components
No.
1
2
3
4
Caution
Part
R1 to R3
C1 to C3, CVDD
RVDD
RCTL
Min.
0.1
0.01
50
0
Typ.
1
0.1
100
100
Max.
10
1
500
500
Unit
kΩ
μF
Ω
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. Set the same constants to R1 to R3 and to C1 to C3 and CVDD.
4. Set RVDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied.
5. Set R1 to R3, C1 to C3, and CVDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is
satisfied.
6. Since “H” may be output at CO transiently when the battery is being connected, connect the
positive terminal of BAT1 last in order to prevent the three terminal protection fuses from cutoff.
21
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
(3) 2-serial cell
SCP
EB+
VDD
RVDD
CVDD
SENSE
BAT1
BAT2
R1
R2
C1
C2
VC1
S-8264A/B/C
VC2
Series
VC3
FET
CO
DP
VSS
CTL
External
input*1
RCTL
EB−
Figure 15
*1.
Refer to Table 14 for setting on external input.
Table 17 Constants for External Components
No.
1
2
3
4
Caution
22
Part
R1 and R2
C1 and C2, CVDD
RVDD
RCTL
Min.
0.1
0.01
50
0
Typ.
1
0.1
100
100
Max.
10
1
500
500
Unit
kΩ
μF
Ω
Ω
1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the
connection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.
3. Set the same constants to R1 and R2 and to C1 and C2 and CVDD.
4. Set RVDD, C1 and C2, and CVDD so that the condition (RVDD) × (C1 and C2, CVDD) ≥ 5 × 10−6 is
satisfied.
5. Set R1 and R2, C1 and C2, and CVDD so that the condition (R1 and R2) × (C1 and C2, CVDD) ≥ 1 ×
10−4 is satisfied.
6. Since “H” may be output at CO transiently when the battery is being connected, connect the
positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Precautions
•
Do not connect batteries charged with VCU + VHC or higher. If the connected batteries include a battery charged with
VCU + VHC or higher, “H” may be output at CO after all pins are connected.
•
In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough
evaluation with the actual application circuit.
•
In the S-8264B Series, “H” may be output at CO after all the pins are connected. In this case, set the CTL pin from “L”
to “H”.
•
Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figure in “ Battery
Protection IC Connection Example”.
•
The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
•
Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
•
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
23
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Example of Application Circuit
1. Overheat Protection via PTC (S-8264A Series)
SCP
EB+
VDD
RVDD
CVDD
SENSE
BAT1
R1
C1
VC1
BAT2
R2
S-8264A
C2
VC2
BAT3
R3
Series
FET
C3
VC3
BAT4
R4
CO
DP
C4
CCTL
VSS
CTL
PTC
EB−
Figure 16
Cautions 1. The above connection example will not guarantee successful operation. Perform thorough
evaluation using the actual application.
2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in
the S-8264A Series, connect the PTC before connecting batteries.
3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the
S-8264A Series.
4. Since “H” may be output at CO transiently when the battery is being connected, connect the
positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL +81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
[For PTC, contact]
Murata Manufacturing Co., Ltd.
Thermistor Products Department
Nagaokakyo-shi, Kyoto, 617-8555, Japan
TEL +81-75-955-6863
Contact Us: http://www.murata.com/contact/index.html
24
Rev.4.6_00
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Characteristics (Typical Data)
1. Detection Voltage vs. Temperature
(1) Overcharge Detection Voltage vs. Temperature
VCU = 4.3 V
4.40
VCU − VHC [V]
VCU [V]
4.35
4.30
4.25
4.20
40 25
0
25
Ta [C]
50
2.0
1.0
40 25
25
Ta [C]
50
40 25
0
25
Ta [C]
50
75 85
3.0
2.0
1.0
75 85
40 25
0
25
Ta [C]
50
75 85
(2) Overcharge Release Delay Time vs. Temperature
VDD = 14 V
90
80
tCL [ms]
5.0
tCU [s]
3.75
0.0
0
3. Delay Time vs. Temperature
(1) Overcharge Detection Delay Time vs. Temperature
VDD = 20 V
6.0
4.0
3.0
2.0
3.80
(2) Current Consumption during Overdischarge vs. Temperature
VDD = 9.2 V
4.0
IOPED [μA]
IOPE [μA]
3.0
3.85
3.70
75 85
2. Current Consumption vs. Temperature
(1) Current Consumption during Normal Operation vs. Temperature
VDD = 14 V
4.0
0.0
(2) Overcharge Release Voltage vs. Temperature
VHC = 0.52 V
3.90
70
60
50
40
40 25
30
0
25
Ta [C]
50
75 85
40 25
0
25
Ta [C]
50
75 85
25
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
4. Output Current vs. Temperature
(1) CO Pin Sink Current vs. VDD
(2) CO Pin Source Current vs. VDD
Ta = 25 °C
10.0
5.0
2.5
0.0
10
15
VDD [V]
5
20
500
250
25
5. CTL Pin vs. Temperature
(1) CTL Pin Threshold Voltage vs. Temperature
VDD = 14 V
12.0
11.5
0
11.0
10.5
40 25
25
Ta [C]
50
75 85
20
25
12.0
10.0
8.0
6.0
0
10
15
VDD [V]
5
(2) CTL Pin Input Resistance vs. Temperature
VDD = 14 V
14.0
RCTL [M]
VTH.CTL [V]
700
0
0
26
Ta = 25 °C
1000
ICOH [μA]
ICOL [mA]
7.5
10.0
Rev.4.6_00
40 25
0
25
Ta [C]
50
75 85
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
Marking Specifications
(1) SNT-8A
Top view
8
7
6
5
(1)
(2) to (4)
(1) (2) (3) (4)
(5) (6) (7) (8)
(5), (6)
(7) to (11)
Blank
Product code (Refer to Product name vs.
Product code)
Blank
Lot number
(9) (10) (11)
1
2
3
4
Product name vs. Product code
(b) S-8264B Series
(a) S-8264A Series
Product Name
S-8264AAA-I8T1U
S-8264AAB-I8T1U
S-8264AAC-I8T1U
S-8264AAD-I8T1U
S-8264AAE-I8T1U
S-8264AAF-I8T1U
S-8264AAG-I8T1U
S-8264AAH-I8T1U
S-8264AAI-I8T1U
S-8264AAJ-I8T1U
S-8264AAK-I8T1U
S-8264AAO-I8T1U
S-8264AAS-I8T1U
S-8264AAT-I8T1U
S-8264AAV-I8T1U
S-8264AAW-I8T1U
(2)
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Product Code
(3)
(4)
5
A
5
B
5
C
5
D
5
E
5
F
5
G
5
H
5
I
5
J
5
K
5
O
5
S
5
T
5
V
5
W
Product Name
S-8264BAA-I8T1U
S-8264BAB-I8T1U
S-8264BAC-I8T1U
(2)
Q
Q
Q
Product Code
(3)
(4)
6
A
6
B
6
C
(c) S-8264C Series
Product Name
S-8264CAA-I8T1U
S-8264CAB-I8T1U
Product Code
(2)
Q
Q
(3)
7
7
(4)
A
B
27
BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION)
S-8264A/B/C Series
Rev.4.6_00
(2) 8-Pin TSSOP
Top view
1
(1) (2) (3) (4)
2
(5) (6) (7) (8)
3
(9) (10) (11) (12) (13) (14)
4
8
7
(1) to (5)
(6) to (8)
(9) to (14)
Product name: S8264 (Fixed)
Function code
Lot number
6
5
Product name vs. Product code
(b) S-8264B Series
(a) S-8264A Series
Product Name
S-8264AAA-T8T1x
S-8264AAB-T8T1x
S-8264AAK-T8T1U
Remark
28
(6)
A
A
A
Product Code
(7)
(8)
A
A
A
B
A
K
Product Name
S-8264BAB-T8T1x
(6)
B
Product Code
(7)
(8)
A
B
1. x: G or U
2. Please select products of environmental code = U for Sn 100%, halogen-free products.
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.25±0.05
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.3
3.00 -0.2
8
5
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
8.0±0.1
ø1.55 -0.05
(4.4)
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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