STK17TA8-RF45

THIS SPEC IS OBSOLETE Spec No: 001-52039 Spec Title: STK17TA8 128K X 8 AUTOSTORE NVSRAM WITH REAL TIME CLOCK Sunset Owner: Girija Chougala (GVCH) Replaced by: None STK17TA8 128k X 8 AutoStore nvSRAM with Real Time Clock Features Description ■ nvSRAM Combined with Integrated Real Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor) ■ Capacitor or Battery Backup for RTC The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM (nvSRAM) with a full featured real time clock in a reliable, monolithic integrated circuit. ■ 25 ns [1], 45 ns Read Access and Read/Write Cycle Time ■ Unlimited Read/Write Endurance ■ Automatic nonvolatile STORE on Power Loss ■ Nonvolatile STORE Under Hardware or Software Control ■ Automatic RECALL to SRAM on Power Up ■ Unlimited RECALL Cycles ■ 200K STORE Cycles ■ 20-Year nonvolatile Data Retention ■ Single 3 V +20%, -10% Power Supply ■ Commercial and Industrial Temperatures ■ 48-pin 300-mil SSOP Package (RoHS-Compliant) The 1 Mb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control. Logic Block Diagram VCC VCAP Quantum Trap 1024 X 1024 ROW DECODER A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 POWER CONTROL STORE STATIC RAM ARRAY 1024 X 1024 RECALL STORE/ RECALL CONTROL VRTCbat VRTCcap HSB SOFTWARE DETECT INPUT BUFFERS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A15 – A0 COLUMN I/O COLUMN DEC RTC X1 X2 INT A0 A 1 A 2 A3 A 4 A10 A11 MUX A16 – A0 G E W Note 1. 25 ns speed in Industrial temperature range is over the operating voltage range of 3.3V+ 0.3V only. Cypress Semiconductor Corporation Document #: 001-52039 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 02, 2011 STK17TA8 Contents Features ................................................................................1 Description ...........................................................................1 Logic Block Diagram ...........................................................1 Contents ...............................................................................2 Pinouts .................................................................................3 Pin Descriptions ..................................................................3 Absolute Maximum Ratings ...............................................4 DC Electrical Characteristics .............................................4 AC Test Conditions .............................................................5 Capacitance .........................................................................5 RTC DC Characteristics ......................................................6 SRAM READ Cycles #1 and #2 ...........................................7 SRAM WRITE Cycles #1 and #2 .........................................8 AutoStore/Power Up Recall ................................................9 Software-Controlled STORE/RECALL Cycle ...................10 Hardware STORE Cycle ....................................................11 Soft Sequence Commands ...............................................11 MODE Selection .................................................................12 nvSRAM Operation ............................................................13 SRAM READ ................................................................ 13 SRAM WRITE .............................................................. 13 AutoStore Operation..................................................... 13 Hardware STORE (HSB) Operation............................. 13 Hardware RECALL (POWER UP)................................ 13 Software STORE...........................................................13 Software RECALL ........................................................ 14 Data Protection............................................................. 14 Document #: 001-52039 Rev. *D Noise Considerations ................................................... 14 Preventing AutoStore ................................................... 14 Best Practices .............................................................. 14 Low Average Active Power ...........................................14 RTC Operations .................................................................15 Real Time Clock ........................................................... 15 Reading The Clock....................................................... 15 Setting The Clock ..........................................................15 Backup Power .............................................................. 15 Stopping And Starting The RTC Oscillator................... 15 Calibrating The Clock ................................................... 16 Alarm .............................................................................16 Watchdog Timer ........................................................... 16 Power Monitor .............................................................. 16 Interrupts ...................................................................... 17 Interrupt Register.......................................................... 17 Flags Register .............................................................. 17 RTC Register ......................................................................18 Register Map Detail ...........................................................19 Ordering Information .........................................................22 Ordering Codes .................................................................22 Package Diagrams .............................................................23 Document History Page ....................................................24 Sales, Solutions, and Legal Information .........................24 Worldwide Sales and Design Support.......................... 24 Products ....................................................................... 24 Page 2 of 24 STK17TA8 Pinouts Figure 1. Pin Diagram - 48-PIn SSOP V CAP 1 48 2 47 V CC A 15 3 46 A 12 A7 HSB 4 5 45 44 A6 6 43 W A 13 A8 7 42 A9 INT 8 41 NC A4 A 16 A 14 A5 9 40 A 11 NC 10 39 NC NC 11 38 NC NC V SS 12 37 13 36 NC V RTCbat 14 35 34 DQ 0 15 NC V SS NC V RTCcap 16 33 DQ 6 A3 17 32 A2 18 31 G A 10 A1 19 30 A0 DQ 1 DQ 2 20 29 E DQ 7 21 28 DQ 5 27 DQ 4 X1 22 23 26 X2 24 25 DQ 3 V CC (TOP) Relative PCB Area Usage[2] Pin Descriptions Pin Name I/O Type Description A16-A0 Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes in the clock register map DQ7-DQ0 I/O E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tristate. X1 Output X2 Input Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC Crystal Connection, drives crystal on startup Crystal Connection for 32.768 kHz crystal VRTCcap Power Supply Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used) VRTCbat Power Supply Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used) VCC Power Supply Power: 3.0V, +20%, -10% HSB I/O INT Output Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. Programmable to either active high (push/pull) or active low (open-drain) VCAP Power Supply Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground NC No Connect Unlabeled pins have no internal connections. Note 2. For detailed package size specifications, See “Package Diagrams” on page 23.. Document #: 001-52039 Rev. *D Page 3 of 24 STK17TA8 Absolute Maximum Ratings Note Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground ................–0.1V to 4.1V Voltage on Input Relative to VSS .........–0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB.....................–0.5V to (VCC + 0.5V) Temperature under Bias ............................... –55C to 125C Junction Temperature ................................... –55C to 140C Storage Temperature .................................... –65C to 150C Power Dissipation............................................................. 1W DC Output Current (1 output at a time, 1s duration).... 15 mA RF (SSOP-48) Package Thermal Characteristics jc 6.2 C/W; ja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm] DC Electrical Characteristics (VCC = 2.7V-3.6V) Symbol Parameter Commercial Min Max 65 50 Industrial Min Max 70 55 Units Notes mA mA tAVAV = 25 ns tAVAV = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care, VCC = max Average current for duration of STORE cycle (tSTORE) W  (V CC – 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE) E VCC -0.2V) All Others VIN0.2V or  (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = – 2 mA (except HSB) IOUT = 4 mA ICC1 Average VCC Current ICC2 Average VCC Current during STORE 3 3 mA ICC3 Average VCC Current at tAVAV = 200ns 3V, 25°C, Typical 10 10 mA ICC4 Average VCAP Current during AutoStore™ Cycle 3 3 mA ISB VCC Standby Current (Standby, Stable CMOS Levels) 3 3 mA IILK Input Leakage Current ±1 ±1 mA IOLK Off-State Output Leakage Current ±1 ±1 mA VIH VIL VOH VOL Note Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage 2.0 VCC + 0.5 2.0 VCC + 0.5 VSS –0.5 0.8 VSS –0.5 0.8 2.4 2.4 0.4 0.4 V V V V ■ The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested. ■ The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below. Document #: 001-52039 Rev. *D Page 4 of 24 STK17TA8 DC Electrical Characteristics (continued) (VCC = 2.7V-3.6V) TA VCC VCAP Operating Temperature Operating Voltage Storage Capacitance Commercial Min Max 0 70 2.7 3.6 17 57 NVC DATAR Nonvolatile STORE operations Data Retention 200 20 Symbol Parameter Industrial Min Max – 40 85 2.7 3.6 17 57 Units 200 20 K Years At 55 C C V F Notes 3.0V +20%, -10% Between VCAP pin and VSS, 5V rated. AC Test Conditions Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times ............................................