LV5768V-A
Bi-CMOS IC
1-channel Step-down Switching
Regulator
www.onsemi.com
Overview
The LV5768V-A is a 1-channel step-down switching regulator.
Feature
1 channel step-down switching regulator controller.
Frequency decrease function at pendent.
Load-independent soft start circuit.
ON/OFF function.
Built-in pulse-by-pulse OCP circuit.
It is detected by using ON resistance of an external MOS.
Synchronous rectification
Current mode control
SSOP16(225mil)
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
Symbol
Conditions
VIN max
Allowable pin voltage
VIN, SW
Ratings
Unit
45
V
45
V
HDRV, CBOOT
52
V
LDRV
6.0
V
Between CBOOT to SW
6.0
V
Between CBOOT to HDRV
EN, ILIM
Between VIN to ILIM
VDD
SS, FB, COMP,RT
Mounted on a specified board. *1
VIN+0.3
V
1.0
V
6.0
V
VDD+0.3
V
Allowable Power dissipation
Pd max
0.74
W
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-55 to +150
C
*1 Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
February 2015 - Rev. 0
1
Publication Order Number :
LV5678V-A/D
LV5768V-A
Recommended Operating Range at Ta = 25C
Parameter
Symbol
Supply voltage range
VIN
Error amplifier input voltage
VFB
Oscillatory frequency
FOSC
Conditions
Ratings
Unit
8.5 to 42
0 to 1.6
80 to 500
V
V
kHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta 25C, VIN = 12V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Reference voltage block
Internal reference voltage
Vref
Including offset of E/A
0.654
0.67
0.686
V
5V power supply
VDD
IOUT = 0 to 5mA
4.7
5.2
5.7
V
Oscillation frequency
FOSC
RT=220kΩ
110
125
140
kHz
Frequency variation
FOSC DV
VIN = 8.5 to 42V
Oscillation frequency fold back
VOSC FB
FB voltage detection after SS ends
Triangular waveform oscillator block
1
%
0.1
V
detection voltage
Oscillation frequency after fold back
FOSC FB
1/3FOSC
kHz
ON/OFF circuit block
IC start-up voltage
VEN on
2.5
3.0
3.5
V
IC off voltage
VEN off
1.0
1.2
1.4
V
4
5
6
A
Soft start circuit block
Soft start source current
ISS SC
EN 3.5V
Soft start sink current
ISS SK
EN 1V, VDD = 5V
2
mA
UVLO circuit block
UVLO lock release voltage
VUVLO
UVLO hysteresis
VUVLO H
8
V
0.7
V
Error amplifier
Input bias current
IEA IN
Error amplifier gain
GEA
1000
Sink output current
IEA OSK
FB = 1.0V
Source output current
IEA OSC
FB = 0V
Current detection amplifier gain
GISNS
1400
100
nA
1800
A/V
-100
A
100
A
1.5
over current limiter circuit block
Reference current
ILIM1
Over current detection comparator
VLIM OFS
+10%
A
-5
+5
mV
VIN-0.45
VIN
V
-10%
18.5
offset voltage
Over current detection comparator
common mode input range
PWM comparator
Input threshold voltage
(FOSC=125kHz)
Vt max
Duty cycle = DMAX
0.9
1.0
1.1
V
Vt0
Duty cycle = 0%
0.4
0.5
0.6
V
Maximum ON duty
DMAX
86
90
95
%
Output block
Output stage ON resistance
RONH
5
RONL
5
(the upper side)
Output stage ON resistance
(the lower side)
Output stage ON current
IONH
240
mA
IONL
240
mA
(the upper side)
Output stage ON current
(the lower side)
Continued on next page
No.A2093-2/2
LV5768V-A
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
The whole device
Standby current
ICCS
EN 1V
Mean consumption current
ICCA
EN 3.5V
TSD on
TSD hys
10
A
3
mA
* Design certification
170
C
* Design certification
30
C
Security function
Protection function operating
temperature at high temperature
Protection function hysteresis at high
temperature
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Package Dimensions
unit : mm
SSOP16 (225mil)
CASE 565AM
ISSUE A
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
5.80
1.0
(Unit: mm)
0.32
0.65
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A2093-3/3
LV5768V-A
Pd max -- Ta
Allowable power dissipation, Pd max -- W
1.0
Specified board : 114.3 × 76.1 × 1.6mm3
glass epoxy board.
0.8
0.74
0.6
0.4
0.38
0.2
0
--40
--20
0
20
40
60
8085
100
Ambient temperature, Ta -- C
Pin Assignment
FB 1
16 SS
COMP 2
15 ILIM
EN 3
14 VIN
13 NC
RT 4
NC 5
LV5768V
12 SUBGND
SW 6
11 GND
CBOOT 7
10 VDD
9 LDRV
HDRV 8
Top view
No.A2093-4/4
LV5768V-A
Block Diagram
VIN 14
5V
5V
REGULATOR
REFERENCE
VOLTAGE
TSD
VIN UVLO
VDD UVLO
+
OCP Comp
ILIM 15
18.5uA
1.1V
SD
SS 16
FB 1
0.67V
+
-
SD
0.1V
1.2V
+
Current
Amp
7 CBOOT
8 HDRV
DMAX = 90%
SAW WAVE
OSCILLATOR
fosc forcec
1/3
1.0V
0.5V
6 SW
CONTROL
Logic
+
PWM Comp
5V
10 VDD
9 LDRV
11 GND
0.1V
shut down(SD)
Err
Amp
COMP 2
RT 4
VIN
S Q
R
+
SS Amp
+
+
-
S Q
R
+
-
12 SUBGND
FFOLD
Comp
+
3
EN
Pin Function
Pin No.
1
Pin name
FB
Description
Error amplifier reverse input pin. By operating the converter, the voltage of this pin becomes 0.67V.
The voltage in which the output voltage is divided by an external resistance is applied to this pin. Moreover, when this pin
voltage becomes 0.1V or less after a soft start ends, the oscillatory frequency becomes 1/3.
2
COMP
Error amplifier output pin. Connect a phase compensation circuit between this pin and GND.
3
EN
ON/OFF pin.
4
RT
Oscillation frequency setting pin. Resistance is connected with this pin between GND.
5
N.C.
No connection *2
6
SW
Pin to connect with switching node. A source of external Upper NchMOSFET is connected with a drain of external lower
7
CBOOT
NchMOSFET.
Bootstrap capacitor connection pin. This pin becomes a GATE drive power supply of an external NchMOSFET.
Connect a bypath capacitor between CBOOT and SW.
8
HDRV
An external upper MOSFET gate drive pin.
9
LDRV
An external lower MOSFET gate drive pin.
10
VDD
Power supply pin for an external the lower MOS-FET gate drive.
11
GND
Ground pin. Each reference voltage is based on the voltage of the ground pin.
12
SUBGND
It is connected with the GND pin of 11pin inside. *3
13
N.C.
No connection *2
14
VIN
Power supply pin. This pin is monitored by UVLO function. When the voltage of this pin becomes 8V or more, the IC starts by
15
ILIM
Reference current pin for current detection. The sink current of about 18.5μA flows to this pin.
UVLO function and the soft start function operates.
When a resistance is connected between this pin and VIN outside and the voltage applied to the SW pin is lower than the
voltage of the terminal side of the resistance, the upper NchMOSFET is off by operating the current limiter comparator.
This operation is reset with respect to each PWM pulse.
16
SS
Pin to connect a capacitor for soft start. A capacitor for soft start is charged by using the current of about 5μA.
When this pin voltage becomes about 1.1V, the soft start period is expired. And the frequency fold back function becomes
active.
*2 The problem does not occur even if connected to the GND.
*3 Short-circuit 11pin and 12pin.
No.A2093-5/5
LV5768V-A
I/O pin equivalent circuit chart
Pin No.
Equivalent Circuit
FB,SS
COMP
Continued on next page
No.A2093-6/6
LV5768V-A
Continued from preceding page.
Pin No.
Equivalent Circuit
EN
RT
SW
CBOOT
HDRV
Continued on next page
No.A2093-7/7
LV5768V-A
Continued from preceding page.
Pin No.
Equivalent Circuit
LDRV
VDD
ILIM
No.A2093-8/8
LV5768V-A
Boot sequence, UVLO, and TSD operation
UVLO 8V
7.3V
VIN
VDD=90%
VDD
VREF 0.67V
1.1V
Permisson of Foldback
SS
VOUT
HDRV-SW
LDRV
170 C
140 C
TSD
Sequence of overcurrent protection
VIN
ILIM
SW
Normal
operation
Overcurrent protection operation
Overcurrent protection operation (Foldback
operation)
Soft start section
Normal
operation
Iout
SS
FB
0.67V
FB=0.1V
No.A2093-9/9
LV5768V-A
Sample Application Circuit
VIN=24V, VOUT=12V, IOUT=7A, Fosc=100kHz
VIN=24V
C6=1000pF
VIN
+
C7=1000pF
ILIM
CBOOT
Q1=ATP201
(SANYO)
HDRV
EN
OUT=12V
SW
D2=CMS15
(60V,3A)
SS
COMP
Q2=ATP206
(SANYO)
FB
RT
D1=DSE010
GND
+
C12=47pF
LDRV
VDD
Cx=1nF
GND
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10
LV5768V-A
Part selection and set
1) Output voltage set
Output voltage (VOUT) is shown the equation (1).
22kΩ
R4
VOUT = (1 + R3 )×VREF = (1 + 1.3kΩ )×0.67 (typ)
[V]
(1)
Ex) To set output voltage of 12V, set resistors as follows: R3=1.3kΩ and R4=22kΩ.
2) Soft start set
Soft start capacitor (C5) is obtained by the equation (2).
C5 =
ISS×TSS 5µ×TSS
VREF = 0.67V
[µF]
(2)
ISS: Charge current value, TSS: soft start time
Ex) To set soft start time of 15ms (approx.), set C5=0.1µF.
3) Overcurrent protector set
Overcurrent limit setting resistor (R5) is obtained by the equation (3).
R5 =
Rdson×IL max Rdson×IL max
=
18.5µ
IIlim
[Ω]
(3)
IIlim: ILIM current value,
ILmax: the maximum value of coil current,
Rdson: Ron between drain and source of Q1 (upper Nch MOS FET).
Ron of ATP201 ≈ 23mΩ (when VGS=4.5V at 25°C)
Ex) To set current limit operation point to 11.3A (load current) where coil peak current value is 12A
(approx.), set R5 = 15kΩ. Set an optimum resistor taking variation of ON resistance into consideration
due to temperature change and make sure to confirm it with the user's specific board. For C6, connect a
capacitor of 1000pF to filter unwanted noise for the proper operation of current limiting.
ON resistance of FET
* Rdson of FET has its own temperature coefficient and the resistor becomes higher in proportion to the
temperature.
* To set Rdson value within the range of operating temperature, it is advisable that the user confirm the data sheet
by the FET supplier.
4) How to set oscillation frequency
Oscillation frequency Fosc is adjustable by RT resistor as
shown in the correlation chart as follows:
SW frequency setting range: 80kHz to 500kHz
FOSC -- RT
500
450
Frequency, FOSC - kHz
400
350
300
250
200
150
100
50
0
0
50
100
150
200
250
300
Resistance, RT - kΩ
5) Boot strap capacitor set
For boot strap capacitor C2, use capacitor 100 times larger than Ciss of power MOSFET.
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11
350
400
450
500
LV5768V-A
6) Phase compensation set
Since LV5768V adopts current mode control, low ESR capacitor and solid polymer capacitor such as OS capacitor
can be used as output capacitor with simple phase compensation.
*Frequency characteristics
Frequency characteristics of LV5768V consist of the following transfer functions.
(1) Output resistor divider
; HR
(2) Voltage gain of error amplifier
; GVEA
Current gain (Transconductance)
; GMEA
(3) Impedance of external phase compensation part
; ZC
(4) Current sense loop gain
; GCS
(5) Output smoothing impedance
; ZO
SLOPE
1/GCS
CLK
GVER
ΔVI
VREF
+
GMER
ΔVO
PWM
comparator
+
Current
sense loop
Control logic
OSC
COMP
Error
amplifier
CC
VIN
L
VO
SW
CO
R2
RC
FB
RL
HR
R1
Fig. Current control loop of LV5768V
Closed loop gain is obtained by the equation (4)
G = HR GMEA ZC GCS ZO
RL
VREF
1
GMEA (RC + C ) GCS 1+ C R
R5 = V
S C
S O L
O
(4)
From the equation (4), the frequency characteristics of closed loop gain is given by pole fp1 which consists of output
capacitor Co and output load resistor RL, zero point fz which is given by external resistor Rc and capacitor Cc of
phase compensation pin COMP and pole fp2 which is given by output impedance of error amplifier ZEA and
external phase compensation capacitor Cc. fp1, fz, fp2 are given by the equation (5), (6) and (7).
1
1
1
(7)
fp1 = 2πC R (5), fz = 2πC R (6), fp2 =
2π ZEA CC
C C
O L
*Calculation of the phase compensation by external part RC and CC
In general, the frequency where closed loop gain becomes 1 (zero cross frequency fzc) should be 1/10 of the
switching frequency (or 1/5 at the highest) to stabilize the operation of switching regulator.
Ex) When switching frequency of LV5768V is 100kHz:
fzc =
100kHz
10 ≈ 10kHz
(8)
Since the closed loop gain becomes 1 with this frequency, the equation (7) = 1
RL
VREF
1
G
(R
+
)
G
MEA
C
CS
1+SCORL = 1
VO
SCC
In reality for zero cross frequency, since capacity element
the resistance element RC:
RC »
(9)
1
of phase compensation becomes lower enough than
SCC
1
SCC
(10)
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12
LV5768V-A
The equation (9) becomes
VREF
RL
VO GMEA RC GCS 1+2 fZC CO RL = 1
(11)
From the equation, phase compensation external resistor RC is obtained by the following formula. However,
GCS=0.67/Rdson=29A/V, GMEA=1400µA/V.
Given that output is 12V and load resistor is 1.7Ω (7A load):
VO
1+2 fZC CO RL
1
1
RC = V
RL
REF GMEA GCS
(12)
1+2 10k 1410µ 1.7
12
1
1
= 0.67 1400µA/V 29A/V
1.7
≈ 39kΩ
(13)
This is the external resistor value RC obtained from this calculation (the calculation reveals that the last block where
load resistor RL is inserted is 1 « 2π fZC CO RL. Therefore, there is no dependence on RL.).
When point zero fZ (6) and pole fp1 (5) are the same values, they cancel out each other. Hence, there is only one pole
frequency for the phase characteristics of closed loop gain. In other words, you can obtain characteristics in which
waveform is stable because the gain frequency lowers at -20dB/DEC and phase only rotates by -90 degree.
Since (6) = (5)
fZ = fp1
(14)
1
1
=
2CCRC 2CORL
RL CO 1.7 1410µ
CC = R
=
= 0.062µF
39k
C
The external resistor value RC and capacitor value CC between phase compensator pin COMP and GND is obtained
as such using ideal equations. In reality, stable phase margin should be defined based on testing under the entire
temperature, load and input voltage range. On the other hand, such ideal value is used as starting point for the
assessment. In the deliverable evaluation board, the above values are used as defaults. CC and RC are defined
according to conditions of transient response too. If the influence of noise is significant, it is advisable to increase the
capacitance of CC.
7) Input capacitor selection
When switching of the IC occurs, ripple current flows into the input capacitor of DC-DC converter. Like input
current, the more the output current flows, the more the ripple current into input capacitor flows. Also, the lower the
input voltage is, the more the duty expands. As a result, the ripple current flows more. Allow higher ripple current
than the result of the equation. The input capacitor should be connected adjacent to the power IC and minimize the
inductance from the pattern layout. Root mean squared value is obtained by the equation (15).
Irip_in = D(1-D) IOUT [Arms]
(15)
D represents duty cycle defined by VOUT/VIN.
8) Output capacitor selection
If ceramic capacitor is used to output, output ripple voltage is obtained as follows since ESR of capacitance is small.
Vrip =
VOUT
VOUT
(1- V
) [V]
8 L CO fOSC2
IN
(16)
Also if electrolytic capacitor is used to output, output ripple voltage is affected by ESR since ESR of capacitance is
large. In this case, output ripple voltage is obtained by the following equation.
Vrip =
VIN - VOUT
VOUT RESR
L
fOSC VIN
[V]
Since the allowable ripple current of electrolytic capacitor is lower compared to that of ceramic capacitor, the
allowable ripple current value must not be exceeded. Root mean squared value is obtained by the following
equation.
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13
(17)
LV5768V-A
Irip_out =
1
2
3
VOUT (VIN - VOUT)
L fOSC VIN
[Arms]
(18)
It is advisable to use ceramic capacitor in combination with electrolytic capacitor to reject high frequency noise. The
electrolytic capacitor can be low ESR aluminum electrolytic capacitor or polymer aluminum electrolytic capacitor.
9) Inductor selection
L1: Caution is required due to the heat generation of choke coil caused by overload and load short. The inductance
value is determined by output ripple voltage (Vrip) and the impedance of output capacitor for switching frequency.
The minimum inductance is obtained by the equation (19).
L min =
VIN - VOUT
VOUT RESR
Vrip
fOSC VIN
[µH]
(19)
In the above equation, ESR is used in place of the impedance of output capacitor. The reason is, the impedance of
output capacitor for switching frequency is close to RESR in many cases. However with ceramic capacitor, real
impedance is used instead of RESR.
Ex)VIN(max)=24V, VOUT=12V, Vrip=20mV, RESR=9mΩ, fOSC=100kHz
L min =
24V - 12V
12V 9m
20mV
100k 24V
(20)
≈ 27 [µH]
In the actual part selection, ripple voltage is defined first, then capacitor and inductor are selected. Take the
maximum value and minimum value of input voltage, output voltage and load variation into consideration. Also, the
ripple current of inductor is used as basis for output inductor selection in many cases. Ripple current is obtained by
the equation (21).
Irip =
VIN - VOUT
D [A]
fOSC L
(21)
D represents duty cycle defined by VOUT/VIN.
The important term is the ripple current represented as Irip/IOUT. As long as the ripple element is less than 50%, it
should not be a problem. If the ripple element is higher, inductor loss becomes significant.
Ex)VIN=24V, VOUT=12V, fOSC=100kHz, L=45μH
Irip =
24V - 12V
0.5
100k 45µ
(22)
= 1.3 [A]
10) Power consumption of high side MOSFET
The power consumption in the external high side MOSFET is represented by conduction loss and switching loss.
The conduction loss of MOSFET is obtained by the following equation (23).
Psat = IO2 RDS(ON) D
[W]
(23)
Since RDS(ON) is affected by temperature, it is advisable to confirm the actual FET temperature and data sheet.
The switching loss of high side MOSFET is obtained by the following equation (24).
Psw = VIN IO tSW fSW [W]
(24)
IO: DC output current
tSW: Rise time of switching waveform
fSW: Switching frequency
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14
LV5768V-A
The junction temperature of high side MOSFET is obtained by the following equation (25).
Tj = Ta + (Psat + Psw) θja [W]
(25)
θja: heat resistor between junction and ambient.
Tj should not exceed the Tjmax as stated in the data sheet.
11) Power consumption of low side MOSFET
The power consumption in low side MOSFET consists of conduction loss from RDS (ON) as well as from body
diode and reverse recovery loss. The conduction loss due to RDS (ON) is obtainable by the equation (23) which is
represented in the equation (26).
Psat = IO2 RDS(ON) (1-D) [W]
(26)
The conduction loss from body diode occurs when the body diode is conducted forwardly between high side off and
low side off zone, which is represented in the equation (27).
Pdf = 2 IO Vf tdelay fSW [W]
(27)
Vf: Forward voltage of body diode
tdelay: Delay time immediately before surge of SW node
The total power consumption of low side MOSFET is obtained by the equation (28).
Pls = Psat + Pdf [W]
(28)
12) Power consumption of LV5768V
The total power consumption of LV5768V is represented in the equation (29) given that the same MOSFET is
selected for high side and low side.
Pd_ic = (2 Qg fSW + ICCA) VIN [W]
ICCA: IC consumption current when switching is stopped.
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15
(29)
LV5768V-A
Caution for pattern layout
C1: input capacitor
When the IC performs switching, a ripple current flows into the input capacitor of DC-DC converter. The capacitor
of input should be connected adjacent to the power IC and minimize the inductance from pattern layout. C1 should
be connected adjacently to VIN pin of the IC and Q1 (high side FET- drain). If implementation to IC side is not
feasible, insert adjacently to Q1.
C7 (bypass capacitor connected to VIN pin of the IC) should be connected adjacently to VIN pin and GND pin. In
rare cases, intensive ringing may occur in the VIN pin by connecting bypass capacitor. The recommendation value is
1000pF.
Q1, Q2 (D1): external FET
Both high and low sides are driven by Nch-MOSFET. In Q1, a transition of SW node takes place between VIN and
GND by turn on and off, where high frequency noise occurs. The noise affects the surrounding pattern layouts and
parts. The high/ low side gate and SW node should be laid out as fat and short as possible and connect to HDRV,
LDRV and SW pins of the IC. HDRV, LDRV and SW pins should be shielded with GND to prevent influence from
noise.
When high side FET is turned on, ripple current path is as follows: VIN + (C1) --> Q1--> inductor (L) --> C9 -->
GND. When low side FET is turned on, current path is as follows: Q2(D1) --> inductor (L) --> C9 --> GND. By
minimizing the area of current path and keeping the pattern layout fat and short, noise is eliminated and error
operation is prevented. Hence, Q1, Q2, D1, C1 and C9 should be implemented nearby.
R5,C6: ILIM (overcurrent limiter set pin)
ILIM pin detects overcurrent which is used as set point where current limit comparator in the IC starts operation. The
overcurrent limiter is adjustable by the resistor between ILIM pin and VIN pin. When the voltage of SW pin
becomes lower than that of ILIM pin, current limit comparator functions and turns off the high side MOSFET. This
operation is reset at every PWM pulse.
To filter unwanted noise, C6 should be connected in parallel to the set resistor (the recommendation is 1000pF). R5
and C6 should be implemented adjacently to the VIN side of the IC. If they are apart from the VIN side, detection
precision for overcurrent point may be deteriorated.
Small signal blocks: part for FB, COMP, EN, CBOOT, VDD and SS pins.
The parts should be implemented adjacently to the IC and be connected as short as possible. Also the GND of the
parts should have common GND pattern as the IC. FB pattern layout should not be under nor nearby the inductor or
SW node. This must be complied to avoid error operation.
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16
LV5768V-A
ORDERING INFORMATION
Device
LV5768V-A-TLM-E
Package
SSOP16 (225mil)
(Pb-Free)
LV5768V-A-MPB-E
SSOP16 (225mil)
(Pb-Free)
Shipping (Qty / Packing)
2000 / Tape & Reel
90 / Fan-Fold
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and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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