STK17T88-RF25

STK17T88 32K x 8 AutoStore nvSRAM with Real Time Clock Description ■ nvSRAM Combined With Integrated Real-Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor) The Cypress STK17T88 combines a 256 Kb nonvolatile static RAM (nvSRAM) with a full-featured real-time clock in a reliable, monolithic integrated circuit. ■ Capacitor or Battery Backup for RTC ■ 25, 45 ns Read Access and R/W Cycle Time The 256 Kb nvSRAM is a fast static RAM with a nonvolatile QuantumTrap storage element included with each memory cell. ■ Unlimited Read/Write Endurance ■ Automatic Nonvolatile STORE on Power Loss ■ Nonvolatile STORE Under Hardware or Software Control ■ Automatic RECALL to SRAM on Power Up ■ Unlimited RECALL Cycles ■ 200K STORE Cycles ■ 20-Year Nonvolatile Data Retention ■ Single 3V +20%, -10% Power Supply ■ Commercial and Industrial Temperatures ■ 48-Pin 300-mil SSOP Package (RoHS Compliant) ig ns Features D es The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. de d fo rN ew The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control. om ROW DECODER VCC Quantum Trap 512 X 512 STORE STATIC RAM ARRAY 512 X 512 RECALL STORE/ RECALL CONTROL VRTCbat VRTCcap HSB SOFTWARE DETECT INPUT BUFFERS ot N DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCAP POWER CONTROL R ec A5 A6 A7 A8 A9 A11 A12 A13 A14 m en Logic Block Diagram A13 – A0 COLUMN I/O COLUMN DEC RTC X1 X2 INT A 0 A 1 A 2 A 3 A 4 A10 MUX A14 – A0 G E W Cypress Semiconductor Corporation Document Number: 001-52040 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 25, 2009 [+] Feedback STK17T88 Contents fo rN ew D es ig ns Software STORE.......................................................... Software RECALL ........................................................ Data Protection............................................................. Noise Considerations ................................................... Preventing AutoStore ................................................... Best Practices .............................................................. Real Time Clock................................................................. Reading the Clock ........................................................ Setting the Clock .......................................................... Backup Power .............................................................. Stopping and Starting the RTC Oscillator .................... Calibrating The Clock ................................................... Alarm ............................................................................ Watchdog Timer ........................................................... Power Monitor .............................................................. Interrupt Register.......................................................... Flags Register .............................................................. RTC Register Map.............................................................. Commercial and Industrial Ordering Information......................................................... Ordering Codes ................................................................. Package Diagram............................................................... Document History Page .................................................... Sales, Solutions, and Legal Information ......................... Worldwide Sales and Design Support.......................... Products ....................................................................... 14 14 14 14 14 14 15 15 15 15 15 15 16 16 16 17 17 18 22 22 23 24 24 24 24 N ot R ec om m en de d Features................................................................................ 1 Description........................................................................... 1 Logic Block Diagram........................................................... 1 Contents ............................................................................... 2 Pin Configurations .............................................................. 3 Pin Descriptions .................................................................. 3 Absolute Maximum Ratings ............................................... 4 RF (SSOP-48) Package Thermal Characteristics................................................................ 4 DC Characteristics (VCC = 2.7V-3.6V) ............................... 4 AC Test Conditions ............................................................. 5 Capacitance ......................................................................... 5 RTC DC Characteristics ...................................................... 6 SRAM READ Cycles #1 and #2........................................... 7 SRAM WRITE Cycles #1 and #2 ......................................... 8 AutoStore/Power Up RECALL ............................................ 9 Software-Controlled STORE/RECALL Cycle................... 10 Hardware STORE Cycle .................................................... 11 Soft Sequence Commands ............................................... 11 Mode Selection .................................................................. 12 nvSRAM Operation............................................................ 13 SRAM READ ................................................................ 13 SRAM WRITE .............................................................. 13 AutoStore Operation..................................................... 13 Hardware STORE (HSB) Operation............................. 13 Hardware Recall (POWER UP).................................... 13 Document Number: 001-52040 Rev. *C Page 2 of 24 [+] Feedback STK17T88 Pin Configurations Figure 1. 48-Pin SSOP 47 V CC NC 3 46 HSB A 12 A7 4 5 45 44 A6 A5 6 43 W A 13 A8 7 42 A9 INT 8 41 NC A4 9 40 A 11 NC 10 39 NC NC 11 38 NC NC V SS 12 37 NC 13 36 NC 14 35 15 34 V SS NC V RTCcap DQ 0 16 33 DQ 6 A3 A2 17 32 G 18 31 A 10 A1 19 30 A0 DQ 1 DQ 2 20 29 21 28 27 X1 22 23 26 DQ 4 DQ 3 X2 24 25 V CC ew E DQ 7 DQ 5 fo V RTCbat rN (TOP) Relative PCB Area Usage[1] ig ns 48 2 es 1 NC A 14 D V CAP d Pin Descriptions I/O Type Description A14-A0 Input DQ7-DQ0 I/O E Input Chip Enable: The active low E input selects the device. W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E. G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tristate. X1 Output de Pin Name en Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes in the clock register map. ec om m Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC. R Crystal Connection, Drives Crystal on Startup. Input Power Supply Capacitor Supplied Backup RTC Supply Voltage (Left unconnected if VRTCbat is used). VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage (Left unconnected if VRTCcap is used). Power Supply Power: 3.0V, +20%, -10% N VCC ot X2 VRTCcap Crystal Connection for 32.768 kHz Crystal. HSB I/O Hardware Store Busy: When low this output indicates a store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). INT Output Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. Programmable to either active high (push/pull) or active low (open-drain) VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground. NC No Connect Unlabeled Pins have no Internal Connections. Note 1. For detailed package size specifications, see Package Diagram on page 23. Document Number: 001-52040 Rev. *C Page 3 of 24 [+] Feedback STK17T88 Absolute Maximum Ratings Note Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground.................–0.5V to 4.1V Voltage on Input Relative to VSS ...........–0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V) Temperature under Bias ............................... –55°C to 125°C Junction Temperature ................................... –55°C to 140°C Storage Temperature .................................... –65°C to 150°C ig ns Power Dissipation............................................................. 1W DC Output Current (1 output at a time, 1s duration).... 15 mA RF (SSOP-48) Package Thermal Characteristics Average VCC Current ICC2 Average VCC Current during STORE 3 ICC3 Average VCC Current at tAVAV = 200 ns 3V, 25°C, Typical 10 ICC4 Average VCAP Current during AutoStore Cycle ISB VCC Standby Current (Standby, Stable CMOS Levels) IILK Input Leakage Current IOLK Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE Operations Data Retention DATAR D Notes mA mA tAVAV = 25 ns tAVAV = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care, VCC = Max Average current for duration of STORE cycle (tSTORE) W ≥ (V CC – 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE) E ≥ (VCC -0.2V) All Others VIN≤ 0.2V or ≥ (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = Max VIN = VSS to VCC VCC = Max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 2 mA IOUT = 4 mA 3 mA 10 mA 3 3 mA 3 3 mA ±1 ±1 μA ±1 ±1 μA de en m om ec R ot N VIH VIL VOH VOL TA VCC VCAP NVC Units rN ICC1 Industrial Min Max 70 55 ew Commercial Min Max 65 50 Parameter fo Symbol (VCC = 2.7V-3.6V) d DC Characteristics es θjc 6.2 C/W; θja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm] 2.0 VCC + 0.5 2.0 VCC + 0.5 VSS - 0.5 0.8 VSS - 0.5 0.8 2.4 2.4 0.4 0.4 0 70 - 40 85 2.7 3.6 2.7 3.6 17 57 17 57 200 200 20 20 V V V V °C V μF K 3.0V +20%, -10% Between VCAP pin and VSS, 5V rated. Years At 55°C Note ■ The HSB pin has IOUT=-10 µA for VOH of 2.4V, this parameter is characterized but not tested. ■ The INT is open-drain and does not source or sink high current when interrupt register bit D3 is low. Document Number: 001-52040 Rev. *C Page 4 of 24 [+] Feedback STK17T88 AC Test Conditions Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times .................................................. ≤5 ns Input and Output Timing Reference Levels .................... 1.5V Output Load..................................See Figure 2 and Figure 3 Capacitance Symbol Parameter[2] Max Units Conditions Input Capacitance 7 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V es ig ns CIN Figure 3. AC Output Loading for Tristate Specifications (THZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ) N ot R ec om m en de d fo rN ew D Figure 2. AC Output Loading Note 2. These parameters are guaranteed but not tested. Document Number: 001-52040 Rev. *C Page 5 of 24 [+] Feedback STK17T88 RTC DC Characteristics Commercial Symbol Industrial Parameter Units Min VRTCbat Notes Max – 300 – 350 nA From either VRTCcap or VRTCbat RTC Battery Pin Voltage 1.8 3.3 1.8 3.3 V Typical = 3.0V during normal operation VRTCcap RTC Capacitor Pin Voltage 1.2 2.7 1.2 2.7 V Typical = 2.4V during normal operation tOSCS RTC Oscillator Time to Start – 10 – 10 sec At minimum temperature from power up or enable – 5 – 5 sec At 25°C from power up or enable ig ns RTC Backup Current Min fo Y1 X1 X2 en de d C2 RF C1 rN ew D Figure 4. RTC Component Configuration es IBAK Max m Recommended Values C2 = 56 pF ± 10% (do not vary from this value) N ot R ec om Y1 = 32.768 kHz RF = 10 MO C1 = 0 (install cap footprint, but leave unloaded) Document Number: 001-52040 Rev. *C Page 6 of 24 [+] Feedback STK17T88 SRAM READ Cycles #1 and #2 Symbols No. STK17T88-25 STK17T88-45 Min Min Parameter #1 #2 1 Units Alt. tELQV tACS Chip Enable Access Time Max Max 25 45 ns 2 tAVAV[3] tELEH[5] tRC Read Cycle Time 3 tAVQV[4] tAVQV[6] tAA Address Access Time 25 45 ns tGLQV tOE Output Enable to Data Valid 12 20 ns tAXQX tOH Output Hold after Address Change 3 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 7 tEHQZ tHZ Address Change or Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZ[5] tOHZ Output Disable to Output Inactive 10 tELICCL[3] tPA Chip Enable to Power Active tPS Chip Disable to Power Standby tEHICCH [3] ig ns ns 3 ns es 3 D 10 0 ns 15 0 10 ns 15 0 0 25 ns ns ns 45 ns fo 11 tAXQX 45 ew 5 [4] rN 4 25 d Figure 5. SRAM READ Cycle #1: Address Controlled[3,4,6] de 2 tAVAV en ADDRESS 5 3 tAVQV tAXQX DATA VALID om m DQ (DATA OUT) 2 29 1 11 6 ot R ec Figure 6. SRAM READ Cycle #2: E and G Controlled[6] N 7 3 9 4 8 10 Notes 3. W must be high during SRAM READ cycles. 4. Device is continuously selected with E and G both low 5. Measured ± 200 mV from steady state output voltage. 6. HSB must remain high during READ and WRITE cycles. Document Number: 001-52040 Rev. *C Page 7 of 24 [+] Feedback STK17T88 SRAM WRITE Cycles #1 and #2 Symbols No. STK17T88-25 STK17T88-45 Min Min Parameter #1 #2 Units Alt. Max Max tAVAV tWC Write Cycle Time 25 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 30 ns 15 tDVWH tDVEH tDW Data Setup to End of Write 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns 17 tAVWH tAVEH tAW Address Setup to End of Write 20 30 ns 18 tAVWL tAVEL tAS Address Setup to Start of Write 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns 20 tWLQZ tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write D es ig ns 12 tAVAV ew 10 3 ns ns rN 3 15 Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8] fo 12 tAVAV ADDRESS 19 tWHAX de d 14 tELWH E en 17 tAVWH 18 tAVWL om m W ec DATA IN DATA OUT 13 tWLWH 15 tDVWH DATA VALID 20 tWLQZ Figure 8. SRAM WRITE Cycle #2: E Controlled[7, 8] ot R 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA N 16 tWHDX 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE Notes 7. If W is low when E goes low, the outputs remain in the high impedance state. 8. E or W must be ≥ VIH during address transitions. Document Number: 001-52040 Rev. *C Page 8 of 24 [+] Feedback STK17T88 AutoStore/Power Up RECALL Symbols STK17T88 No. Parameter Standard Units Notes 40 ms 9 STORE Cycle Duration 12.5 ms 10, 11 2.65 V Alternate Min 22 tHRECALL 23 tSTORE 24 VSWITCH Low Voltage Trigger Level 25 VCCRISE VCC Rise Time Max Power up RECALL Duration μS 150 ig ns tHLHZ de d fo rN ew D es Figure 9. AutoStore Power Up RECALL 23 23 om m en 25 22 N ot R ec 22 Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH Notes 9. tHRECALL starts from the time VCC rises above VSWITCH 10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place 11. Industrial Grade devices require 15 ms maximum. Document Number: 001-52040 Rev. *C Page 9 of 24 [+] Feedback STK17T88 Software-Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [12, 13] Symbols No. STK17T88-35 STK17T88-45 Min Min Parameter E Cont Alternate Max Units Notes 13 Max tRC STORE/RECALL Initiation Cycle Time 25 45 ns 27 tAVEL tAS Address Setup Time 0 0 ns 28 tELEH tCW Clock Pulse Width 20 30 ns 29 tEHAX Address Hold Time 1 1 ns 30 tRECALL RECALL Duration ig ns 26 tAVAV 100 us es 100 D Figure 10. Software Store/Recall Cycle: E CONTROLLED[13] 26 27 rN ew 26 fo 28 23 30 N ot R ec om m en de d 29 Notes 12. The software sequence is clocked on the falling edge of E controlled READs 13. The six consecutive addresses must be read in the order listed in the Mode Selection table. W must be high during all six consecutive cycles. Document Number: 001-52040 Rev. *C Page 10 of 24 [+] Feedback STK17T88 Hardware STORE Cycle Symbols STK17T88 No. Parameter Standard 31 tDELAY 32 tHLHX Alternate tHLQZ Min Max Hardware STORE to SRAM Disabled 1 70 Hardware STORE Pulse Width 15 Units Notes μs 14 ns ig ns Figure 11. Hardware STORE Cycle es 32 ew D 23 d fo rN 31 Parameter en Symbol No. STK17T88 Min m Standard tSS Soft Sequence Processing Time Units Notes μs 15, 16 Max 70 om 33 de Soft Sequence Commands 33 33 N ot R ec Figure 12. Soft Sequence Command Notes 14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete 15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 16. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command Document Number: 001-52040 Rev. *C Page 11 of 24 [+] Feedback STK17T88 Mode Selection W G A14-A0 Mode I/O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Active 0x0FC0 Nonvolatile Store Output High Z 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z es ICC2 Active D L 17,18,19 17,18,19 ew H Notes N ot R ec om m en de d fo rN L ig ns E Notes 17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. 18. While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes. 19. I/O state depends on the state of G. The I/O table assumes G low. Document Number: 001-52040 Rev. *C Page 12 of 24 [+] Feedback STK17T88 nvSRAM Operation AutoStore Operation The STK17T88 stores data to nvSRAM using one of three storage operations. These operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). The STK17T88 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates similar to a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK17T88 supports unlimited read and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. AutoStore operation, a unique feature of Cypress QuanumTrap technology that is a standard feature on the STK17T88. ig ns During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 13 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC Characteristics (VCC = 2.7V-3.6V) table for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. D ew d de 0.1µF N ot R ec om W m VCAP 10k Ohm V CC en V CC SRAM WRITE rN Hardware STORE (HSB) Operation Figure 13. AutoStore Mode V CAP To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. fo The STK17T88 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-14 determine which of the 32,768 data bytes are accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs are valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and remain valid until another address change or until E or G is brought high, or W and HSB is brought low. es SRAM READ A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 are written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry turns off the output buffers tWLQZ after W goes low. Document Number: 001-52040 Rev. *C The STK17T88 provides the HSB pin to control and acknowledge the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK17T88 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pull up and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin must be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK17T88 continues to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it is allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low are inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the STK17T88 continues to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation, the STK17T88 remains disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. Hardware Recall (POWER UP) During power up or after any low power condition (VCC