74AUP1T17
Low-power buffer with voltage-level translator
Rev. 2 — 19 July 2021
Product data sheet
1. General description
The 74AUP1T17 provides the single buffer function. This device ensures a very low static and
dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.
The 74AUP1T17 is designed for logic-level translation applications with input switching levels that
accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply
voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to
2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire
VCC range.
2. Features and benefits
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
• HBM JESD22-A114F Class 3A exceeds 5000 V
• CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP1T17GW
-40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AUP1T17GX
-40 °C to +125 °C
X2SON5
plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 × 0.8 × 0.32 mm
SOT1226-3
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
4. Marking
Table 2. Marking
Type number
Marking code[1]
74AUP1T17GW
57
74AUP1T17GX
57
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
2
A
Y
4
2
mnb150
Fig. 1.
4
A
Y
mnb152
mnb151
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram
6. Pinning information
6.1. Pinning
74AUP1T17
74AUP1T17
n.c.
1
A
2
GND
3
5
VCC
4
Y
n.c.
5
VCC
4
Y
3
GND
A
2
aaa-027772
Transparent top view
aaa-027771
Fig. 4.
1
Pin configuration SOT353-1 (TSSOP5)
Fig. 5.
Pin configuration SOT1226-3 (X2SON5)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
Description
n.c.
1
not connected
A
2
data input
GND
3
ground (0 V)
Y
4
data output
VCC
5
supply voltage
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
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Nexperia B.V. 2021. All rights reserved
2 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
A
Y
L
L
H
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO < 0 V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
ICC
IGND
Max
Unit
-0.5
+4.6
V
-50
-
-0.5
+4.6
-50
-
-0.5
+4.6
V
-
±20
mA
supply current
-
50
mA
ground current
-50
-
mA
Tstg
storage temperature
-65
+150
°C
Ptot
total power dissipation
-
250
mW
Min
Max
Unit
2.3
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
-40
+125
°C
[1]
[2]
VI < 0 V
Min
[1]
Tamb = -40 °C to +125 °C
[1]
[2]
mA
V
mA
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT1226-3 (X2SON5) package: Ptot derates linearly with 3.0 mW/K above 67 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
Conditions
ambient temperature
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
©
Nexperia B.V. 2021. All rights reserved
3 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VT+
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.16
V
VT-
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.23
-
0.60
V
VCC = 3.0 V to 3.6 V
0.25
-
0.56
V
VCC - 0.1
-
-
V
IO = -2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = -3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = -2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = -4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 μA; VCC = 2.3 V to 3.6 V
-
-
0.10
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
VH
VOH
HIGH-level output voltage
VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V
VOL
LOW-level output voltage
VI = VT+ or VT-
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.1
μA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.1
μA
ΔIOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.1
μA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.2
μA
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.8
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
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Nexperia B.V. 2021. All rights reserved
4 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +85 °C
VT+
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VT-
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
VCC - 0.1
-
-
V
IO = -2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = -3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = -2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = -4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 μA; VCC = 2.3 V to 3.6 V
-
-
0.1
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
VH
VOH
HIGH-level output voltage
VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V
VOL
LOW-level output voltage
VI = VT+ or VT-
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.5
μA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.5
μA
ΔIOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.5
μA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.5
μA
ΔICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
0.6
μA
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
10
μA
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
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Nexperia B.V. 2021. All rights reserved
5 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +125 °C
VT+
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VT-
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
0.33
-
0.64
V
VCC = 3.0 V to 3.6 V
0.46
-
0.85
V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
VCC - 0.11
-
-
V
IO = -2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = -3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = -2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = -4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 μA; VCC = 2.3 V to 3.6 V
-
-
0.11
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
VH
VOH
HIGH-level output voltage
VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V
VOL
LOW-level output voltage
VI = VT+ or VT-
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.75
μA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.75
μA
ΔIOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.75
μA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
3.5
μA
ΔICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
1.8
μA
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
18
μA
[1]
[2]
One input at 0.3 V or 1.1 V, other input at VCC or GND.
One input at 0.45 V or 1.2 V, other input at VCC or GND.
74AUP1T17
Product data sheet
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Nexperia B.V. 2021. All rights reserved
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74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.
Symbol Parameter
Conditions
25 °C
Min
-40 °C to +85 °C -40 °C to +125 °C Unit
Typ[1] Max
Min
Max
Min
Max
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
tpd
propagation
delay
A to Y; see Fig. 6
[2]
CL = 5 pF
2.0
3.2
4.9
0.5
6.8
0.5
7.5
ns
CL = 10 pF
2.4
3.8
5.6
1.0
7.9
1.0
8.7
ns
CL = 15 pF
2.7
4.3
6.1
1.0
8.7
1.0
9.6
ns
CL = 30 pF
3.6
5.4
7.6
1.5
10.8
1.5
11.9
ns
CL = 5 pF
1.6
3.1
5.0
0.5
6.0
0.5
6.6
ns
CL = 10 pF
2.0
3.7
5.7
1.0
7.1
1.0
7.9
ns
CL = 15 pF
2.3
4.1
6.3
1.0
7.9
1.0
8.7
ns
CL = 30 pF
3.2
5.3
7.8
1.5
10.0
1.5
11.0
ns
CL = 5 pF
1.2
2.8
4.5
0.5
5.5
0.5
6.1
ns
CL = 10 pF
1.7
3.4
5.1
1.0
6.5
1.0
7.2
ns
CL = 15 pF
2.0
3.9
5.7
1.0
7.4
1.0
8.2
ns
CL = 30 pF
2.8
5.0
7.2
1.5
9.5
1.5
10.5
ns
CL = 5 pF
1.8
2.7
3.7
0.5
8.0
0.5
8.8
ns
CL = 10 pF
2.2
3.2
4.4
1.0
8.5
1.0
9.4
ns
CL = 15 pF
2.7
3.7
5.0
1.0
9.1
1.0
10.1
ns
CL = 30 pF
3.5
4.9
6.3
1.5
9.8
1.5
10.8
ns
CL = 5 pF
1.4
2.6
3.8
0.5
5.3
0.5
5.9
ns
CL = 10 pF
1.9
3.1
4.5
1.0
6.1
1.0
6.8
ns
CL = 15 pF
2.2
3.6
5.1
1.0
6.8
1.0
7.5
ns
CL = 30 pF
3.0
4.8
6.6
1.5
8.5
1.5
9.4
ns
CL = 5 pF
1.1
2.5
4.0
0.5
4.7
0.5
5.2
ns
CL = 10 pF
1.6
3.1
4.5
1.0
5.7
1.0
6.3
ns
CL = 15 pF
1.9
3.6
5.1
1.0
6.2
1.0
6.9
ns
CL = 30 pF
2.7
4.7
6.6
1.5
7.8
1.5
8.6
ns
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A to Y; see Fig. 6
[2]
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation
delay
A to Y; see Fig. 6
[2]
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation
delay
A to Y; see Fig. 6
[2]
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A to Y; see Fig. 6
[2]
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
tpd
propagation
delay
74AUP1T17
Product data sheet
A to Y; see Fig. 6
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 July 2021
©
Nexperia B.V. 2021. All rights reserved
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74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
Symbol Parameter
Conditions
25 °C
Min
-40 °C to +85 °C -40 °C to +125 °C Unit
Typ[1] Max
Min
Max
Min
Max
Tamb = 25 °C
CPD
[1]
[2]
[3]
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC [3]
VCC = 2.3 V to 2.7 V
-
4
-
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
5
-
-
-
-
-
pF
All typical values are measured at nominal VCC.
tpd is the same as tPLH and tPHL
CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
Σ(CL x VCC x fo) = sum of the outputs.
11.1. Waveforms and test circuit
VI
VM
A input
GND
t PHL
t PLH
VOH
VM
Y output
VOL
mnb153
Measurement points are given in Table 9
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6.
Input A to output Y propagation delay times
Table 9. Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
2.3 V to 3.6 V
0.5 × VCC
0.5 × VI
1.65 V to 3.6 V
≤ 3.0 ns
74AUP1T17
Product data sheet
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74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
VCC
G
VI
DUT
VEXT
5 kΩ
VO
RT
CL
RL
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 7.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
Load
VEXT
VCC
CL
RL [1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 kΩ or 1 MΩ
open
GND
2 × VCC
[1]
For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
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Nexperia B.V. 2021. All rights reserved
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74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
D
E
SOT353-1
A
X
c
y
HE
v M A
Z
5
4
A2
A
(A3)
A1
θ
1
Lp
3
e
e1
L
w M
bp
detail X
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
e1
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.1
0
1.0
0.8
0.15
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
1.3
2.25
2.0
0.425
0.46
0.21
0.3
0.1
0.1
0.60
0.15
7°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT353-1
Fig. 8.
REFERENCES
IEC
JEDEC
JEITA
MO-203
SC-88A
EUROPEAN
PROJECTION
ISSUE DATE
00-09-01
03-02-19
Package outline SOT353-1 (TSSOP5)
74AUP1T17
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 July 2021
©
Nexperia B.V. 2021. All rights reserved
10 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.32 mm
SOT1226-3
C
Seating Plane
X
5x
y C
D
A
B
E
A
A3
pin 1
index area
A1
pin 1
index area
e
1
2
b
(4x)
v
w
y1 C
C A B
C
L
(4x)
3
k
D
h
(6x)
x)
(4
5
4
0
1 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
A3
D
Dh
E
b
e
K
L
max 0.35 0.04
0.85 0.30 0.85 0.25
0.27
0.10
0.80 0.25 0.80 0.20 0.50
0.22
nom 0.32 0.02
(Typ.)
min 0.30 0.00
0.75 0.20 0.75 0.15
0.20 0.17
v
0.1
w
y
y1
0.05 0.05 0.05
sot1226-3_po
Outline
version
SOT1226-3
Fig. 9.
References
IEC
JEDEC
EIAJ
European
projection
Issue date
19-11-06
19-11-07
---
Package outline SOT1226-3 (X2SON5)
74AUP1T17
Product data sheet
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74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
14. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1T17 v.2
20210719
Product data sheet
-
74AUP1T17 v.1
Modifications:
•
•
74AUP1T17 v.1
20171128
74AUP1T17
Product data sheet
SOT1226 (X2SON5) package changed to SOT1226-3 (X2SON5) package.
Table 5: Derating values for Ptot total power dissipation updated.
Product data sheet
-
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-
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12 / 14
74AUP1T17
Nexperia
Low-power buffer with voltage-level translator
15. Legal information
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[1][2]
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[1]
[2]
[3]
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74AUP1T17
Product data sheet
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Nexperia
Low-power buffer with voltage-level translator
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking.......................................................................... 2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description............................................................. 2
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 8
12. Package outline........................................................ 10
13. Abbreviations............................................................ 12
14. Revision history........................................................12
15. Legal information......................................................13
©
Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 19 July 2021
74AUP1T17
Product data sheet
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Rev. 2 — 19 July 2021
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14 / 14