STK14C88-3WF45

STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM Functional Description ■ 35 ns and 45 ns Access Times ■ Automatic Nonvolatile STORE on power loss ■ Nonvolatile STORE under Hardware or Software control ■ Automatic RECALL to SRAM on power up ■ Unlimited Read/Write endurance ■ Unlimited RECALL Cycles ■ 1,000,000 STORE Cycles ■ 100 year Data Retention The Cypress STK14C88-3 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. ■ Single 3.3V+0.3V Power Supply ■ Commercial and Industrial Temperatures ■ 32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages ■ RoHS compliance rN ew D es ig ns Features Logic Block Diagram fo Quantum Trap 512 X 512 A5 RECALL ot POWER CONTROL en STORE/ RECALL CONTROL SOFTWARE DETECT m DQ 5 DQ 6 de ROW DECODER om R DQ 4 ec DQ 2 DQ 3 STATIC RAM ARRAY 512 X 512 INPUT BUFFERS DQ 0 DQ 1 VCAP d STORE A6 A7 A8 A9 A 11 A 12 A 13 A 14 VCC HSB A13 - A 0 COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 N DQ 7 OE CE WE Cypress Semiconductor Corporation Document Number: 001-50592 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 01, 2009 [+] Feedback STK14C88-3 Contents rN ew D es ig ns Data Retention and Endurance .......................................... 9 Capacitance ......................................................................... 9 Thermal Resistance............................................................. 9 AC Test Conditions ............................................................. 9 AC Switching Characteristics ........................................... 10 SRAM Read Cycle ....................................................... 10 Switching Waveforms ....................................................... 10 Switching Waveforms ....................................................... 11 AutoStore or Power Up RECALL ..................................... 12 Switching Waveforms ....................................................... 12 Software Controlled STORE/RECALL Cycle................... 13 Switching Waveforms ....................................................... 13 Hardware STORE Cycle .................................................... 14 Switching Waveforms ........................................................ 14 Part Numbering Nomenclature.......................................... 15 Ordering Information......................................................... 15 Package Diagrams............................................................. 16 Document History Page ..................................................... 17 Sales, Solutions and Legal Information .......................... 17 Worldwide Sales and Design Support.......................... 17 Products ....................................................................... 17 fo 1 1 1 2 3 4 4 4 4 4 5 5 5 6 6 6 6 6 7 8 8 N ot R ec om m en de d Features................................................................................ Functional Description........................................................ Logic Block Diagram........................................................... Contents ............................................................................... Pin Configurations .............................................................. Device Operation ................................................................. SRAM Read .......................................................................... SRAM Write .......................................................................... AutoStore Operation ........................................................... AutoStore Inhibit Mode ....................................................... Hardware STORE (HSB) Operation.................................... Hardware RECALL (Power Up)........................................... Software STORE .................................................................. Software RECALL................................................................ Preventing STORE............................................................... Hardware Protect................................................................. Noise Considerations.......................................................... Low Average Active Power................................................. Best Practices...................................................................... Maximum Ratings................................................................ DC Electrical Characteristics ............................................. Document Number: 001-50592 Rev. *A Page 2 of 17 [+] Feedback STK14C88-3 Pin Configurations I/O Type Input DQ0-DQ7 Input or Output W Input CE E Input OE G HSB VCAP Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. ec R Input ot Ground Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. N VSS VCC Bidirectional Data I/O lines. Used as input or output lines depending on operation. om WE Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. en Alt A0–A14 m Pin Name de Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP d fo rN ew D es ig ns Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document Number: 001-50592 Rev. *A Page 3 of 17 [+] Feedback STK14C88-3 The STK14C88-3 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14C88-3 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor having a capacity of between 68 uF and 220 uF (+20%) rated at 4.7V should be provided. Figure 2. AutoStore Mode ig ns Device Operation D ew rN fo The STK14C88-3 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. es SRAM Read de d SRAM Write To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. ec om m en A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. R AutoStore Operation ot The STK14C88-3 can be powered in one of three storage operations: N During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Document Number: 001-50592 Rev. *A If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 1 ohm resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP. AutoStore Inhibit Mode If an automatic STORE on power loss is not required, then VCC is tied to ground and +3.3V is applied to VCAP (Figure 3 on page 5). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK14C88-3 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control. It is not permissible to change between these options “On the fly”. Page 4 of 17 [+] Feedback STK14C88-3 capacitor. The capacitor size is scaled by the number of devices connected to it. When any one of the STK14C88-3 detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle. (A STORE takes place in those STK14C88-3 that are written since the last nonvolatile cycle.) Figure 3. AutoStore Inhibit Mode During any STORE operation, regardless of how it is initiated, the STK14C88-3 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK14C88-3 remains disabled until the HSB pin returns HIGH. ig ns If HSB is not used, it is left unconnected. Hardware RECALL (Power Up) es During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. ew D If the STK14C88-3 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC. rN Software STORE fo Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14C88-3 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Hardware STORE (HSB) Operation om m en de d The STK14C88-3 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK14C88-3 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver. N ot R ec SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK14C88-3 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. The HSB pin is used to synchronize multiple STK14C88-3 while using a single larger capacitor. To operate in this mode, the HSB pin is connected together to the HSB pins from the other STK14C88-3. An external pull up resistor to VCAP is required, since HSB acts as an open drain pull down. The VCAP pins from the other STK14C88-3 parts are tied together and share a single Document Number: 001-50592 Rev. *A Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. Page 5 of 17 [+] Feedback STK14C88-3 Low Average Active Power Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle CMOS technology provides the STK14C88-3 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 and Figure 5 show the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-3 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. I/O loading Figure 4. Current Versus Cycle Time (READ) es D ew Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. ig ns Software RECALL en de d fo The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it has to overpower the internal pull down device. This device drives HSB LOW for 20 μs at the onset of a STORE. When the STK14C88-3 is connected for AutoStore operation (system VCC connected to VCC and a 68 μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK14C88-3 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and aborts the STORE attempt. rN Preventing STORE Hardware Protect Figure 5. Current Versus Cycle Time (WRITE) om m The STK14C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCAP (VCC – 0.2V). All other inputs cycling. at tRC= 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained without output loads. 25°C Typical ICC4 Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Average current for duration tSTORE Cycle ISB1[7] Average VCC Current tRC=35ns, CE > VIH (Standby, Cycling TTL tRC=45ns, CE > VIH Input Levels) en de d fo rN ICC2 VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). (Standby, Stable CMOS Input Levels) IIX Input Leakage Current VCC = Max, VSS < VIN < VCC -1 +1 μA IOZ Off State Output Leakage Current -1 +1 μA VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage VSS – 0.5 0.8 V om ot R ec VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL N VOH m ISB2[7] Output HIGH Voltage IOUT = –4 mA except HSB 2.4 V VOL Output LOW Voltage IOUT = 8 mA except HSB 0.4 V VBL Logic ‘0’ Voltage on HSB output IOUT = 3 mA 0.4 V VCAP Storage Capacitor Between VCAP pin and Vss, 68 to 220uF +20%, 4.7V rated. 264 uF 54 Notes 6. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 7. CE > VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-50592 Rev. *A Page 8 of 17 [+] Feedback STK14C88-3 Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 100 Years 1,000 K Capacitance In the following table, the capacitance parameters are listed.[8] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Thermal Resistance Thermal Resistance (Junction to Case) 5 pF 7 pF D Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 32-SOIC 32-PDIP Unit TBD TBD °C/W TBD TBD °C/W rN ΘJC Thermal Resistance (Junction to Ambient) Test Conditions ew ΘJA Description Unit es In the following table, the thermal resistance parameters are listed.[8] Parameter Max ig ns Parameter Figure 6. AC Test Loads fo R1 317Ω d 3.3V de Output om AC Test Conditions R2 351Ω m en 30 pF N ot R ec Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................