S-34C02B
www.ablic.com
2-WIRE SERIAL E2PROM
FOR DIMM SERIAL PRESENCE DETECT
Rev.2.0_00_U
© ABLIC Inc., 2012-2019
This IC is a 2-wire serial E2PROM for DIMM Serial Presence Detect which operates with low current consumption and the
wide range operation. This IC has the capacity of 2 K-bit and the organization of 256 words × 8-bit. Page write and
sequential read are available.
This IC has hardware write protect and software write protect. Hardware write protect inhibits write to all memory area when
connecting the WP pin to VCC. Software write protect inhibits write in 50% of the lower address (address 00h to 7Fh) in all
memory area by inputting command when the WP pin is left open or connected to the GND pin.
Caution
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, it is imperative to contact our sales
representatives.
Features
• Operation voltage range
Read:
1.7 V to 5.5 V
Write:
1.7 V to 5.5 V
• Operation frequency:
400 kHz max. (VCC = 1.7 V to 5.5 V)
• Write time:
5.0 ms max.
• Page write:
16 bytes / page
• Sequential read
• Noise suppression:
Schmitt trigger and noise filter on input pins (SCL, SDA)
• Write protect function during low power supply voltage
• Endurance:
106 cycle / word*1 (Ta = +25°C)
• Data retention: 100 years (Ta = +25°C)
• Memory capacity:
2 K-bit
• Initial delivery state:
FFh
• Operation temperature range:
Ta = −40°C to +85°C
• Write protect:
Hardware protect 100%
(addresses 00h to FFh)
Software protect for the lower address of 50%
(addresses 00h to 7Fh)
• Lead-free (Sn 100%), halogen-free
*1.
Package
• DFN-8(2030)A
5
8
4
1
(3.0 × 2.0 × t0.6 mm)
For each address (Word: 8-bit)
1
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
Block Diagram
VCC
WP
SCL
GND
Start / Stop
Detector
SDA
Voltage Detector
Serial Clock
Controller
High-Voltage Generator
LOAD
Device Address
Comparator
COMP
Data Register
LOAD INC
A2
R/W
A1
Address
Counter
X Decoder
Memory Cell Array
A0
Y Decoder
Data Output
ACK Output
Controller
DIN
DOUT
2
Selector
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
Product Name Structure
1.
Product name
S-34C02B
I
-
A8T3
U
5
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
A8T3: DFN-8(2030)A, Tape
Operation temperature
I:
Ta = −40°C to +85°C
Product name
S-34C02B: 2 K-bit
*1.
2.
Refer to the tape drawing.
Package
Package Name
DFN-8(2030)A
3.
Dimension
PQ008-A-P-SD
Tape
PQ008-A-C-SD
Reel
PQ008-A-R-SD
Land
PQ008-A-L-SD
Product name list
Product Name
S-34C02BI-A8T3U5
Capacity
2 K-bit
Package Name
DFN-8(2030)A
Pin Configuration
1.
DFN-8(2030)A
Top view
Pin No.
1
8
2
7
3
6
4
5
*1.
Symbol
1
2
3
4
5
6
A0
A1
A2
GND
SDA*1
SCL*1
7
WP
8
VCC
Description
Slave address input
Slave address input
Slave address input
Ground
Serial data I/O
Serial clock input
Write protect input
Connected to VCC: Protection valid
Open or connected to GND: Protection invalid
Power supply
Do not use it in "High-Z".
Remark For DFN-8(2030)A package, connect the heatsink of backside to the board, and set electric potential open or GND.
However, do not use it as the function of electrode.
3
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
Absolute Maximum Ratings
Table 1
Item
Power supply voltage
Input voltage
A0 high level input voltage
Output voltage
Operation ambient temperature
Storage temperature
Symbol
VCC
VIN
VHV
VOUT
Topr
Tstg
Absolute Maximum Rating
−0.3 to +6.5
−0.3 to +6.5
−0.3 to +10.0
−0.3 to +6.5
−40 to +85
−65 to +150
Unit
V
V
V
V
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 2
Symbol
Item
Power supply voltage
VCC
High level input voltage
Low level input voltage
A0 high level input voltage
VIH
VIL
VHV
Condition
Read
Write
VCC = 1.7 V to 5.5 V
VCC = 1.7 V to 5.5 V
VHV − VCC > 4.8 V
Ta = −40°C to +85°C
Min.
Max.
1.7
5.5
1.7
5.5
0.7 × VCC
5.5
−0.3
0.3 × VCC
7.0
10.0
Unit
V
V
V
V
V
Pin Capacitance
Table 3
Item
Input capacitance
I/O capacitance
Symbol
CIN
CI/O
Condition
VIN = 0 V (SCL, A0, A1, A2, WP)
VI/O = 0 V (SDA)
(Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
−
8
pF
−
8
pF
Endurance
Table 4
Item
Symbol
Operation Ambient Temperature
Endurance
NW
Ta = +25°C
*1. For each address (Word: 8-bit)
Min.
106
Max.
−
Unit
cycle / word*1
Min.
100
Max.
−
Unit
year
Data Retention
Table 5
Item
Data retention
4
Symbol
−
Operation Ambient Temperature
Ta = +25°C
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
DC Electrical Characteristics
Table 6
Item
Current consumption (READ)
Symbol
ICC1
Condition
−
Ta = −40°C to +85°C
VCC = 1.7 V to 5.5 V
fSCL = 400 kHz
Min.
Max.
−
0.8
Unit
mA
Table 7
Item
Current consumption (WRITE)
Symbol
ICC2
Condition
−
Ta = −40°C to +85°C
VCC = 1.7 V to 5.5 V
fSCL = 400 kHz
Min.
Max.
−
2.0
Unit
mA
Table 8
Ta = −40°C to +85°C
Item
Symbol
Standby current consumption
ISB
Input leakage current
ILI
Output leakage current
ILO
Input current 1
IIL
Input current 2
IIH
Input impedance 1
ZIL
Input impedance 2
ZIH
Low level output voltage
VOL
Condition
VIN = VCC or GND
SCL, SDA
VIN = GND to VCC
SDA
VOUT = GND to VCC
A0, A1, A2, WP
VIN < 0.3 × VCC
A0, A1, A2, WP
VIN > 0.7 × VCC
A0, A1, A2, WP
VIN = 0.3 × VCC
A0, A1, A2, WP
VIN = 0.7 × VCC
IOL = 3.2 mA
IOL = 1.5 mA
IOL = 0.7 mA
VCC = 1.7 V to 5.5 V
Unit
Min.
Max.
−
1.0
μA
−
1.0
μA
−
1.0
μA
−
50.0
μA
−
2.0
μA
30
−
kΩ
500
−
kΩ
−
−
−
0.4
0.3
0.2
V
V
V
5
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
AC Electrical Characteristics
Table 9
Measurement Conditions
Input pulse voltage
Input pulse rising / falling time
Output reference voltage
Output load
Input pulse voltage
0.2 × VCC to 0.8 × VCC
20 ns or less
0.3 × VCC to 0.7 × VCC
100 pF
Output reference voltage
0.8 × VCC
0.7 × VCC
0.3 × VCC
0.2 × VCC
Figure 1
Input / Output Waveform during AC Measurement
Table 10
Item
SCL clock frequency
SCL clock time "L"
SCL clock time "H"
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rising time
SCL, SDA falling time
WP setup time
WP hold time
WP release setup time
WP release hold time
Bus release time
Noise suppression time
Write time
6
Symbol
fSCL
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tWS1
tWH1
tWS2
tWH2
tBUF
tI
tWR
Ta = −40°C to +85°C
VCC = 1.7 V to 5.5 V
Min.
Max.
0
400
1.3
−
0.6
−
0.1
0.9
50
−
0.6
−
0.6
−
100
−
0
−
0.6
−
−
0.3
−
0.3
0
−
0
−
0
−
0
−
1.3
−
−
100
−
5.0
Unit
kHz
μs
μs
μs
ns
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
ns
ms
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
tHIGH
tF
tLOW
tR
SCL
tHD.STA
tSU.DAT
tHD.DAT
tSU.STA
tSU.STO
SDA
input
tAA
tDH
tBUF
SDA
output
Figure 2
Start Condition
Bus Timing
Acknowledge
Write Data
Stop Condition
tWR
Start Condition
SCL
D0
SDA
tWS1
tWH1
tWS2
tWH2
WP
(valid)
WP
(invalid)
Figure 3
Write Cycle Timing
7
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
Pin Functions
1.
VCC (Power supply) pin
The VCC pin is used to apply positive supply voltage. Regarding the applied voltage value, refer to "
Recommended Operating Conditions". Set a bypass capacitor of about 0.1 μF between the VCC pin and the
GND pin to make the power supply voltage stable.
2.
A0, A1 and A2 (Slave address input) pins
In this IC, to set the slave address, connect each of A0 pin, A1 pin and A2 pin to the GND pin or the VCC pin.
Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins.
Comparing the slave address transmitted from the master device and one that you set, makes possible to select
one slave address from other devices connected onto the bus.
Each of A0 pin, A1 pin and A2 pin has a built-in pull-down resistor. In open, the pin is set to the same status as it
connected to the GND pin.
3.
SDA (Serial data I/O) pin
The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch
open-drain output pin.
In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with
Wired-OR connection by pulling up to VCC by a resistor. Figure 4 shows the relation with an output load.
4.
SCL (Serial clock input) pin
The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL
clock, pay attention to the rising and falling time and comply with the specification.
5.
WP (Write protect input) pin
When hardware write protect is used, connect the WP pin to VCC. When hardware write protect is not used, be sure
to leave the WP pin open or connect it to the GND pin.
When software write protect is used, it inhibits write in 50% of the lower address (addresses 00h to 7Fh) in all
memory area according to the status of the protect register when the WP pin is left open or connected to the GND
pin.
20
18
16
14
Maximum value of 12
pull-up resistor
10
[kΩ]
8
fSCL = 400 kHz
6
4
2
0
100
10
Value of load capacity
[pF]
Figure 4
8
Output Load
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
Initial Delivery State
Initial delivery state of all addresses is "FFh".
Operation
1.
Initialization operation after power-on
By a power-on-clear circuit, this IC initializes the internal circuit at the time of power-on. Perform the beginning (start
condition) of the instruction transmission to this IC after the initialization by the power-on-clear circuit. Regarding the
datails of power-on-clear, refer to "5. Power-on-clear circuit" in " Usage".
2.
Start condition
Start is identified by a "H" to "L" transition of the SDA line while the SCL line is stable at "H".
Every operation begins from a start condition.
3.
Stop condition
Stop is identified by a "L" to "H" transition of the SDA line while the SCL line is stable at "H".
When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device
enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is halted, and this IC
initiates a write cycle.
tINIT
VCC
tSU.STA
tHD.STA
tSU.STO
SCL
SDA
Start condition
Figure 5
Stop condition
Start / Stop Conditions after Power-on
9
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
4.
Rev.2.0_00_U
Data transmission
Changing the SDA line while the SCL line is "L", data is transmitted.
Changing the SDA line while the SCL line is "H", a start or stop condition is recognized.
tSU.DAT
tHD.DAT
SCL
SDA
Figure 6
5.
Data Transmission Timing
Acknowledge
The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA
line to acknowledge the receipt of the 8-bit data.
When an internal write cycle is in progress, the device does not generate an acknowledge.
SCL
(E2PROM input)
1
8
9
SDA
(Master output)
Acknowledge
output
SDA
(E PROM output)
2
Start condition
tAA
Figure 7
10
Acknowledge Output Timing
tDH
Rev.2.0_00_U
6.
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Device addressing
To start communication, the master device on the system generates a start condition to the bus line. Next, the master
device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The higher 4 bits of the device address are the "Device Code", and are fixed to "1010".
In this IC, successive 3 bits are the "Slave Address". These 3 bits are used to identify a device on the system bus and
are compared with the predetermined value which is defined by the address input pins (A2, A1, A0). When the
comparison result matches, the slave device responds with an acknowledge during the 9th clock cycle.
Slave
Address
Device Code
1
0
1
0
A2
A1
MSB
A0
R/W
LSB
Figure 8
Device Address
11
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
7.
Rev.2.0_00_U
Write
7. 1
Byte write
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start
condition, this IC acknowledges it.
This IC then receives an 8-bit word address and responds with an acknowledge. After this IC receives 8-bit write
data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the
addressed memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
M
S
B
W
R
I
T
E
0 1 0 A2 A1 A0 0
WORD ADDRESS
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
Figure 9
12
A
A
C
C
K
K
Byte Write
S
T
O
P
A
C
K
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
7. 2
Page write
The page write mode allows up to 16 bytes to be written in a single write operation in this IC.
Its basic process to transmit data is as same as byte write, but it operates page write by sequentially receiving
8-bit write data as much data as the page size has.
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start
condition, it generates an acknowledge. Then this IC receives an 8-bit word address, and responds with an
acknowledge. After this IC receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data
corresponding to the next word address, and generates an acknowledge. This IC repeats reception of 8-bit write
data and generation of acknowledge in succession. This IC can receive as many write data as the maximum page
size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and
having the page size equal to the received write data.
S
T
A
R
T
SDA
LINE
DEVICE
ADDRESS
W
R
I
T
E
1 0 1 0 A2 A1 A0 0
M
S
B
L R A
S / C
BWK
WORD ADDRESS (n)
DATA (n)
W7W6 W5W4 W3 W2 W1W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
Figure 10
DATA (n + 1)
D7
A
C
K
S
T
O
P
DATA (n + x)
D0
D7
A
C
K
D0
A
C
K
Page Write
The lower 4 bits of the word address are automatically incremented every time when it receives 8-bit write data. If
the size of the write data exceeds 16 bytes, the higher 4 bits (W7 to W4) of the word address remain unchanged,
and the lower 4 bits are rolled over and the last 16-byte data that this IC received will be overwritten.
13
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
7. 3
Rev.2.0_00_U
Hardware write protect
Hardware write protect is available in this IC. When the WP pin is connected to VCC, write in all memory area is
inhibited.
Fix the WP pin during the period from the start condition to the stop condition in write operation (byte write and
page write). Written data in the address is not assurable if the condition of the WP pin is changed during this period.
Regarding the timing of hardware write protect, refer to "Figure 3 Write Cycle Timing".
Be sure to connect the WP pin to GND pin when hardware write protect is not used. Hardware write protect is valid
in the range of operation power supply voltage.
In this case, the users cannot perform the SWP (Set RSWP), CWP (Clear RSWP), PSWP (Set PSWP)
instructions.
As seen in Figure 11 when the hardware write protect is valid, this IC does not generate an acknowledge after data
input.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
M
S
B
W
R
I
T
E
0 1 0 A2 A1 A0 0
WORD ADDRESS
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
A
A
C
C
K
K
WP
Figure 11
14
Hardware Write Protect
S
T
O
P
N
A
C
K
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
7. 4
Software write protect
This IC has Permanent Software Write Protect (PSWP) and Reversible Software Write Protect (RSWP).
7. 4. 1
PSWP
If the software protect has been set with the PSWP (Set PSWP) instruction, 50% of the lower address (addresses
00h to 7Fh) in all memory is permanently write-protected. This write protect cannot be cleared by any instruction,
or by power-cycling the device, and regardless the state of WP pin. Also, once the PSWP instruction has been
successfully excuted, this IC no longer acknowledges any instruction (device code of "0110") to access the write
protect setting.
7. 4. 2
RSWP
If the software protect has been set with the SWP (Set RSWP) instruction, 50% of the lower address (addresses
00h to 7Fh) in all memory is write-protected. This write protect can be cleared with the CWP (Clear RSWP)
instruction.
These two instructions have the same format as a byte write instruction, but have a different device code. Like
the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents can be
set in all "Don't care". In the instructions of SWP and CWP, be sure to apply the high voltage of VHV to the A0 pin,
and input "H" or "L" to the A1 pin and A2 pin.
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
0 1 1 0 A2 A1 A0 0
SDA LINE
M
S
B
S
T
O
P
WORD ADDRESS
DATA
X X X X X X X X
X X X X X X X X
L R A
S / C
B W K
A
C
K
A
C
K
Remark X: Don't care
Figure 12
Table 11
Instruction
Memory area select*1
Software Write Protect
Device Select Code
Device Code
Slave Address
B7
B6
B5
B4
B3
B2
B1
1
0
1
0
A2
A1
A0
Set RSWP (SWP)
0
1
1
0
0
0
Clear RSWP (CWP)
0
1
1
0
0
1
*1
Set PSWP (PSWP)
0
1
1
0
A2
A1
Read SWP
0
1
1
0
0
0
Read CWP
0
1
1
0
0
1
Read PSWP*1
0
1
1
0
A2
A1
*1. Slave addresses (A2, A1, A0) are compared by the address input pins (A0,
address value which is set beforehand.
R/W
B0
Pin Condition
A2
A1
A2
A1
R/W
1
0
VSS
VSS
1
0
VSS
VCC
A0
0
A2
A1
1
1
VSS
VSS
1
1
VSS
VCC
A0
1
A2
A1
A1, A2) of a memory device
A0
A0
VHV
VHV
A0
VHV
VHV
A0
with the
15
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Table 12
Status
WP
Permanent
Software Write
Protect (PSWP)
X
0
Reversible
Software Write
Protect (RSWP)
1
0
No software protect
1
Table 13
Status
Permanent Software Write
Protect (PSWP)
Reversible Software Write
Protect (RSWP)
No software protect
16
Rev.2.0_00_U
Acknowledge for Write Instruction ( R / W bit = 0)
Instruction
SWP, CWP or PSWP
Page or byte write in
lower 128 bytes
SWP
CWP
PSWP
Page or byte write in
lower 128 bytes
SWP
CWP
PSWP
Page or byte write
SWP, CWP or PSWP
Page or byte write
SWP, CWP or PSWP
Page or byte write
ACK
Output
No
Word
Address
Don't care
ACK
Output
No
Don't care
ACK
Output
No
No
Yes
Address
Yes
Data
No
No
No
Yes
Yes
Don't care
Don't care
Don't care
No
Yes
Yes
Don't care
Don't care
Don't care
No
Yes
Yes
No
Yes
Yes
Yes
Address
Yes
Data
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Don't care
Don't care
Don't care
Address
Don't care
Address
Don't care
Address
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Don't care
Don't care
Don't care
Data
Don't care
Data
Don't care
Data
No
No
No
No
Yes
Yes
No
No
No
No
No
No
Yes
Yes
No
No
Data
Write
Acknowledge for Read Instruction ( R / W bit = 1)
Instruction
ACK
Output
Word
Address
ACK
Output
Data
ACK
Output
SWP, CWP or PSWP
No
Don't care
No
Don't care
No
SWP
CWP
PSWP
SWP, CWP or PSWP
No
Yes
Yes
Yes
Don't care
Don't care
Don't care
Don't care
No
No
No
No
Don't care
Don't care
Don't care
Don't care
No
No
No
No
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
7. 5
Acknowledge polling
Acknowledge polling is used to know the completion of the write cycle in this IC.
After this IC receives a stop condition and once starts the write cycle, all operations are forbidden and no
response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in this IC by detecting a response
from the slave device after transmitting the start condition, the device address and the read / write instruction
code to this IC, namely to the slave devices.
That is, if this IC does not generate an acknowledge, the write cycle is in progress and if this IC generates an
acknowledge, the write cycle has been completed.
It is recommended to use the read instruction "1" as the read / write instruction code transmitted by the master
device.
Acknowledge polling during read
DATA
SDA
LINE
S
T
O
P
S
T
A
R
T
S
T
A
R
T
R
E
A
D
DEVICE
ADDRESS 1
D2 D1 D0
NO ACK from
R Master Device
E
A
D
DEVICE
ADDRESS 1
R N
/ A
W C
K
S
T
O
P
S
T
A
R
T
DEVICE
ADDRESS
DATA
R A
/ C
WK
R A
/ C
WK
tWR
Acknowledge polling during write
DATA
SDA
LINE
D2 D1 D0
S
T
O
P
W
R
I
T
E
S
T
A
R
T
DEVICE
ADDRESS 0
R N
/ A
W C
K
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS 0
WORD
ADDRESS
R A
/ C
WK
A
C
K
tWR
Remark
Users are able to read data after acknowledge output in acknowledge polling during read.
Users are able to input word address and data after acknowledge output in acknowledge polling during write.
However, after that users input the write instruction, a start condition may not be input during data output. Input a
stop condition and the next instruction after data output and acknowledge output.
Figure 13
Usage Example of Acknowledge Polling
17
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
8.
Rev.2.0_00_U
Read
8. 1
Current address read
Either in writing or in reading this IC holds the last accessed memory address. The memory address is maintained
when the instruction transmission is not interrupted, and the memory address is maintained as long as the power
voltage does not decrease less than the operating voltage.
The master device can read the data at the memory address of the current address pointer without assigning the
word address as a result, when it recognizes the position of the address pointer in this IC. This is called "current
address read".
In the following the address counter in this IC is assumed to be "n".
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition, it responds with an acknowledge.
Next an 8-bit data at the address "n" is sent from this IC synchronous to the SCL clock. The address counter is
incremented and the content of the address counter becomes n + 1. The master device outputs stop condition not
an acknowledge, the reading of this IC is ended.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1
0
1
NO ACK from
Master Device
R
E
A
D
DATA
0 A2 A1 A0 1
M
S
B
L R
S /
B W
Figure 14
S
T
O
P
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in this IC.
In Read, the memory address counter in this IC is automatically incremented after output of the 8th bit of the data.
In Write, on the other hand, the higher bits of the memory address (the higher bits of the word address)*1 are left
unchanged and are not incremented.
∗1.
18
The higher 4 bits (W7 to W4) of the word address.
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
8. 2
Random read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "0" following a start
condition, it responds with an acknowledge.
This IC then receives an 8-bit word address and responds with an acknowledge. The memory address is loaded
to the address counter in this IC by these operations. Reception of write data does not follow in a dummy write
whereas reception of write data follows in byte write and in page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device can
read the data starting from the arbitrary memory address by transmitting a new start condition and performing the
same operation in the current address read.
That is, when this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1", following a
start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from this IC in synchronous
to the SCL clock. The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
S
T
A
R
T
SDA
LINE
DEVICE
ADDRESS
W
R
I
T
E
1 0 1 0 A2 A1 A0 0
M
S
B
S
T
A
R
T
WORD ADDRESS (n)
1 0 1 0 A2 A1 A0 1
W7 W6 W5 W4 W3 W2 W1 W0
L R A
S / C
B W K
DEVICE
ADDRESS
R
E
A
D
A
C
K
M
S
B
NO ACK from
Master Device
DATA
S
T
O
P
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
DUMMY WRITE
Figure 15
Random Read
19
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
8. 3
Rev.2.0_00_U
Sequential read
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition both in current address read and random read, it responds with an acknowledge.
When an 8-bit data is output from this IC synchronous to the SCL clock, the address counter is automatically
incremented.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in this IC incremented and
makes it possible to read data in succession. This is called sequential read.
The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first word address.
NO ACK from
Master Device
R
E
DEVICE A
ADDRESS D
SDA
LINE
1
R A
/ C
W K
A
C
K
D7
D0
DATA (n)
A
C
K
D7
D0
DATA (n + 1)
Figure 16
20
S
T
O
P
A
C
K
D7
D0
DATA (n + 2)
Sequential Read
D7
D0
DATA (n + x)
Rev.2.0_00_U
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Usage
1.
A pull-up resistor to SDA I/O pin and SCL input pin
In consideration of I2C-bus protocol function, the SDA I/O pin should be connected with a pull-up resistor. This IC
cannot transmit normally without using a pull-up resistor.
In case that the SCL input pin of this IC is connected to the Nch open-drain output pin of the master device, connect
the SCL pin with a pull-up resistor. As well, in case the SCL input pin of this IC is connected to the tri-state output pin
of the master device, connect the SCL pin with a pull-up resistor in order not to set it in "High-Z". This prevents this IC
from error caused by an uncertain output (High-Z) from the tri-state pin when resetting the master device during the
voltage drop.
2.
Equivalent circuits of input pin and I/O pin
The SCL pin and the SDA pin of this IC does not have a built-in pull-down or pull-up resistor. Each of A0 pin, A1 pin,
A2 pin and WP pin has a built-in pull-down resistor. The SDA pin is an open-drain output. The followings are
equivalent circuits of the pins.
SDA
SCL
Figure 17
SCL Pin
Figure 18
SDA Pin
A0, A1, A2
WP
Figure 19
WP Pin
Figure 20
A0, A1, A2 Pin
21
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
3.
Rev.2.0_00_U
Phase adjustment of the I2C-bus product
The I2C-bus product does not have a pin to reset (the internal circuit). The users cannot forcibly reset it externally. If
the communication interrupted, the users need to handle it as you do for software.
In this IC, users are able to reset the internal circuit by inputting a start condition and a stop condition.
Although the reset signal is input to the master device, this IC’s internal circuit does not go in reset, but it does by
inputting a stop condition to this IC. This IC keeps the same status thus cannot do the next operation. Especially, this
case corresponds to that only the master device is reset when the power supply voltage drops.
If the power supply voltage restored in this status, input the instruction after resetting (adjusting the phase with the
master device) this IC. How to reset is shown below.
[How to reset this IC]
This IC is able to be reset by a start and stop instructions. When this IC is reading data "0" or is outputting the
acknowledge signal, outputs "0" to the SDA line. In this status, the master device cannot output an instruction to the
SDA line. In this case, terminate the acknowledge output operation or the Read operation, and then input a start
condition.
Figure 21 shows this procedure.
First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets
the SDA line to "H". By this operation, this IC interrupts the acknowledge output operation or data output, so input a
start condition*1. When a start condition is input, this IC is reset. To make doubly sure, input the stop condition to
this IC. The normal operation is then possible.
Start
Condition
Start
Condition
Dummy Clock
1
2
8
Stop
Condition
9
SCL
SDA
Figure 21
Resetting Method
*1. After 9 clocks (dummy clock), if the SCL clock continues to being output without inputting a start condition, this
IC may go in the write operation when it receives a stop condition. To prevent this, input a start condition after
9 clocks (dummy clock).
Remark
22
Regarding this reset procedure with dummy clock, it is recommended to perform at the system
initialization after applying the power supply voltage.
Rev.2.0_00_U
4.
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Acknowledge check
The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a communication
error. This function allows detection of a communication failure during data communication between the master
device and this IC. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge
check with the master device.
5.
Power-on-clear circuit
By power-on-clear circuit, this IC initializes at the same time when the power supply voltage is raised. After the
initialization by the power-on-clear circuit is completed, this IC becomes standby state.
In order to use this IC safely, raise the power supply voltage depending on the following conditions.
5. 1
Initialization time
This IC initializes at the same time when the power supply voltage is raised. Input instructions to this IC after
initialization. This IC does not accept any instruction during initialization.
Figure 22 shows the initialization time of this IC.
100 m
10 m
Initialization time
(tINIT) max.
[s]
1.0 m
100 μ
10 μ
1.0 μ
1.0 μ
10 μ 100 μ 1.0 m 10 m 100 m
Power supply rise time (tRISE)
[s]
Figure 22
Initialization Time
23
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
5. 2
Rev.2.0_00_U
Caution when raising the power supply voltage
The internal circuit of this IC is reset by the power-on-clear circuit. In order for the power-on-clear circuit to
operate normally, the condition showed in Table 14 must be obeyed for raising the power supply voltage.
Due to the voltage drop, this IC may not perform normal communication if the power-on-clear operation condition
is not fulfilled, even when the master device is reset.
However, the interface of this IC is reset normally and the master device can make normal communication if
phase adjustment is performed, even when the power-on-clear operation condition of this IC is not fulfilled.
Table 14
Item
Power-off time
Power-off voltage
Symbol
tOFF
VBOT
Min.
100
−
Max.
−
0.6
Unit
μs
V
VCC min.
Power supply
voltage
0V
VBOT
*1
tINIT
*2
tOFF
tINIT
*2
*1. 0 V means that there is no potential difference between the VCC pin and the GND pin of this IC.
*2. tINIT is the time to initialize the internal IC. This IC does not accept any instruction during the initialization time.
Figure 23
6.
Caution When Raising the Power Supply Voltage
Write protect function during the low power supply voltage
This IC has a built-in detection circuit which operates with the low power supply voltage, cancels write when the power
supply voltage drops and power-on. Its detection and release voltages are 1.3 V typ. (refer to Figure 24).
This IC cancels write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission
and the write operation, data in the address written during the low power supply voltage is not assurable.
Power supply voltage
Detection voltage (−VDET)
1.3 V typ.
Release voltage (+VDET)
1.3 V typ.
Write instruction cancel
Figure 24
24
Operation during Low Power Supply Voltage
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
Rev.2.0_00_U
7.
Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of this IC are changed at the same time, it is necessary to prevent a start / stop condition from being
mistakenly recognized due to the effect of noise.
This IC may error if it does not recognize a start / stop condition correctly during transmission.
In this IC, it is recommended to set the delay time of 0.3 μs minimum from a falling edge of SCL for the SDA.
This is to prevent this IC from going in a start / stop condition due to the time lag caused by the load of the bus line.
tHD.DAT = 0.3 μs min.
SCL
SDA
Figure 25
8.
Data Hold Time
SDA pin and SCL pin noise suppression time
This IC includes a built-in low-pass filter at the SDA pin and the SCL pin to suppress noise. If the power supply
voltage is 5.0 V, noise with a pulse width of 100 ns or less can be suppressed.
For details of the assurable value, refer to noise suppression time (tl) in Table 10 in " AC Electrical
Characteristics".
300
Noise suppression time
(tI) max.
200
[ns]
100
2
3
4
5
Power supply voltage (VCC)
[V]
Figure 26
Noise Suppression Time for SDA Pin and SCL Pin
25
2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C02B
9.
Rev.2.0_00_U
Operation when input stop condition during input write data
This IC does the write operation only when it receives data of 1 byte or more and receives a stop condition
immediately after an acknowledge output.
Refer to Figure 27 regarding details.
Write valid
by stop condition
Write invalid
by stop condition
S
T
A
R
T
SDA
LINE
WORD ADDRESS (n)
DATA (n)
1 0 1 0 A2 A1 A0 0
W7W6 W5W4 W3 W2 W1W0
D7 D6 D5 D4 D3 D2 D1 D0
M
S
B
L R A
S / C
BWK
Figure 27
10.
Write invalid
by stop condition
W
R
I
T
E
DEVICE
ADDRESS
A
C
K
Write valid
by stop condition
Write invalid
by stop condition
DATA (n + 1)
D7
A
C
K
Write valid
by stop condition
S
T
O
P
DATA (n + x)
D0
D7
A
C
K
D0
A
C
K
Write Operation by Inputting Stop Condition during Write
Command cancel by start condition
By a start condition, users are able to cancel command which is being input. However, adjust the phase while this IC
is outputting "L" because users are not able to input a start condition. When users cancel the command, there may be
a case that the address will not be identified. Use random read for the read operation, not current address read.
Precautions
• Do not operate these ICs in excess of the absolute maximum ratings. Attention should be paid to the power supply
voltage, especially. The surge voltage which exceeds the absolute maximum ratings can cause latch-up and
malfunction. Perform operations after confirming the detailed operation condition in the data sheet.
• Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
26
2.0±0.1
(1.60)
0.5
0.25±0.1
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
No. PQ008-A-P-SD-3.0
TITLE
DFN-8-A-PKG Dimensions
No.
PQ008-A-P-SD-3.0
ANGLE
UNIT
mm
ABLIC Inc.
ø1.5 +0.1
-0
2.0±0.05
4.0±0.1
0.2±0.05
0.75±0.1
+0.1
ø1.0 - 0
4.0±0.1
2.3±0.1
4 3 21
5 6 78
Feed direction
No. PQ008-A-C-SD-1.0
TITLE
DFN-8- A - C a r r i e r T a p e
PQ008-A-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.2±0.5
Enlarged drawing in the central part
ø13±0.2
No. PQ008-A-R-SD-1.0
DFN-8- A - R e e l
TITLE
PQ008-A-R-SD-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
1.6
0.30
0.50
No. PQ008-A-L-SD-1.0
TITLE
DFN-8-A-Land Recommendation
PQ008-A-L-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
工商网监
湘ICP备2023018690号
