S-93A46B/56B/66B/76B/86B
www.ablic.com
FOR AUTOMOTIVE 125°C OPERATION
3-WIRE SERIAL E2PROM
Rev.1.3_00
© ABLIC Inc., 2016-2019
This IC is a high temperature operation 3-wire serial E2PROM for automotive components. This IC has the capacity of 1 K-bit,
2 K-bit, 4 K-bit, 8 K-bit and 16 K-bit, and the organization is 64 words × 16-bit, 128 words × 16-bit, 256 words × 16-bit, 512
words × 16-bit and 1024 words × 16-bit, respectively. Sequential read is available, at which time addresses are automatically
incremented in 16-bit blocks. The communication method is by the Microwire bus.
Caution
Before using the product in automobile control unit or medical equipment, it is imperative to contact our
sales representatives.
Features
• Memory capacity
S-93A46B:
1 K-bit (64-word × 16-bit)
S-93A56B:
2 K-bit (128-word × 16-bit)
S-93A66B:
4 K-bit (256-word × 16-bit)
S-93A76B:
8 K-bit (512-word × 16-bit)
S-93A86B:
16 K-bit (1024-word × 16-bit)
• Operation voltage range
Read:
2.5 V to 5.5 V
Write:
2.5 V to 5.5 V
• Operation frequency:
2.0 MHz max.
• Write time:
4.0 ms max.
• Sequential read
• CMOS schmitt input (CS, SK, DI)
• Write protect function during the low power supply voltage
• Function to protect against write due to erroneous instruction recognition
106 cycle / word*1 (Ta = +85°C)
• Endurance:
8 × 105 cycle / word*1 (Ta = +105°C)
5 × 105 cycle / word*1 (Ta = +125°C)
• Data retention:
100 years (Ta = +25°C)
50 years (Ta = +125°C)
• Initial delivery state:
FFFFh
• Wafer level burn-in (standard specification)
• Operation temperature range: Ta = −40°C to +125°C
• Lead-free (Sn 100%), halogen-free
• AEC-Q100 qualified *2
*1.
*2.
For each address (Word: 16-bit)
Contact our sales representatives for details.
Packages
•
8-Pin SOP (JEDEC)
5
8
4
1
(5.0 × 6.0 × t1.75 mm)
•
8
8-Pin TSSOP
5
1
4
(3.0 × 6.4 × t1.1 mm)
•
8
TMSOP-8
5
4
1
(2.9 × 4.0 × t0.8 mm)
•
5
8
HSNT-8(2030)
4
1
(3.0 × 2.0 × t0.5 mm)
1
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Block Diagram
Memory array
VCC
Address
decoder
Data register
GND
Output buffer
DI
Mode decode logic
CS
Clock pulse
monitoring circuit
SK
2
Clock generator
Voltage detector
DO
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales representatives for details of AEC-Q100 reliability specification.
Product Name Structure
1.
Product name
S-93AxxB
D0
A -
xxxx
U
3
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specification*1
J8T2:
8-Pin SOP (JEDEC), Tape
T8T2: 8-Pin TSSOP, Tape
K8T2: TMSOP-8, Tape
A8T1: HSNT-8(2030), Tape
Operation temperature
A:
Ta = −40°C to +125°C
Fixed
Product name
S-93A46B:
S-93A56B:
S-93A66B:
S-93A76B:
S-93A86B:
*1.
2.
1 K-bit
2 K-bit
4 K-bit
8 K-bit
16 K-bit
Refer to the tape drawing.
Packages
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
Dimension
FJ008-A-P-SD
FT008-A-P-SD
FM008-A-P-SD
PP008-A-P-SD
Tape
FJ008-D-C-SD
FT008-E-C-SD
FM008-A-C-SD
PP008-A-C-SD
Reel
FJ008-D-R-S1
FT008-E-R-S1
FM008-A-R-SD
PP008-A-R-SD
Land
−
−
−
PP008-A-L-SD
3
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
3.
Product name list
Product Name
S-93A46BD0A-J8T2U3
S-93A46BD0A-T8T2U3
S-93A46BD0A-K8T2U3
S-93A46BD0A-A8T1U3
S-93A56BD0A-J8T2U3
S-93A56BD0A-T8T2U3
S-93A56BD0A-K8T2U3
S-93A56BD0A-A8T1U3
S-93A66BD0A-J8T2U3
S-93A66BD0A-T8T2U3
S-93A66BD0A-K8T2U3
S-93A66BD0A-A8T1U3
S-93A76BD0A-J8T2U3
S-93A76BD0A-T8T2U3
S-93A76BD0A-K8T2U3
S-93A76BD0A-A8T1U3
S-93A86BD0A-J8T2U3
S-93A86BD0A-T8T2U3
S-93A86BD0A-K8T2U3
S-93A86BD0A-A8T1U3
4
Capacity
1 K-bit
1 K-bit
1 K-bit
1 K-bit
2 K-bit
2 K-bit
2 K-bit
2 K-bit
4 K-bit
4 K-bit
4 K-bit
4 K-bit
8 K-bit
8 K-bit
8 K-bit
8 K-bit
16 K-bit
16 K-bit
16 K-bit
16 K-bit
Package Name
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
HSNT-8(2030)
Rev.1.3_00
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Pin Configuration
1.
8-Pin SOP (JEDEC)
Top view
2.
1
8
2
7
3
6
4
5
1
2
3
4
8
7
6
5
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test
No connection
Power supply
Pin No.
1
2
3
4
5
6
7
8
Symbol
CS
SK
DI
DO
GND
TEST*1
NC
VCC
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test
No connection
Power supply
TMSOP-8
Top view
1
2
3
4
*1.
Symbol
CS
SK
DI
DO
GND
TEST*1
NC
VCC
8-Pin TSSOP
Top view
3.
Pin No.
1
2
3
4
5
6
7
8
Pin No.
8
7
6
5
1
2
3
4
5
6
7
8
Symbol
CS
SK
DI
DO
GND
TEST*1
NC
VCC
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test
No connection
Power supply
Connect to GND or the VCC pin, or set to open. Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
5
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
4.
Rev.1.3_00
HSNT-8(2030)
Top view
Pin No.
1
8
4
5
Bottom view
8
1
5
4
1
2
3
4
5
6
7
8
Symbol
CS
SK
DI
DO
GND
TEST*2
NC
VCC
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test
No connection
Power supply
*1
*1.
*2.
6
Connect the heat sink of backside at shadowed area to the board, and set electric potential open or GND.
However, do not use it as the function of electrode.
Connect to GND or the VCC pin, or set to open. Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Absolute Maximum Ratings
Table 1
Item
Power supply voltage
Input voltage
Output voltage
Operation ambient temperature
Storage temperature
Symbol
VCC
VIN
VOUT
Topr
Tstg
Absolute Maximum Rating
−0.3 to +6.5
−0.3 to +6.5
−0.3 to VCC + 0.3
−40 to +125
−65 to +150
Unit
V
V
V
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 2
Item
Symbol
Power supply voltage
VCC
High level input voltage
Low level input voltage
VIH
VIL
Condition
READ, EWDS, WRITE, ERASE, WRAL,
ERAL, EWEN
−
−
Ta = −40°C to +125°C
Min.
Max.
Unit
2.5
5.5
V
0.8 × VCC
0.0
VCC
0.2 × VCC
V
V
Pin Capacitance
Table 3
Item
Input capacitance
Output capacitance
Symbol
CIN
COUT
Condition
VIN = 0 V
VOUT = 0 V
(Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
8
pF
−
10
pF
−
Endurance
Item
Endurance
Symbol
NW
Table 4
Operation Ambient Temperature
Ta = −40°C to +85°C
Ta = −40°C to +105°C
Ta = −40°C to +125°C
Min.
106
8 × 105
5 × 105
Max.
−
−
−
Unit
cycle / word*1
cycle / word*1
cycle / word*1
Table 5
Operation Ambient Temperature
Ta = +25°C
Ta = −40°C to +125°C
Min.
100
50
Max.
−
−
Unit
year
year
*1. For each address (Word: 16-bit)
Data Retention
Item
Data retention
Symbol
−
7
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
DC Electrical Characteristics
Table 6
Item
Symbol
Current consumption (read) ICC1
Condition
No load at DO pin
Ta = −40°C to +125°C
VCC = 2.5 V to 4.5 V,
VCC = 4.5 V to 5.5 V,
fSK = 2.0 MHz
fSK = 2.0 MHz
Min.
Max.
Min.
Max.
−
−
0.5
0.8
Unit
mA
Table 7
Item
Symbol
Current consumption (write) ICC2
Condition
No load at DO pin
Ta = −40°C to +125°C
VCC = 2.5 V to 4.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
−
−
3.0
3.0
Unit
mA
Table 8
Item
Symbol
Standby current
consumption
ISB
Input leakage current
ILI
Output leakage current
ILO
Pull-down current
IPD
Low level output voltage
VOL
High level output voltage VOH
Data hold voltage
of write enable latch
8
VDH
Condition
CS = GND,
DO = Open,
Other input pins are
VCC or GND
CS, SK, DI,
VIN = GND to VCC
DO,
VOUT = GND to VCC
TEST,
VIN = GND ~ VCC
IOL = 2.1 mA
IOL = 100 μA
IOH = −400 μA
IOH = −100 μA
IOH = −10 μA
Only program disable
mode
Ta = −40°C to +125°C
VCC = 2.5 V to 4.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Unit
−
8.0
−
8.0
μA
−
1.5
−
1.5
μA
−
1.5
−
1.5
μA
−
2.0
−
2.0
μA
−
−
−
VCC − 0.3
VCC − 0.2
−
0.2
−
−
−
−
−
2.4
VCC − 0.3
VCC − 0.2
0.6
0.2
−
−
−
V
V
V
V
V
1.5
−
1.5
−
V
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
AC Electrical Characteristics
Table 9 Measurement Conditions
0.1 × VCC to 0.9 × VCC
0.5 × VCC
100 pF
Input pulse voltage
Output reference voltage
Output load
Table 10
Ta = −40°C to +125°C
Item
Symbol
Unit
VCC = 2.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
CS pin setup time
tCSS
0.15
−
0.15
−
μs
CS pin hold time
tCSH
0
−
0
−
μs
CS pin deselect time
tCDS
0.2
−
0.2
−
μs
Data setup time
tDS
0.1
−
0.1
−
μs
Data hold time
tDH
0.1
−
0.1
−
μs
Output delay time
tPD
−
0.25
−
0.25
μs
Clock frequency*1
0
2.0
0
2.0
MHz
fSK
Clock pulse width
tSKH, tSKL
0.2
−
0.1
−
μs
Output disable time
tHZ1, tHZ2
0
0.2
0
0.15
μs
Output enable time
tSV
0
0.2
0
0.15
μs
Write time
tPR
−
4.0
−
4.0
ms
*1. The clock cycle of the SK clock (frequency fSK) is 1/fSK μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.) + tSKH (min.) by minimizing
the SK clock cycle time.
1/fSK*2
tCSS
tCDS
CS
tSKH
tSKL
tCSH
SK
tDS
DI
tPD
tPD
High-Z
High-Z
tSV
(READ)
DO
tDH
Valid data
Valid data
*1
DO
tDS
tDH
High-Z
tHZ1
tHZ2
High-Z
(VERIFY)
*1.
*2.
Indicates high impedance.
1/fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics.
Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.) + tSKH (min.) by minimizing the SK clock cycle
time.
Figure 1
Timing Chart
9
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Pin Functions
1.
CS (chip select input) pin
This is an input pin to set a chip in the select status. In the "L" input level, this IC is in the non-select status and its
output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip
select to "H". Input any instruction code after power-on and a rising of chip select.
2.
SK (serial clock input) pin
This is a clock input pin to set the timing of serial data. A start bit, an operation code, an address and a write data are
received at a rising edge of clock. Data is output during rising edge of clock.
3.
DI (serial data input) pin
This pin is to input serial data. This pin receives a start bit, an operation code, an address and a write data. This pin
latches data at rising edge of serial clock.
4.
SO (serial data output) pin
This pin is to output serial data. The data output changes at rising edge of serial clock.
5.
TEST (test input) pin
This is an input pin in test mode. Connect to GND or the VCC pin, or set to open. Because this pin has a built-in
pull-down element, pull-down current flows when it connected to VCC pin.
Initial Delivery State
Initial delivery state of all addresses is "FFFFh".
10
Rev.1.3_00
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Instruction Sets
1.
S-93A46B
Table 11
Operation
Instruction
Start Bit
Address
Data
Code
SK input clock
1
2
3
4
5
6
7
8
9
10 to 25
READ (Data read)
1
1
0
A5
A4
A3
A2
A1
A0
D15 to D0 output*1
WRITE (Data write)
1
0
1
A5
A4
A3
A2
A1
A0
D15 to D0 input
ERASE (Data erase)
1
1
1
A5
A4
A3
A2
A1
A0
−
WRAL (Chip write)
1
0
0
0
1
x
x
x
x
D15 to D0 input
ERAL (Chip erase)
1
0
0
1
0
x
x
x
x
−
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
−
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
2.
S-93A56B
Table 12
Operation
Instruction
Start Bit
Address
Data
Code
SK input clock
1
2
3
4
5
6
7
8
9
10 11
12 to 27
READ (Data read)
1
1
0
x
A6 A5 A4 A3 A2 A1 A0 D15 to D0 output*1
WRITE (Data write)
1
0
1
x
A6 A5 A4 A3 A2 A1 A0
D15 to D0 input
ERASE (Data erase)
1
1
1
x
A6 A5 A4 A3 A2 A1 A0
−
WRAL (Chip write)
1
0
0
0
1
x
x
x
x
x
x
D15 to D0 input
ERAL (Chip erase)
1
0
0
1
0
x
x
x
x
x
x
−
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
−
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
−
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
3.
S-93A66B
Table 13
Instruction
SK input clock
READ (Data read)
WRITE (Data write)
ERASE (Data erase)
WRAL (Chip write)
ERAL (Chip erase)
EWEN (Write enable)
EWDS (Write disable)
*1.
Start Bit
1
1
1
1
1
1
1
1
Operation
Code
2
3
1
0
0
1
1
1
0
0
0
0
0
0
0
0
Address
4
A7
A7
A7
0
1
1
0
5
A6
A6
A6
1
0
1
0
6
A5
A5
A5
x
x
x
x
7
A4
A4
A4
x
x
x
x
8
A3
A3
A3
x
x
x
x
Data
9
A2
A2
A2
x
x
x
x
10
A1
A1
A1
x
x
x
x
11
A0
A0
A0
x
x
x
x
12 to 27
D15 to D0 output*1
D15 to D0 input
−
D15 to D0 input
−
−
−
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
11
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
4.
Rev.1.3_00
S-93A76B
Table 14
Operation
Address
Data
Instruction
Start Bit
Code
SK input clock
1
2
3
4
5
6
7
8
9 10 11 12 13
14 to 29
READ (Data read)
1
1
0
x A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 output*1
WRITE (Data write)
1
0
1
x A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 input
−
ERASE (Data erase)
1
1
1
x A8 A7 A6 A5 A4 A3 A2 A1 A0
WRAL (Chip write)
1
0
0
0
1
x
x
x
x
x
x
x
x
D15 to D0 input
−
ERAL (Chip erase)
1
0
0
1
0
x
x
x
x
x
x
x
x
−
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
x
x
−
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
x
x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
5.
S-93A86B
Table 15
Instruction
SK input clock
Operation
Start Bit
Code
1
2
3
READ (Data read)
1
0
4
5
6
A9 A8 A7
7
8
9
Data
10
11
A6 A5 A4 A3 A2
12
13
14 to 29
A1 A0 D15 to D0 output*1
WRITE (Data write)
1
0
1
A9 A8 A7
A6 A5 A4 A3 A2
A1 A0
ERASE (Data erase)
1
1
1
A9 A8 A7
A6 A5 A4 A3 A2
A1 A0
WRAL (Chip write)
1
0
0
0
1
x
x
x
x
x
x
x
x
ERAL (Chip erase)
1
0
0
1
0
x
x
x
x
x
x
x
x
D15 to D0 input
−
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
x
x
−
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
x
x
−
*1.
D15 to D0 input
−
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x = Don't care.
12
1
Address
Rev.1.3_00
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Operation
All instructions are executed by inputting the DI pin in synchronization with the rising of the SK pulse after the CS pin
goes to "H". An instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when the CS pin goes to "L". "L" must be input to the CS pin between commands during tCDS.
While "L" is being input to the CS pin, this IC is in standby mode, so the SK pin and the DI pin inputs are invalid and no
instructions are allowed.
1.
Start Bit
A start bit is recognized when the DI pin goes to "H" at the rising of the SK pulse after the CS pin goes to "H". After the
CS pin goes to "H", a start bit is not recognized even if the SK pulse is input as long as the DI pin is "L".
1. 1
Dummy clock
The SK clocks input while the DI pin is "L" before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when the CPU instruction set is 16 bits, the number of instruction set clocks can
be adjusted by inserting the 7-bit dummy clock in S-93A46B, the 5-bit dummy clock in S-93A56B/66B and the 3-bit
dummy clock in S-93A76B/86B.
1. 2
Start bit input failure
(1) When the output of the DO pin is "H" during the verify period after a write operation, if "H" is input to the DI pin
at the rising of the SK pulse, this IC recognizes that a start bit has been input. To prevent this failure, input "L"
to the DI pin during the verify operation period (refer to "3. 1 Verify operation").
(2) When a 3-wire interface is configured by connecting the DI input pin and the DO output pin, a period in which
the data output from the CPU and the serial memory collide may be generated, preventing successful input of
the start bit. Take the measures described in " 3-Wire Interface (Direct Connection between DI Pin and
DO Pin)".
2.
Reading (READ)
The READ instruction reads data from a specified address.
After the CS pin goes to "H", input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A0) has been latched, the output status of the DO pin changes from "High-Z" to "L", which is held
until the next rising of the SK pulse. 16-bit data starts to be output in synchronization with the next rising of the SK
pulse.
2. 1
Sequential read
After the 16-bit data at the specified address has been output, inputting the SK pulse while the CS pin is "H"
automatically increments the address, and causes the 16-bit data at the next address to be output sequentially.
The above method makes it possible to read the data in the whole memory space. The last address (An A1
A0 = 1 1 1) rolls over to the top address (An A1 A0 = 0 0 0).
13
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
CS
SK
1
DI
2
3
1
0
4
A5
5
6
7
A4 A3
A2
8
9
11
12
22
23
24
25
26
27
38
39
40
41
42
43
A1 A0
High-Z
DO
10
0
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
ADRINC
Figure 2
High-Z
ADRINC
Read Timing (S-93A46B)
CS
SK
1
DI
2
1
3
4
0
5
6
A6
A5
8
9
A4 A3
A2
10
11
12
13
14
24
25
26
27
28
40
29
41
42
43
44
45
A1 A0
x: S-93A56B
A7: S-93A66B
High-Z
DO
7
0
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
ADRINC
High-Z
ADRINC
Figure 3 Read Timing (S-93A56B/66B)
CS
SK
DI
DO
1
2
1
3
0
4
5
6
A8 A7
High-Z
7
8
9
A6 A5 A4
10
A3
11
A2
12
A1
13
14
15
16
26
27
28
29
30
31
43
44
45
46
47
A0
x: S-93A76B
A9: S-93A86B
0
D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
ADRINC
ADRINC
Figure 4 Read Timing (S-93A76B/86B)
14
42
High-Z
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
3.
Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when "L" is input to the
CS pin after a specified number of clocks have been input. The SK pin and the DI pin inputs are invalid during the
write period, so do not input an instruction.
Input an instruction while the output status of the DO pin is "H" or "High-Z".
A write operation is valid only in program enable mode (refer to "4. Write enable (EWEN) / write disable (EWDS)").
3. 1
Verify operation
A write operation executed by any instruction is completed within 4 ms (write time tPR), so if the completion of the
write operation is recognized, the write cycle can be minimized. A sequential operation to confirm the status of a
write operation is called a verify operation.
3. 1. 1
Operation method
After the write operation has started (CS pin = "L"), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting "H" to the CS pin again. This sequence is called a verify
operation, and the period that "H" is input to the CS pin after the write operation has started is called the verify
operation period.
The relationship between the output status of the DO pin and the write operation during the verify operation
period is as follows.
(1) DO pin = "L": Writing in progress (busy)
(2) DO pin = "H": Writing completed (ready)
3. 1. 2
Operation example
There are two methods to perform a verify operation: Waiting for a change in the output of the DO pin while
keeping the CS pin "H", or suspending the verify operation (CS pin = "L") once and then performing it again to
verify the output of the DO pin. The latter method allows the CPU to perform other processing during the wait
period, allowing an efficient system to be designed.
Caution
1. Input "L" to the DI pin during a verify operation.
2. If "H" is input to the DI pin at the rising of the SK pulse when the output status of the DO pin is
"H", this IC latches the instruction assuming that a start bit has been input. In this case, note
that the DO pin immediately enters "High-Z".
15
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
3. 2
Rev.1.3_00
Writing data (WRITE)
To write 16-bit data to a specified address, change the CS pin to "H" and then input the WRITE instruction,
address, and 16-bit data following the start bit. The write operation starts when the CS pin goes to "L". There is no
need to set the data to "1" before writing. When the clocks more than the specified number have been input, the
clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer
to " Function to Protect Against Write due to Erroneous Instruction Recognition".
tCDS
CS
Standby
Verify
SK
1
DI
2
3
0
1
4
5
6
7
8
9
10
25
A5
A4
A3
A2
A1
A0
D15
D0
High-Z
DO
tSV
tHZ1
busy
ready
High-Z
tPR
Figure 5
Data Write Timing (S-93A46B)
tCDS
CS
Standby
Verify
SK
1
DI
2
0
3
4
1
5
6
7
8
9
A6
A5
A4
A3
A2
10
A1
11
12
27
A0
D15
D0
tSV
x: S-93A56B
High-Z
DO
tHZ1
A7: S-93A66B
busy
ready
High-Z
tPR
Figure 6
Data Write Timing (S-93A56B/66B)
tCDS
CS
SK
1
DI
DO
2
0
3
4
1
High-Z
5
6
7
8
9
10
11
12
13
14
29
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D0
x: S-93A76B
A9: S-93A86B
tSV
tHZ1
busy
tPR
Figure 7
16
Standby
Verify
Data Write Timing (S-93A76B/86B)
ready
High-Z
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
3. 3
Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to "1", change the CS pin to "H", and then
input the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when the CS pin goes to "L". When the clocks more than the specified number have been input,
the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit,
refer to " Function to Protect Against Write due to Erroneous Instruction Recognition".
tCDS
Standby
Verify
CS
SK
1
2
DI
1
3
1
4
5
6
7
8
A5
A4
A3
A2
A1
9
A0
tSV
High-Z
DO
tHZ1
busy
ready
High-Z
tPR
Figure 8
Data Erase Timing (S-93A46B)
tCDS
CS
Standby
Verify
SK
1
2
DI
1
3
4
1
5
6
7
8
9
A6
A5
A4
A3
A2
A1
11
A0
tSV
x: S-93A56B
A7: S-93A66B
High-Z
DO
10
busy
tHZ1
ready
High-Z
tPR
Figure 9
Data Erase Timing (S-93A56B/66B)
tCDS
SK
1
2
DI
1
DO
Standby
Verify
CS
3
4
1
High-Z
5
6
7
8
9
A8
A7
A6
A5
A4
x: S-93A76B
A9: S-93A86B
10
A3
11
A2
12
A1
13
A0
tSV
busy
tPR
Figure 10
tHZ1
ready
High-Z
Data Erase Timing (S-93A76B/86B)
17
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
3. 4
Rev.1.3_00
Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change the CS pin to "H", and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write
operation starts when the CS pin goes to "L". There is no need to set the data to "1" before writing. When the
clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL
instruction. For details of the clock pulse monitoring circuit, refer to " Function to Protect Against Write due to
Erroneous Instruction Recognition".
tCDS
CS
Standby
Verify
SK
1
2
DI
0
3
0
4
5
0
6
7
8
1
10
25
D15
D0
4xs
High-Z
DO
9
tSV
tHZ1
busy
ready
High-Z
tPR
Figure 11
Chip Write Timing (S-93A46B)
tCDS
CS
Standby
Verify
SK
1
2
DI
0
3
4
0
5
0
6
7
9
10
11
1
12
27
D15
D0
tSV
6xs
High-Z
DO
8
tHZ1
busy
ready
High-Z
tPR
Figure 12
Chip Write Timing (S-93A56B/66B)
tCDS
CS
SK
1
2
DI
0
DO
3
0
4
0
5
6
7
8
9
10
1
8xs
High-Z
11
12
13
14
29
D15
D0
tSV
tHZ1
busy
tPR
Figure 13
18
Standby
Verify
Chip Write Timing (S-93A76B/86B)
ready
High-Z
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
3. 5
Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to "1", change the CS pin to "H", and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to
input data. The chip erase operation starts when the CS pin goes to "L". When the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock
pulse monitoring circuit, refer to " Function to Protect Against Write due to Erroneous Instruction
Recognition".
CS
SK
1
2
3
4
DI
0
0
1
5
6
7
9
0
t HZ1
tSV
4xs
High-Z
DO
8
Standby
Verify
tCDS
Busy
Ready
High-Z
tPR
Figure 14
Chip Erase Timing (S-93A46B)
CS
SK
1
2
3
4
DI
0
0
1
5
6
7
8
9
10
Standby
Verify
tCDS
11
0
t HZ1
tSV
6xs
High-Z
Busy
DO
Ready
High-Z
tPR
Figure 15
Chip Erase Timing (S-93A56B/66B)
CS
tCDS
SK
1
2
3
4
DI
0
0
1
DO
5
6
7
8
9
10
11
12
Standby
Verify
13
0
8xs
High-Z
tSV
tHZ1
busy
ready
High-Z
tPR
Figure 16
Chip Erase Timing (S-93A76B/86B)
19
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
4.
Rev.1.3_00
Write enable (EWEN) / write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is enabled
is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After the CS pin goes to "H", input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting "L" to the CS pin after the last address (optional) has been input.
Standby
CS
SK
1
DI
2
3
0
4
5
6
7
8
9
0
4xs
11 = EWEN
00 = EWDS
Figure 17
Write Enable / Disable Timing (S-93A46B)
Standby
CS
SK
1
DI
2
0
3
4
5
6
7
8
9
10
11
0
6xs
11 = EWEN
00 = EWDS
Figure 18
Write Enable / Disable Timing (S-93A56B/66B)
Standby
CS
SK
1
DI
2
0
3
4
5
6
7
8
9
10
11
12
13
0
11 = EWEN
00 = EWDS
Figure 19
8xs
Write Enable / Disable Timing (S-93A76B/86B)
Remark It is recommended to execute an EWDS instruction for preventing an incorrect write operation if a write
instruction is erroneously recognized when executing instructions other than write instruction, and
immediately after power-on and before power-off.
20
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Write Protect Function during the Low Power Supply Voltage
This IC provides a built-in detection circuit to detect a low power supply voltage. When the power supply voltage is low or
at power-on, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable (EWDS)
status is automatically set. The detection voltage is 1.55 V typ., the release voltage is 1.85 V typ., and there is a
hysteresis of about 0.3 V (refer to Figure 20). Therefore, when a write operation is performed after the power supply
voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN)
must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
Hysteresis
about 0.3 V
Power supply voltage
Detection voltage (−VDET)
1.55 V typ.
Release voltage (+VDET)
1.85 V typ.
Write instructions are cancelled
Write disable status (EWDS) is automatically set
Figure 20
Operation during the Low Power Supply Voltage
21
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Rev.1.3_00
Function to Protect Against Write due to Erroneous Instruction Recognition
This IC provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by
canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock
count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse
whose count other than the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected.
Example:
Erroneous Recognition of EWDS as ERASE
Example of S-93A76B/86B
Noise pulse
CS
1
2
3
4
5
6
7
8
9
10
11 12
13
SK
DI
0
0
0
0
0
0
0
0
0
0
0
0
Erroneous recognition as ERASE 1 1 1 0
instruction due to noise pulse
0
0 00
0
0
0
0
0
0
0
0
Input EWDS instruction
1
In products that do not incorporate a clock pulse monitoring circuit, "FFFFh" is mistakenly written to address
00h. However the S-93A76B/86B detects the overcount and cancels the instruction without performing a write
operation.
Figure 21
22
Example of Clock Pulse Monitoring Circuit Operation
Rev.1.3_00
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
3-Wire Interface (Direct Connection between DI Pin and DO Pin)
There are two types of serial interface configurations: a 4-wire interface configured using the CS pin, the SK pin, the DI
pin and the DO pin and a 3-wire interface that connects the DI pin and the DO pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI pin and the DO
pin of this IC via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in being input to
the DI pin (refer to Figure 22).
CPU
S-93A46B/56B/66B/76B/86B
SIO
DI
DO
R: 10 kΩ to 100 kΩ
Figure 22
Connection of 3-Wire Interface
Input Pin and Output Pin
1.
Connection of input pin
All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you design.
Especially, set the CS pin to "L" at power-on, power-off, and during standby. The error write does not occur as long as
the CS pin is "L". Set the CS pin to GND via a resistor (the pull-down resistor of 10 kΩ to 100 kΩ).
To prevent the error for sure, it is recommended to use equivalent pull-down resistors for input pins other than the CS
pin.
2.
Equivalent circuit of input pin and output pin
Figure 23, Figure 24 and Figure 25 show the equivalent circuits of input pins in this IC. In Figure 23 and Figure 24,
none of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to
prevent a floating status.
In Figure 25, the TEST pin has a built-in pull-down element.
Figure 26 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z".
23
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
2. 1
Input pin
CS
Figure 23
CS Pin
SK, DI
Figure 24
SK, DI Pin
Figure 25
TEST Pin
TEST
24
Rev.1.3_00
Rev.1.3_00
2. 2
FOR AUTOMOTIVE 125°C OPERATION 3-WIRE SERIAL E2PROM
S-93A46B/56B/66B/76B/86B
Output pin
VCC
DO
Figure 26
3.
DO Pin
Input pin noise suppression time
This IC has a built-in low-pass filter at the SK pin, the DI pin and the CS pin to suppress noise. If the supply voltage is
5.0 V, noise with a pulse width of 20 ns or less at room temperature can be suppressed by the low-pass filter.
Note that noise with a pulse width of more than 20 ns is recognized as a pulse since the noise can not be suppressed
if the voltage exceeds VIH / VIL.
Precautions
• Do not operate these ICs in excess of the absolute maximum ratings. Attention should be paid to the power supply
voltage, especially. The surge voltage which exceeds the absolute maximum ratings can cause latch-up and
malfunction. Perform operations after confirming the detailed operation condition in the data sheet.
• Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
25
5.02±0.2
8
5
1
4
1.27
0.20±0.05
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø2.0±0.05
8.0±0.1
2.1±0.1
6.7±0.1
1
8
4
5
Feed direction
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
+0.3
3.00 -0.2
8
5
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
8.0±0.1
ø1.55 -0.05
(4.4)
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
4.00±0.1
4.00±0.1
1.00±0.1
+0.1
1.5 -0
1.05±0.05
0.30±0.05
3.25±0.05
4
1
5
8
Feed direction
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
16.5max.
13.0±0.3
Enlarged drawing in the central part
13±0.2
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
2.0±0.1
8
5
(1.70)
1
4
+0.05
0.08 -0.02
0.5
0.23±0.1
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
No. PP008-A-P-SD-2.0
TITLE
HSNT-8-A-PKG Dimensions
No.
PP008-A-P-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.0±0.05
4.0±0.1
0.25±0.05
+0.1
ø1.0 -0
0.60±0.05
4.0±0.1
2.3±0.05
4 321
5 6 78
Feed direction
No. PP008-A-C-SD-1.0
TITLE
HSNT-8-A-Carrier Tape
No.
PP008-A-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
+1.0
9.0 - 0.0
11.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PP008-A-R-SD-1.0
HSNT-8-A-Reel
TITLE
No.
PP008-A-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
5,000
1.6
0.30
0.50
No. PP008-A-L-SD-1.0
TITLE
No.
HSNT-8-A
-Land Recommendation
PP008-A-L-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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