3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
DATASHEET
1
GD25Q40C
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Contents
1.
FEATURES .................................................................................................................................................. 4
2.
GENERAL DESCRIPTION .......................................................................................................................... 5
3.
MEMORY ORGANIZATION ......................................................................................................................... 7
4.
DEVICE OPERATION .................................................................................................................................. 8
5.
DATA PROTECTION ................................................................................................................................... 9
6.
STATUS REGISTER .................................................................................................................................. 11
7.
COMMANDS DESCRIPTION .................................................................................................................... 13
7.1.
W RITE ENABLE (WREN) (06H) ............................................................................................................. 16
7.2.
W RITE DISABLE (WRDI) (04H) .............................................................................................................. 16
7.3.
READ STATUS REGISTER (RDSR) (05H OR 35H) ................................................................................... 17
7.4.
W RITE STATUS REGISTER (WRSR) (01H) ............................................................................................. 17
7.5.
W RITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................ 18
7.6.
READ DATA BYTES (READ) (03H) ........................................................................................................ 18
7.7.
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) ..................................................................... 19
7.8.
DUAL OUTPUT FAST READ (3BH) .......................................................................................................... 19
7.9.
QUAD OUTPUT FAST READ (6BH) ......................................................................................................... 20
7.10. DUAL I/O FAST READ (BBH) ................................................................................................................. 20
7.11. QUAD I/O FAST READ (EBH) ................................................................................................................. 22
7.12. QUAD I/O W ORD FAST READ (E7H) ...................................................................................................... 23
7.13. SET BURST WITH W RAP (77H) .............................................................................................................. 24
7.14. PAGE PROGRAM (PP) (02H) ................................................................................................................. 24
7.15. QUAD PAGE PROGRAM (32H)................................................................................................................ 25
7.16. SECTOR ERASE (SE) (20H) .................................................................................................................. 26
7.17. 32KB BLOCK ERASE (BE) (52H) ........................................................................................................... 27
7.18. 64KB BLOCK ERASE (BE) (D8H) .......................................................................................................... 27
7.19. CHIP ERASE (CE) (60/C7H) .................................................................................................................. 28
7.20. DEEP POWER-DOWN (DP) (B9H) .......................................................................................................... 28
7.21. RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH) 29
7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) .............................................................................. 30
7.23. READ IDENTIFICATION (RDID) (9FH) ..................................................................................................... 31
7.24. HIGH PERFORMANCE MODE (HPM) (A3H) ............................................................................................. 31
7.25. CONTINUOUS READ MODE RESET (CRMR) (FFH) ................................................................................. 32
7.26. READ UNIQUE ID (4BH) ........................................................................................................................ 33
7.27. PROGRAM/ERASE SUSPEND (PES) (75H) .............................................................................................. 33
7.28. PROGRAM/ERASE RESUME (PER) (7AH)............................................................................................... 34
7.29. ERASE SECURITY REGISTERS (44H) ...................................................................................................... 34
7.30. PROGRAM SECURITY REGISTERS (42H) ................................................................................................. 35
7.31. READ SECURITY REGISTERS (48H)........................................................................................................ 36
7.32. ENABLE RESET (66H) AND RESET (99H) ............................................................................................... 36
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Dual and Quad Serial Flash
GD25Q40C
7.33. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ........................................................................ 37
8.
ELECTRICAL CHARACTERISTICS ......................................................................................................... 42
8.1.
POWER-ON TIMING .......................................................................................................................... 42
8.2.
INITIAL DELIVERY STATE................................................................................................................. 42
8.3.
ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 42
8.4.
CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 43
8.5.
DC CHARACTERISTICS .................................................................................................................... 44
8.6.
AC CHARACTERISTICS .................................................................................................................... 47
9.
ORDERING INFORMATION ...................................................................................................................... 54
9.1.
10.
VALID PART NUMBERS .......................................................................................................................... 55
PACKAGE INFORMATION .................................................................................................................... 57
10.1. PACKAGE SOP8 150MIL ...................................................................................................................... 57
10.2. PACKAGE SOP8 208MIL ...................................................................................................................... 58
10.3. PACKAGE TSSOP8 173MIL.................................................................................................................. 59
10.4. PACKAGE DIP8 300MIL ........................................................................................................................ 60
10.5. PACKAGE USON8 (3*2MM, THICKNESS 0.45MM) .................................................................................... 61
10.6. PACKAGE USON8 (3*4MM) ................................................................................................................... 62
11.
REVISION HISTORY.............................................................................................................................. 63
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Dual and Quad Serial Flash
GD25Q40C
1. FEATURES
◆ 4M-bit Serial Flash
◆ Fast Program/Erase Speed
-512K-byte
-Page Program time: 0.6ms typical
-256 bytes per programmable page
-Sector Erase time: 45ms typical
-Block Erase time: 0.15/0.25s typical
◆ Standard, Dual, Quad SPI
-Chip Erase time: 2.5s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
◆ Flexible Architecture
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
◆ High Speed Clock Frequency
◆ Low Power Consumption
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-1μA typical deep power down current
-Quad I/O Data transfer up to 480Mbits/s
-1μA typical standby current
◆ Software/Hardware Write Protection
◆ Advanced Security Features
-Write protect all/portion of memory via software
-128-Bit Unique ID for each device
-Enable/Disable protection with WP# Pin
-4x256-Byte Security Registers With OTP Locks
-Top/Bottom block protection
-Serial Flash Discoverable Parameters (SFDP) Register
◆ Minimum 100,000 Program/Erase Cycles
◆ Single Power Supply Voltage
-Full voltage range: 2.7~3.6V
◆ Data Retention
◆ Allows XIP (execute in place) Operation
-20-year data retention typical
-Continuous Read With 8/16/32/64-byte Wrap
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Dual and Quad Serial Flash
GD25Q40C
2. GENERAL DESCRIPTION
The GD25Q40C (4M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
CS#
1
8
SO/
IO1
2
7
Top View
VCC
CS#
1
8
HOLD#/
IO3
SO/
IO1
2
7
HOLD#/
IO3
3
6
SCLK
4
5
SI/
IO0
WP#/
IO2
3
6
SCLK
WP#/
IO2
VSS
4
5
SI/
IO0
VSS
Top View
8–LEAD VSOP/SOP
VCC
8–LEAD WSON/USON
PIN DESCRIPTION
Pin Name
I/O
Description
CS#
I
Chip Select Input
SO (IO1)
I/O
Data Output (Data Input Output 1)
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
Ground
VSS
SI (IO0)
I/O
Data Input (Data Input Output 0)
SCLK
I
Serial Clock Input
HOLD# (IO3)
I/O
Hold Input (Data Input Output 3)
VCC
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
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Dual and Quad Serial Flash
GD25Q40C
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SPI
Command &
Control Logic
Write Protect Logic
and Row Decode
Status
Register
High Voltage
Generators
Page Address
Latch/Counter
Flash
Memory
Column Decode And
256-Byte Page Buffer
SO(IO1)
Byte Address
Latch/Counter
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
3. MEMORY ORGANIZATION
GD25Q40C
Each device has
Each block has
Each sector has
Each page has
512K
64/32K
4K
256
bytes
2K
256/128
16
-
pages
128
16/8
-
-
sectors
8/16
-
-
-
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q40C 64K Bytes Block Sector Architecture
Block
7
6
……
……
2
1
0
Sector
Address range
127
07F000H
07FFFFH
……
……
……
112
070000H
070FFFH
111
06F000H
06FFFFH
……
……
……
96
060000H
060FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q40C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q40C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q40C supports Quad SPI operation when using the “Quad Output Fast Read” (6BH), ”Quad I/O Fast
Read”(EBH), “Quad I/O Word Fast Read” (E7H) and “Quad Page Program” (32H) commands. These commands allow data
to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the
SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI
commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
5. DATA PROTECTION
The GD25Q40C provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
◆
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.
◆
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
◆
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1.0 GD25Q40C Protected area size (CMP=0)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
7
070000H-07FFFFH
64KB
Upper 1/8
0
0
0
1
0
6 and 7
060000H-07FFFFH
128KB
Upper 1/4
0
0
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/8
0
1
0
1
0
0 and 1
000000H-01FFFFH
128KB
Lower 1/4
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
X
1
X
X
0 to 7
000000H-07FFFFH
512KB
ALL
1
0
0
0
1
7
07F000H-07FFFFH
4KB
Upper 1/128
1
0
0
1
0
7
07E000H-07FFFFH
8KB
Upper 1/64
1
0
0
1
1
7
07C000H-07FFFFH
16KB
Upper 1/32
1
0
1
0
X
7
078000H-07FFFFH
32KB
Upper 1/16
1
0
1
1
0
7
078000H-07FFFFH
32KB
Upper 1/16
1
1
0
0
1
0
000000H-000FFFH
4KB
Lower 1/128
1
1
0
1
0
0
000000H-001FFFH
8KB
Lower 1/64
1
1
0
1
1
0
000000H-003FFFH
16KB
Lower 1/32
1
1
1
0
X
0
000000H-007FFFH
32KB
Lower 1/16
1
1
1
1
0
0
000000H-007FFFH
32KB
Lower 1/16
1
X
1
1
1
0 to 7
000000H-07FFFFH
512KB
ALL
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Dual and Quad Serial Flash
GD25Q40C
Table1.1 GD25Q40C Protected area size (CMP=1)
Status Register Content
BP4
BP3
BP2
BP1
Memory Content
BP0
Blocks
Addresses
Density
Portion
000000H-07FFFFH
512KB
ALL
X
X
0
0
0
0 to 7
0
0
0
0
1
0 to 6
000000H-06FFFFH
448KB
Lower 7/8
0
0
0
1
0
0 to 5
000000H-05FFFFH
384KB
Lower 3/4
0
0
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
1
0
0
1
1 to 7
010000H-07FFFFH
448KB
Upper 7/8
0
1
0
1
0
2 to 7
020000H-07FFFFH
384KB
Upper 3/4
0
1
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
X
1
X
X
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 7
000000H-07EFFFH
508KB
Lower 127/128
1
0
0
1
0
0 to 7
000000H-07DFFFH
504KB
Lower 63/64
1
0
0
1
1
0 to 7
000000H-07BFFFH
496KB
Lower 31/32
1
0
1
0
X
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
0
1
1
0
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
1
0
0
1
0 to 7
001000H-07FFFFH
508KB
Upper 127/128
1
1
0
1
0
0 to 7
002000H-07FFFFH
504KB
Upper 63/64
1
1
0
1
1
0 to 7
004000H-07FFFFH
496KB
Upper 31/32
1
1
1
0
X
0 to 7
008000H-07FFFFH
480KB
Upper 15/16
1
1
1
1
0
0 to 7
008000H-07FFFFH
480KB
Upper 15/16
1
X
1
1
1
NONE
NONE
NONE
NONE
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
6. STATUS REGISTER
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
HPF
Reserved
Reserved
LB
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1
SRP0
#WP
Status Register
0
0
X
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
X
Power Supply Lock-Down(1) (2)
1
1
X
One Time Program(2)
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
WP#=0, the Status Register locked and cannot be written
to.
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
pins are enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD# pin is tied directly to the power
supply or ground.)
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits
to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
HPF bit
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit sets to 1,
it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is not in High
Performance Mode.
SUS bit
The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, powerup cycle.
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Dual and Quad Serial Flash
GD25Q40C
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might
be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been shifted in. For the commands of Read, Fast Read, Read Status Register or Release from Deep PowerDown, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can
be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to
deselected status.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command
is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
Write Enable
Write Disable
Volatile SR
Write Enable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Continuous Read Mode
Reset
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
06H
04H
50H
Enable Reset
Reset
Set Burst with Wrap
Byte 2
05H
35H
01H
03H
0BH
3BH
(S7-S0)
(S15-S8)
S7-S0
A23-A16
A23-A16
A23-A16
BBH
A23-A8(2)
6BH
A23-A16
EBH
E7H
Byte 3
Byte 4
Byte 5
Byte 6
(continuous)
(continuous)
S15-S8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
A7-A0
M7-M0(2)
A15-A8
(D7-D0)(1)
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy(5)
(D7-D0)(3)
(continuous)
dummy(6)
(D7-D0)(3)
(continuous)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(continuous)
dummy
(D7-D0)(3)
FFH
02 H
32H
20H
52H
D8H
C7/60
H
66H
99H
77H
n-Bytes
W6-W4
13
D7-D0
D7-D0
Next byte
(continuous)
3.3V Uniform Sector
Dual and Quad Serial Flash
Program/Erase
Suspend
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Manufacturer/
Device ID
High Performance
Mode
Read Serial Flash
Discoverable
Parameter
Read Identification
75H
Read Unique ID
7AH
B9H
ABH
GD25Q40C
dummy
dummy
dummy
(DID7DID0)
(continuous)
90H
00H
00H
00H
(MID7MID0)
(DID7DID0)
(continuous)
A3H
dummy
dummy
dummy
5AH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
(continuous)
9FH
(MID7M0)
(JDID15JDID8)
(JDID7JDID0)
4BH
00H
00H
00H
ABH
(continuous)
dummy
(UID7UID0)
Erase Security
Registers(8)
Program Security
Registers(8)
Read Security
Registers(8)
44H
A23-A16
A15-A8
A7-A0
42H
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8,
A4, A0, M4, M0
IO1 = A21, A17, A13, A9,
A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
14
(continuous)
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address;
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
9. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, x, x)
10. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0,
M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1,
M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2,
x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3,
x, x, x, x, MID7, MID3, DID7, DID3, …)
Table of ID Definitions:
GD25Q40C
Operation Code
MID7-MID0
ID15-ID8
ID7-ID0
9FH
C8
40
13
90H
C8
12
ABH
12
15
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), and Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Powerup and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure 3. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
Command
04H
High-Z
16
6
7
3.3V Uniform Sector
Dual and Quad Serial Flash
7.3.
GD25Q40C
Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The
command code “35H”, the SO will output Status Register bits S15~S8.
Figure 4. Read Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Command
SI
05H or 35H
SO
High-Z
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
MSB
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
7
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S13, S12, S11, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register
(WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bit will be cleared
to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the
Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status
Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with
the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to
be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware
Protected Mode is entered.
Figure 5. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
6
Command
SI
SO
01H
Status Register in
MSB
5
4
3
High-Z
17
2
1
0 15 14 13 12 11 10 9
8
3.3V Uniform Sector
Dual and Quad Serial Flash
7.5.
GD25Q40C
Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command, and any other commands cannot be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command
will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure 6. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
SI
SO
High-Z
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a
Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore,
be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
SO
03H
High-Z
24-bit address
23 22 21
3
2
1
0
MSB
MSB
18
7
6
5
Data Out1
4 3 2 1
Data Out2
0
3.3V Uniform Sector
Dual and Quad Serial Flash
7.7.
GD25Q40C
Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
0BH
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
SO
7 6
MSB
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24-bit address
3BH
23 22 21
3
2
1
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
6
0
6
Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB
7
19
4
2
0
6
4
2
0
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 10. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI(IO0)
24-bit address
6BH
23 22 21
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
3
2
1
0
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
7.10.
SI(IO0)
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next
command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M7-0) before issuing normal command.
20
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 11. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
5
3
1
7
Command
SI(IO0)
BBH
SO(IO1)
7
A23-16
4
2
0
6
5
3
1
7
A15-8
4
2
0
5
3
1
A7-0
CS#
SCLK
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
Figure 12. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
6
4
2
0
6
4
5
3
1
7
5
3
1
7
5
3
1
7
5
7
A23-16
A15-8
A7-0
M7-4 Dummy
CS#
SCLK
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
21
Byte4
6
4
7
5
M7-4 Dummy
3.3V Uniform Sector
Dual and Quad Serial Flash
7.11.
GD25Q40C
Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
Command
SI(IO0)
EBH
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure 14. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0 M7-0
22
8
9 10 11 12 13 14 15
Dummy
Byte1 Byte2
3.3V Uniform Sector
Dual and Quad Serial Flash
7.12.
GD25Q40C
Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address
bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read
command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the
next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code.
The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
1
2
3
4
5
6
7
Command
SI(IO0)
E7H
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Figure 16. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
8
9 10 11 12 13 14 15
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
23
3.3V Uniform Sector
Dual and Quad Serial Flash
7.13.
GD25Q40C
Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24
dummy bits Send 8 bits “Wrap bits” CS# goes high.
W6,W5
W4=0
W4=1 (default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0, 0
Yes
8-byte
No
N/A
0, 1
Yes
16-byte
No
N/A
1, 0
Yes
32-byte
No
N/A
1, 1
Yes
64-byte
No
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1.
Figure17. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
x
x
x
x
x
x
4
x
SO(IO1)
x
x
x
x
x
x
5
x
WP#(IO2)
x
x
x
x
x
x
6
x
HOLD#(IO3)
x
x
x
x
x
x
x
x
SCLK
Command
SI(IO0)
77H
W6-W4
7.14.
Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least
1 byte data on SI CS# goes high. The command sequence is shown in Figure18. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Page Program (PP) command is not executed.
24
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure 18. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24-bit address
23 22 21
3
2
Data Byte 1
1
0 7
MSB
6
5
4
3
2
1
0
2078
2079
6
2077
7
2075
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
MSB
CS#
2076
02H
2074
SI
1
0
SCLK
Data Byte 2
SI
7
6
5
4
3
2
MSB
7.15.
Data Byte 3
1
0 7
6
5
4
3
2
MSB
Data Byte 256
1
0
5
4
3
2
MSB
Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure19. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
25
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 19.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI(IO0)
24-bit address
32H
23 22 21
3
Byte1 Byte2
0 4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
538
539
540
541
542
543
1
537
2
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
536
CS#
SCLK
Byte11Byte12
Byte253
Byte256
SI(IO0)
4
SO(IO1)
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
WP#(IO2)
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
HOLD#(IO3)
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7.16.
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
Sector Erase (SE) (20H)
The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
26
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 20. Sector Erase Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
8
Command
SI
9
29 30 31
24 Bits Address
20H
7.17.
7
23 22
MSB
2
1
0
32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 21. 32KB Block Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
Command
52H
7.18.
7
8
9
29 30 31
24 Bits Address
23 22
MSB
2
1
0
64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
27
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 22. 64KB Block Erase Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
8
9
Command
SI
29 30 31
24 Bits Address
D8H
7.19.
7
23 22
MSB
2
1
0
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase (CE)
command is ignored if one or more sectors are protected.
Figure 23. Chip Erase Sequence Diagram
CS#
SCLK
0
1
SI
7.20.
2
3
4
5
6
7
Command
60H or C7H
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep
Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby
Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#
must be driven low for the entire duration of the sequence.
28
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 24. Deep Power-Down Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7
Command
SI
tDP
Stand-by mode Deep Power-down mode
B9H
7.21. Release from Deep Power-Down or High Performance Mode and Read
Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. The Device ID value is listed in
Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by
driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure27, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure 25. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
t RES1
Command
ABH
Deep Power-down mode
29
Stand-by mode
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 26. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
t RES2
3 Dummy Bytes
23 22
ABH
2
1
0
MSB
High-Z
7
Device ID
5 4 3 2
6
MSB
7.22.
1
0
Deep Power-down Mode Stand-by Mode
Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure28. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure 27. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
90H
23 22 21
3
2
High-Z
SO
CS#
24-bit address
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO
7
MSB
6
Manufacturer ID
5 4 3 2 1
Device ID
0
7
MSB
30
6
5
4
3
2
1
0
1
0
3.3V Uniform Sector
Dual and Quad Serial Flash
7.23.
GD25Q40C
Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This
is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being
shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure 31. The Read Identification
(RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device
is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and
execute commands.
Figure 28. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
Manufacturer ID
6 5 4 3 2 1
SCLK
SI
9FH
Command
SO
0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
MSB
7.24.
6
5 4 3 2 1
Memory Type
JDID15-JDID8
0
7
MSB
6
5 4 3 2
Capacity
JDID7-JDID0
1
0
High Performance Mode (HPM) (A3H)
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fC2 and fC3 in AC Electrical Characteristics). This command allows pre-charging of
internal charge pumps so the voltages required for accessing the flash memory array are readily available. The
command sequence: CS# goes lowSending A3H command Sending 3-dummy byteCS# goes high. See Figure32.
After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than standard SPI
operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby
current (Icc1). In addition, Power-Down command (B9H) will also release the device from HPM mode back to standard
SPI standby state.
31
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 29. High Performance Mode Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
A3H
t HPM
3 Dummy Bytes
23 22
MSB
2
1
0
SO
High Performance Mode
7.25.
Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce
command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the
BBH/EBH/E7H command code.
Because the GD25Q40C has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q40C
will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous
Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in
Figure28.
Figure 30. Continuous Read Mode Reset Sequence Diagram
Mode Bit Reset for Quad/Dual I/O
CS#
0
1
2
3
4
5
SCLK
SI(IO0)
FFH
SO(IO1)
Don`t Care
WP#(IO2)
Don`t Care
HOLD#(IO3)
Don`t Care
32
6
7
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
7.26. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command 3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure 31. Read Unique ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
4BH
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7.27.
7
6
5
4
3
2
1
0
7
MSB
Data Out1
6 5 4 3 2
1
Data Out2
0 7 6 5
MSB
Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase
commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H / 32H) are not allowed during Program/Erase
suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of
time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register equal
to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS bit equal to
1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within
“tsus” and the SUS bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend
period will reset the device and release the suspend state. The command sequence is show in Figure30.
33
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 32. Program/Erase Suspend Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
tSUS
Command
SI
75H
High-Z
SO
Accept read command
7.28.
Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the SUS
bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0 immediately,
the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will
complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend
is active. The command sequence is show in Figure31.
Figure 33. Program/Erase Resume Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
7
Command
7AH
SO
7.29.
6
Resume Erase/Program
Erase Security Registers (44H)
The GD25Q40C provides four 256-byte Security Registers which can be read and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command
code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high,
the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is
in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be
permanently locked; the Erase Security Registers command will be ignored.
34
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Address
A23-A16
A15-A8
A7-A0
Security Registers
00000000
00000000
Don’t Care
Figure 34. Erase Security Registers command Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9
Command
SI
7.30.
29 30 31
24 Bits Address
23 22
MSB
44H
2
1
0
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes
Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set
the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers
command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data
byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address
A23-A16
A15-A8
A7-A0
Security Registers 0
00H
00H
Byte Address
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
Figure 35. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24-bit address
23 22 21
3
2
1
0 7
6
5
4
3
2
1
2078
2079
2077
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2076
CS#
2075
MSB
2072
MSB
2074
42H
Data Byte 1
2073
SI
1
0
SCLK
Data Byte 2
SI
7
MSB
6
5
4
3
2
Data Byte 3
1
0 7
6
5
4
3
MSB
2
Data Byte 256
1
0
7
MSB
35
6
5
4
3
2
0
3.3V Uniform Sector
Dual and Quad Serial Flash
7.31.
GD25Q40C
Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address
(A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out. Once the A7-A0 address reaches the last byte of the register (Byte FFH), it will reset to 00H, the
command is completed by driving CS# high.
Address
A23-A16
A15-A8
A7-A0
Security Registers 0
00H
00H
Byte Address
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
Figure 36. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
48H
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
SO
7.32.
6
5
4
3
2
1
0
7
MSB
Data Out1
6 5 4 3 2
1
Data Out2
0 7 6 5
MSB
Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7M0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low Sending Enable Reset command CS# goes
high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted by the device,
the device will take approximately tRST/ tRST_E to reset. During this period, no command will be accepted. Data corruption
may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is
accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the
Reset command sequence.
36
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 37. Enable Reset and Reset command Sequence Diagram
CS#
0
SCLK
1
2
SI
3
4
5
6
7
0
2
3
4
5
Command
Command
66H
99H
6
7
High-Z
SO
7.33.
1
Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure 38. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
5AH
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7
6
5
4
3
2
1
0
7 6
MSB
37
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Table3. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed:50444653H
Add(H)
DW Add
Data
Data
(Byte)
(Bit)
00H
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
SFDP Minor Revision Number
Start from 00H
04H
07:00
00H
00H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
Unused
Contains 0xFFH and can never
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Start from 0x00H
09H
15:08
00H
00H
Start from 0x01H
0AH
23:16
01H
01H
Parameter Table Length
How many DWORDs in the
0BH
31:24
09H
09H
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
0CH
07:00
30H
30H
Parameter table
0DH
15:08
00H
00H
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
C8H
C8H
be changed
ID number (JEDEC)
00H: It indicates a JEDEC
specified header
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Unused
Contains 0xFFH and can never
be changed
ID Number
It is indicates GigaDevice
(GigaDevice Manufacturer ID)
manufacturer ID
Parameter Table Minor Revision
Start from 0x00H
11H
15:08
00H
00H
Start from 0x01H
12H
23:16
01H
01H
Parameter Table Length
How many DWORDs in the
13H
31:24
03H
03H
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of GigaDevice Flash
14H
07:00
60H
60H
Parameter table
15H
15:08
00H
00H
16H
23:16
00H
00H
17H
31:24
FFH
FFH
Number
Parameter Table Major Revision
Number
Unused
Contains 0xFFH and can never
be changed
38
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
01:00
01b
02
1b
03
0b
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction
0: Nonvolatile status bit
Requested for Writing to Volatile
1: Volatile status bit
Status Registers
(BP status register bit)
30H
E5H
0: Use 50H Opcode,
Write Enable Opcode Select for
1: Use 06H Opcode,
Writing to Volatile Status
Note: If target flash status register
Registers
is Nonvolatile, then bits 3 and 4
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
0b
must be set to 00b.
Unused
Contains 111b and can never be
changed
4KB Erase Opcode
31H
(1-1-2) Fast Read
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
32H
F1H
(1-2-2) Fast Read
0=Not support, 1=Support
20
1b
(1-4-4) Fast Read
0=Not support, 1=Support
21
1b
(1-1-4) Fast Read
0=Not support, 1=Support
22
1b
23
1b
33H
31:24
FFH
37H:34H
31:00
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
(1-4-4) Fast Read Number of
Mode Bits
39H
(1-1-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
Mode Bits
00100b
44H
07:05
010b
15:08
EBH
20:16
01000b
3AH
000b:Mode Bits not support
(1-1-4) Fast Read Opcode
3BH
39
FFH
003FFFFFH
38H
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of
04:00
000b:Mode Bits not support
20H
EBH
08H
23:21
000b
31:24
6BH
6BH
3.3V Uniform Sector
Dual and Quad Serial Flash
Description
Comment
(1-1-2) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
(1-1-2) Fast Read Number
of Mode Bits
(Byte)
(Bit)
04:00
3DH
0 0000b: Wait states (Dummy
of Wait states
Clocks) not support
000b: Mode Bits not support
3FH
0=not support
Data
1=support
Unused
08H
07:05
000b
15:08
3BH
20:16
00010b
0=not support
1=support
Unused
3BH
42H
23:21
010b
31:24
BBH
00
0b
03:01
111b
04
0b
07:05
111b
40H
(4-4-4) Fast Read
Data
01000b
3EH
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
DW Add
000b: Mode Bits not support
(1-2-2) Fast Read Number
of Mode Bits
Add(H)
3CH
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
GD25Q40C
BBH
EEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
(2-2-2) Fast Read Number
0 0000b: Wait states (Dummy
of Wait states
Clocks) not support
(2-2-2) Fast Read Number
of Mode Bits
46H
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
Unused
(4-4-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
(4-4-4) Fast Read Number
of Mode Bits
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
000b
47H
31:24
FFH
FFH
49H:48H
15:00
0xFFH
0xFFH
20:16
00000b
000b: Mode Bits not support
Sector Type 1 erase Opcode
Sector Type 2 Size
23:21
4AH
(4-4-4) Fast Read Opcode
Sector Type 1 Size
00H
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
40
00H
23:21
000b
4BH
31:24
FFH
FFH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
00H
00H
53H
31:24
FFH
FFH
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
Description
Comment
2000H=2.000V
Vcc Supply Maximum Voltage
Add(H)
DW Add
(Byte)
(Bit)
61H:60
2700H=2.700V
H
3600H=3.600V
Data
Data
15:00
3600H
3600H
31:16
2700H
2700H
1650H=1.650V
Vcc Supply Minimum Voltage
2250H=2.250V
63H:62
2300H=2.300V
H
2700H=2.700V
HW Reset# pin
0=not support
1=support
00
0b
HW Hold# pin
0=not support
1=support
01
1b
Deep Power Down Mode
0=not support
1=support
02
1b
SW Reset
0=not support
1=support
03
1b
Should
SW Reset Opcode
be
issue
Reset
Enable(66H)
65H:64
H
before Reset cmd.
11:04
99H
F99EH
Program Suspend/Resume
0=not support
1=support
12
1b
Erase Suspend/Resume
0=not support
1=support
13
1b
14
1b
15
1b
66H
23:16
77H
77H
67H
31:24
64H
64H
00
0b
01
0b
09:02
FFH
10
0b
11
1b
Unused
Wrap-Around Read mode
Wrap-Around
Read
0=not support
1=support
mode
Opcode
08H:support
8B
wrap-around
read
Wrap-Around Read data length
16H:8B&16B
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support
0=Volatile
1=support
1=Nonvolatile
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect
1=unprotect
6BH:68
H
Secured OTP
0=not support
1=support
Read Lock
0=not support
1=support
12
0b
Permanent Lock
0=not support
1=support
13
1b
Unused
15:14
11b
Unused
31:16
FFFFH
41
EBFCH
FFFFH
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Figure 39. Power-on Timing Sequence Diagram
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully
accessible
VWI
Time
Table6. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
tVSL
VCC (min) To CS# Low
1.8
VWI
Write Inhibit Voltage
1.5
Max
Unit
ms
2.5
V
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register
contains 00H (all Status Register bits are 0).
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Ambient Operating Temperature
-40 to 85
Unit
℃
-40 to 105
-40 to 125
℃
Storage Temperature
-65 to 150
Applied Input/Output Voltage
-0.6 to VCC+0.4
V
Transient Input/Output Voltage (note: overshoot)
-2.0 to VCC+2.0
V
-0.6 to 4.2
V
VCC
42
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q40C
Figure 40. Maximum Negative and Positive Overshoot Waveform
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4. CAPACITANCE MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
Input Rise And Fall time
pF
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
Output Timing Reference Voltage
0.5VCC
V
Figure 41. Input Test Waveform and Measurement Level
Input timing reference level
0.8VCC
0.7VCC
0.1VCC
0.2VCC
Output timing reference level
AC Measurement Level
Note: Input pulse rise and fall time are
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