GVT71256G18T-5

327A CY7C1327A/GVT71256G18 256K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Fast access times: 3.5, 3.8, and 4.0 ns Fast clock speed: 166, 150, 133, and 117 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.5 ns and 3.8 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V –5% and +10% power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. Functional Description The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1327A/GVT71256G18 operates from a +3.3V power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that benefit from a wide synchronous data bus. The CY7C1327A/GVT71256G18 SRAM integrates 262,144x18 SRAM cells with advanced synchronous periph- Selection Guide 7C1327A-166 71256G18-3 7C1327A-150 71256G18-4 7C1327A-133 71256G18-5 7C1327A-117 71256G18-6 Maximum Access Time (ns) 3.5 3.8 4.0 4.0 Maximum Operating Current (mA) 425 400 375 350 Maximum CMOS Standby Current (mA) 10 10 10 10 Cypress Semiconductor Corporation Document #: 38-05129 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 13, 2002 CY7C1327A/GVT71256G18 256K x 18 (CY7C1327A/GVT71256G18) Functional Block Diagram[1] UPPER BYTE WRITE WEH# BWE# D Q LOWER BYTE WRITE D Q CE# lo byte write GW# ENABLE D CE2 Q D hi byte write WEL# Q CE2# ZZ Power Down Logic OE# ADSP# ADSC# CLR ADV# A1-A0 Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers Address Register 256K x 9 x 2 SRAM Array A17-A2 Input Register DQ1DQ16, DQP1, DQP2 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05129 Rev. *A Page 2 of 16 CY7C1327A/GVT71256G18 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP Top View NC NC NC CY7C1327A/GVT71256G18 (256K X 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 A16 A17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Document #: 38-05129 Rev. *A Page 3 of 16 CY7C1327A/GVT71256G18 Pin Configurations (continued) 119-Ball Bump BGA 256Kx18—CY7C1327A/GVT71256G18 Top View 1 2 3 4 5 6 7 A VCCQ A6 A4 ADSP A8 A16 VCCQ B NC CE2 A3 ADSC A9 CE2 NC C NC A7 A2 VCC A12 A15 NC D DQ9 NC VSS NC VSS DQ”P1 NC E NC DQ10 VSS CE VSS NC DQ8 F VCCQ NC VSS OE VSS DQ7 VCCQ G NC DQ11 BWH ADV VSS NC DQ6 H DQ12 NC VSS GW VSS DQ5 NC J VCCQ VCC NC VCC NC VCC VCCQ K NC DQ13 VSS CLK VSS NC DQ4 L DQ14 NC VSS NC BWL DQ3 NC M VCCQ DQ15 VSS BWE VSS NC VCCQ N DQ18 NC VSS A1 VSS DQ2 NC P NC DQP2 VSS A0 VSS NC DQ1 R NC A5 MODE VCC NC A13 NC T NC A10 A11 NC A14 A17 ZZ U VCCQ NC NC NC NC NC VCCQ Pin Descriptions BGA Pins QFP Pins Pin Name Type Description 4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A17 InputAddresses: These inputs are registered and must meet the set-up 5A, 6A, 3B, 5B, 33, 32, 100, 99, Synchronous and hold times around the rising edge of CLK. The burst counter 2C, 3C, 5C, 6C, 82, 81, 80, 48, generates internal addresses associated with A0 and A1, during 2R, 6R, 2T, 3T, 47, 46, 45, 44, burst cycle and wait cycle. 5T, 6T 49, 50 5L, 3G 93, 94 WEL, WEH InputByte Write Enables: A byte write enable is LOW for a Write cycle Synchronous and HIGH for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. 4M 87 BWE InputWrite Enable: This active LOW input gates byte write operations Synchronous and must meet the set-up and hold times around the rising edge of CLK. 4H 88 GW InputGlobal Write: This active LOW input allows a full 18-bit Write to Synchronous occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. 4K 89 CLK InputClock: This signal registers the addresses, data, chip enables, write Synchronous control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. Document #: 38-05129 Rev. *A Page 4 of 16 CY7C1327A/GVT71256G18 Pin Descriptions (continued) BGA Pins QFP Pins Pin Name 4E 98 CE InputChip Enable: This active LOW input is used to enable the device Synchronous and to gate ADSP. 6B 92 CE2 InputChip Enable: This active LOW input is used to enable the device. Synchronous 2B 97 CE2 inputChip Enable: This active HIGH input is used to enable the device. Synchronous 4F 86 OE 4G 83 ADV InputAddress Advance: This active LOW input is used to control the Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no address advance). 4A 84 ADSP InputAddress Status Processor: This active LOW input, along with CE Synchronous being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. 4B 85 ADSC InputAddress Status Controller: This active LOW input causes device to Synchronous be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs. 3R 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. 7T 64 ZZ InputAsynchronous Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). DQ1– DQ16 Input/ Output Data Inputs/Outputs: Low Byte is DQ1–DQ8. HIgh Byte is DQ9–DQ16. Input data must meet set-up and hold times around the rising edge of CLK. 7P, 6N, 6L, 7K, 58, 59, 62, 63, 6H, 7G, 6F, 7E, 68, 69, 72, 73, 8, 1D, 2E, 2G, 1H, 9, 12, 13, 18, 19, 2K, 1L, 2M, 1N 22, 23 Type Input Description Output Enable: This active LOW asynchronous input enables the data output drivers. 6D, 2P 74, 24 DQP1, DQP2 Input/ Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16. 4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC Supply Power Supply: +3.3V –5% and +10% 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 17, 40, 67, 90 VSS Ground Ground: GND 1A, 7A, 1F, 7F, 4, 11, 20, 27, 54, 1J, 7J, 1M, 7M, 61, 70, 77 1U, 7U VCCQ I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC) 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND NC - 1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16, 2D, 4D, 7D, 1E, 25, 28-30, 38, 6E, 2F, 1G, 6G, 39, 42, 43, 512H, 7H, 3J, 5J, 53, 56, 57, 66, 1K, 6K, 2L, 4L, 75, 78, 79, 80, 7L, 6M, 2N, 7N, 95, 96 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U Document #: 38-05129 Rev. *A No Connect: These signals are not internally connected. Page 5 of 16 CY7C1327A/GVT71256G18 Burst Address Table (MODE = NC/VCC) Burst Address Table (MODE = GND) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z Next X X X H H L H L L-H Q READ Cycle, Continue Burst READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D Notes: 2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. 3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. Document #: 38-05129 Rev. *A Page 6 of 16 CY7C1327A/GVT71256G18 Maximum Ratings Partial Truth Table for Read/Write FUNCTION GW BWE WEH READ H H X X READ H L H H WRITE one byte H L L H WRITE all bytes H L L L WRITE all bytes L X X X (Above which the useful life may be impaired. For user guidelines only, not tested.) WEL Voltage on VCC Supply Relative to VSS ..........–0.5V to +4.6V VIN ......................................................... –0.5V to +VCC+0.5V Storage Temperature (plastic) .................... –55°C to +150°C Junction Temperature ............................................... +150°C Power Dissipation.......................................................... 1.0W Short Circuit Output Current ....................................... 50 mA . Operating Range Range Ambient Temperature[9] VCC 0°C to +70°C 3.3V –5%/+10% Com’l Electrical Characteristics Over the Operating Range Parameter VIHD Description Min. Max. Data Inputs (DQxx) Test Conditions 1.7 VCC+0.3 All other 1.7 4.6 V –0.3 0.7 V 0V < VIN < VCC –2 2 µA Output(s) disabled, 0V < VOUT < VCC –2 2 µA Output High Voltage[10, 13] IOH = –2.0 mA 1.7 Output Low Voltage[10, 13] IOL = 2.0 mA Input High (Logic 1) Voltage[10, 11] VIH VIl Input Low (Logic 0) Voltage[10, 11] Current[12] ILI Input Leakage ILO Output Leakage Current VOH VOL Voltage[10] VCC Supply VCCQ I/O Supply Parameter Description Conditions ICC Power Supply Device selected; Current: all inputs < VILor > VIH; Operating[14, 15, 16] cycle time > tKC Min.; VCC = Max.; outputs open ISB2 CMOS Standby[15, 16] Unit V 0.7 V 3.135 3.6 V 2.375 VCC V -3 -4 -5 -6 Typ. 166 MHz 150 MHz 133 MHz 117 MHz Unit 150 425 400 375 350 mA Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC – 0.2; all inputs static; CLK frequency = 0 5 10 10 10 10 mA ISB3 TTL Standby[15, 16] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 10 20 20 20 20 mA ISB4 Clock Running[15, 16] 40 90 80 70 60 mA Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC Min. Notes: 9. TA is the case temperature. 10. All voltages referenced to VSS (GND). 11. Overshoot: VIH < +6.0V for t < tKC /2. Undershoot: VIL < –2.0V for t < tKC /2. 12. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 13. AC I/O curves are available upon request. 14. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 15. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 16. Typical values are measured at 3.3V, 25°C and 20-ns cycle time. Document #: 38-05129 Rev. *A Page 7 of 16 CY7C1327A/GVT71256G18 Thermal Consideration Parameter Description ΘJA Thermal Resistance - Junction to Ambient ΘJC Thermal Resistance - Junction to Case Conditions TQFP Typ. Unit Still air, soldered on 4.25 x 1.125 inch 4-layer PCB 25 °C/W 9 °C/W Capacitance Parameter Description Test Conditions Input Capacitance[17] CI [17] CO Input/Output Capacitance (DQ) Typ. Max. Unit 4 5 pF 7 8 pF TA = 25°C, f = 1 MHz, VCC= 3.3V Typical Output Buffer Characteristics Output High Voltage Pull-up Current Output Low Voltage Pull-down Current VOH (V) IOH (mA) Min. IOH (mA) Max. VOL (V) IOL (mA) Min. IΟL (mA) Max. –0.5 –38 –105 –0.5 0 0 0 –38 –105 0 0 0 0.8 –38 –105 0.4 10 20 1.25 –26 –83 0.8 20 40 1.5 –20 –70 1.25 31 63 2.3 0 –30 1.6 40 80 2.7 0 –10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 AC Test Loads and Waveforms DQ ALL INPUT PULSES 2.5V Z0 = 50Ω RL = 50Ω Vt = 1.25V 10% 0V Rise Time: 1 V/ns 90% 90% 10% Fall Time: 1 V/ns Note: 17. This parameter is sampled. Document #: 38-05129 Rev. *A Page 8 of 16 CY7C1327A/GVT71256G18 Switching Characteristics Over the Operating Range[18] -3 166 MHz Parameter Description Min. Max. -4 150 MHz Min. Max. -5 133 MHz Min. Max. -6 117 MHz Min. Max. Unit Clock tKC Clock Cycle Time 6.0 6.7 7.5 8.5 ns tKH Clock HIGH Time 2.4 2.6 2.8 3.4 ns tKL Clock LOW Time 2.4 2.6 2.8 3.4 ns Output Times tKQ Clock to Output Valid tKQX Clock to Output Invalid 3.5 Low-Z[17, 19, 20] tKQLZ Clock to Output in tKQHZ Clock to Output in High-Z[17, 19, 20] tOEQ Valid[21] tOELZ tOEHZ OE to Output OE to Output in 4.0 4.0 ns 1.5 1.5 1.5 1.5 ns 0 0 0 0 ns 1.5 6.0 1.5 3.5 Low-Z[17, 19, 20] OE to Output in High-Z 3.8 0 [17, 19, 20] 6.7 1.5 3.5 0 3.5 7.5 1.5 3.8 0 3.5 8.5 ns 3.8 ns 0 3.8 ns 3.8 ns Set-Up Times tS Address, Controls and Data In[22] 1.5 1.5 1.5 2.0 ns Address, Controls and Data In[22] 0.5 0.5 0.5 0.5 ns Hold Times tH Notes: 18. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. 19. Output loading is specified with CL=5 pF as in AC Test Loads. 20. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 21. OE is a “Don’t Care” when a byte write enable is sampled LOW. 22. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table. Document #: 38-05129 Rev. *A Page 9 of 16 CY7C1327A/GVT71256G18 Timing Diagrams Read Timing[23] t KC t KL CLK t t S KH ADSP# t H ADSC# t S ADDRESS A1 t A2 H WEL#, WEH#, BWE#, GW# CE# (See Note) t S ADV# t H OE# t KQLZ DQ t KQ t KQ t OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Note: 23. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active. Document #: 38-05129 Rev. *A Page 10 of 16 CY7C1327A/GVT71256G18 Timing Diagrams (continued) Write Timing[23] CLK t S ADSP# t H ADSC# t S ADDRESS A1 A2 A3 tH WEL#, WEH#, BWE# GW# CE# (See Note) t S ADV# t H OE# t OEHZ t KQX DQ Q D(A1) SINGLE WRITE Document #: 38-05129 Rev. *A D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 11 of 16 CY7C1327A/GVT71256G18 Timing Diagrams (continued) Read/Write Timing[23] CLK tS ADSP# tH ADSC# tS ADDRESS A1 A2 A3 A4 A5 tH WEL#, WEH#, BWE#, GW# CE# (See Note) ADV# OE# DQ Q(A1) Single Reads Document #: 38-05129 Rev. *A Q(A2) D(A3) Single Write Q(A3) Pass Through Q(A4) Q(A4+1) Burst Read Q(A4+2) D(A5) D(A5+1) Burst Write Page 12 of 16 CY7C1327A/GVT71256G18 Ordering Information Speed (MHz) 166 Ordering Code CY7C1327A-166AC Package Name A101 Package Type Operating Range 100-Lead Thin Quad Flat Pack Commercial GVT71256G18T-3 CY7C1327A-166BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71256G18B-3 150 CY7C1327A-150AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71256G18T-4 CY7C1327A-150BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71256G18B-4 133 CY7C1327A-133AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71256G18T-5 CY7C1327A-133BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71256G18B-5 117 CY7C1327A-117AC A101 100-Lead Thin Quad Flat Pack Commercial GVT71256G18T-6 CY7C1327A-117BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm) GVT71256G18B-6 Document #: 38-05129 Rev. *A Page 13 of 16 CY7C1327A/GVT71256G18 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05129 Rev. *A Page 14 of 16 CY7C1327A/GVT71256G18 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05129 Rev. *A Page 15 of 16 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1327A/GVT71256G18 Document History Page Document Title: CY7C1327A/GVT71256G18 256K x 18 Synchronous Pipelined Burst SRAM Document Number: 38-05129 REV. ECN NO. Issue Date ** 108984 09/25/01 BRI New Cypress spec—converted from Galvantech format *A 121072 11/13/02 DSG Updated package diagram 51-85115 (BG119) to rev. *B Document #: 38-05129 Rev. *A Orig. of Change Description of Change Page 16 of 16