S-93L76A
N
LOW VOLTAGE OPERATION
3-WIRE SERIAL E2PROM
DE
SI
G
www.ablicinc.com
Rev.6.0_03
© ABLIC Inc., 2004-2015
The S-93L76A is a low voltage operating, high speed, low current consumption, 3-wire serial E2PROM with a wide operating
voltage range. The S-93L76A has the capacity of 8 K-bit, and the organization is 512-word 16 bit. It is capable of
sequential read, at which time addresses are automatically incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Read
Write
1.6 V to 5.5 V
1.8 V to 5.5 V (WRITE, ERASE)
2.7 V to 5.5 V (WRAL, ERAL)
2.0 MHz (Vcc = 4.5 V to 5.5 V)
10.0 ms max.
DE
D
FO
R
Operating frequency:
Write time:
Sequential read capable
Write protect function during the low power supply voltage
Endurance:
106 cycles / word*1 (Ta = 85C)
Data retention:
100 years (Ta = 25C)
20 years (Ta = 85C)
Memory capacity:
8 K-bit
Initial delivery state:
FFFFh
Operation temperature range:
Ta = 40°C to 85C
Lead-free, Sn 100%, halogen-free*2
NE
Operating voltage range:
W
Features
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC
Inc. is indispensable.
NO
T
RE
C
Caution
OM
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
M
Packages
EN
*1. For each address (Word: 16-bit)
*2. Refer to “ Product Name Structure” for details.
1
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
8-Pin SOP (JEDEC)
Top view
Table 1
1
8
2
7
3
6
4
5
Symbol
CS
Chip select input
Description
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
1
R
S-93L76AD0I-J8T1x
8-Pin TSSOP
8-Pin TSSOP
Top view
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
D
8
7
6
5
Table 2
Symbol
CS
DE
1
2
3
4
Pin No.
1
FO
2.
Pin No.
1
NE
Figure
DE
SI
G
8-Pin SOP (JEDEC)
W
1.
N
Pin Configurations
Description
5
2
M
S-93L76AD0I-T8T1x
GND
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
EN
Figure
NO
T
RE
C
OM
Remark 1. Refer to the “Package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
2
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
TMSOP-8
TMSOP-8
Top view
1
2
3
4
Table 3
8
7
6
5
DE
SI
G
3.
N
Rev.6.0_03
Pin No.
1
Symbol
CS
Chip select input
Description
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
W
Figure 3
NO
T
RE
C
OM
M
EN
DE
D
FO
Remark Refer to the “Package drawings” for the details.
R
NE
S-93L76AD0I-K8T3U
3
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
Address
Memory array
decoder
Data register
W
Voltage detector
NO
T
RE
C
OM
M
EN
DE
D
FO
R
Clock generator
Figure 4
4
GND
NE
Mode decode logic
SK
VCC
Output buffer
DI
CS
DE
SI
G
N
Block Diagram
DO
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
N
Instruction Set
Instruction
Start Bit Operation Code
Address
Data
SK input clock
1
2
3
4
5
6
7
8
9
10
READ (Read data)
1
1
0
x
A8
A7
A6
A5
A4
A3
1
0
1
x
A8
A7
A6
A5
A4
A3
ERASE (Erase data)
1
1
1
x
A8
A7
A6
A5
A4
A3
WRAL (Write all)
1
0
0
0
1
x
x
x
x
x
ERAL (Erase all)
1
0
0
1
0
x
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
11
12
13
A2
A1
*1
A0 D15 to D0 Output
14 to 29
A2
A1
A0 D15 to D0 Input
A2
A1
A0
x
x
x
x
x
x
x
x
x
x
x
x
D15 to D0 Input
NE
W
WRITE (Write data)
*1.
DE
SI
G
Table 4
When the 16-bit data in the specified address has been output, the data in the next address is output.
NO
T
RE
C
OM
M
EN
DE
D
FO
R
Remark x: Don't care
5
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
N
Absolute Maximum Ratings
Item
DE
SI
G
Table 5
Symbol
Ratings
Unit
W
Power supply voltage
VCC
0.3 to 7.0
V
Input voltage
VIN
0.3 to VCC 0.3
V
Output voltage
VOUT
0.3 to VCC
V
Operation ambient temperature
Topr
40 to 85
C
Storage temperature
Tstg
65 to 150
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These
values must therefore not be exceeded under any conditions.
Table 6
Symbol
VCC
High level input voltage
VIH
Low level input voltage
VIL
READ, EWDS
WRITE, ERASE , EWEN
WRAL, ERAL
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
D
DE
EN
Pin Capacitance
Item
Symbol
Item
Endurance
RE
C
Endurance
Symbol
NW
V
V
V
V
V
V
V
V
V
Table 7
(Ta = 25C, f = 1.0 MHz, VCC = 5.0 V)
Conditions
Min.
Max.
Unit
VIN = 0 V
8
pF
COUT
VOUT = 0 V
10
pF
OM
Output capacitance
Unit
CIN
M
Input capacitance
Ta =40C to 85C
Min.
Max.
1.6
5.5
1.8
5.5
2.7
5.5
2.0
VCC
0.8 VCC
VCC
0.8 VCC
VCC
0.0
0.8
0.0
0.2 VCC
0.0
0.15 VCC
FO
Power supply voltage
Conditions
R
Item
NE
Recommended Operating Conditions
Table 8
Operation Ambient Temperature
Min.
Max.
Unit
106
cycles / word*1
Min.
Max.
Unit
Ta =25C
100
year
Ta =40C to 85C
20
year
Ta =40C to 85C
*1. For each address (Word: 16-bit)
NO
T
Data Retention
Item
Data retention
6
Table 9
Symbol
Operation Ambient Temperature
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
N
DC Electrical Characteristics
Item
Current consumption
(READ)
Symbol
ICC1
Conditions
DE
SI
G
Table 10
Ta =40C to 85C
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.6 V to 2.5 V Unit
Min.
Max.
Min.
Max.
Min.
Max.
DO no load
0.8
Table 11
Current consumption
(WRITE)
ICC2
Ta =40C to 85C
VCC = 4.5 V to 5.5 V
VCC = 1.8 V to 4.5 V
Min.
Max.
Min.
Max.
Conditions
DO no load
2.0
Data hold voltage
FO
ILO
VOUT = GND to VCC
VOH
VDH
Ta =40C to 85C
VCC =
VCC =
2.5 V to 4.5 V
1.6 V to 2.5 V
Min.
Max.
Min.
Max.
Unit
2.0
2.0
2.0
A
1.0
1.0
1.0
A
1.0
1.0
1.0
A
IOL = 2.1 mA
IOL = 100 A
IOH = 400 A
IOH = 100 A
IOH = 10 A
2.4
VCC0.3
VCC0.2
0.4
0.1
VCC0.3
VCC0.2
0.1
VCC0.2
0.1
V
V
V
V
V
Only program disable mode
1.5
1.5
1.5
V
D
DE
VOL
mA
NO
T
RE
C
OM
of write enable latch
ILI
CS = GND, DO = Open,
Other inputs to VCC or GND
VIN = GND to VCC
ISB
1.5
EN
High level output
voltage
VCC =
4.5 V to 5.5 V
Min.
Max.
Conditions
Unit
M
Standby current
consumption
Input leakage current
Output leakage
current
Low level output
voltage
Symbol
mA
R
Table 12
Item
0.4
W
Symbol
NE
Item
0.5
7
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
Measurement Conditions
DE
SI
G
Table 13
N
AC Electrical Characteristics
0.1 VCC to 0.9 VCC
Input pulse voltage
0.5 VCC
Output reference voltage
Output load
100 pF
Table 14
Symbol
VCC = 4.5 V to 5.5 V
VCC = 2.5 V to 4.5 V
Min.
Max.
Min.
Max.
VCC = 1.6 V to 2.5 V
Min.
Max.
Unit
tCSS
0.2
—
0.4
—
1.0
—
s
CS hold time
tCSH
0
—
0
—
0
—
s
CS deselect time
tCDS
0.2
—
0.2
—
0.4
—
s
Data setup time
tDS
0.1
—
0.2
—
0.4
—
s
Data hold time
tDH
0.1
—
0.2
—
0.4
—
s
Output delay time
tPD
—
0.4
—
0.8
—
2.0
s
Clock frequency
SK clock time “L” *1
SK clock time “H” *1
fSK
tSKL
tSKH
0
0.1
0.1
2.0
—
—
0
0.25
0.25
1.0
—
—
0
1.0
1.0
0.25
—
—
MHz
s
s
Output disable time
tHZ1, tHZ2
0.15
0
0.5
0
1.0
s
FO
D
0
R
CS setup time
NE
Item
W
Ta =40C to 85C
OM
Item
M
EN
DE
Output enable time
tSV
0
0.15
0
0.5
0
1.0
s
*1. The clock cycle of the SK clock (frequency: fSK) is 1 / fSK s. This clock cycle is determined by a combination of
several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot
be made equal to tSKL (min.) tSKH (min.).
NO
T
RE
C
Write time
8
Symbol
tPR
Table 15
Ta =40C to 85C
VCC = 1.8 V to 5.5 V
Min.
Typ.
Max.
4.0
10.0
Unit
ms
Rev.6.0_03
tCSS
tCDS
*2
CS
tSKH
tSKL
tCSH
SK
tDS
DI
tPD
tPD
W
High-Z
tSV
tHZ2
High-Z
NE
(READ)
DO
High-Z
tHZ1
High-Z
R
(VERIFY)
Indicates high impedance.
1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics,
so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot be made equal
to tSKL (min.) tSKH (min.).
FO
*1.
*2.
tDH
Valid data
Valid data
*1
DO
tDS
tDH
DE
SI
G
1 / fSK
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Timing Chart
NO
T
RE
C
OM
M
EN
DE
D
Figure 5
9
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
N
Initial Delivery State
DE
SI
G
Initial delivery state of all addresses is “FFFFh”.
Operation
1.
NE
W
All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction
is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at
the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized
even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input
is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the
internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory
IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the
period of tCDS in between instructions.
“L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.
Reading (READ)
FO
R
The READ instruction is used to read the data at a specified address. When this instruction is executed, the
address A0 is input at the rising edge of SK and the DO pin, which has been in a high-impedance (High-Z) state,
outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK.
If SK is output after the 16-bit data of the specified address has been output, the address is automatically
incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at
“H”, the data of the entire memory space can be read. When the address is incremented from the last address (A8
… A1 A0 = 1 … 1 1), it returns to the first address (A8 … A1 A0 = 0 … 0 0).
DI
1
1
2
1
3
0
4
5
6
7
8
9 10 11 12 13 14 15 16
High-Z
DO
M
OM
RE
C
T
42 43 44 45 46 47 48
High-Z
0 D15 D14 D13
NO
10
26 27 28 29 30 31 32
X A8 A7 A6 A5 A4 A3 A2 A1 A0
EN
SK
DE
D
CS
D2 D1 D0 D15 D14 D13
A8A7A6A5A4A3A2A1A0+1
Figure 6
Read Timing
D2 D1 D0 D15 D14 D13
A8A7A6A5A4A3A2A1A0+2
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
Writing (WRITE, ERASE, WRAL, ERAL)
N
2.
Writing data (WRITE)
R
2. 1
NE
W
DE
SI
G
Write instructions (WRITE, ERASE, WRAL, and ERAL) are used to start writing data to the non-volatile memory by
making CS “L” after the specified number of clocks has been input.
The write operation is completed within the write time tPR (10 ms) no matter which write instruction is used. The
typical write time is less than half 10 ms. If the end of the write operation is known, therefore, the write cycle can
be minimized. To ascertain the end of a write operation, make CS “L” to start the write operation and then make
CS “H” again to check the status of the DO output pin. This series of operations is called a verify operation.
If DO outputs “L” during the verify operation period in which CS is “H”, it indicates that a write operation is in
progress. If DO outputs “H”, it indicates that the write operation is finished. The verify operation can be executed
as many times as required. This operation can be executed in two ways. One is detecting the positive transition
of DO output from “L” to “H” while holding CS at “H”. The other is detecting the positive transition of DO output
from “L” to “H” by making CS “H” once and checking DO output, and then returning CS to “L”.
During the write period, SK and DI are invalid. Do not input any instructions during this period. Input an
instruction while the DO pin is outputting “H” or is in a high-impedance state. Even while the DO pin is outputting
“H”, DO immediately goes into a high-impedance (High-Z) state if “H” of DI (start bit) is input at the rising edge of
SK.
Keep DI “L” during the verify operation period.
FO
This instruction is used to write 16-bit data to a specified address.
After making CS “H”, input a start bit, the WRITE instruction, an address, and 16-bit data. If data of more than
16 bits is input, the written data is sequentially shifted at each clock, and the 16 bits input last are the valid
data. The write operation is started when CS is made “L”. It is not necessary to set data to “1” before it is
written.
tCDS
D
SK
1
2
3
4
5
DI
0
1
X
A8
DE
CS
Verify
6
7
8
9
10
11
12
A7
A6
A5
A4
A3
A2
A1
13
14
29
A0 D15
D0
tSV
High-Z
Figure 7
Busy
tPR
tHZ1
Ready
High-Z
Data Write Timing
NO
T
RE
C
OM
M
EN
DO
Standby
11
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Erasing data (ERASE)
N
2. 2
Rev.6.0_03
DE
SI
G
This instruction is used to erase specified 16-bit data. All the 16 bits of the data are “1”. After making CS
“H”, input a start bit, the ERASE instruction, and an address. It is not necessary to input data. The data
erase operation is started when CS is made “L”.
tCDS
Verify
CS
SK
1
2
3
4
5
6
DI
1
1
X
A8
A7
7
8
9
10
11
12
13
A6
A5
A4
A3
A2
A1
A0
tSV
High-Z
Busy
Figure 8
2. 3
tHZ1
Ready
High-Z
tPR
NE
W
DO
Standby
Data Erase Timing
Writing to chip (WRAL)
CS
1
2
3
4
5
DI
0
0
0
1
6
7
8
9
DE
SK
D
FO
R
This instruction is used to write the same 16-bit data to the entire address space of the memory.
After making CS “H”, input a start bit, the WRAL instruction, an address, and 16-bit data. Any address may be
input. If data of more than 16 bits is input, the written data is sequentially shifted at each clock, and the 16-bit
data input last is the valid data. The write operation is started when CS is made “L”. It is not necessary to
set the data to “1” before it is written.
High-Z
EN
DO
11
12
13
14
29
D15
D0
Standby
tSV
8Xs
Busy
tHZ1
Ready
tPR
High-Z
Chip Write Timing
Erasing chip (ERAL)
OM
2. 4
Verify
M
Figure 9
10
tCDS
RE
C
This instruction is used to erase the data of the entire address space of the memory.
All the data is “1”. After making CS “H”, input a start bit, the ERAL instruction, and an address. Any address
may be input. It is not necessary to input data. The chip erase operation is started when CS is made “L”.
tCDS
Verify
CS
SK
1
2
3
4
5
DI
0
0
1
0
7
8
High-Z
9
10
11
12
13
8Xs
NO
12
tSV
Busy
tPR
T
DO
6
Figure 10
Standby
Chip Erase Timing
tHZ1
Ready
High-Z
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
Write enable (EWEN) and write disable (EWDS)
N
3.
DE
SI
G
The EWEN instruction is used to enable a write operation. The status in which a write operation is enabled is
called the program-enabled mode.
The EWDS instruction is used to disable a write operation. The status in which a write operation is disabled is
called the program-disabled mode.
The write operation is disabled upon power application and detection of a low supply voltage. To prevent an
unexpected write operation due to external noise or a CPU malfunctions, it should be kept in write disable mode
except when performing write operations, after power-on and before shutdown.
Standby
CS
1
2
3
DI
0
0
4
5
6
7
9
10
11
8Xs
12
13
NE
11 = EWEN
00 = EWDS
Write Enable / Disable Timing
R
Figure 11
8
W
SK
FO
Start Bit
NO
T
RE
C
OM
M
EN
DE
D
A start bit is recognized by latching the high level of DI at the rising edge of SK after changing CS to high (start bit
recognition). A write operation begins by inputting the write instruction and setting CS to low. Subsequently, by setting
CS to high again, the DO pin outputs a low level if the write operation is still in progress and a high level if the write
operation is complete (verify operation). Therefore, only after a write operation, in order to input the next command, CS
is set to high, which switches the DO pin from a high-impedance state (High-Z) to a data output state. However, if start
bit is recognized, the DO pin returns to the high-impedance state (refer to Figure 5 Timing Chart).
Make sure that data output from the CPU does not interfere with the data output from the serial memory IC when
configuring a 3 -wire interface by connecting the DI input pin and DO output pin, as such interference may cause a start
bit fetch problem. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
13
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Write Protect Function during the Low Power Supply Voltage
N
Rev.6.0_03
W
DE
SI
G
The S-93L76A provides a built-in detection circuit to detect a low power supply voltage. When the power supply
voltage is low or at power-on, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write
disable state (EWDS) is automatically set. The detection voltage and the release voltage are 1.4 V typ. (refer to
Figure 12).
Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to
the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE,
ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
NE
Power supply voltage
Release voltage (VDET)
1.4 V typ.
R
Detection voltage (VDET)
1.4 V typ.
Operation during Low Power Supply Voltage
NO
T
RE
C
OM
M
EN
DE
D
Figure 12
FO
Write instruction cancelled
Write disable state (EWDS) automatically set
14
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
N
3-Wire Interface (Direct Connection between DI and DO)
CPU
SIO
NE
DI
DO
W
S-93L76A
DE
SI
G
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93L76A via a resistor (10 k to 100 k) so that the data output from the CPU takes precedence in being input
to the DI pin (refer to Figure 13).
R: 10 k to 100 k
Connection of 3-Wire Interface
FO
R
Figure 13
Input Pin and Output Pin
1.
Connection of input pins
2.
EN
DE
D
All the input pins of the S-93L76A have the CMOS structure. Do not set these pins in high impedance during
operation when you design. Especially, set the CS pin to “L” at power-on, power-off, and during standby. The error
write does not occur as long as the CS pin is “L”. Set the CS pin to GND via a resistor (the pull-down resistor of 10 k
to 100 k).
To prevent the error for sure, it is recommended to use equivalent pull-down resistors for input pins other than the CS
pin.
Equivalent circuit of input pin and output pin
NO
T
RE
C
OM
M
The following shows the equivalent circuits of input pins of the S-93L76A. None of the input pins incorporate pull-up
and pull-down elements, so special care must be taken when designing to prevent a floating status.
Output pins are high-level / low-level / high-impedance tri-state outputs.
The TEST pin is disconnected from the internal circuit by a switching transistor during normal operation. As long as
the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected.
15
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
N
Input pin
DE
SI
G
2. 1
Rev.6.0_03
CS Pin
R
Figure 14
NE
W
CS
DE
D
FO
SK, DI
SK, DI Pin
NO
T
RE
C
OM
TEST
M
EN
Figure 15
16
Figure 16
TEST Pin
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
VCC
N
Output pin
DE
SI
G
2. 2
NE
W
DO
3.
R
DO Pin
FO
Figure 17
Input pin noise elimination time
DE
D
The S-93L76A has a built-in low-pass filter at the SK pin, the DI pin and the CS pin to suppress noise. If the supply
voltage is 5.0 V, noise with a pulse width of 20 ns or less at room temperature can be suppressed by the low-pass
filter.
Note that noise with a pulse width of more than 20 ns is recognized as a pulse since the noise can not be
suppressed if the voltage exceeds VIH / VIL.
Precaution
EN
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
NO
T
RE
C
OM
M
● ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
17
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
DC Characteristics
1. 1
Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 2
Current consumption (READ) ICC1
vs. ambient temperature Ta
VCC 3.3 V
fSK 500 kHz
DATA 0101
VCC 5.5 V
fSK 2 MHz
DATA 0101
0.4
0.4
ICC1
(mA)
ICC1
(mA)
0.2
0
85
Ta (C)
1. 4
Current consumption (READ) ICC1
vs. ambient temperature Ta
VCC 1.8 V
fSK 10 kHz
DATA 0101
D
0.4
DE
ICC1
(mA)
0
40
0
Ta 25C
fSK 1 MHz, 500 kHz
DATA 0101
ICC1
(mA)
1 MHz
0.2
500 kHz
0
85
M
Ta (C)
Current consumption (READ) ICC1
vs. power supply voltage VCC
1. 6
OM
1. 5
ICC1
(mA)
100 kHz
T
NO
18
3
4
5
VCC (V)
6
6
7
0.2
0
10 kHz
2
4 5
VCC (V)
0.4
0.2
0
3
VCC 5.0 V
Ta 25C
RE
C
ICC1
(mA)
2
Current consumption (READ) ICC1
vs. Clock frequency fSK
Ta 25C
fSK 100 kHz, 10 kHz
DATA 0101
0.4
85
0.4
EN
0.2
0
Ta (C)
Current consumption (READ) ICC1
vs. power supply voltage VCC
FO
1. 3
40
0
R
40
NE
W
0.2
0
DE
SI
G
1.
N
Characteristics (Typical Data)
7
10 k 100 k 1 M 2M 10M
fSK (Hz)
1. 7
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1. 8
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
VCC 3.3 V
VCC 5.5 V
1.0
1.0
ICC2
(mA)
ICC2
(mA)
0.5
0
0
85
Ta (C)
1. 10
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
FO
VCC 2.7 V
1.0
0.5
40
0
85
EN
0
1.0
ICC2
(mA)
0.5
0
2
3
OM
M
Current consumption in standby mode ISB
vs. ambient temperature Ta
1. 12
1.0
Ta 25C
CS GND
RE
C
ISB
(A)
T
0
Ta (°C)
85
0
2
3
4
5 6
7
VCC (V)
NO
40
1.0
0.5
0.5
0
5 6 7
Current consumption in standby mode ISB
vs. power supply voltage VCC
VCC 5.5 V
CS GND
ISB
(A)
4
VCC (V)
Ta (C)
1. 11
85
Ta 25C
DE
D
ICC2
(mA)
0
Ta (C)
Current consumption (WRITE) ICC2
vs. power supply voltage VCC
R
1. 9
40
NE
40
W
0.5
0
DE
SI
G
Rev.6.0_03
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
19
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Input leakage current ILI
vs. ambient temperature Ta
VCC 5.5 V
CS, SK, DI,
TEST 0 V
VCC 5.5 V
CS, SK, DI,
TEST 5.5 V
1.0
1.0
ILI
(A)
ILI
(A)
0.5
W
0.5
40
0
85
Ta (C)
1. 16
Output leakage current ILO
vs. ambient temperature Ta
FO
VCC 5.5 V
DO 0 V
1.0
0.5
40
0
85
EN
0
Ta (C)
VCC 5.5 V
DO 5.5 V
ILO
(A)
0.5
0
40
0
Ta (C)
M
High-level output voltage VOH
vs. ambient temperature Ta
4.6
4.4
RE
C
VOH
(V)
NO
T
40
20
1. 18
High-level output voltage VOH
vs. ambient temperature Ta
2.7
VOH
(V)
4.2
0
Ta (C)
85
Ta (°C)
VCC 4.5 V
IOH 400 A
OM
1. 17
85
1.0
DE
D
ILO
(A)
0
Output leakage current ILO
vs. ambient temperature Ta
R
1. 15
40
NE
0
0
N
1. 14
Input leakage current ILI
vs. ambient temperature Ta
DE
SI
G
1. 13
Rev.6.0_03
VCC 2.7 V
IOH 100 A
2.6
2.5
85
40
0
Ta (C)
85
1. 19
High-level output voltage VOH
vs. ambient temperature Ta
High-level output voltage VOH
vs. ambient temperature Ta
VCC 2.5 V
IOH 100 A
2.5
VOH
(V)
1. 20
1.9
VOH
(V)
2.4
2.3
85
40
Ta (C)
Low-level output voltage VOL
vs. ambient temperature Ta
40
0
R
85
EN
Ta (C)
M
High-level output current IOH
vs. ambient temperature Ta
40
OM
RE
C
85
Ta (C)
1. 24
High-level output current IOH
vs. ambient temperature Ta
VCC 2.7 V
VOH 2.4 V
IOH
(mA)
1
10.0
0
Ta (C)
85
0
40
0
85
Ta (C)
NO
T
40
0
2
20.0
0
VCC 1.8 V
IOL 100 A
0.01
VCC 4.5 V
VOH 2.4 V
IOH
(mA)
85
VOL 0.02
(V)
DE
0.1
1. 23
0.03
D
0.2
0
Ta (C)
Low-level output voltage VOL
vs. ambient temperature Ta
FO
VCC 4.5 V
IOL 2.1 mA
0.3
VOL
(V)
1. 22
NE
0
VCC 1.8 V
IOH 10 A
W
1.7
40
1. 21
1.8
DE
SI
G
Rev.6.0_03
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
21
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
1. 26
High-level output current IOH
vs. ambient temperature Ta
VCC 2.5 V
VOH 2.2 V
VCC 1.8 V
VOH 1.6 V
2
1.0
IOH
(mA)
IOH
(mA)
1
W
0.5
0
40
0
85
Ta (C)
Low-level output current IOL
vs. ambient temperature Ta
1. 28
20
VCC 1.8 V
VOL 0.1 V
1.0
IOL
(mA)
IOL
(mA)
0
Ta (C)
85
0.5
DE
40
EN
0
D
10
Input inverted voltage VINV
vs. power supply voltage VCC
0
Ta 25C
CS, SK, DI
RE
C
1.5
0
1
2
3
4
NO
T
VCC (V)
22
5
0
Ta (C)
85
VCC 5.0 V
CS, SK, DI
OM
3.0
VINV
(V)
40
1. 30 Input inverted voltage VINV
vs. ambient temperature Ta
M
1. 29
85
Low-level output current IOL
vs. ambient temperature Ta
FO
VCC 4.5 V
VOL 0.4 V
0
Ta (C)
R
1. 27
40
NE
0
N
High-level output current IOH
vs. ambient temperature Ta
DE
SI
G
1. 25
Rev.6.0_03
3.0
VINV
(V)
2.0
6
7
0
40
0
Ta (C)
85
1. 31
Low supply voltage detection voltage VDET
vs. ambient temperature Ta
1. 32 Low supply voltage release voltage VDET
vs. ambient temperature Ta
2.0
2.0
VDET
(V)
VDET
(V)
1.0
0
0
85
Ta (C)
AC Characteristics
2. 1
Maximum operating frequency fMAX.
vs. power supply voltage VCC
2. 2
Ta 25C
D
100k
1
2
3
4
tPR
(ms)
2
5
1
2
3
M
VCC (V)
Write time tPR
vs. ambient temperature Ta
OM
2. 3
2. 4
tPR
(ms)
2
2
Ta (C)
85
40
0
85
Ta (C)
NO
T
6
4
0
7
Write time tPR
vs. ambient temperature Ta
4
40
5 6
VCC 3.0 V
RE
C
6
4
VCC (V)
VCC 5.0 V
tPR
(ms)
Ta (C)
4
EN
10k
85
Ta 25C
DE
fMAX.
(Hz)
2M
1M
0
Write time tPR
vs. power supply voltage VCC
FO
2.
40
NE
40
R
0
W
1.0
DE
SI
G
Rev.6.0_03
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
23
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
2. 6
Data output delay time tPD
vs. ambient temperature Ta
VCC 2.7 V
tPR
(ms)
VCC 4.5 V
6
tPD
(s)
4
2
85
40
2. 8
VCC 2.7 V
0.6
FO
tPD
(s)
0.2
40
0
85
NO
T
RE
C
OM
M
EN
Ta (C)
DE
D
0.4
24
0
Ta (C)
85
Data output delay time tPD
vs. ambient temperature Ta
R
Data output delay time tPD
vs. ambient temperature Ta
NE
0
W
0.1
Ta (C)
2. 7
0.3
0.2
40
N
Write time tPR
vs. ambient temperature Ta
DE
SI
G
2. 5
Rev.6.0_03
tPD
(s)
VCC 1.8 V
1.5
1.0
0.5
40
0
Ta (C)
85
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L76A
Rev.6.0_03
Product name
1. 1
DE
SI
G
1.
N
Product Name Structure
8-Pin SOP (JEDEC), 8-Pin TSSOP
S-93L76A D0I
-
xxxx
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office)
W
Package name (abbreviation) and IC packing specifications
Fixed
1. 2
FO
R
Product name
S-93L76A: 8 K-bit
NE
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
TMSOP-8
-
K8T3
U
D
S-93L76A D0I
DE
Environmental code
U:
Lead-free (Sn 100%), halogen-free
EN
Package name (abbreviation) and IC packing specifications
K8T3: TMSOP-8, Tape
Packages
RE
C
2.
Package Name
8-Pin SOP
(JEDEC)
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
Package
Drawing Code
Tape
Reel
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
FM008-A-P-SD
FJ008-D-C-SD
FJ008-D-C-SD
FT008-E-C-SD
FT008-E-C-SD
FM008-A-C-SD
FJ008-D-R-SD
FJ008-D-R-S1
FT008-E-R-SD
FT008-E-R-S1
FM008-A-R-SD
NO
T
8-Pin
TSSOP
TMSOP-8
Product name
S-93L76A: 8 K-bit
OM
M
Fixed
25
1
4
DE
SI
G
5
NE
W
8
N
5.02±0.2
DE
D
FO
R
0.20±0.05
1.27
NO
T
RE
C
OM
M
EN
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
N
2.0±0.05
ø1.55±0.05
2.1±0.1
FO
R
NE
8.0±0.1
ø2.0±0.05
W
DE
SI
G
0.3±0.05
5
Feed direction
NO
T
RE
C
OM
M
4
8
EN
1
DE
D
6.7±0.1
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
2,000
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
+0.3
5
1
4
R
NE
W
8
DE
SI
G
3.00 -0.2
DE
D
FO
0.17±0.05
EN
0.2±0.1
NO
T
RE
C
OM
M
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
+0.1
8.0±0.1
NE
ø1.55 -0.05
W
DE
SI
G
N
0.3±0.05
FO
R
(4.4)
+0.4
EN
DE
D
6.6 -0.2
8
M
1
4
NO
T
RE
C
OM
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
DE
SI
G
2.90±0.2
5
1
4
NE
W
8
D
FO
R
0.13±0.1
0.2±0.1
NO
T
RE
C
OM
M
EN
DE
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
1.00±0.1
N
4.00±0.1
+0.1
1.5 -0
NE
W
DE
SI
G
4.00±0.1
1.05±0.05
FO
R
0.30±0.05
1
EN
4
DE
D
3.25±0.05
8
Feed direction
NO
T
RE
C
OM
M
5
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
FO
R
NE
W
DE
SI
G
16.5max.
13±0.2
OM
M
EN
Enlarged drawing in the central part
DE
D
13.0±0.3
NO
T
RE
C
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
EN
DE
D
FO
R
NE
W
DE
SI
G
N
1.
M
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
OM
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
RE
C
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
T
14. For more details on the information described herein, contact our sales office.
NO
2.0-2018.01
www.ablicinc.com
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