S-93L46A/56A/66A
N
LOW VOLTAGE OPERATION
3-WIRE SERIAL E2PROM
DE
SI
G
www.ablicinc.com
Rev.8.1_02
© ABLIC Inc., 2004-2015
W
The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide
operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64word 16-bit, 128-word 16-bit, and 256-word 16-bit. It is capable of sequential read, at which time addresses are
automatically incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Features
Read
Write
1.6 V to 5.5 V
1.8 V to 5.5 V (WRITE, ERASE)
2.7 V to 5.5 V (WRAL, ERAL)
2.0 MHz (VCC = 4.5 V to 5.5 V)
8.0 ms max.
NE
Operating voltage range:
EN
DE
D
FO
R
Operation frequency:
Write time:
Sequential read capable
Write protect function during the low power supply voltage
Function to protect against write due to erroneous instruction recognition
Endurance:
106 cycles / word*1 (Ta = 85C)
Data retention:
100 years (Ta = 25C)
20 years (Ta = 85C)
Memory capacity:
S-93L46A:
1 K-bit
S-93L56A:
2 K-bit
S-93L66A:
4 K-bit
Initial delivery state:
FFFFh
Operation temperature range:
Ta = 40°C to 85C
Lead-free, Sn 100%, halogen-free*2
M
*1. For each address (Word: 16-bit)
*2. Refer to “ Product Name Structure” for details.
OM
Packages
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC
Inc. is indispensable.
NO
T
Caution
RE
C
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
1
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC)
Top view
Table 1
Pin No.
8
2
7
3
6
4
5
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
NE
Figure 1
8-Pin SOP (JEDEC) (Rotated)
Top view
Pin No.
7
3
6
4
5
1
NC
No connection
2
VCC
Power supply
3
CS
Chip select input
4
SK
Serial clock input
5
DI
Serial data input
6
DO
Serial data output
7
GND
Ground
TEST*1
8
Test
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
M
OM
S-93L46AR0I-J8T1x
S-93L56AR0I-J8T1x
S-93L66AR0I-J8T1x
Description
D
2
Table 2
DE
8
Symbol
EN
1
FO
R
S-93L46AD0I-J8T1x
S-93L56AD0I-J8T1x
S-93L66AD0I-J8T1x
Figure 2
Description
W
1
Symbol
DE
SI
G
1.
N
Pin Configurations
NO
T
RE
C
Remark 1. Refer to the “Package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
2
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
8-Pin TSSOP
8-Pin TSSOP
Top view
Table 3
Pin No.
1
2
3
4
W
NE
S-93L46AD0I-T8T1x
S-93L56AD0I-T8T1x
S-93L66AD0I-T8T1x
Pin No.
8
7
6
5
DE
EN
OM
SNT-8A
Top view
RE
C
8
7
6
5
Figure 5
T
S-93L46AD0I-I8T1U
S-93L56AD0I-I8T1U
S-93L66AD0I-I8T1U
NO
Description
M
SNT-8A
1
2
3
4
Symbol
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
Figure 4
S-93L46AD0I-K8T3U
S-93L56AD0I-K8T3U
S-93L66AD0I-K8T3U
Table 4
D
1
2
3
4
FO
R
TMSOP-8
TMSOP-8
Top view
4.
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
8
7
6
5
Figure 3
3.
Symbol
DE
SI
G
2.
Table 5
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
TEST*1
6
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
Remark 1. Refer to the “Package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
3
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Block Diagram
decoder
Data register
W
NE
Mode decode logic
CS
Clock pulse
monitoring circuit
R
Voltage detector
FO
Clock generator
NO
T
RE
C
OM
M
EN
DE
D
Figure 6
4
GND
Output buffer
DI
SK
VCC
DE
SI
G
Address
Memory array
N
Rev.8.1_02
DO
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
1.
N
Instruction Sets
S-93L46A
DE
SI
G
Table 6
Remark x: Don’t care
2.
S-93L56A
Table 7
Operation
Code
Address
FO
Start Bit
Instruction
SK input clock
R
NE
W
Operation
Address
Data
Start Bit
Instruction
Code
SK input clock
1
2
3
4
5
6
7
8
9
10 to 25
D15 to D0 Output*1
READ (Read data)
1
1
0
A5
A4
A3
A2
A1
A0
WRITE (Write data)
1
0
1
A5
A4
A3
A2
A1
A0
D15 to D0 Input
ERASE (Erase data)
1
1
1
A5
A4
A3
A2
A1
A0
WRAL (Write all)
1
0
0
0
1
x
x
x
x
D15 to D0 Input
ERAL (Erase all)
1
0
0
1
0
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Data
EN
DE
D
1
2
3
4
5
6
7
8
9
10 11
12 to 27
D15 to D0 Output*1
READ (Read data)
1
1
0
x
A6 A5 A4 A3 A2 A1 A0
WRITE (Write data)
1
0
1
x
A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data)
1
1
1
x
A6 A5 A4 A3 A2 A1 A0
WRAL (Write all)
1
0
0
0
1
x
x
x
x
x
x
D15 to D0 Input
ERAL (Erase all)
1
0
0
1
0
x
x
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
M
Remark x: Don’t care
Instruction
SK input clock
OM
3. S-93L66A
Start Bit
1
Table 8
Operation
Code
2
Address
Data
3
NO
T
RE
C
4
5
6
7
8
9
10 11
12 to 27
D15 to D0 Output*1
READ (Read data)
1
1
0
A7 A6 A5 A4 A3 A2 A1 A0
WRITE (Write data)
1
0
1
A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data)
1
1
1
A7 A6 A5 A4 A3 A2 A1 A0
WRAL (Write all)
1
0
0
0
1
x
x
x
x
x
x
D15 to D0 Input
ERAL (Erase all)
1
0
0
1
0
x
x
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
5
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
Absolute Maximum Ratings
Table 9
DE
SI
G
Item
Symbol
Ratings
Unit
Power supply voltage
VCC
0.3 to 7.0
V
Input voltage
VIN
0.3 to VCC 0.3
V
Output voltage
VOUT
0.3 to VCC
V
Operation ambient temperature
Topr
40 to 85
C
Storage temperature
Tstg
65 to 150
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
W
Recommended Operating Conditions
Item
Symbol
VCC
High level input voltage
VIH
Low level input voltage
VIL
Ta = 40C to 85C
Min.
Max.
1.6
5.5
1.8
5.5
2.7
5.5
2.0
VCC
0.8 VCC
VCC
0.8 VCC
VCC
0.0
0.8
0.0
0.2 VCC
0.0
0.15 VCC
Conditions
READ, EWDS
WRITE, ERASE, EWEN
WRAL, ERAL
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.6 V to 2.7 V
DE
D
FO
R
Power supply voltage
NE
Table 10
Pin Capacitance
Unit
V
V
V
V
V
V
V
V
V
Table 11
Symbol
OM
Symbol
Endurance
Conditions
VIN = 0 V
VOUT = 0 V
M
CIN
COUT
Endurance
Item
(Ta = 25C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
8
pF
10
pF
EN
Item
Input Capacitance
Output Capacitance
NW
Table 12
Operation Ambient Temperature
Min.
6
Ta = 40C to 85C
10
Max.
Unit
Cycles / word*1
Max.
Unit
year
year
RE
C
*1. For each address (Word: 16-bit)
Data Retention
Item
NO
T
Data Retention
6
Symbol
Table 13
Operation Ambient Temperature
Ta = 25C
Ta = 40C to 85C
Min.
100
20
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
DC Electrical Characteristics
Table 14
Symbol
Current consumption
ICC1
(READ)
Conditions
VCC = 4.5 V to 5.5 V
Min.
Max.
Ta = 40C to 85C
VCC = 4.5 V to 5.5 V
VCC = 1.8 V to 4.5 V
Min.
Max.
Min.
Max.
Unit
DO no load
Table 16
VOH
Data hold voltage
of write enable latch
VDH
VOUT = GND to VCC
FO
R
Ta = 40C to 85C
VCC =
2.5 V to 4.5 V
Min.
Max.
1.5
mA
VCC =
1.6 V to 2.5 V
Min.
Max.
Unit
1.5
1.5
1.5
A
1.0
1.0
1.0
A
1.0
1.0
1.0
A
0.4
0.1
VCC0.3
VCC0.2
0.1
VCC0.2
0.1
V
V
V
V
V
1.5
1.5
V
IOL = 2.1 mA
IOL = 100 A
IOH = 400 A
2.4
IOH = 100 A
VCC0.3
IOH = 10 A
VCC0.2
Only program disable
1.5
mode
NO
T
RE
C
OM
High level output
voltage
CS = GND,
DO = Open,
Other input pins are
VCC or GND
VIN = GND to VCC
D
Input leakage current ILI
Output leakage
ILO
current
Low level output
VOL
voltage
Conditions
DE
ISB
VCC =
4.5 V to 5.5 V
Min.
Max.
EN
Standby current
consumption
Symbol
M
Item
2.0
W
Current consumption
ICC2
(WRITE)
Conditions
0.5
NE
Symbol
Unit
mA
0.8
Table 15
Item
VCC = 1.6 V to 2.5 V
Min.
Max.
0.4
DO no load
Ta = 40C to 85C
VCC = 2.5 V to 4.5 V
Min.
Max.
DE
SI
G
Item
7
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Measurement Conditions
0.1 VCC to 0.9 VCC
0.5 VCC
100 pF
Input pulse voltage
Output reference voltage
Output load
DE
SI
G
Table 17
N
AC Electrical Characteristics
Table 18
DE
D
FO
R
NE
W
Ta = 40C to 85C
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.6 V to 2.5 V Unit
Item
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
CS setup time
tCSS
0.2
—
0.4
—
1.0
—
s
CS hold time
tCSH
0
—
0
—
0
—
s
CS deselect time
tCDS
0.2
—
0.2
—
0.4
—
s
Data setup time
tDS
0.1
—
0.2
—
0.4
—
s
Data hold time
tDH
0.1
—
0.2
—
0.4
—
s
Output delay time
tPD
—
0.4
—
0.8
—
2.0
s
Clock frequency*1
0
2.0
0
1.0
0
0.25
MHz
fSK
SK clock time “L” *1
0.1
—
0.25
—
1.0
—
s
tSKL
*1
SK clock time “H”
0.1
—
0.25
—
1.0
—
s
tSKH
Output disable time
tHZ1, tHZ2
0
0.15
0
0.5
0
1.0
s
Output enable time
tSV
0
0.15
0
0.5
0
1.0
s
*1. The clock cycle of the SK clock (frequency: fSK) is 1 / fSK s. This clock cycle is determined by a combination of several
AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot be
made equal to tSKL (min.) tSKH (min.).
Item
Symbol
tPR
NO
T
RE
C
OM
M
Write time
EN
Table 19
8
Ta = 40C to 85C
VCC = 1.8 V to 5.5 V
Min
Typ.
Max.
—
4.0
8.0
Unit
ms
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
tCSS
tCDS
*2
1 / fSK
N
Rev.8.1_02
CS
tSKL
tCSH
SK
tDS
DI
tPD
tPD
High-Z
High-Z
tSV
(READ)
W
DO
tHZ2
NE
High-Z
(VERIFY)
tHZ1
High-Z
R
Indicates high impedance.
1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics,
so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK) cannot be made
equal to tSKL (min.) tSKH (min.).
Timing Chart
NO
T
RE
C
OM
M
EN
DE
D
Figure 7
FO
*1.
*2.
tDH
Valid data
Valid data
*1
DO
tDS
tDH
DE
SI
G
tSKH
9
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
Initial Delivery State
DE
SI
G
Initial delivery state of all addresses is “FFFFh”.
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS. While
a low level is being input to CS, the S-93L46A/56A/66A is in standby mode, so the SK and DI inputs are invalid and no
instructions are allowed.
W
Start Bit
1.
NE
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit
is not recognized even if the SK pulse is input as long as the DI pin is low.
Dummy clock
2.
FO
R
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks can
be adjusted by inserting a 7-bit dummy clock for the S-93L46A and a 5-bit dummy clock for the S-93L56A/66A.
Start bit input failure
DE
D
When the output status of the DO pin is high during the verify period after a write operation, if a high level is input
to the DI pin at the rising edge of SK, the S-93L46A/56A/66A recognizes that a start bit has been input. To
prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4. 1 Verify
operation”).
NO
T
RE
C
OM
M
EN
When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the
data output from the CPU and the serial memory collide may be generated, preventing successful input of the
start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
10
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Reading (READ)
N
3.
DE
SI
G
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A0) has been latched, the output status of the DO pin changes from high impedance (High-Z) to
low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of
SK.
W
3. 1 Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically
increments the address, and causes the 16-bit data at the next address to be output sequentially. The above
method makes it possible to read the data in the whole memory space. The last address (An A1 A0 = 1 1
1) rolls over to the top address (An A1 A0 = 0 0 0).
DI
2
1
3
4
0
A5
5
A4
6
A3
7
A2
8
A1
11
12
23
24
25
26
A0
High-Z
DO
10
9
D15
0
D14
D13
D2
27
R
1
D1
D0
D15
D14
28
39
D13
40
D2
41
D1
FO
SK
NE
CS
ADRINC
D15
43
D14
44
D13
High-Z
ADRINC
Read Timing (S-93L46A)
CS
DI
1
2
1
3
4
0
5
A6
6
7
8
9
A5
A4
A3
A2
A1
A7: S-93L66A
12
13
14
24
25
26
27
28
29
40
41 42
43
44
45
A0
0
OM
DO
11
M
x: S-93L56A
High-Z
10
EN
SK
DE
D
Figure 8
D0
42
D15 D14 D13
D1
D0 D15 D14 D13
ADRINC
D2
D1
D0 D15 D14 D13
High-Z
ADRINC
Read Timing (S-93L56A, S-93L66A)
NO
T
RE
C
Figure 9
D2
11
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Writing (WRITE, ERASE, WRAL, ERAL)
N
4.
Rev.8.1_02
Verify operation
A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4 ms), so if the
completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to
confirm the status of a write operation is called a verify operation.
NE
W
4. 1
DE
SI
G
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is
input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write
period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
Operation
After the write operation has started (CS = low), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting a high level to CS again. This sequence is called
a verify operation, and the period that a high level is input to the CS pin after the write operation has
started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify
operation period is as follows.
DO pin = low: Writing in progress (busy)
DO pin = high: Writing completed (ready)
4. 1. 2
Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the
DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing it
again to verify the output status of the DO pin. The latter method allows the CPU to perform other
processing during the wait period, allowing an efficient system to be designed.
DE
D
FO
R
4. 1. 1
NO
T
RE
C
OM
M
EN
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93L46A/56A/66A latches the instruction assuming that a start bit has been input. In
this case, note that the DO pin immediately enters a high-impedance (High-Z) state.
12
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address,
and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to set
the data to 1 before writing. If the clocks more than the specified number have been input, the clock pulse
monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer to
“ Function to Protect Against Write due to Erroneous Instruction Recognition”.
DE
SI
G
N
4. 2
tCDS
CS
Standby
Verify
1
DI
2
0
3
1
4
5
6
7
8
9
10
A5
A4
A3
A2
A1
A0
D15
25
D0
High-Z
DO
W
SK
tSV
Busy
tHZ1
Ready
NE
tPR
Data Write Timing (S-93L46A)
CS
2
0
3
4
1
5
6
7
8
9
A6
A5
A4
A3
A2
High-Z
DO
tCDS
11
12
27
A1
A0
D15
D0
tSV
x : S-93L56A
A7: S-93L66A
tHZ1
Busy
tPR
Ready
High-Z
Data Write Timing (S-93L56A, S-93L66A)
NO
T
RE
C
OM
M
EN
Figure 11
Standby
Verify
10
DE
DI
1
D
SK
FO
R
Figure 10
High-Z
13
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input
the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when CS goes low. If the clocks have been input more than the specified number, the clock
pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer
to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
DE
SI
G
N
4. 3
Rev.8.1_02
tCDS
CS
1
2
DI
1
3
1
4
5
6
7
8
A5
A4
A3
A2
A1
tSV
Busy
tHZ1
Ready
High-Z
NE
tPR
1
2
DI
1
3
4
1
5
6
7
A6
A5
A4
8
9
A3
A2
D
SK
FO
R
Data Erase Timing (S-93L46A)
CS
High-Z
DE
DO
x : S-93L56A
A7: S-93L66A
M
OM
RE
C
10
A1
tCDS
Standby
Verify
11
A0
tSV
Busy
tPR
Data Erase Timing (S-93L56A, S-93L66A)
EN
Figure 13
T
A0
High-Z
Figure 12
NO
9
W
SK
DO
14
Standby
Verify
tHZ1
Ready
High-Z
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write
operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks more
than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL instruction.
For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
tCDS
CS
DE
SI
G
N
4. 4
Standby
Verify
1
2
DI
0
3
0
4
0
5
6
7
9
1
10
25
D0
D15
4Xs
tSV
NE
High-Z
DO
8
W
SK
tHZ1
Busy
Ready
High-Z
tPR
Chip Write Timing (S-93L46A)
CS
2
DI
0
3
0
4
0
5
1
High-Z
DO
6
7
8
9
D
1
10
11
tCDS
12
27
D15
D0
tSV
tHZ1
Busy
tPR
Ready
High-Z
Chip Write Timing (S-93L56A, S-93L66A)
NO
T
RE
C
OM
M
EN
Figure 15
Standby
Verify
6Xs
DE
SK
FO
R
Figure 14
15
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then input
the ERAL instruction and an address following the start bit. Any address can be input. There is no need to
input data. The chips erase operation starts when CS goes low. When the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the
clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction
Recognition”.
CS
DE
SI
G
N
4. 5
Rev.8.1_02
1
2
3
4
DI
0
0
1
5
6
7
8
9
W
SK
0
4Xs
tHZ1
NE
tSV
High-Z
DO
Standby
Verify
tCDS
Busy
Ready
High-Z
Chip Erase Timing (S-93L46A)
FO
Figure 16
R
tPR
CS
2
3
4
DI
0
0
1
5
0
6
D
1
7
8
DE
SK
M
DO
EN
6Xs
High-Z
NO
T
RE
C
OM
Figure 17
16
9
10
Standby
Verify
tCDS
11
tHZ1
tSV
Busy
tPR
Chip Erase Timing (S-93L56A, S-93L66A)
Ready
High-Z
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Write enable (EWEN) and write disable (EWDS)
N
5.
DE
SI
G
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is
enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been
input.
Standby
CS
1
DI
2
3
4
5
6
7
8
0
0
11 = EWEN
00 = EWDS
NE
Write Enable / Disable Timing (S-93L46A)
CS
1
DI
2
0
3
4
5
0
8
9
10
11
6Xs
Write Enable / Disable Timing (S-93L56A, S-93L66A)
EN
Figure 19
7
DE
11 = EWEN
00 = EWDS
6
Standby
D
SK
FO
R
Figure 18
4Xs
9
W
SK
NO
T
RE
C
OM
M
Remark It is recommended to execute an EWDS instruction for preventing an incorrect write operation if a write
instruction is erroneously recognized when executing instructions other than write instruction, and
immediately after power-on and before power-off.
17
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Write Protect Function during the Low Power Supply Voltage
N
Rev.8.1_02
W
DE
SI
G
The S-93L46A/56A/66A provides a built-in detection circuit to detect a low power supply voltage. When the power
supply voltage is low or at power-on, the write instructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the
write disable state (EWDS) is automatically set. The detection voltage and the release voltage are 1.4 V typ. (refer to
Figure 20).
Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to
the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE,
ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
NE
Power supply voltage
Release voltage (VDET)
1.4 V typ.
R
Detection voltage (VDET)
1.4 V typ.
Operation during Low Power Supply Voltage
NO
T
RE
C
OM
M
EN
DE
D
Figure 20
FO
Write instructions are cancelled
Write disable state (EWDS) is automatically set
18
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
Function to Protect Against Write due to Erroneous Instruction Recognition
DE
SI
G
The S-93L46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write
operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an
erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation (WRITE,
ERASE, WRAL, or ERAL) is detected.
Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93L46A
W
Noise pulse
1
2
3
4
SK
5
6
7
8
9
1
0
Erroneous recognition as
ERASE instruction due to
noise pulse
1 1 10
0
0
0
0
0
0
0
0
0
00
0
0
0
0
DE
D
Input EWDS instruction
FO
R
DI
NE
CS
M
EN
In products that do not include a clock pulse monitoring circuit, FFFFh is mistakenly written
on address 00h. However the S-93L46A detects the overcount and cancels the instruction
without performing a write operation.
Example of Clock Pulse Monitoring Circuit Operation
NO
T
RE
C
OM
Figure 21
19
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
N
3-Wire Interface (Direct Connection between DI and DO)
DE
SI
G
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93L46A/56A/66A via a resistor (10 k to 100 k) so that the data output from the CPU takes precedence in
being input to the DI pin (refer to Figure 22).
CPU
SIO
NE
DI
DO
W
S-93L46A/56A/66A
R: 10 k to 100 k
Figure 22
Connection of 3-Wire Interface
Connection of input pins
FO
1.
R
Input Pin and Output Pin
2.
DE
D
All input pins in S-93L46A/56A/66A have the CMOS structure. Do not set these pins in high impedance during
operation when you design. Especially, set the CS pin to “L” at power-on, power-off, and during standby. The error
write does not occur as long as the CS pin is “L”. Set the CS pin to GND via a resistor (the pull-down resistor of 10
k to 100 k).
To prevent the error for sure, it is recommended to use equivalent pull-down resistors for input pins other than the CS
pin.
Equivalent circuit of input pin and output pin
NO
T
RE
C
OM
M
EN
The following shows the equivalent circuits of input pins of the S-93L46A/56A/66A. None of the input pins incorporate
pull-up and pull-down resistors, so special care must be taken when designing to prevent a floating status.
Output pins are high-level / low-level / high-impedance tri-state outputs.
The TEST pin is disconnected from the internal circuit by a switching transistor during normal operation.
As long as the absolute maximum rating is satisfied, the TEST pin and internal circuit will never be connected.
20
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Input pin
CS
CS Pin
NE
Figure 23
W
DE
SI
G
N
2. 1
DE
D
FO
R
SK, DI
SK, DI Pin
Figure 25
TEST Pin
NO
T
RE
C
OM
M
TEST
EN
Figure 24
21
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Output pin
N
2. 2
Rev.8.1_02
DE
SI
G
VCC
Input pin noise suppression time
FO
3.
DO Pin
R
Figure 26
NE
W
DO
DE
D
This IC has a built-in low-pass filter at the SK pin, the DI pin and the CS pin to suppress noise. If the supply voltage is
5.0 V, noise with a pulse width of 20 ns or less at room temperature can be suppressed by the low-pass filter.
Note that noise with a pulse width of more than 20 ns is recognized as a pulse since the noise can not be suppressed
if the voltage exceeds VIH / VIL.
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
NO
T
RE
C
OM
M
EN
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
22
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
DC Characteristics
1. 2
VCC 3.3 V
fSK 500 kHz
DATA 0101
VCC 5.5 V
fSK 2 MHz
DATA 0101
0.4
0.4
ICC1
(mA)
ICC1
(mA)
40
0
85
0
1. 4
VCC 1.8 V
fSK 10 kHz
DATA 0101
0.4
D
ICC1
(mA)
0
85
Ta (C)
EN
40
OM
M
Current consumption (READ) ICC1
vs. power supply voltage VCC
RE
C
Ta 25C
fSK 100 kHz, 10 kHz
DATA 0101
100 kHz
1 MHz
0.2
DE
0.2
ICC1
(mA)
Current consumption (READ) ICC1
vs. power supply voltage VCC
FO
0.4
0.4
85
Ta 25C
fSK 1 MHz, 500 kHz
DATA 0101
ICC1
(mA)
1. 5
0
R
Current consumption (READ) ICC1
vs. ambient temperature Ta
0
40
Ta (C)
Ta (C)
1. 3
W
0.2
0.2
0
Current consumption (READ) ICC1
vs. ambient temperature Ta
DE
SI
G
Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 1
NE
1.
N
Characteristics (Typical Data)
500 kHz
0
2
3
4
5
6
7
VCC (V)
1. 6
Current consumption (READ) ICC1
vs. Clock frequency fSK
VCC 5.0 V
Ta 25C
0.4
ICC1
(mA)
0.2
0.2
0
10 kHz
2
NO
T
0
3
4
5 6
7
10 k
100 k
1 M 2M 10M
fSK (Hz)
VCC (V)
23
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
N
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
DE
SI
G
1. 8
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
VCC 3.3 V
VCC 5.5 V
1.0
0.5
ICC2
(mA)
0.5
ICC2
(mA)
0
40
0
0
85
40
Ta (C)
1. 10
Current consumption (WRITE) ICC2
vs. ambient temperature Ta
FO
VCC 2.7 V
1.0
Ta 25C
1.0
ICC2
(mA)
D
ICC2
(mA)
40
0
85
Ta (C)
1. 12
Current consumption in standby mode ISB
vs. ambient temperature Ta
OM
VCC 5.5 V
CS GND
ISB
(A)
0.5
40
0
85
Ta (°C)
NO
T
0
RE
C
1.0
2
3
4
5 6
7
VCC (V)
M
1. 11
0.5
0
EN
0
DE
0.5
24
Current consumption (WRITE) ICC2
vs. power supply voltage VCC
R
1. 9
0
85
Ta (C)
NE
1.0
W
1. 7
Rev.8.1_02
Current consumption in standby mode ISB
vs. power supply voltage VCC
Ta 25C
CS GND
ISB
(A)
1.0
0.5
0
2 3 4 5 6
VCC (V)
7
1. 13
1. 14
Input leakage current ILI
vs. ambient temperature Ta
Input leakage current ILI
vs. ambient temperature Ta
DE
SI
G
Rev.8.1_02
VCC 5.5 V
CS, SK, DI,
TEST 0 V
VCC 5.5 V
CS, SK, DI,
TEST 5.5 V
1.0
1.0
ILI
(A)
ILI
(A)
0
0
85
85
1. 16
Output leakage current ILO
vs. ambient temperature Ta
R
Output leakage current ILO
vs. ambient temperature Ta
FO
VCC 5.5 V
DO 0 V
VCC 5.5 V
DO 5.5 V
1.0
1.0
ILO
(A)
ILO
(A)
0.5
0
40
0
DE
D
0.5
85
High-level output voltage VOH
vs. ambient temperature Ta
VCC 4.5 V
IOH 400 A
OM
4.6
RE
C
4.4
4.2
40
0
85
40
0
85
Ta (°C)
1. 18
2.7
VOH
(V)
High-level output voltage VOH
vs. ambient temperature Ta
VCC 2.7 V
IOH 100 A
2.6
2.5
40
0
85
Ta (C)
NO
T
Ta (C)
0
M
1. 17
EN
Ta (C)
VOH
(V)
0
Ta (C)
Ta (C)
1. 15
40
NE
40
W
0.5
0.5
0
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
25
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
VCC 2.5 V
IOH 100 A
2.5
VOH
(V)
2.4
N
1.8
0
85
40
Ta (C)
1. 21
0
85
Ta (C)
Low-level output voltage VOL
vs. ambient temperature Ta
1. 22
Low-level output voltage VOL
vs. ambient temperature Ta
VCC 1.8 V
IOL 100 A
R
VCC 4.5 V
IOL 2.1 mA
0.03
FO
0.3
W
1.7
40
0.2
VOL 0.02
(V)
40
0
85
EN
Ta (C)
1. 23
High-level output current IOH
vs. ambient temperature Ta
OM
20.0
IOH
(mA)
0
RE
C
10.0
40
0
NO
T
Ta (C)
40
85
0
85
Ta (C)
1. 24
High-level output current IOH
vs. ambient temperature Ta
VCC 2.7 V
VOH 2.4 V
M
VCC 4.5 V
VOH 2.4 V
0.01
DE
D
0.1
26
VCC 1.8 V
IOH 10 A
1.9
2.3
VOL
(V)
High-level output voltage VOH
vs. ambient temperature Ta
NE
VOH
(V)
1. 20
High-level output voltage VOH
vs. ambient temperature Ta
DE
SI
G
1. 19
Rev.8.1_02
2
IOH
(mA)
1
0
40
0
85
Ta (C)
1. 25
High-level output current IOH
vs. ambient temperature Ta
1. 26
High-level output current IOH
vs. ambient temperature Ta
DE
SI
G
Rev.8.1_02
VCC 2.5 V
VOH 2.2 V
VCC 1.8 V
VOH 1.6 V
2
1.0
IOH
(mA)
IOH
(mA)
1
0
40
0
40
85
Ta (C)
1. 27
W
0.5
0
85
Ta (C)
Low-level output current IOL
vs. ambient temperature Ta
1. 28
NE
0
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Low-level output current IOL
vs. ambient temperature Ta
VCC 1.8 V
VOL 0.1 V
R
VCC 4.5 V
VOL 0.4 V
1.0
FO
20
IOL
(mA)
IOL
(mA)
0.5
Input inverted voltage VINV
vs. power supply voltage VCC
Ta 25C
CS, SK, DI
3.0
OM
VINV
(V)
0
RE
C
1.5
1
2
3
4 5
6 7
0
1. 30
40
0
85
Ta (C)
Input inverted voltage VINV
vs. ambient temperature Ta
VCC 5.0 V
CS, SK, DI
3.0
VINV
(V)
2.0
0
40
0
Ta (C)
85
NO
T
VCC (V)
DE
0
85
Ta (C)
EN
1. 29
40
M
0
D
10
27
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
+VDET
(V)
1.0
0
0
85
Ta (C)
AC Characteristics
Maximum operating frequency fMAX.
vs. power supply voltage VCC
2M
1M
4
D
tPR
(ms)
DE
100k
3
4
5
VCC (V)
40
0
NO
T
Ta (C)
28
2. 4
M
RE
C
4
OM
6
85
2
3
4
5 6
7
VCC (V)
Write time tPR
vs. ambient temperature Ta
VCC 5.0 V
2
1
EN
2
1
2
Write time tPR
vs. power supply voltage VCC
Ta 25C
10k
tPR
(ms)
85
R
2. 2
Ta 25C
2. 3
0
Ta (C)
FO
2. 1
-40
NE
-40
W
1.0
0
fMAX.
(Hz)
N
2.0
2.0
-VDET
(V)
2.
Low power supply release voltage VDET
vs. ambient temperature Ta
1. 32
DE
SI
G
Low power supply detection voltage VDET
vs. ambient temperature Ta
1. 31
Rev.8.1_02
Write time tPR
vs. ambient temperature Ta
VCC 3.0 V
tPR
(ms)
6
4
2
40
0
Ta (C)
85
2. 6
Write time tPR
vs. ambient temperature Ta
Data output delay time tPD
vs. ambient temperature Ta
VCC 2.7 V
6
tPD
(s)
4
0.3
0.2
2
0.1
40
0
85
40
Ta (C)
2. 7
Data output delay time tPD
vs. ambient temperature Ta
2. 8
VCC 2.7 V
85
Data output delay time tPD
vs. ambient temperature Ta
0.6
tPD
(s)
R
VCC 1.8 V
1.5
FO
tPD
(s)
0
Ta (C)
NE
tPR
(ms)
VCC 4.5 V
W
2. 5
DE
SI
G
Rev.8.1_02
N
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
0.4
1.0
0.2
40
0
DE
D
0.5
85
40
0
85
Ta (C)
NO
T
RE
C
OM
M
EN
Ta (C)
29
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A
Rev.8.1_02
Product name
1. 1
8-Pin SOP (JEDEC), 8-Pin TSSOP
S-93LxxA
x
0I
-
xxxx
DE
SI
G
1.
N
Product Name Structure
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office)
W
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
Fixed
NE
Pin configurations
D:
8-Pin SOP (JEDEC)
8-Pin TSSOP
R:
8-Pin SOP (JEDEC) (Rotated)
TMSOP-8, SNT-8A
S-93LxxA
D0I
-
xxxx
U
D
1. 2
FO
R
Product name
S-93L46A: 1 K-bit
S-93L56A: 2 K-bit
S-93L66A: 4 K-bit
Packages
RE
C
2.
OM
M
EN
DE
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package Name
8-Pin SOP
(JEDEC)
8-Pin TSSOP
NO
T
TMSOP-8
SNT-8A
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
30
Package name (abbreviation) and IC packing specifications
K8T3: TMSOP-8, Tape
I8T1: SNT-8A, Tape
Fixed
Product name
S-93L46A: 1 K-bit
S-93L56A: 2 K-bit
S-93L66A: 4 K-bit
Drawing Code
Package
Tape
Reel
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
FM008-A-P-SD
PH008-A-P-SD
FJ008-D-C-SD
FJ008-D-C-SD
FT008-E-C-SD
FT008-E-C-SD
FM008-A-C-SD
PH008-A-C-SD
FJ008-D-R-SD
FJ008-D-R-S1
FT008-E-R-SD
FT008-E-R-S1
FM008-A-R-SD
PH008-A-R-SD
Land
PH008-A-L-SD
1
4
DE
SI
G
5
NE
W
8
N
5.02±0.2
DE
D
FO
R
0.20±0.05
1.27
NO
T
RE
C
OM
M
EN
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
N
2.0±0.05
ø1.55±0.05
2.1±0.1
FO
R
NE
8.0±0.1
ø2.0±0.05
W
DE
SI
G
0.3±0.05
5
Feed direction
NO
T
RE
C
OM
M
4
8
EN
1
DE
D
6.7±0.1
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
2,000
N
DE
SI
G
FO
R
NE
W
60°
D
13.5±0.5
2±0.5
ø13±0.2
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
2±0.5
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
+0.3
5
1
4
R
NE
W
8
DE
SI
G
3.00 -0.2
DE
D
FO
0.17±0.05
EN
0.2±0.1
NO
T
RE
C
OM
M
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
+0.1
8.0±0.1
NE
ø1.55 -0.05
W
DE
SI
G
N
0.3±0.05
FO
R
(4.4)
+0.4
EN
DE
D
6.6 -0.2
8
M
1
4
NO
T
RE
C
OM
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
N
DE
SI
G
W
NE
R
FO
D
17.5±1.0
2±0.5
ø13±0.5
NO
T
RE
C
OM
M
EN
ø21±0.8
DE
Enlarged drawing in the central part
13.4±1.0
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
N
DE
SI
G
2.90±0.2
5
1
4
NE
W
8
D
FO
R
0.13±0.1
0.2±0.1
NO
T
RE
C
OM
M
EN
DE
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
1.00±0.1
N
4.00±0.1
+0.1
1.5 -0
NE
W
DE
SI
G
4.00±0.1
1.05±0.05
FO
R
0.30±0.05
1
EN
4
DE
D
3.25±0.05
8
Feed direction
NO
T
RE
C
OM
M
5
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
N
FO
R
NE
W
DE
SI
G
16.5max.
13±0.2
OM
M
EN
Enlarged drawing in the central part
DE
D
13.0±0.3
NO
T
RE
C
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
6
5
3
4
DE
SI
G
7
W
8
N
1.97±0.03
+0.05
0.5
2
0.08 -0.02
NO
T
RE
C
OM
M
EN
DE
0.2±0.05
D
FO
R
0.48±0.02
NE
1
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
N
DE
SI
G
W
ø0.5±0.1
4.0±0.1
0.25±0.05
0.65±0.05
D
FO
R
2.25±0.05
4.0±0.1
2.0±0.05
NE
+0.1
ø1.5 -0
DE
4 321
EN
5 6 78
NO
T
RE
C
OM
M
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
FO
R
NE
W
DE
SI
G
N
12.5max.
D
9.0±0.3
DE
Enlarged drawing in the central part
EN
ø13±0.2
(60°)
NO
T
RE
C
OM
M
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
DE
SI
G
N
0.52
2
NE
W
2.01
FO
R
0.52
0.2 0.3
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
D
1.
2.
1
3.
4.
0.03 mm
DE
1.
2.
SNT
EN
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
NO
T
RE
C
1.
2.
OM
M
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
No. PH008-A-L-SD-4.1
TITLE
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
EN
DE
D
FO
R
NE
W
DE
SI
G
N
1.
M
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
OM
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
RE
C
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
T
14. For more details on the information described herein, contact our sales office.
NO
2.0-2018.01
www.ablicinc.com
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