GD25Q127CFIGR

3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C DATASHEET 1 GD25Q127C 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Contents 1. FEATURES .................................................................................................................................................. 4 2. GENERAL DESCRIPTION .......................................................................................................................... 5 3. MEMORY ORGANIZATION ......................................................................................................................... 9 4. DEVICE OPERATION ................................................................................................................................ 10 5. DATA PROTECTION ................................................................................................................................. 12 6. STATUS REGISTER .................................................................................................................................. 14 7. COMMANDS DESCRIPTION .................................................................................................................... 16 7.1. W RITE ENABLE (WREN) (06H) ............................................................................................................. 19 7.2. W RITE DISABLE (WRDI) (04H) .............................................................................................................. 19 7.3. W RITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................ 19 7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) ...................................................................... 20 7.5. W RITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) .................................................................... 20 7.6. READ DATA BYTES (READ) (03H) ........................................................................................................ 21 7.7. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) ..................................................................... 22 7.8. DUAL OUTPUT FAST READ (3BH) .......................................................................................................... 22 7.9. QUAD OUTPUT FAST READ (6BH) ......................................................................................................... 23 7.10. DUAL I/O FAST READ (BBH) ................................................................................................................. 23 7.11. QUAD I/O FAST READ (EBH) ................................................................................................................. 24 7.12. QUAD I/O W ORD FAST READ (E7H) ...................................................................................................... 26 7.13. SET BURST WITH W RAP (77H) .............................................................................................................. 27 7.14. PAGE PROGRAM (PP) (02H) ................................................................................................................. 28 7.15. QUAD PAGE PROGRAM (32H)................................................................................................................ 28 7.16. SECTOR ERASE (SE) (20H) .................................................................................................................. 29 7.17. 32KB BLOCK ERASE (BE) (52H) ........................................................................................................... 30 7.18. 64KB BLOCK ERASE (BE) (D8H) .......................................................................................................... 30 7.19. CHIP ERASE (CE) (60/C7H) .................................................................................................................. 31 7.20. DEEP POWER-DOWN (DP) (B9H) .......................................................................................................... 31 7.21. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ............................................... 32 7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) .............................................................................. 33 7.23. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ............................................................................. 33 7.24. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)............................................................................. 34 7.25. READ IDENTIFICATION (RDID) (9FH) ..................................................................................................... 35 7.26. PROGRAM/ERASE SUSPEND (PES) (75H) .............................................................................................. 36 7.27. PROGRAM/ERASE RESUME (PER) (7AH)............................................................................................... 37 7.28. ERASE SECURITY REGISTERS (44H) ...................................................................................................... 37 7.29. PROGRAM SECURITY REGISTERS (42H) ................................................................................................. 38 7.30. READ SECURITY REGISTERS (48H)........................................................................................................ 39 7.31. ENABLE RESET (66H) AND RESET (99H) ............................................................................................... 39 7.32. READ UNIQUE ID (4BH) ........................................................................................................................ 40 2 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 7.33. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ........................................................................ 41 8. ELECTRICAL CHARACTERISTICS ......................................................................................................... 46 8.1. POWER-ON TIMING .......................................................................................................................... 46 8.2. INITIAL DELIVERY STATE................................................................................................................. 46 8.3. ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 46 8.4. CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 47 8.5. DC CHARACTERISTICS .................................................................................................................... 48 8.6. AC CHARACTERISTICS .................................................................................................................... 54 9. ORDERING INFORMATION ...................................................................................................................... 68 9.1. 10. VALID PART NUMBERS .......................................................................................................................... 69 PACKAGE INFORMATION .................................................................................................................... 71 10.1. PACKAGE SOP8 208MIL ...................................................................................................................... 71 10.2. PACKAGE VSOP8 208MIL .................................................................................................................... 72 10.3. PACKAGE DIP8 300MIL ........................................................................................................................ 73 10.4. PACKAGE SOP16 300MIL .................................................................................................................... 74 10.5. PACKAGE WSON8 (6*5MM) .................................................................................................................. 75 10.6. PACKAGE WSON8 (8*6MM) .................................................................................................................. 76 10.7. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY) ....................................................................................... 77 11. REVISION HISTORY.............................................................................................................................. 78 3 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 1. FEATURES ◆ ◆ 128M-bit Serial Flash Fast Program/Erase Speed -16384K-byte -Page Program time: 0.5ms typical -256 bytes per programmable page -Sector Erase time: 50ms typical -Block Erase time: 0.16/0.3s typical ◆ Standard, Dual, Quad SPI -Chip Erase time: 50s typical -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET# ◆ -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 Flexible Architecture -Uniform Sector of 4K-byte -Uniform Block of 32/64K-byte ◆ High Speed Clock Frequency -104MHz for Standard and Dual SPI fast read with 30PF load ◆ ◆ ◆ -Dual I/O Data transfer up to 208Mbits/s -20μA typical standby current -Quad I/O Data transfer up to 416Mbits/s -1μA typical power down current ◆ Software/Hardware Write Protection Advanced Security Features -Write protect all/portion of memory via software -128-bit Unique ID for each device -Enable/Disable protection with WP# Pin -3x1024-Byte Security Registers With OTP Locks -Top/Bottom Block protection -Discoverable parameters (SFDP) register ◆ Allows XIP (execute in place) Operation -Continuous Read With 8/16/32/64-byte Wrap ◆ Low Power Consumption Single Power Supply Voltage -Full voltage range: 2.7~3.6V ◆ Minimum 100,000 Program/Erase Cycles Package Information -SOP8 (208mil) ◆ Data Retention -VSOP8 (208mil) -20-year data retention typical -SOP16 (300mil) -DIP8 (300mil) -WSON8 (8*6mm) -WSON8 (6*5mm) -TFBGA-24 (6*4 ball array) 4 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 2. GENERAL DESCRIPTION The GD25Q127C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 416Mbits/s. CONNECTION DIAGRAM CS# 1 8 VCC SO (IO1) 2 7 WP# (IO2) 3 VSS 4 CS# 1 8 HOLD#/ RESET# (IO3) SO (IO1) 2 HOLD#/ 7 RESET# (IO3) 6 SCLK WP# (IO2) 3 5 SI (IO0) Top View Top View 6 SCLK VSS 4 5 8–LEAD SOP/VSOP/DIP HOLD#/ RESET# (IO3) VCC SI (IO0) 8–LEAD WSON 1 16 SCLK 2 15 SI (IO0) NC 3 14 NC NC 4 13 NC (1) VCC Top View 4 (1) NC VCC WP# HOLD#/ NC (IO2) RESET# (IO3) NC NC VSS NC SI(IO0) NC NC NC SCLK CS# SO(IO1) NC NC NC NC NC NC C D E F 3 Top View 2 NC 5 12 NC NC 6 11 NC CS# 7 10 VSS NC NC SO (IO1) 8 9 WP# (IO2) A B 1 24-BALL TFBGA 16-LEAD SOP Note: (1) Only for special order, Pin 3 of 16-LEAD SOP package or Pin A4 of 24-BALL TFBGA (6x4 ball array) package is RESET# pin. Please contact GigaDevice for detail. (2) CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 5 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C PIN DESCRIPTION Table 1. Pin Description for SOP8 /VSOP8 /DIP8 package Pin No. Pin Name I/O 1 CS# I 2 SO (IO1) I/O Data Output (Data Input Output 1) 3 WP# (IO2) I/O Write Protect Input (Data Input Output 2) 4 VSS 5 SI (IO0) I/O 6 SCLK I 7 HOLD#/RESET# (IO3) I/O 8 VCC Description Chip Select Input Ground Data Input (Data Input Output 0) Serial Clock Input Hold or Reset Input (Data Input Output 3) Power Supply Table 2. Pin Description for WSON8 package Pin No. Pin Name I/O Description 1 CS# I 2 SO (IO1) I/O Data Output (Data Input Output 1) 3 WP# (IO2) I/O Write Protect Input (Data Input Output 2) 4 VSS 5 SI (IO0) I/O 6 SCLK I 7 HOLD#/RESET# (IO3) I/O 8 VCC Chip Select Input Ground Data Input (Data Input Output 0) Serial Clock Input Hold or Reset Input (Data Input Output 3) Power Supply 6 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Table 3. Pin Description for SOP16 package Pin No. Pin Name I/O Description 1 HOLD#/ RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3) 2 VCC 7 CS# I 8 SO (IO1) I/O Data Output (Data Input Output 1) 9 WP# (IO2) I/O Write Protect Input (Data Input Output 2) 10 VSS 15 SI (IO0) I/O 16 SCLK I Power Supply Chip Select Input Ground Data Input (Data Input Output 0) Serial Clock Input Table 4 Pin Description for TFBGA24 4*6package Pin No. Pin Name I/O Description B2 SCLK I B3 VSS Ground B4 VCC Power Supply C2 CS# I C4 WP# (IO2) I/O Write Protect Input (Data Input Output 2) D2 SO (IO1) I/O Data Output (Data Input Output 1) D3 SI (IO0) I/O Data Input (Data Input Output 0) D4 HOLD#/RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3) Serial Clock Input Chip Select Input 7 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C BLOCK DIAGRAM Write Control Logic Status Register HOLD#/ RESET#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 8 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 3. MEMORY ORGANIZATION GD25Q127C Each device has Each block has Each sector has Each page has 16M 64/32K 4K 256 bytes 64K 256/128 16 - pages 4096 16/8 - - sectors 256/512 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q127C 64K Bytes Block Sector Architecture Block 255 254 …… …… 2 1 0 Sector Address range 4095 FFF000H FFFFFFH …… …… …… 4080 FF0000H FF0FFFH 4079 FEF000H FEFFFFH …… …… …… 4064 FE0000H FE0FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 9 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 4. DEVICE OPERATION SPI Mode Standard SPI The GD25Q127C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q127C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q127C supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read”(6BH,EBH,E7H)commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit(QE) in Status Register to be set. Hold The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin. The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure1. Hold Condition CS# SCLK HOLD# HOLD HOLD 10 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Reset The RESET# pin allows the device to be reset by the control. For the WSON8 package, the pin7 can be configured as a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. On the SOP16 package, a dedicated RESET# pin is provided and it is independent of QE bit setting. The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the following states: -Standby mode -All the volatile bits will return to the default status as power on. Figure2. RESET Condition CS# RESET# RESET 11 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 5. DATA PROTECTION The GD25Q127Cprovide the following data protection methods: ◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) ◆ Software Protection Mode: -The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. ◆ Hardware Protection Mode: WP# goes low to protect the writable bit of Status Register. ◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command and reset command (66H+99H). Table 5.1. GD25Q127C Protected area size (CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 to 255 FC0000H-FFFFFFH 256KB Upper 1/64 0 0 0 1 0 248 to 255 F80000H-FFFFFFH 512KB Upper 1/32 0 0 0 1 1 240 to 255 F00000H-FFFFFFH 1MB Upper 1/16 0 0 1 0 0 224 to 255 E00000H-FFFFFFH 2MB Upper 1/8 0 0 1 0 1 192 to 255 C00000H-FFFFFFH 4MB Upper 1/4 0 0 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2 0 1 0 0 1 0 to 3 000000H-03FFFFH 256KB Lower 1/64 0 1 0 1 0 0 to 7 000000H-07FFFFH 512KB Lower 1/32 0 1 0 1 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/16 0 1 1 0 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/8 0 1 1 0 1 0 to 63 000000H-3FFFFFH 4MB Lower 1/4 0 1 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 X X 1 1 1 0 to 255 000000H-FFFFFFH 16MB ALL 1 0 0 0 1 255 FFF000H-FFFFFFH 4KB Top Block 1 0 0 1 0 255 FFE000H-FFFFFFH 8KB Top Block 1 0 0 1 1 255 FFC000H-FFFFFFH 16KB Top Block 1 0 1 0 X 255 FF8000H-FFFFFFH 32KB Top Block 1 0 1 1 0 255 FF8000H-FFFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block 12 3.3V Uniform Sector Dual and Quad Serial Flash 1 1 1 1 0 0 GD25Q127C 000000H-007FFFH 32KB Bottom Block Table 5.2. GD25Q127C Protected area size (CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 0 to 255 000000H-FFFFFFH ALL ALL 0 0 0 0 1 0 to 251 000000H-FBFFFFH 16128KB Lower 63/64 0 0 0 1 0 0 to 247 000000H-F7FFFFH 15872KB Lower 31/32 0 0 0 1 1 0 to 239 000000H-EFFFFFH 15MB Lower 15/16 0 0 1 0 0 0 to 223 000000H-DFFFFFH 14MB Lower 7/8 0 0 1 0 1 0 to 191 000000H-BFFFFFH 12MB Lower 3/4 0 0 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 0 1 0 0 1 4 to 255 040000H-FFFFFFH 16128KB Upper 63/64 0 1 0 1 0 8 to 255 080000H-FFFFFFH 15872KB Upper 31/32 0 1 0 1 1 16 to 255 100000H-FFFFFFH 15MB Upper 15/16 0 1 1 0 0 32 to 255 200000H-FFFFFFH 14MB Upper 7/8 0 1 1 0 1 64 to 255 400000H-FFFFFFH 12MB Upper 3/4 0 1 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 255 000000H-FFEFFFH 16380KB L-4095/4096 1 0 0 1 0 0 to 255 000000H-FFDFFFH 16376KB L-2047/2048 1 0 0 1 1 0 to 255 000000H-FFBFFFH 16368KB L-1023/1024 1 0 1 0 X 0 to 255 000000H-FF7FFFH 16352KB L-511/512 1 0 1 1 0 0 to 255 000000H-FF7FFFH 16352KB L-511/512 1 1 0 0 1 0 to 255 001000H-FFFFFFH 16380KB U-4095/4096 1 1 0 1 0 0 to 255 002000H-FFFFFFH 16376KB U-2047/2048 1 1 0 1 1 0 to 255 004000H-FFFFFFH 16368KB U-1023/1024 1 1 1 0 X 0 to 255 008000H-FFFFFFH 16352KB U-511/512 1 1 1 1 0 0 to 255 008000H-FFFFFFH 16352KB U-511/512 13 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 6. STATUS REGISTER S23 S22 S21 S20 S19 S18 S17 S16 HOLD/RST DRV1 DRV0 Reserved Reserved LPE Reserved Reserved S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 5.1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X 1 1 X Power Supply LockDown(1)(2) One Time Program(2) Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and cannot be written to. WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 14 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 2. This feature is available on special order. (GD25Q127CxxSx)Please contact GigaDevice for details. QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly to the power supply or ground.) LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once they are set to 1, the Security Registers will become read-only permanently. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bits The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H) command as well as a power-down, power-up cycle. DRV1, DRV0 bits The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations. DRV1,DRV0 Driver Strength 00 100% 01 75% 10 50% (default) 11 25% HOLD/RST bit The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O pin. LPE bit The Low Power Enable (LPE) bit is a non-volatile writable bit, indicating the status of Low Power Mode (LPM). When LPE bit sets to 1, it means the device is in Low Power Mode, when LPE bit sets 0 (default), it means the device is not in Low Power Mode. 15 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with most significant bit first on SI, and each bit being latched on the rising edges of SCLK. See Table 7.1., every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table 7.1. Commands (Standard/Dual/Quad SPI) Command Name Byte 1 Write Enable Write Disable Volatile SR Write Enable Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Status Register-1 Write Status Register-2 Write Status Register-3 Read Data Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Quad I/O Word Fast Read(7) Page Program Quad Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase 06H 04H 50H Enable Reset Reset Set Burst with Wrap Byte 2 05H 35H 15H 01H 31H 11H 03H 0BH 3BH (S7-S0) (S15-S8) (S23-S16) S7-S0 S15-S8 S23-S16 A23-A16 A23-A16 A23-A16 BBH A23-A8(2) 6BH A23-A16 EBH A23-A0 M7-M0(4) A23-A0 M7-M0(4) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 E7H 02H 32H 20H 52H D8H C7/60 H 66H 99H 77H Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 M7-M0(2) A15-A8 (D7-D0)(1) dummy(5) (D7-D0)(3) (continuous) dummy(6) (D7-D0)(3) (continuous) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 dummy(9) 16 A7-A0 (D7-D0) dummy dummy (Next byte) (D7-D0) (D7-D0)(1) (continuous) (continuous) (continuous) (continuous) dummy D7-D0 D7-D0 (D7-D0)(3) Next byte (continuous) 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C W7-W0 Program/Erase Suspend Program/Erase Resume Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Deep Power-Down Manufacturer/ Device ID Manufacturer/ Device ID by Dual I/O 75H 7AH ABH dummy dummy (DID7DID0) dummy dummy 00H (MID7MID0) A23-A8 A7-A0, M7-M0 (MID7MID0) (DID7DID0) (continuous) ABH B9H 90H 92H Manufacturer/ Device ID by Quad I/O 94H Read Identification dummy A23-A0, M7-M0 (DID7DID0) (continuous) dummy (10)(MID7MID0) (DID7DID0) (JDID15JDID8) A15-A8 (JDID7JDID0) A7-A0 dummy (D7-D0) (continuous) dummy (UID7UID0) (continuous) (continuous) Read Serial Flash Discoverable Parameter Read Unique ID 5AH (MID7MID0) A23-A16 4BH dummy dummy dummy Erase Security Registers(8) Program Security Registers(8) Read Security Registers(8) 44H A23-A16 A15-A8 A7-A0 42H A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0) 9FH (continuous) NOTE: 1. Dual Output data IO0=(D6,D4,D2,D0) IO1=(D7,D5,D3,D1) 2. Dual Input Address IO0=A22,A20,A18,A16,A14,A12,A10,A8 A6,A4,A2,A0,M6,M4,M2,M0 IO1=A23,A21,A19,A17,A15,A13,A11,A9 A7,A5,A3,A1,M7,M5,M3,M1 3. Quad Output Data IO0=(D4,D0,…..) IO1=(D5,D1,…..) IO2=(D6,D2,…..) IO3=(D7,D3,…..) 4. Quad Input Address IO0=A20,A16,A12,A8, A4,A0,M4,M0 IO1=A21,A17,A13,A9, A5,A1,M5,M1 (continuous) IO2=A22,A18,A14,A10,A6,A2,M6,M2 IO3=A23,A19,A15,A11,A7,A3,M7,M3 5. Fast Read Quad I/O Data 17 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C IO0=(x,x,x,x, D4, D0,…) IO1=(x,x,x,x, D5, D1,…) IO2=(x,x,x,x, D6, D2,…) IO3=(x,x,x,x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0=(x,x, D4, D0,…) IO1=(x,x, D5, D1,…) IO2=(x,x, D6, D2,…) IO3=(x,x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. 8. Security Registers Address: Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address; Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address; Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address. 9. Dummy bits and Wrap Bits IO0=(x,x, x,x, x,x, W4,x) IO1=(x,x, x,x, x,x, W5, x) IO2=(x,x, x,x, x,x, W6, x) IO3=(x,x, x,x, x,x, x, x) 10.Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID IO0=(A20, A16, A12, A8, A4, A0, M4, M0, x,x, x,x, MID4, MID0, DID4, DID0, …) IO1=(A21, A17, A13, A9, A5, A1, M5, M1, x,x, x,x, MID5, MID1, DID5, DID1, …) IO2=(A22, A18, A14, A10, A6, A2, M6, M2,x,x, x,x, MID6, MID2, DID6, DID2, …) IO3=(A23, A19, A15, A11, A7, A3, M7, M3, x,x, x,x, MID7, MID3, DID7, DID3, …) Table 7.2. Table of ID Definitions for GD25Q127C Operation Code MID7-MID0 ID15-ID8 ID7-ID0 9FH C8 40 18 90H/92H/94H C8 17 ABH 17 18 3.3V Uniform Sector Dual and Quad Serial Flash 7.1. GD25Q127C Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high. Figure3. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes lowSending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Powerup and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure4. Write Disable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 04H High-Z 7.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command, and any other commands cannot be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. 19 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure5. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”/ “35H” / “15H”, the SO will output Status Register bits S7~S0/ S15-S8 / S23-S16. Figure6. Read Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 Register0/1/2 6 5 4 3 2 1 Command SI 05H or 35H or 15H SO High-Z MSB 7.5. Register0/1/2 0 7 6 5 4 3 2 1 0 7 MSB Write Status Register (WRSR) (01H or 31H or 11H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the 20 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Hardware Protected Mode is entered. Figure7. Write Status Register Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 Command SI 9 10 11 12 13 14 15 Status Register in 7 01H/31H/11H 6 MSB SO 5 4 3 2 1 0 High-Z 7.6. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. Then the memory content at that address is shifted out on SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure8. Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI SO 03H High-Z 24-bit address 23 22 21 3 2 1 0 MSB MSB 21 7 6 5 Data Out1 4 3 2 1 Data Out2 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.7. GD25Q127C Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 0BH 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 7.8. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure10. Dual Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24-bit address 3BH 23 22 21 3 2 1 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI SO 6 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 MSB MSB 7 22 4 2 0 6 4 2 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 7.9. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure11. Quad Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI(IO0) 24-bit address 6BH 23 22 21 SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z 3 2 1 0 CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks 7.10. SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. 23 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure12. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0)) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) BBH SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 5 3 1 A7-0 6 4 7 5 M7-4 Dummy CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 5 3 1 7 5 3 1 7 5 3 1 7 5 7 A23-16 A15-8 A7-0 M7-4 Dummy CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 7.11. Byte2 Byte3 Byte4 Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock4-bit per clock by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. 24 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure13. Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) EBH A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 8 9 10 11 12 13 14 15 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache 25 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.12. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure14a.If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0)) CS# 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 1 2 3 4 5 6 7 Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Figure14a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0)) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 8 9 10 11 12 13 14 15 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 26 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.13. Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page. The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24 dummy bits  Send 8 bits “Wrap bits”  CS# goes high. W6,W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 Yes 8-byte No N/A 0, 1 Yes 16-byte No N/A 1, 0 Yes 32-byte No N/A 1, 1 Yes 64-byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. Figure15. Set Burst with Wrap Sequence Diagram CS# 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK 0 1 2 3 4 5 6 7 Command SI(IO0) 77H W6-W4 27 3.3V Uniform Sector Dual and Quad Serial Flash 7.14. GD25Q127C Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1 byte data on SI CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure16. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-bit address 23 22 21 3 2 Data Byte 1 1 0 7 MSB 6 5 4 3 2 1 0 2078 2079 6 2077 7 2076 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 2075 02H 2074 SI 1 0 SCLK Data Byte 2 SI 7 6 5 4 3 2 MSB 7.15. Data Byte 3 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 5 4 3 2 MSB Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1).A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on 28 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure17.Quad Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI(IO0) 24-bit address 32H 23 22 21 3 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 538 539 540 541 542 543 1 537 2 Byte1 Byte2 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 536 CS# SCLK Byte11Byte12 Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7.16. 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 Sector Erase (SE) (20H) The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the 29 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not executed. Figure18. Sector Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 Command SI 9 29 30 31 24 Bits Address 20H 7.17. 7 23 22 MSB 2 1 0 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed. Figure19. 32KB Block Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 Command 52H 7.18. 7 8 9 29 30 31 24 Bits Address 23 22 MSB 2 1 0 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is 30 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed. Figure20. 64KB Block Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 9 Command SI 29 30 31 24 Bits Address D8H 7.19. 7 23 22 MSB 2 1 0 Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are protected Figure21. Chip Erase Sequence Diagram CS# SCLK 0 1 SI 7.20. 2 3 4 5 6 7 Command 60H or C7H Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands can release the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command releases 31 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C the device from deep power down mode , also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after PowerUp. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure22. Deep Power-Down Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 7.21. tDP Stand-by mode Deep Power-down mode B9H Release from Deep Power-Down and Read Device ID (RDI) (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown below. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown below. The Device ID value is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure23. Release Power-Down Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 t RES1 Command ABH Deep Power-down mode 32 Stand-by mode 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure24. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 SCLK Command SI SO t RES2 3 Dummy Bytes 23 22 ABH 2 1 0 MSB High-Z 7 Device ID 5 4 3 2 6 MSB 7.22. 1 0 Deep Power-down Mode Stand-by Mode Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure25. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 23 22 21 3 2 1 0 High-Z SO CS# 24-bit address 90H 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO 7 MSB 7.23. 6 Manufacturer ID 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 1 0 MSB Read Manufacture ID/ Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be 33 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C read first. Figure26. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) 92H SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 MFR ID 7.24. Device ID MFR ID (Repeat) Device ID (Repeat) MFR ID (Repeat) Device ID (Repeat) Read Manufacture ID/ Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device ID will be read first. 34 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure27. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 SCLK Command SI(IO0) 94H A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID CS# 24 25 26 27 28 29 30 31 SCLK SI(IO0) 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 7.25. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. 35 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure28. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 SCLK SI 9FH Command SO Manufacturer ID 5 4 3 2 1 0 MSB CS# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI SO 7 6 MSB 7.26. 5 4 3 2 1 Memory Type JDID15-JDID8 0 7 6 MSB 5 4 3 2 Capacity JDID7-JDID0 1 0 Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H, 32H) are not allowed during Program suspend. The Write Status Register command (01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29. Figure29. Program/Erase Suspend Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 tSUS Command 75H High-Z Accept read command 36 3.3V Uniform Sector Dual and Quad Serial Flash 7.27. GD25Q127C Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure30. Figure30. Program/Erase Resume Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 Command SI 7AH SO 7.28. Resume Erase/Program Erase Security Registers (44H) The GD25Q127C provides three 1024-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-10 00 00 00 Figure31. Erase Security Registers command Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 44H 8 9 29 30 31 24 Bits Address 23 22 MSB 37 2 1 0 A9-0 Don’t care Don’t care Don’t care 3.3V Uniform Sector Dual and Quad Serial Flash 7.29. GD25Q127C Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-10 00 00 00 A9-0 Byte Address Byte Address Byte Address Figure32. Program Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-bit address 23 22 21 3 2 1 0 7 MSB 6 5 4 3 2 1 2078 2079 2077 2075 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2076 CS# 2072 MSB 2073 42H Data Byte 1 2074 SI 1 0 SCLK Data Byte 2 SI 7 MSB 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 7 MSB 38 6 5 4 3 2 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.30. GD25Q127C Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-10 00 00 00 A9-0 Byte Address Byte Address Byte Address Figure33. Read Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 SO 0 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Figure38. The Global Block/Sector Unlock Sequence Diagram CS# SCLK SI SO 7.31. 0 1 2 3 4 5 6 7 Command 98H High-Z Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI mode. The “Reset (99H)” 39 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure39. Enable Reset and Reset command Sequence Diagram CS# 0 SCLK SI 1 2 3 4 5 6 7 0 2 3 4 5 Command Command 66H 99H 6 7 High-Z SO 7.32. 1 Read Unique ID (4BH) The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command Dummy Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4128bit Unique ID Out CS# goes high. Figure40 Read Unique ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 4-Byte Dummy 4BH 7 6 High-Z SO CS# 40 41 42 43 44 45 46 47 SCLK SI SO 7 MSB Data Out1 6 5 4 3 2 1 Data Out2 0 7 6 5 MSB 40 5 3 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 7.33. Read Serial Flash Discoverable Parameter (5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. Figure41. Read Serial Flash Discoverable Parameter command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 5AH 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 41 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Table 7.3. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed:50444653H Add(H) DW Add Data Data (Byte) (Bit) 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H 06H 23:16 01H 01H Unused Contains 0xFFH and can never be 07H 31:24 FFH FFH 08H 07:00 00H 00H Start from 0x00H 09H 15:08 00H 00H Start from 0x01H 0AH 23:16 01H 01H Parameter Table Length How many DWORDs in the 0BH 31:24 09H 09H (in double word) Parameter table Parameter Table Pointer (PTP) First address of JEDEC Flash 0CH 07:00 30H 30H Parameter table 0DH 15:08 00H 00H 0EH 23:16 00H 00H 0FH 31:24 FFH FFH 10H 07:00 C8H C8H changed ID number (JEDEC) 00H: It indicates a JEDEC specified header Parameter Table Minor Revision Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed ID Number It is indicates GigaDevice (GigaDevice Manufacturer ID) manufacturer ID Parameter Table Minor Revision Start from 0x00H 11H 15:08 00H 00H Start from 0x01H 12H 23:16 01H 01H Parameter Table Length How many DWORDs in the 13H 31:24 03H 03H (in double word) Parameter table Parameter Table Pointer (PTP) First address of GigaDevice Flash 14H 07:00 60H 60H Parameter table 15H 15:08 00H 00H 16H 23:16 00H 00H 17H 31:24 FFH FFH Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed 42 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Table 7.4. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) Data Data 00: Reserved; 01: 4KB erase; Block/Sector Erase Size 10: Reserved; 01:00 01b 02 1b 03 0b 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction 0: Nonvolatile status bit Requested for Writing to Volatile 1: Volatile status bit Status Registers (BP status register bit) 30H E5H 0: Use 50H Opcode, Write Enable Opcode Select for 1: Use 06H Opcode, Writing to Volatile Status Note: If target flash status register is Registers Nonvolatile, then bits 3 and 4 must 04 0b 07:05 111b 15:08 20H 16 1b 18:17 00b 19 0b be set to 00b. Unused Contains 111b and can never be changed 4KB Erase Opcode 31H (1-1-2) Fast Read 0=Not support, 1=Support Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte, addressing flash array 10: 4Byte only, 11: Reserved Double Transfer Rate (DTR) clocking 0=Not support, 1=Support 32H F1H (1-2-2) Fast Read 0=Not support, 1=Support 20 1b (1-4-4) Fast Read 0=Not support, 1=Support 21 1b (1-1-4) Fast Read 0=Not support, 1=Support 22 1b 23 1b 33H 31:24 FFH 37H:34H 31:00 Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-4-4) Fast Read Number of Mode Bits 39H (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support Mode Bits 00100b 44H 07:05 010b 15:08 EBH 20:16 01000b 3AH 000b:Mode Bits not support (1-1-4) Fast Read Opcode 3BH 43 FFH 07FFFFFFH 38H (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of 04:00 000b:Mode Bits not support 20H EBH 08H 23:21 000b 31:24 6BH 6BH 3.3V Uniform Sector Dual and Quad Serial Flash Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of Mode Bits (Byte) (Bit) 04:00 3DH 0 0000b: Wait states (Dummy of Wait states Clocks) not support 000b: Mode Bits not support 3FH 0=not support Data 1=support Unused 08H 07:05 000b 15:08 3BH 20:16 00010b 0=not support 1=support Unused 3BH 42H 23:21 010b 31:24 BBH 00 0b 03:01 111b 04 0b 07:05 111b 40H (4-4-4) Fast Read Data 01000b 3EH (1-2-2) Fast Read Opcode (2-2-2) Fast Read DW Add 000b: Mode Bits not support (1-2-2) Fast Read Number of Mode Bits Add(H) 3CH (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number GD25Q127C BBH EEH Unused 43H:41H 31:08 0xFFH 0xFFH Unused 45H:44H 15:00 0xFFH 0xFFH 20:16 00000b (2-2-2) Fast Read Number 0 0000b: Wait states (Dummy of Wait states Clocks) not support (2-2-2) Fast Read Number of Mode Bits 46H 000b: Mode Bits not support (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of Mode Bits Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 3 erase Opcode Sector Type 4 Size 000b 47H 31:24 FFH FFH 49H:48H 15:00 0xFFH 0xFFH 20:16 00000b 000b: Mode Bits not support Sector Type 1 erase Opcode Sector Type 2 Size 23:21 4AH (4-4-4) Fast Read Opcode Sector Type 1 Size 00H Sector/block size=2^N bytes 0x00b: this sector type don’t exist Sector Type 4 erase Opcode 44 00H 23:21 000b 4BH 31:24 EBH EBH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Table 7.5. Parameter Table (1): GigaDevice Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) 61H:60H 63H:62H Data Data 15:00 3600H 3600H 31:16 2700H 2700H 2000H=2.000V Vcc Supply Maximum Voltage 2700H=2.700V 3600H=3.600V 1650H=1.650V Vcc Supply Minimum Voltage 2250H=2.250V 2350H=2.350V 2700H=2.700V HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable(66H) before Reset cmd. 65H:64H 11:04 1001 1001b (99H) F99FH Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 66H 23:16 77H 77H 67H 31:24 64H 64H 00 0b 01 0b 09:02 FFH Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 08H:support 8B wrap-around read Wrap-Around Read data length 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B Individual block lock Individual block lock bit (Volatile/Nonvolatile) 0=not support 0=Volatile 1=support 1=Nonvolatile Individual block lock Opcode Individual block lock Volatile protect bit default protect status CBFC/ 0=protect 1=unprotect 10 0b 6BH:68H Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b/1b(1) Unused 15:14 11b Unused 31:16 FFFFH NOTE: (1) GD25Q127CxxSx support Permanent Lock. Please contact GigaDevice for details. 45 EBFCH (1) FFFFH 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure 42. Power-on Timing Sequence Diagram Vcc(max) Chip Selection is not allowed Vcc(min) tVSL Device is fully accessible VWI Time Table 8.1. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min tVSL VCC (min) To CS# Low 2.5 VWI Write Inhibit Voltage 1.5 Max Unit ms 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register bits are set to 0, except DRV1 bit (S22) is set to 1. 8.3. ABSOLUTE MAXIMUM RATINGS Parameter Value Ambient Operating Temperature Unit -40 to 85 -40 to 105 ℃ -40 to 125 ℃ Storage Temperature -65 to 150 Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V VCC -0.6 to 4.2 V 46 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C Figure 43. Maximum Negative/positive Overshoot Diagram Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns 8.4. CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ. Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 pF Input Rise And Fall time 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure44. Input Test Waveform and Measurement Level Input timing reference level 0.8VCC 0.7VCC 0.1VCC 0.2VCC Output timing reference level AC Measurement Level Note: Input pulse rise and fall time are