STK12C68-PF55

STK12C68 STK12C68-M SMD#5962-94599 8K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • 25ns, 35ns, 45ns and 55ns Access Times • “Hands-off” Automatic STORE with External 68µF Capacitor on Power Down • STORE to Nonvolatile Elements Initiated by Hardware, Software or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Elements (Commercial/Industrial) • 100-Year Data Retention in Nonvolatile Elements (Commercial/Industrial) • Commercial, Industrial and Military Temperatures • 28-Pin SOIC, DIP and LCC Packages The Simtek STK12C68 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down. A 68µF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from “hot swapping”. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be software controlled by entering specific read sequences. A hardware STORE may be initiated with the HSB pin. BLOCK DIAGRAM PIN CONFIGURATIONS VCCX QUANTUM TRAP 128 x 512 VCAP VCAP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS POWER CONTROL A6 A7 A8 A9 A11 ROW DECODER A5 STORE STATIC RAM ARRAY 128 x 512 RECALL HSB 28 - LCC A12 SOFTWARE DETECT INPUT BUFFERS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE/ RECALL CONTROL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 G E W October 2003 1 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCCX W HSB A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - DIP 28 - SOIC A0 - A12 PIN NAMES A0 - A12 Address Inputs DQ0 -DQ7 Data In/Out E Chip Enable W Write Enable G Output Enable HSB Hardware Store Busy (I/O) VCCX Power (+ 5V) VCAP Capacitor VSS Ground Document Control # ML0008 rev 0.4 STK12C68 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (VCC = 5.0V ± 10%)e DC CHARACTERISTICS SYMBOL INDUSTRIAL/ MILITARY COMMERCIAL PARAMETER MIN MAX MIN UNITS NOTES MAX ICC b Average VCC Current 85 75 65 55 90 75 65 55 mA mA mA mA ICC c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max ICC b Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels Average VCAP Current during AutoStore™ Cycle 2 2 mA 27 23 20 19 28 24 21 19 mA mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH tAVAV = 55ns, E ≥ VIH 1.5 2.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) ±1 ±1 µA VCC = max VIN = VSS to VCC ±5 ±5 µA VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs 1 2 3 ICC c 4 tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns All Inputs Don’t Care ISB d Average VCC Current (Standby, Cycling TTL Input Levels) ISB d VCC Standby Current (Standby, Stable CMOS Input Levels) IILK Input Leakage Current IOLK Off-State Output Leakage Current VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA except HSB VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 8mA except HSB VBL Logic “0” Voltage on HSB Output 0.4 0.4 V IOUT = 3mA TA Operating Temperature 85/125 °C 1 2 Note b: Note c: Note d: Note e: 2.4 0 2.4 70 –40/-55 ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. AC TEST CONDITIONS 5.0V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEf SYMBOL OUTPUT (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V Note f: 480 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading These parameters are guaranteed but not tested. October 2003 255 Ohms 2 Document Control # ML0008 rev 0.4 STK12C68 (VCC = 5.0V ± 10%)e SRAM READ CYCLES #1 & #2 NO. SYMBOLS #1, #2 Alt. PARAMETER STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55 MIN MIN MIN MIN MAX 25 MAX MAX tELQV tACS Chip Enable Access Time 2 tAVAVg tRC Read Cycle Time 3 tAVQVh tAA Address Access Time 25 35 45 55 ns 4 tGLQV tOE Output Enable to Data Valid 10 15 20 35 ns 5 tAXQXh tOH Output Hold after Address Change 5 5 5 5 6 tELQX tLZ Chip Enable to Output Active 5 5 5 5 7 tEHQZi tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZi tOHZ Output Disable to Output Inactive 10 tELICCHf tPA Chip Enable to Power Active 11 tEHICCLf tPS Chip Disable to Power Standby 35 10 0 0 55 12 0 12 0 ns ns 12 ns 12 ns ns 0 35 45 ns ns 0 10 0 25 55 45 10 10 0 45 UNITS 1 25 35 MAX ns 55 ns Note g: W and HSB must be high during SRAM READ cycles. Note h: Device is continuously selected with E and G both low. Note i: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledg, h 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledg 2 tAVAV ADDRESS 1 11 tELQV tEHICCL 6 tELQX E 7 tEHQZ G 9 tGHQZ 4 8 tGLQX tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ICC October 2003 ACTIVE STANDBY 3 Document Control # ML0008 rev 0.4 STK12C68 (VCC = 5.0V ± 10%)e SRAM WRITE CYCLES #1 & #2 NO. SYMBOLS STK12C68-25 PARAMETER MIN MAX STK12C68-35 MIN MIN MAX STK12C68-55 Alt. 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 25 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 0 ns 20 tWLQZ i, j tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 13 5 5 MIN 14 5 MAX UNITS #2 10 MAX STK12C68-45 #1 15 5 ns ns Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles. SRAM WRITE CYCLE #1: W Controlledk, l 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX SRAM WRITE CYCLE #2: E Controlledk, l 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT October 2003 16 tEHDX DATA VALID HIGH IMPEDANCE 4 Document Control # ML0008 rev 0.4 STK12C68 HARDWARE MODE SELECTION E W HSB A12 - A0 (hex) MODE I/O POWER H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z lCC H 0000 1555 0AAA 1FFF 10F0 0F0F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z H 0000 1555 0AAA 1FFF 10F0 0F0E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z L H L H NOTES o m 2 Active lCC n, o 2 n, o Active Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. (VCC = 5.0V ± 10%)e HARDWARE STORE CYCLE NO. SYMBOLS Standard Alternate STK12C68 PARAMETER 22 tSTORE tHLHZ STORE Cycle Duration 23 tDELAY tHLQZ Time Allowed to Complete SRAM Cycle 24 tRECOVER tHHQX Hardware STORE High to Inhibit Off 25 tHLHX Hardware STORE Pulse Width 26 tHLBL Hardware STORE Low to Store Busy MIN MAX 10 UNITS NOTES ms i, p µs i, q 700 ns p, r 300 ns 1 15 ns Note p: E and G low for output behavior. Note q: E and G low and W high for output behavior. Note r: tRECOVER is only applicable after tSTORE is complete. HARDWARE STORE CYCLE 25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE HSB (OUT) 26 tHLBL HIGH IMPEDANCE HIGH IMPEDANCE 23 tDELAY DQ (DATA OUT) October 2003 DATA VALID DATA VALID 5 Document Control # ML0008 rev 0.4 STK12C68 (VCC = 5.0V ± 10%)e AutoStore™/POWER-UP RECALL NO. SYMBOLS Standard MIN UNITS NOTES 550 µs s STORE Cycle Duration 10 ms p, q, t tRESTORE 28 tSTORE 29 tVSBL 30 tDELAY 31 VSWITCH Low Voltage Trigger Level 32 VRESET Low Voltage Reset Level Low Voltage Trigger (VSWITCH) to HSB Low tBLQZ MAX Power-up RECALL Duration 27 tHLHZ STK12C68 PARAMETER Alternate Time Allowed to Complete SRAM Cycle 300 1 4.0 ns l µs p 4.5 V 3.9 V Note s: tRESTORE starts from the time VCC rises above VSWITCH. Note t: HSB is asserted low for 1µs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no STORE will take place. AutoStore™/POWER-UP RECALL VCC 31 VSWITCH 32 VRESET AutoStoreTM POWER-UP RECALL 29 tVSBL 27 tRESTORE 28 tSTORE HSB 30 tDELAY W DQ (DATA OUT) POWER-UP RECALL October 2003 BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT AutoStore™ BROWN OUT AutoStore™ NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 6 Document Control # ML0008 rev 0.4 STK12C68 SOFTWARE-CONTROLLED STORE/RECALL CYCLEv NO. SYMBOLS PARAMETER STK12C68-25 MIN MAX (VCC = 5.0V ± 10%)e STK12C68-35 MIN MAX STK12C68-45 MAX Alternate 33 tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 55 ns p 34 tAVEL tAS Address Set-up Time 0 0 0 0 ns u 35 tELEH tCW Clock Pulse Width 20 25 30 30 ns u 36 tELAX Address Hold Time 20 ns u 37 tRECALL RECALL Duration 20 20 MIN MAX UNITS NOTES Standard 20 MIN STK12C68-55 20 20 20 20 µs Note u: The software sequence is clocked with E controlled READs. Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledv 33 33 tAVAV ADDRESS tAVAV ADDRESS #1 34 tAVEL ADDRESS #6 35 tELEH E 36 tELAX 28 tSTORE DQ (DATA OUT) October 2003 DATA VALID DATA VALID 7 37 / tRECALL HIGH IMPEDANCE Document Control # ML0008 rev 0.4 STK12C68 DEVICE OPERATION POWER-UP RECALL The STK12C68 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to Nonvolatile Elements (the STORE operation) or from Nonvolatile Elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled. During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request will be latched. When VCAP once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK12C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. NOISE CONSIDERATIONS The STK12C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SOFTWARE NONVOLATILE STORE The STK12C68 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. SRAM READ The STK12C68 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. October 2003 Read address Read address Read address Read address Read address Read address 8 Document Control # ML0008 rev 0.4 STK12C68 SOFTWARE NONVOLATILE RECALL Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 68µF and 220µF (± 20%) rated at 6V should be provided. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle If an automatic STORE on power loss is not required, then VCCX can be tied to ground and + 5V applied to VCAP (Figure 4). This is the AutoStore™ Inhibit mode, in which the AutoStore™ function is disabled. If the STK12C68 is operated in this configuration, references to VCCX should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered through software control or the HSB pin. It is not permissable to change between these three options “on the fly”. Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. AutoStore™ OPERATION In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. This can be used to signal the system that the AutoStore™ cycle is in progress. 1 28 10kΩ 10kΩ∗ 10kΩ During normal AutoStore™ operation, the STK12C68 will draw current from VCCX to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation. 1 28 27 10kΩ The STK12C68 can be powered in one of three modes. 1 28 27 27 26 26 10kΩ∗ 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) 0.1µF Bypass Read address Read address Read address Read address Read address Read address 10kΩ∗ 1. 2. 3. 4. 5. 6. In system power mode (Figure 3), both VCCX and VCAP are connected to the + 5V power supply without the 68µF capacitor. In this mode the AutoStore™ function of the STK12C68 will operate on the stored system charge as power goes down. The user must, however, guarantee that VCCX does not drop below 3.6V during the 10ms STORE cycle. 0.1µF Bypass + 0.1µF Bypass 68µF 6v, ±20% 26 15 14 14 14 15 15 Figure 2: AutoStore™ Mode Figure 3: System Power Mode Figure 4: AutoStore™ Inhibit Mode *If HSB is not used, it should be left unconnected. October 2003 9 Document Control # ML0008 rev 0.4 STK12C68 HSB OPERATION PREVENTING STORES The STK12C68 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK12C68 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20µs at the onset of a STORE. When the STK12C68 is connected for AutoStore™ operation (system VCC connected to VCCX and a 68µF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68 will attempt to pull HSB low; if HSB doesn’t actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK12C68 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. HARDWARE PROTECT The STK12C68 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore™ can be completely disabled by tying VCCX to ground and applying + 5V to VCAP . This is the AutoStore™ Inhibit mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin. The HSB pin can be used to synchronize multiple STK12C68s while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other STK12C68s. An external pull-up resistor to + 5V is required since HSB acts as an open drain pull down. The VCAP pins from the other STK12C68 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK12C68s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK12C68s that have been written since the last nonvolatile cycle). LOW AVERAGE ACTIVE POWER The STK12C68 draws significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 6 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK12C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. During any STORE operation, regardless of how it was initiated, the STK12C68 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK12C68 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. October 2003 10 Document Control # ML0008 rev 0.4 100 100 80 80 Average Active Current (mA) Average Active Current (mA) STK12C68 60 40 TTL 20 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 200 50 Figure 5: Icc (max) Reads October 2003 100 150 Cycle Time (ns) 200 Figure 6: Icc (max) Writes 11 Document Control # ML0008 rev 0.4 STK12C68 ORDERING INFORMATION STK12C68 - 5 P F 45 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) M = Military (–55 to 125°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns 55 = 55ns Lead Finish (Plastic only) Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin) Package P = Plastic 28-pin 300 mil DIP W= Plastic 28-pin 600 mil DIP S = Plastic 28-pin 350 mil SOIC C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC Retention / Endurance Blank = Comm/Ind (100 years/106cycles) 5962-94599 01 MX X 5 = Military (10 years/105cycles) Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Access Time 01 = 55ns 02 = 45ns 03 = 35ns October 2003 12 Document Control # ML0008 rev 0.4 STK12C68 Document Revision History Revision Date Summary 0.0 December 2002 Combined commercial, industrial and military datasheets. Removed 20 nsec device. 0.1 January 2003 Added 35 nsec SMD to order information 0.2 July 2003 Added “28 - SOIC” label to page 1 pinout drawing 0.3 September 2003 Added lead-free lead finish 0.4 October 2003 Restored “W” 600 mil DIP package to ordering information October 2003 13 Document Control # ML0008 rev 0.4