ASNT2140-KMA

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT2140-KMA DC-to-32Gbps Programmable DDR Demultiplexer 1:16 / Deserializer Programmable digital deserializer 1-to-16 Supports data rates from DC to 32Gb/s in DDR clocking mode CML input data buffer CML input sampling clock buffer 16-bit parallel LVDS output data interface LVDS output forwarded clock-divided-by-16 with a selectable phase Divider external reset for synchronization of multiple devices Single +3.3V power supply Industrial temperature range Power consumption of 1350mW at maximum speed Custom 100-pin CQFP package (13mm x 13mm) vee 75 nc 74 q04n 73 q04p 72 vcc 71 q03n 70 q03p 69 vcc 68 q02n 67 q02p 66 vcc 65 q01n 64 q01p 63 vcc 62 q00n 61 q00p 60 nc 59 vee 58 phs1 57 phs2 56 vcc 55 nc 54 nc 53 vee 52 vee 51            Rev. 1.6.2 ASNT 2140 vee 50 nc 49 nc 48 nc 47 rstp 46 rstn 45 vcc 44 nc 43 nc 42 vcc 41 dp 40 dn 39 vcc 38 cdcadj 37 vee 36 vcc 35 nc 34 nc 33 vcc 32 vtrm 31 vtrm 30 vcc 29 c2p 28 c2n 27 vcc 26 1 vee 2 nc 3 q13p 4 q13n 5 vcc 6 q14p 7 q14n 8 vcc 9 q15p 10 q15n 11 vcc 12 clop 13 clon 14 vcc 15 vee 16 bitorder 17 vee 18 nc 19 nc 20 nc 21 nc 22cdccn 23 vee 24 cdccp 25 vcc 76 vcc 77 q05p 78 q05n 79 vcc 80 q06p 81 q06n 82 vcc 83 q07p 84 q07n 85 vcc 86 q08p 87 q08n 88 vcc 89 q09p 90 q09n 91 vcc 92 q10p 93 q10n 94 vcc 95 q11p 96 q11n 97 vcc 98 q12p 99 q12n 100 vcc 1 August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION bitorder q00p/q00n dp/dn Data IB DMX 1:16 LVDS DOB x16 16 vtrm cdccp cdccn cdcadj c2p/c2n rstp/rstn q15p/q15n C16 HS CIB C2 /8 LVDS COB clop/clon CLK Proc phs1 phs2 Fig. 1. Functional Block Diagram ASNT2140-KMA is a high-speed DDR (dual data rate) digital 1-to-16 demultiplexer (DMX) / deserializer. The IC shown in Fig. 1 functions seamlessly over the specified range of data rates (fbit). The main function of the IC is to demultiplex a high-speed serial bit stream running at fbit into 16 parallel data channels running at a bit rate of fbit/16. It accepts a high-speed data transmitted over a controlled impedance media of 50Ohm. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degree of noise coupling to the signaling environment. During normal operation, the deserializer’s CML data input buffer (Data IB) accepts a HS serial input data signal dp/dn and delivers it to the demultiplexer’s core (DMX1:16) for deserialization. A half-rate CML sampling clock (a full-rate clock divided by 2) must be provided by an external source to the inputs c2p/c2n of the high-speed clock input buffer (HS CIB) where it is routed to the internal divider-by-8 (/8). The high-speed CML data and clock input buffers provide on-chip 50Ohm termination and are designed to be driven by devices with 50Ohm source impedance. The duty cycle of the internal clock c2 can be adjusted either through a single ended control pin cdcadj or through a dual control port cdccp/cdccn. The clock input buffer uses a separate positive supply vtrm for additional common mode voltage adjustment. The divider provides signaling for DMX1:16 and produces a divided-by-16 full-rate forwarded clock C16 for the low-speed LVDS-compliant clock output buffer (LVDS COB). The divider can be preset to a certain initial state using external CML signals rstp/rstn. The phase of the low-speed forwarded clock clop/clon can be modified in 90° increments by utilizing pins phs1 and phs2 and the clock processing block (CLK Proc). The deserialized digital words are delivered to the output parallel interface through 16 LVDS-compliant data output buffers LVDS DOBx16. By utilizing the pin bitorder, the deserializer can designate either q00p/q00n or q15p/q15n as the MSB (most significant bit that is delivered first to the serial interface), thus simplifying the interface between the demultiplexer and a following ASIC. The chip uses a single +3.3V power supply and is characterized for junction temperature from −25°C to 125°C. Rev. 1.6.2 August 2020 2 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Data IB The Data Input Buffer (Data IB) can accept high-speed serial data signals at its differential CML input port dp/dn. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS DIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended 50Ohm termination to vcc for each input line. HS CIB The High-Speed Clock Input Buffer (HS CIB) can accept high-speed clock signals at its differential CML input port c2p/c2n. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended 50Ohm termination to vtrm for each input line. This termination voltage can be adjusted within the range from vcc to vcc-0.8V. The buffer provides two options for adjustment of the output signal duty cycle. The duty cycle can be adjusted by changing two control voltages cdccp and cdccn that affect the input signals c2p and c2n respectively. It can also be adjusted using one control voltage cdcadj following the diagram shown in Fig. 2. Here red lines correspond to the dp input, blue lines correspond to the dn input, solid lines represent typical conditions while dotted and dashed lines represent slow and fast conditions respectively. Fig. 2. Duty Cycle Control Diagram It should be noted that only one control option should be activated at a certain time. Either cdccp/cdccn or cdcadj pins should be left not connected or AC-terminated with 50Ohm loads. Otherwise, the two internal control circuits interact and the desired result cannot be achieved. /8 The Divider-by-8 (/8) includes three divide-by-2 circuits connected in series. The half-speed clock C2 is routed internally to the first divide-by-2 circuit and outside of the block to MUX16:1 as a sampling clock. Other divided down clock signals are formed and routed to MUX16:1 in a similar fashion. C16 is passed on to LVDS COB to become the output low-speed forwarded clock signal clop/clon. The divider can be preset to a “0” state using external differential CML signals rstp/rstn that have on-chip 50Ohm termination to vcc. The reset circuitry can operate at high speed and features internal retiming by the Rev. 1.6.2 August 2020 3 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com falling edge of half-rate clock. The desired phase relation between the reset signal and the sampling input clock c2p/c2n is illustrated by Fig. 3. tremoval Input c2p trecovery Input rstp Fig. 3. Reset Timing Diagram Recovery (trecovery) and removal (tremoval) times depend on the input reset signal slew rate, the process corner, and the die temperature. Maximum required values are tremoval = 33ps and trecovery = -18ps. DMX1:16 The 1-to-16 demultiplexer (DMX1:16) utilizes the tree-type architecture and latches in the data stream from Data IB on both edges of the half-rate clock signal that is supplied by the divider /8. The high speed data signal is subsequently demultiplexed down and delivered to LVDS data output buffers (LVDS DOBx16) as16-bit wide parallel words. CLK Proc By utilizing the 3.3V CMOS control pins phs1 and phs2, the phase of the main low-speed forwarded clock output signal clop/clon can be selected in accordance with the table below. Table 1. Clock Phase Selection phs1 phs2 C16 phase vee (default) vee (default) 270° 180° vee vcc 90° vcc vee 0° vcc vcc LVDS DOBx16 LVDS data output buffers (LVDS DOBx16) accept 16-bit wide words from DMX1:16 and convert them into sixteen LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at bit rates up to 2Gb/s with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. The block also provides a bit order selection under control of the external 3.3V CMOS signal bitorder. The first input serial bit (MSB) is assigned to q15p/q15n at bitorder = “0” (default) or to q00p/q00n at bitorder = “1”. LVDS COB The LVDS clock output buffer (LVDS COB) utilizes a faster version of the same proprietary output buffer as in DOBx16. It receives the C16 clock signal from the Clk Proc and converts it into the LVDS output forwarded clock signal clop/clon. The phase of clop/clon can be adjusted as described above. Rev. 1.6.2 4 August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Input Timing Reliable latching of the incoming HS data dp/dn requires a certain phase relation between the input data and the half-rate input clock c2p/c2n that is specified in Table 2 and illustrated by Fig. 4. Table 2. Input High-Speed Data to Input High-Speed Clock Phase Delay Maximum required setup time, ps Maximum required hold time, ps -10 20 thold c2p/c2n tsetup tsetup thold dp/dn Fig. 4. Input Timing Diagram Output Timing The phase relation between the output LVDS data qXXp/qXXn and the divided-by-16 full-rate output forwarded clock clop is illustrated by Fig. 5, when phs1 = “0” and phs2 = “1”. Data-to-clock delay (tqc) varies from 48ps to 99ps depending on the process corner and the die temperature. tqc clop qXXp/ qXXn Fig. 5. Output Timing Diagram ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee). Rev. 1.6.2 August 2020 5 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Table 3. Absolute Maximum Ratings Parameter Supply Voltage (vcc) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min -40 10 10 Max +3.6 1.0 1.2 +90 +100 98 98 Units V W V ºC ºC % % TERMINAL FUNCTIONS Name vcc vee vtrm nc Name Supply and Termination Voltages Description Pin Number Positive power supply (+3.3V) 5, 8, 11, 14, 25, 26, 29, 32, 35, 38, 41, 44, 55, 62, 65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100 Negative power supply (GND 1, 15, 17, 23, 36, 50, 51, 52, 58, 75 or 0V) Termination voltage for clock 30, 31 inputs (default – vcc, minimum – vcc-0.8V) Unconnected pin 2, 18, 19, 20, 21, 33, 34, 42, 43, 47, 48, 49, 53, 54, 59, 74 TERMINAL No. Type dp dn c2p c2n rstp rstn 40 39 28 27 46 45 Input bitorder 16 CMOS input cdcadj cdccp cdccn phs1 phs2 37 24 22 57 56 Analog input Analog input Rev. 1.6.2 Input Input DESCRIPTION High-Speed I/Os CML differential data inputs with internal SE 50Ohm termination to vcc CML differential sampling clock inputs with internal SE 50Ohm termination to vtrm CML differential internal divider reset inputs with internal SE 50Ohm termination to vcc Controls Output bit order selection (default: low, the first serial bit (MSB) is q15p/q15n; active: high, MSB is q00p/q00n) Internal half-rate clock duty cycle adjustment, SE Internal half-rate clock duty cycle adjustment, Differential LS In., CMOS Low-speed output forwarded selection (default: both low) 6 clock clop/clon phase August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com TERMINAL Name No. Type DESCRIPTION Low-Speed I/Os q15n q15p q14n q14p q13n q13p q12n q12p q11n q11p q10n q10p q09n q09p q08n q08p q07n q07p q06n q06p q05n q05p q04n q04p q03n q03p q02n q02p q01n q01p q00n q00p clop clon Rev. 1.6.2 10 9 7 6 4 3 99 98 96 95 93 92 90 89 87 86 84 83 81 80 78 77 73 72 70 69 67 66 64 63 61 60 12 13 Output LVDS data outputs Output LVDS low-speed full-rate forwarded clock outputs. Can transmit four different clock phases as defined in Table 1 7 August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX UNIT COMMENTS General Parameters +3.14 +3.3 +3.47 V ±5% vcc vcc vcc-0.8 V vtrm 0.0 V External ground vee Ivcc 409 mA Power consumption 1350 mW Junction temperature -25 50 125 °C HS Input Data (dp/dn) Maximum Data rate 32 Gbps Minimum Data rate Gbps Swing (Diff or SE) 0.02 1.0 V Peak-to-peak CM Voltage Level vcc-0.8 vcc V HS Input Sampling Clock (c2p/c2n) Maximum Frequency 16 GHz Minimum Frequency GHz Swing (Diff or SE) 0.2 1.0 V Peak-to-peak CM Voltage Level vcc -0.8 vcc V Duty Cycle 40 50 60 % LS Output Data (q00p/q00n-q15p/q15n) Maximum Data Rate 2 Gbps Minimum Data Rate Gbps Interface LVDS Meets the IEEE Std. 1596.3-1996 LS Output Forwarded Clocks (clop/clon) Maximum Frequency 2 GHz Minimum Frequency GHz Interface LVDS Meets the IEEE Std. 1596.3-1996 CMOS Control Inputs (bitorder, phs1, phs2) Logic “1” level vcc -0.4 V Logic “0” level vee +0.4 V Analog Control Inputs (cdcadj, cdccp/cdccn) Voltage range V vee vcc cdcadj termination 22 / 5.6 KOhm to vee / vcc cdccp termination 0.95 KOhm to c2p cdccn termination 0.95 KOhm to c2n Rev. 1.6.2 8 August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com PACKAGE INFORMATION Fig. 6. CQFP 100-Pin Package Drawing (All Dimensions in mm) Rev. 1.6.2 9 August 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com The chip die is housed in a custom 100-pin CQFP package shown in Fig. 6. The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will be further processed as follows: 1. The lead’s gold plating will be removed per the following sections of J-STD-001D: 3.9.1 Solderability 3.2.2 Solder Purity Maintenance 3.9.2 Solderability Maintenance 3.9.3 Gold Removal 2. The leads will be tinned with Sn63Pb37 solder The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is power for a positive supply. The part’s identification label is ASNT2140-KMA. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. REVISION HISTORY Revision 1.6.2 1.5.2 1.4.2 1.4.1 Date 08-2020 05-2020 07-2019 02-2016 1.3.1 07-2015 1.2.1 07-2015 1.1.1 05-2015 1.0.1 03-2015 1.0.0 11-2014 Rev. 1.6.2 Changes Corrected terminal descriptions for vtrm, dp/dn, c2p/c2n Updated Package Information Updated Letterhead Updated frequency of operation Updated Electrical characteristics table Corrected pinout diagram (pins 52 and 53) Corrected Terminal Functions Updated frequency of operation Updated Electrical characteristics table Updated Description Corrected Terminal Functions table Revised package information section Corrected format Updated pin out diagram Updated Terminal Functions table Included vtrm function description Preliminary release 10 August 2020