S-25A256B
FOR AUTOMOTIVE 125°C OPERATION
SPI SERIAL E2PROM
www.ablic.com
www.ablicinc.com
Rev.1.2_02
© ABLIC Inc., 2011-2014
2
This IC is a SPI serial E PROM which operates under the high temperature, at high speed, with the wide range operation for
automotive components. This IC has the capacity of 256 K-bit and the organization of 32768 words 8-bit. Page write and
Sequential read are available.
Caution
Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is
indispensable.
Features
Package
Operating voltage range
Read:
2.5 V ~ 5.5 V
Write:
2.5 V ~ 5.5 V
Operation frequency:
5.0 MHz max.
Write time:
5.0 ms max.
SPI mode (0, 0) and (1, 1)
Page write:
64 bytes / page
Sequential read
Write protect:
Software, Hardware
Protect area:
25%, 50%, 100%
Monitoring of a write memory state by the status register
Function to prevent malfunction by monitoring clock pulse
Write protect function during the low power supply voltage
8-Pin SOP (JEDEC)
5
8
4
1
(5.0 6.0 t1.75 mm)
CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
Endurance*1:
106 cycle / word *2 (Ta = 25C)
3 105 cycle / word *2 (Ta = 125C)
Data retention:
100 years (Ta = 25C)
50 years (Ta = 125C)
Memory capacity:
256 K-bit
Initial delivery state:
FFh, SRWD = 0, BP1 = 0, BP0 = 0
Burn-in specifications:
Wafer level burn-in
Operation temperature range: Ta = 40°C to 125°C
Lead-free (Sn 100%), halogen-free*3
AEC-Q100 qualified*4
*1.
*2.
*3.
*4.
Refer to " Endurance" for details.
For each address (Word: 8-bit)
Refer to " Product Name Structure" for details.
Contact our sales office for details.
Remark Refer to "3.
Product name list" in " Product Name Structure" for details of package and product.
1
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
Block Diagram
Step-up Circuit
Voltage Detector
SCK
SI
HOLD
WP
Clock Counter
Mode
Decoder
Data Register
Address Register
Output
Control
Circuit
SO
Status Register
Read Circuit
VCC
GND
Figure 1
2
X Decoder
Input Control Circuit
CS
Page Latch
Memory
Cell
Array
Status
Memory Cell Array
Y Decoder
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales office for details of AEC-Q100 reliability specification.
Product Name Structure
1.
Product name
S-25A256B
0A
J8T2
U
3
Fixed
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
J8T2: 8-Pin SOP (JEDEC), Tape
Fixed
Product name
S-25A256B: 256 K-bit
*1.
Refer to the tape drawing.
Remark
2.
This IC is wafer level burn-in specification.
Package
Table 1
Package Name
8-Pin SOP (JEDEC)
3.
Package Drawing Codes
Dimension
Tape
Reel
FJ008-A-P-SD
FJ008-D-C-SD
FJ008-D-R-S1
Product name list
Table 2
Product Name
Capacity
Package
S-25A256B0A-J8T2U3
256 K bit
Remark This IC is wafer level burn-in specification.
Quantity
8-Pin SOP (JEDEC)
4000 pcs / reel
Pin Configuration
1.
8-Pin SOP (JEDEC)
Table 3
Top view
Pin No.
Symbol
1
CS *1
Chip select input
7
2
SO
Serial data output
3
6
3
4
5
1
8
2
Figure 2
*1.
*1
4
5
6
WP
GND
SI*1
SCK*1
7
HOLD *1
8
VCC
Description
Write protect input
Ground
Serial data input
Serial clock input
Hold input
Power supply
Do not use it in "High-Z".
3
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
Absolute Maximum Ratings
Table 4
Item
Symbol
Absolute Maximum Rating
Unit
Power supply voltage
VCC
0.3 to 6.5
V
Input voltage
VIN
0.3 to 6.5
V
Output voltage
VOUT
0.3 to VCC 0.3
V
Operation ambient temperature
Topr
40 to 125
°C
Storage temperature
Tstg
65 to 150
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 5
Item
Symbol
Power supply voltage
VCC
High level input voltage
Low level input voltage
VIH
VIL
Condition
Read
Write
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
Ta = 40C to 125C
Min.
Max.
2.5
2.5
0.7 VCC
0.3
Unit
5.5
5.5
VCC 1.0
0.3 VCC
V
V
V
V
Pin Capacitance
Table 6
Item
Symbol
Condition
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
Input capacitance
CIN
VIN = 0 V ( CS , SCK, SI, WP , HOLD )
－
8
pF
Output capacitance
COUT
VOUT = 0 V (SO)
－
10
pF
Endurance
Table 7
Item
Endurance
*1.
Symbol
NW
Operation Ambient Temperature
Ta = 25°C
Ta = 40°C to 85°C
Ta = 40°C to 105°C
Ta = 40°C to 125°C
Min.
106
7 105
5 105
3 105
Max.
－
－
－
－
Unit
*1
cycle / word
*1
cycle / word
*1
cycle / word
*1
cycle / word
Min.
Max.
－
－
Unit
For each address (Word: 8-bit)
Data Retention
Table 8
Item
Data retention
4
Symbol
－
Operation Ambient Temperature
Ta = 25°C
Ta = 40°C to 125°C
100
50
year
year
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
DC Electrical Characteristics
Table 9
Item
Symbol
Current consumption
ICC1
(read)
Condition
No load at SO pin
Ta = 40°C to 125°C
VCC = 2.5 V to 4.5 V
VCC = 4.5 V to 5.5 V
fSCK = 5.0 MHz
fSCK = 5.0 MHz
Min.
Max.
Min.
Max.
－
2.0
－
2.5
Unit
mA
Table 10
Item
Symbol
Current consumption
ICC2
(write)
Ta = 40°C to 125°C
VCC = 2.5 V to 5.5 V
fSCK = 5.0 MHz
Condition
No load at SO pin
Unit
Min.
Max.
－
4.0
mA
Table 11
Item
Standby current
consumption
Input leakage current
Output leakage current
Low level
output voltage
High level
output voltage
Symbol
Condition
ISB
CS = VCC,
SO = Open
Other inputs are
VCC or GND
ILI
ILO
VOL1
VOL2
VOH1
VOH2
VIN = GND to VCC
VOUT = GND to VCC
IOL = 2.0 mA
IOL = 1.5 mA
IOH = 2.0 mA
IOH = 0.4 mA
Ta = 40°C to 125°C
VCC = 2.5 V to 4.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Unit
－
8.0
－
10.0
A
－
－
－
－
－
0.8 VCC
2.0
2.0
－
0.4
－
－
－
－
－
－
0.8 VCC
0.8 VCC
2.0
2.0
0.4
0.4
－
－
A
A
V
V
V
V
5
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
AC Electrical Characteristics
Table 12
Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 VCC to 0.8 VCC
0.5 VCC
100 pF
Table 13
Item
Symbol
Ta = 40°C to 125°C
VCC = 2.5 V to 5.5 V
Min.
Max.
Unit
SCK clock frequency
fSCK
－
5.0
MHz
CS setup time during CS falling
tCSS.CL
90
－
ns
CS setup time during CS rising
tCSS.CH
90
－
ns
CS deselect time
tCDS
90
－
ns
CS hold time during CS falling
tCSH.CL
90
－
ns
CS hold time during CS rising
tCSH.CH
90
－
ns
ns
ns
s
s
ns
ns
*1
SCK clock time "H"
SCK clock time "L"*1
Rising time of SCK clock*2
Falling time of SCK clock*2
SI data input setup time
SI data input hold time
tHIGH
tLOW
tRSK
tFSK
tDS
tDH
90
90
－
－
20
30
－
－
1
1
－
－
SCK "L" hold time during HOLD rising
tSKH.HH
70
－
ns
SCK "L" hold time during HOLD falling
tSKH.HL
40
－
ns
SCK "L" setup time during HOLD falling
tSKS.HL
0
－
ns
SCK "L" setup time during HOLD rising
tSKS.HH
0
－
ns
tOZ
tOD
tOH
tRO
tFO
－
－
0
－
－
100
70
－
40
40
ns
ns
ns
ns
ns
tOZ.HL
－
100
ns
tOD.HH
－
50
ns
ns
Disable time of SO output*2
Delay time of SO output
Hold time of SO output
Rising time of SO output*2
Falling time of SO output*2
Disable time of SO output during HOLD falling*2
*2
Delay time of SO output during HOLD rising
WP setup time
tWS1
0
－
WP hold time
tWH1
0
－
ns
WP release / setup time
tWS2
0
－
ns
－
30
ns
tWH2
WP release / hold time
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by
minimizing the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
Table 14
Item
Write time
6
Symbol
tPR
Ta = 40°C to 125°C
VCC = 2.5 V to 5.5 V
Min.
Max.
－
5.0
Unit
ms
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
tCDS
CS
tCSH.CL
tCSS.CH
tCSH.CH
tCSS.CL
SCK
tDS
SI
SO
tDH
tRSK
MSB IN
tFSK
LSB IN
High-Z
Figure 3
Serial Input Timing
CS
tSKS.HL
tSKH.HL
tSKH.HH
SCK
tSKS.HH
SI
tOZ.HL
tOD.HH
SO
HOLD
Figure 4
Hold Timing
7
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
tSCK
CS
tOZ
tHIGH
SCK
tLOW
ADDR
SI LSB IN
tOD
tOH
tOD
tOH
SO
LSB OUT
tRO
tFO
Figure 5
Serial Output Timing
tWS1
tWH1
CS
WP
Figure 6
Valid Timing in Write Protect
tWS2
tWH2
CS
WP
Figure 7
8
Invalid Timing in Write Protect
Rev.1.2_02
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Pin Functions
1.
CS (chip select input) pin
This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its
output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip
select to "L". Input any instruction code after power-on and a falling of chip select.
2.
SI (serial data input) pin
This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches data
at rising edge of serial clock.
3.
SO (serial data output) pin
This pin is to output serial data. The data output changes at falling edge of serial clock.
4.
SCK (serial clock input) pin
This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are received at
a rising edge of clock. Data is output during falling edge of clock.
5.
WP (write protect input) pin
Write protect is purposed to protect the area size against the write instruction (BP1, BP0 in the status register). Fix
this pin "H" or "L" not to set it in the floating state.
Refer to " Protect Operation" for details.
6.
HOLD (hold input) pin
This pin is used to pause serial communications without setting this IC in the non-select status.
In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During the
hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L".
Refer to " Hold Operation" for details.
Initial Delivery State
Initial delivery state of all addresses is "FFh".
Moreover, initial delivery state of the status register nonvolatile memory is as follows.
SRWD = 0
BP1 = 0
BP0 = 0
9
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
Instruction Set
Table 15 is the list of instruction for This IC. the instruction is able to be input by changing the CS pin "H" to "L". Input
the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If this IC receives any
invalid instruction code, this IC goes in the non-select status.
Table 15
Instruction Set
Instruction Code
Instruction
Operation
SCK Input Clock
1 to 8
WREN
WRDI
Address
SCK Input Clock
9 to 16
－
－
Data
SCK Input Clock
17 to 24
－
－
Write enable
0000 0110
Write disable
0000 0100
Read the status
－
b7 to b0 output*1
0000 0101
RDSR
register
Write in the status
－
0000 0001
b7 to b0 input
WRSR
register
A15 to A8*2
READ
Read memory data
0000 0011
A7 to A0
A15 to A8*2
WRITE
Write memory data
0000 0010
A7 to A0
*1. Sequential data reading is possible.
*2. The higher addresses A15 = Don't care.
*3. After outputting data in the specified address, data in the following address is output.
SCK Input Clock
25 to 32
－
－
－
－
D7 to D0 output*3
D7 to D0 input
Operation
1.
Status register
The status register's organization is below. The status register can write and read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect
Write Enable Latch
Write In Progress
Figure 8
Organization of Status Register
The status / control bits of the status register as follows.
1. 1
SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = "1", WP = "L"), this IC goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile memory in the status register (SRWD, BP1, BP0) go in read only, so that the WRSR instruction is not
be performed.
10
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
1. 2
BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory
area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1 and BP0 is
possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of Block Protect.
1. 3
WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL
is "1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this
IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
The power supply voltage is dropping
At power-on
After performing WRDI
After the completion of write operation by the WRSR instruction
After the completion of write operation by the WRITE instruction
1. 4
WIP (b0) : Write In Progress
Bit WIP is read only and shows whether the internal memory is in the write operation or not by the WRITE or
WRSR instruction. Bit WIP is "1" during the write operation but "0" during any other status. Figure 9 shows the
usage example.
CS
WRITE or WRSR instruction
RDSR instruction
D2 D1 D0
SI
RDSR instruction
RDSR
RDSR
S
R
W
D
SO
RDSR instruction
S
R
W
D
BB
PP
1 0
000
RDSR
000
11
S
R
W
D
BB
PP
1 0
11
WEL, WIP
WEL, WIP
BB
PP
1 0
000
00
WEL, WIP
tPR
Figure 9
2.
Usage Example of WEL, WIP Bits during Write
Write enable (WREN)
Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit
WEL. Its operation is below.
After selecting this IC by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL,
set this IC in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction,
input the clock different from a specified value (n = 8 clock) while CS is in "L".
11
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
CS
WP
SCK
High / Low
1
2
3
4
5
6
7
8
Instruction
SI
High-Z
SO
Figure 10
3.
WREN Operation
Write disable (WRDI)
The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting this IC by the chip select
( CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock.
To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L".
Bit WEL is reset after the operations shown below.
The power supply voltage is dropping
At power-on
After performing WRDI
After the completion of write operation by the WRSR instruction
After the completion of write operation by the WRITE instruction
CS
WP
SCK
High / Low
1
2
3
4
5
Instruction
SI
High-Z
SO
Figure 11
12
WRDI Operation
6
7
8
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
4.
Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit in
the status register is output from serial data output (SO). Sequential read is available for the status register. To stop
the read cycle, set CS to "H".
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the write
cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits SRWD, BP1 and BP0 can
be acquired by performing a new RDSR instruction after verifying the completion of the write cycle.
CS
WP
SCK
High / Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Instruction
SI
Outputs Data in the Status Register
SO
High-Z
Figure 12
5.
b7
b6
b5
b4
b3
b2
b1
b0
b7
RDSR Operation
Write in the status register (WRSR)
The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4,
b1, b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown
below.
Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start
WRSR write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial
clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR write. Bit WIP is "1"
during write, "0" during any other status. Bit WEL is reset when write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the
Read only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on
the status of write protect ( WP ). With a combination of bit SRWD and write protect ( WP ), this IC can be set in
Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to " Protect
Operation").
Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction.
The newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L".
13
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
CS
WP
High / Low
SCK
1
2
3
4
5
6
7
9
8
Instruction
11
12
13
14
15
16
Inputs Data in the Status Register
b7
SI
b6
b5
b4
b3
b2
b1
b0
High-Z
SO
Figure 13
6.
10
WRSR Operation
Read memory data (READ)
The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after
inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the
address is output from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in "L", the address is automatically
incremented so that data in the following address is sequentially output. The address counter rolls over to the first
address by increment in the last address.
To finish the read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During write,
the READ instruction code is not be accepted or operated.
CS
WP
High / Low
SCK
1
2
3
4
5
6
Instruction
7
8
9
10
11
21
23
24
25
26
27
28
29
30
31
32
16-bit Address
A15 A14 A13
SI
22
A3 A2 A1 A0
Outputs the First Byte
High-Z
SO
Remark
D7
The higher addresses A15 = Don't care.
Figure 14
14
READ Operation
D6 D5 D4 D3 D2 D1 D0
Outputs
the Second
D7
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
7.
Write memory data (WRITE)
Figure 15 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data from
serial data input (SI) after inputting "L" to the chip select ( CS ). To start WRITE (tPR), set the chip select ( CS ) to "H"
after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to "0" when write
has completed.
This IC can Page write of 64 bytes. Its function to transmit data is as same as Byte write basically, but it operates
Page write by receiving sequential 8-bit write data as much data as page size has. Input the instruction code, the
address and data from serial data input (SI) after inputting "L" in CS , as the WRITE operation (page) shown in
Figure 16. Input the next data while keeping CS in "L". After that, repeat inputting data of 8-bit sequentially. At the
end, by setting CS to "H", the WRITE operation starts (tPR).
6 of the lower bits in the address are automatically incremented every time when receiving write data of 8-bit. Thus,
even if write data exceeds 64 bytes, the higher bits in the address do not change. And 6 of lower bits in the address
roll over so that write data which is previously input is overwritten.
These are cases when the WRITE instruction is not accepted or operated.
Bit WEL is not set to "1" (not set to "1" beforehand immediately before the WRITE instruction)
During WRITE operation
The address to be written is in the protect area by BP1 and BP0
To cancel the WRITE instruction, input the clock different from a specified value (n = 24 m 8 clock) while CS is
in "L".
CS
WP
High / Low
SCK
1
2
3
4
5
6
7
8
9
10
11
22
23
24
25
16-bit Address
Instruction
A15 A14 A13
SI
21
26
27
28
29
30
31
32
Data Byte 1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
High-Z
SO
Remark
The higher addresses A15 = Don't care.
Figure 15
WRITE Operation (1 Byte)
15
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
CS
WP
High / Low
1
2
3
4
5
6
7
8
9
10 11
22 23 24 25 26 27 28 29 30 31 32
SCK
Instruction
A15 A14 A13
SI
Data Byte (n)
16-bit Address (n)
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte (n + x)
D4 D3 D2 D1 D0
High-Z
SO
Remark
The higher addresses A15 = Don't care.
Figure 16
WRITE Operation (Page)
Protect Operation
Table 16 shows the block settings of write protect. Table 17 shows the protect operation for this IC. As long as bit SRWD,
the Status Register write Disable bit, in the status register is reset to "0" (it is in reset before the shipment), the value of
status register can be changed.
These are two statues when bit SRWD is set to "1".
Write in the status register is possible; write protect ( WP ) is in "H".
Write in the status register is impossible; write protect ( WP ) is in "L". Therefore the write protect area which is set by
protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
After setting bit SRWD, set write protect ( WP ) to "L".
Set bit SRWD completed setting write protect ( WP ) to "L".
The timing during the cycle write to the status register is showed in "Figure 6
"Figure 7 Invalid Timing in Write Protect".
Valid Timing in Write Protect" and
By inputting "H" to write protect ( WP ), Hardware Protect (HPM) is released. If the write protect ( WP ) is "H", Hardware
Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status register (BP1, BP0)
only works.
16
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
Table 16
Block Settings of Write Protect
Status Register
BP1
0
0
1
1
BP0
0
1
0
1
Table 17
Mode
Software Protect
(SPM)
Hardware Protect
(HPM)
Area of Write Protect
Address of Write Protect Block
0%
25%
50%
100%
None
6000h to 7FFFh
4000h to 7FFFh
0000h to 7FFFh
Protect Operation
WP Pin
1
1
X
X
0
Bit SRWD
Bit WEL
Write Protect Block
General Block
Status Register
X
X
0
0
1
0
1
0
1
0
0
1
1
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write disable
Remark X = Don't care
Hold Operation
The hold operation is used to pause serial communications without setting this IC in the non-select status. In the hold
status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care". Be
sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status.
Generally, during the hold status, this IC holds the select status. But if setting this IC in the non-select status, the users
can finish the operation even in progress.
Figure 17 shows the hold operation.
These are two statuses when the serial clock (SCK) is set to "L".
If setting hold ( HOLD ) to "L", hold ( HOLD ) is switched at the same time the hold status starts.
If setting hold ( HOLD ) to "H", hold ( HOLD ) is switched at the same time the hold status ends.
These are two statuses when the serial clock (SCK) is set to "H".
If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold ( HOLD ) is switched.
If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold ( HOLD ) is switched.
Hold status
Hold status
SCK
HOLD
Figure 17
Hold Operation
17
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
Write Protect Function during the Low Power Supply Voltage
This IC has a built-in detection circuit which operates with the low power supply voltage. This IC cancels the write
operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time, goes in the write
protect status (WRDI) automatically to reset bit WEL. Its detection and release voltages are 1.20 V typ. (Refer to Figure
18).
To operate write, after the power supply voltage dropped once but rose to the voltage level which allows write again, be
sure to set the write Enable Latch bit (WEL) before operating write (WRITE, WRSR).
In the write operation, data in the address written during the low power supply voltage is not assured.
Power supply voltage
Detection voltage (−VDET)
1.20 V typ.
Release voltage (+VDET)
1.20 V typ.
Cancel the write instruction
Set in write protect (WRDI) automatically
Figure 18
Operation during the Low Power Supply Voltage
Input Pin and Output Pin
1.
Connection of input pin
All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you design.
Especially, set the CS input pin in the non-select status "H" during power-on/off and standby. The error write does
not occur as long as the CS pin is in the non-select status "H". Set the CS pin to VCC via a resistor (the pull-up
resistor of 10 k to 100 k).
If the CS pin and the SCK pin change from "L" to "H" simultaneously, data may be input from the SI pin.
To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to
pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting
the WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.
2.
Equivalent circuit of input pin and output pin
Figure 19 and Figure 20 show the equivalent circuits of input pins in this IC. A pull-up and pull-down elements are
not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 21 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z".
2. 1
Input pin
CS, SCK
Figure 19
18
CS , SCK Pin
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A256B
Rev.1.2_02
SI, WP, HOLD
Figure 20
2. 2
SI, WP , HOLD Pin
Output pin
VCC
SO
Figure 21
SO Pin
Precautions
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the detailed
operation condition in the data sheet.
Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this
IC's pins to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
19
5.02±0.2
8
5
1
4
1.27
0.20±0.05
0.4±0.05
No. FJ008-A-P-SD-2.2
TITLE
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø2.0±0.05
8.0±0.1
2.1±0.1
6.7±0.1
1
8
4
5
Feed direction
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-S1-1.0
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-S1-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
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7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
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ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
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9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
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representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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