S-89713B-I8T1U

S-89713 Series www.ablic.com LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER Rev.3.5_00 © ABLIC Inc., 2009-2021 This IC incorporates a general purpose analog circuit in a small package. The S-89713 Series is an auto-zero operation, zero-drift operational amplifier that has input and output of low input offset voltage and Rail-to-Rail. The S-89713 Series is suitable for applications requiring less offset voltage. The S-89713 Series is a dual operational amplifier (with 2 circuits).  Features • Low input offset voltage: • Operation power supply voltage range: • Low current consumption: • • • • Internal phase compensation: Rail-to-Rail input and output Operation temperature range: Lead-free (Sn 100%), halogen-free VIO = 10 μV max. (Ta = +25°C) VDD = 2.65 V to 5.50 V IDD = 165 μA typ. (Per circuit, Ta = +25°C) IDD = 330 μA typ. (2 circuits, Ta = +25°C) No external parts required Ta = −40°C to +85°C  Applications • • • • • Various sensor interfaces High-accuracy current detection Strain gauge amplifier Game Various electric devices  Packages • TMSOP-8 • SNT-8A 1 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Block Diagram VDD IN1(+) + IN1(−) − OUT1 IN2(+) + IN2(−) − OUT2 VSS Figure 1 2 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Product Name Structure Users can select the package type for the S-89713 Series. Refer to "1. Product name" regarding the contents of product name, "2. Packages" regarding the package drawings and "3. Product name list" regarding the product type. 1. Product name S-89713B - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Product name abbreviation and IC packing specifications*1 K8T2: TMSOP-8, Tape I8T1: SNT-8A, Tape *1. 2. Refer to the tape drawing. Packages Table 1 Package Name TMSOP-8 SNT-8A 3. Dimension FM008-A-P-SD PH008-A-P-SD Package Drawing Codes Tape FM008-A-C-SD PH008-A-C-SD Reel FM008-A-R-SD PH008-A-R-SD Land − PH008-A-L-SD Product name list Table 2 Product Name Package S-89713B-K8T2U TMSOP-8 S-89713B-I8T1U SNT-8A 3 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series  Pin Configurations 1. TMSOP-8 Table 3 Top view Pin No. 1 2 3 4 8 7 6 5 Figure 2 2. 1 2 3 4 5 6 7 8 Symbol OUT1 IN1(−) IN1(+) VSS IN2(+) IN2(−) OUT2 VDD Description Output pin 1 Inverted input pin 1 Non-inverted input pin 1 GND pin Non-inverted input pin 2 Inverted input pin 2 Output pin 2 Positive power supply pin SNT-8A Table 4 Top view 1 2 3 4 8 7 6 5 Figure 3 4 Pin No. 1 2 3 4 5 6 7 8 Symbol OUT1 IN1(−) IN1(+) VSS IN2(+) IN2(−) OUT2 VDD Description Output pin 1 Inverted input pin 1 Non-inverted input pin 1 GND pin Non-inverted input pin 2 Inverted input pin 2 Output pin 2 Positive power supply pin Rev.3.5_00 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Absolute Maximum Ratings Table 5 (Ta = +25°C unless otherwise specified) Item Power supply voltage Input voltage Output voltage Differential input voltage Symbol VDD VIN(+), VIN(−) VOUT VIND ISOURCE ISINK Output pin current Absolute Maximum Rating VSS − 0.3 to VSS + 7.0 VSS − 0.3 to VDD + 0.3 VSS − 0.3 to VDD + 0.3 ±5.5 10.0 10.0 650*1 450*1 −40 to +85 −55 to +125 TMSOP-8 PD SNT-8A Operation ambient temperature Topr Storage temperature Tstg *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Board name: JEDEC STANDARD51-7 Power dissipation The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 700 Power Dissipation (PD) [mW] Caution Unit V V V V mA mA mW mW °C °C 600 TMSOP-8 500 SNT-8A 400 300 200 100 0 0 50 100 150 Ambient Temperature (Ta) [°C] Figure 4 Power Dissipation of Package (When Mounted on Board) 5 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Electrical Characteristics Table 6 (VDD = 3.0 V, Ta = +25°C unless otherwise specified) DC Electrical Characteristics Item Operation power supply voltage range Current consumption (for 2 circuits) Input offset voltage Input offset voltage drift Symbol Condition Min. Typ. Max. Unit Test Circuit − 2.65 3.00 5.50 V − − 330 380 μA 5 VDD IDD VCMR = VOUT = VDD / 2 VIO ΔVIO ΔTa VCMR = VDD / 2 −10 ±1 +10 μV 1 VCMR = VDD / 2 − ±0.1 − μV/°C 1 Input offset current Input bias current Common-mode input voltage range IIO IBIAS − − − − ±140 ±70 − − pA pA − − VCMR − VSS − 0.1 − VDD + 0.1 V 2 Voltage gain (open loop) AVOL VSS + 0.1 V ≤ VOUT ≤ VDD − 0.1 V, VCMR = VDD / 2, RL = 10 kΩ 110 130 − dB 8 VOH RL = 10 kΩ − − V 3 VOL RL = 10 kΩ 2.9 − − 0.1 V 4 CMRR VSS − 0.1 V ≤ VCMR ≤ VDD + 0.1 V 106 130 − dB 2 106 120 − dB 1 Maximum output swing voltage Common-mode input signal rejection ratio Power supply voltage rejection ratio Source current PSRR VDD = 2.65 V to 5.50 V ISOURCE VOUT = VDD − 0.1 V 1.3 1.6 − mA 6 Sink current ISINK VOUT = 0.1 V 1.6 2.0 − mA 7 Table 7 (VDD = 3.0 V, Ta = +25°C unless otherwise specified) AC Electrical Characteristics Item Symbol Slew rate SR Gain-bandwidth product GBP 6 Condition RL = 1.0 MΩ, CL = 15 pF (Refer to Figure 13) CL = 0 pF Min. Typ. Max. Unit − 0.16 − V/μs − 240 − kHz LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Test Circuits (Per circuit) 1. Power supply voltage rejection ratio, input offset voltage CF • Power supply voltage rejection ratio (PSRR) The power supply voltage rejection ratio (PSRR) can be calculated by the following expression, with VOUT measured at each VDD. RF VDDN VDD RS − D.U.T + RS RF + NULL − VOUT CF Test conditions: VDD = 2.65 V: VDD = VDD1, VOUT = VOUT1 VDD = 5.5 V: VDD = VDD2, VOUT = VOUT2 VSSN PSRR = 20 log VCMR = VDD / 2 Figure 5 × RF + RS  RS    • Input offset voltage (VIO) Test Circuit 1 VIO = 2. VDD1 − VDD2   VDD1 VDD2   VOUT1 − 2  − VOUT2 − 2   VOUT − VDD 2   × RS RF + RS Common-mode input signal rejection ratio, common-mode input voltage range CF • Common-mode input signal rejection ratio (CMRR) The common-mode input signal rejection ratio (CMRR) can be calculated by the following expression, with VOUT measured at each VIN. RF VDDN VDD RS − D.U.T + RS RF + NULL − CF VOUT Test conditions: VIN = VCMR Max.: VIN = VIN1, VOUT = VOUT1 VIN = VCMR Min.: VIN = VIN2, VOUT = VOUT2 VSSN VM = VDD / 2 VIN CMRR = 20 log    VIN1 − VIN2 RF + RS  × R  S (VOUT1 − VIN1) − (VOUT2 − VIN2)  • Common-mode input voltage range (VCMR) Figure 6 Test Circuit 2 The common-mode input voltage range is the range of VIN in which VOUT satisfies the common-mode input signal rejection ratio specifications. 7 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series 3. Maximum output swing voltage • Maximum output swing voltage (VOH) VDD − VOH + Test conditions: VDD VIN1 = 2 − 0.1 V VDD VIN2 = 2 + 0.1 V RL = 10 kΩ RL VIN1 Figure 7 4. VDD / 2 VIN2 Test Circuit 3 Maximum output swing voltage VDD VDD / 2 • Maximum output swing voltage (VOL) RL − + VIN1 VIN2 Figure 8 8 Test Circuit 4 VOL Test conditions: VDD VIN1 = 2 + 0.1 V VDD VIN2 = 2 − 0.1 V RL = 10 kΩ Rev.3.5_00 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00 5. Current consumption • Current consumption (IDD) VDD A − + VCMR = VDD / 2 Figure 9 6. Test Circuit 5 Source current • Source current (ISOURCE) VDD − + VIN1 VOUT VIN2 Figure 10 7. A Test conditions: VOUT = VDD − 0.1 V VDD VIN1 = 2 − 0.1 V VDD VIN2 = 2 + 0.1 V Test Circuit 6 Sink current VDD VOUT A − + VIN1 • Sink current (ISINK) Test conditions: VOUT = 0.1 V VDD VIN1 = 2 + 0.1 V VDD VIN2 = 2 − 0.1 V VIN2 Figure 11 Test Circuit 7 9 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series 8. Rev.3.5_00 Voltage gain • Voltage gain (open loop) (AVOL) CF VDD RS VDDN − D.U.T + RS RF CF VCMR = VDD / 2 + NULL − RL VOUT VSSN Test conditions: VM = VDD − 0.1 V: VM = VM1, VOUT = VOUT1 VM = 0.1 V: VM = VM2, VOUT = VOUT2 AVOL = 20 log VM VDD / 2 Figure 12 9. RF The voltage gain (AVOL) can be calculated by the following expression, with VOUT measured at each VM.    VM1 − VM2 RF + RS  × R  S VOUT1 − VOUT2  RL = 10 kΩ Test Circuit 8 Slew rate Measured by the voltage follower circuit. tR = tF = 20 ns (VSS to VDD) VDD • Slew rate (SR) VIN(+) VSS (= 0 V) When falling V × 0.8 SR = DD t THL tTHL VDD × 0.9 VOUT (= VIN(－)) tTLH Figure 13 10 VDD × 0.1 When rising V × 0 .8 SR = DD t TLH LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Usage Example VDD CF RF [Example of Gain = 1000 times] RS = 1 kΩ RF = 1 MΩ CF = 1000 pF RS − VIN VOUT + [Example of Gain = 100 times] RS = 1 kΩ RF = 100 kΩ CF = 1000 pF RS RF CF VCMR = VDD / 2 Figure 14 Differential Amplifier Circuit VDD VDD + RF VOUT − RS − VIN + RF VIN VOUT RS VCMR = VDD / 2 VCMR = VDD / 2 Figure 15 Inverting Amplifier Circuit ILOAD VSUPPLY RS + − VOUT Caution + RSENSE − RS RF CF Figure 17 CF RF RS RSENSE RS VDD VDC CF RF Non-inverting Amplifier Circuit VDD VDC RLOAD Figure 16 Low-side Current Detection Circuit RLOAD ILOAD Figure 18 VOUT RF CF High-side Current Detection Circuit The above connection diagram and constant will not guarantee successful operation. Perform through evaluation using the actual application to set the constant. 11 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Precautions • During the operation of an operational amplifier circuit, when VOUT ≤ VSS + 100 mV or VOUT ≥ VDD − 100 mV, the signal becomes difficult to be output, and the output voltage (VOUT) may become VSS or VDD. If this happens, supply an appropriate input signal to the operational amplifier so that VOUT is within the range of VSS + 100 mV to VDD − 100 mV. Contact our sales representatives if you have any questions for use in the above operation conditions. • Generally an operational amplifier may cause oscillation depending on the selection of external parts. Perform thorough evaluation using the actual application to set the constant. • Do not apply an electrostatic discharge to this IC that exceeds performance ratings of the built-in electrostatic protection circuit. • ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. • Use this IC with the output current of 10 mA or less. • When using the voltage follower circuit (Gain = 1 time), connect a resistor of 470 Ω or more for the stable operation, as shown in Figure 19. The operation may be unstable depending on the value of the load capacitance connected to the output pin, even when the voltage follower circuit is not used. Use the product under thorough evaluation. VDD VIN+ + VIN− − VOUT 470 Ω or more VSS Load capacitance Figure 19 Caution 12 The above connection diagram and constant will not guarantee successful operation. Perform through evaluation using the actual application to set the constant. LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Characteristics (Typical Data) 1. Current consumption (IDD) (2 circuits) vs. Power supply voltage (VDD) VSS = 0 V 500 Ta = −40°C IDD [μA] 400 300 Ta = +25°C Ta = +85°C 200 100 0 2 2. 3 4 VDD [V] 5 6 Voltage gain (AVOL) vs. Frequency (f) VDD = 2.65 V, VSS = 0 V 140 AVOL [dB] 100 Ta = +25°C Ta = −40°C 80 60 40 AVOL [dB] 120 Ta = +85°C 20 0 0.001 0.01 0.1 1 10 100 1000 AVOL [dB] f [kHz] 40 20 60 40 20 VDD = 3.0 V, VSS = 0 V Ta = +25°C Ta = −40°C Ta = +85°C 0 0.001 0.01 0.1 1 10 100 1000 f [kHz] VDD = 5.5 V, VSS = 0 V 140 120 100 80 60 140 120 100 80 Ta = +25°C Ta = −40°C Ta = +85°C 0 0.001 0.01 0.1 1 10 100 1000 f [kHz] 13 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series 3. Output current 3. 1 Source current (ISOURCE) vs. Power supply voltage (VDD) VOUT = VDD − 0.1 V, VSS = 0 V ISOURCE [mA] 3.5 3.0 Ta = −40°C Ta = +25°C 2.5 2.0 1.5 1.0 Ta = +85°C 0.5 0.0 2 3. 2 3 4 VDD [V] 5 6 Sink current (ISINK) vs. Power supply voltage(VDD) VOUT = VSS + 0.1 V, VSS = 0 V ISINK [mA] 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Ta = +25°C 3. 3 Ta = −40°C Ta = +85°C 2 3 4 VDD [V] 5 6 Output voltage (VOUT) vs. Source current (ISOURCE) VDD = 2.65 V, VSS = 0 V VDD = 3.0 V, VSS = 0 V 3.5 3.0 3.0 Ta = −40°C 2.0 1.5 1.0 VOUT [V] VOUT [V] 2.5 Ta = +25°C Ta = +85°C 0.5 0 0 5 10 15 20 VDD = 5.5 V, VSS = 0 V 6 Ta = −40°C VOUT [V] 5 4 Ta = +25°C 3 2 Ta = +85°C 1 0 0 20 40 ISOURCE [mA] 2.5 2.0 1.5 1.0 0.5 0 0 Ta = −40°C Ta = +25°C Ta = +85°C 5 10 15 ISOURCE [mA] ISOURCE [mA] 14 Rev.3.5_00 60 80 20 25 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00 3. 4 Output voltage (VOUT) vs. Sink current (ISINK) VDD = 2.65 V, VSS = 0 V 3.0 2.0 1.5 1.0 VOUT [V] VOUT [V] 2.5 Ta = +25°C Ta = +85°C 0.5 Ta = −40°C 0 0 5 10 ISINK [mA] 15 VDD = 3.0 V, VSS = 0 V 3.5 3.0 2.5 2.0 Ta = +25°C 1.5 Ta = +85°C 1.0 0.5 Ta = −40°C 0 20 0 5 10 15 ISINK [mA] 20 25 VDD = 5.5 V, VSS = 0 V 6.0 VOUT [V] 5.0 4.0 3.0 2.0 Ta = +25°C Ta = +85°C 1.0 Ta = −40°C 0 0 20 40 ISINK [mA] 60 80 4. Input-referred noise voltage vs. Frequency (f) VDD = 3.0 V, VSS = 0 V Voltage Noise [nV/ Hz] 100 10 10 100 1000 10000 f [Hz] 15 LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER S-89713 Series Rev.3.5_00  Marking Specifications 1. TMSOP-8 Top view 8 7 6 5 (1): (2) to (4): (5): (6) to (8): Blank Product code (Refer to Product name vs. Product code) Blank Lot number (1) (2) (3) (4) (5) (6) (7) (8) 1 2 3 4 Product name vs. Product code Product Code (2) (3) (4) Product Name S-89713B-K8T2U 2. Z Y C SNT-8A Top view 8 7 6 5 (1): (2) to (4): (5), (6): (7) to (11): (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) 1 2 3 4 Product name vs. Product code Product Name S-89713B-I8T1U 16 Product Code (2) (3) (4) Z Y C Blank Product code (Refer to Product name vs. Product code) Blank Lot number 2.90±0.2 8 5 1 4 0.13±0.1 0.2±0.1 0.65±0.1 No. FM008-A-P-SD-1.2 TITLE TMSOP8-A-PKG Dimensions No. FM008-A-P-SD-1.2 ANGLE UNIT mm ABLIC Inc. 2.00±0.05 4.00±0.1 4.00±0.1 1.00±0.1 +0.1 1.5 -0 1.05±0.05 0.30±0.05 3.25±0.05 4 1 5 8 Feed direction No. FM008-A-C-SD-2.0 TITLE TMSOP8-A-Carrier Tape FM008-A-C-SD-2.0 No. ANGLE UNIT mm ABLIC Inc. 16.5max. 13.0±0.3 Enlarged drawing in the central part 13±0.2 (60°) (60°) No. FM008-A-R-SD-1.0 TITLE TMSOP8-A-Reel No. FM008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 4,000 1.97±0.03 8 7 6 5 3 4 +0.05 1 0.5 2 0.08 -0.02 0.48±0.02 0.2±0.05 No. PH008-A-P-SD-2.1 TITLE SNT-8A-A-PKG Dimensions No. PH008-A-P-SD-2.1 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 2.25±0.05 4.0±0.1 2.0±0.05 ø0.5±0.1 0.25±0.05 0.65±0.05 4.0±0.1 4 321 5 6 78 Feed direction No. PH008-A-C-SD-2.0 TITLE SNT-8A-A-Carrier Tape No. PH008-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PH008-A-R-SD-1.0 TITLE SNT-8A-A-Reel No. PH008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 2.01 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) 1. 2. 3. 4. 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) TITLE No. PH008-A-L-SD-4.1 SNT-8A-A -Land Recommendation PH008-A-L-SD-4.1 No. ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. 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The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com