Pre-Production
FM24W256
256Kb Wide Voltage Serial F-RAM
Features
256K bit Ferroelectric Nonvolatile RAM
Organized as 32,768 x 8 bits
High Endurance 100 Trillion (1014) Read/Writes
38 year Data Retention (@ +75ºC)
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Description
Low Power Operation
Wide Voltage Operation 2.7V-5.5V
100 A Active Current (100 kHz)
15 A Standby Current (typ.)
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC Package
Pin Configuration
The FM24W256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
A0
A1
A2
1
8
2
7
3
6
VSS
4
5
The FM24W256 performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM24W256 is capable of
supporting 1014 read/write cycles, or 100 million
times more write cycles than EEPROM.
Pin Names
A0-A2
SDA
SCL
WP
VSS
VDD
These capabilities make the FM24W256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24W256 provides substantial benefits to
users of serial EEPROM, yet these benefits are
available in a hardware drop-in replacement. The
FM24W256 is available in industry standard 8-pin
SOIC package using a familiar two-wire protocol. It
is guaranteed over an industrial temperature range of
-40°C to +85°C.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.0
Jan. 2012
VDD
WP
SCL
SDA
Function
Device Select Address
Serial Data/Address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24W256-G
FM24W256-GTR
FM24W256-EG*
FM24W256-EGTR*
8-pin “Green”/RoHS SOIC
8-pin “Green”/RoHS SOIC, Tape
& Reel
8-pin “Green”/RoHS EIAJ SOIC
8-pin “Green”/RoHS EIAJ SOIC,
Tape & Reel
* Not Recommended for New Designs
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Address
Latch
Counter
4,096 x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
Control Logic
A0-A2
Figure 1. Block Diagram
Pin Description
Pin Name
A0-A2
Type
Input
SDA
I/O
SCL
Input
WP
Input
VDD
VSS
Rev. 2.0
Jan. 2012
Supply
Supply
Pin Description
Device Select Address 0-2: These pins are used to select one of up to 8 devices of
the same type on the same two-wire bus. To select the device, the address value on
the three pins must match the corresponding bits contained in the slave address. The
address pins are pulled down internally.
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of
the part on the falling edge, and into the device on the rising edge. The SCL input
also incorporates a Schmitt trigger input for noise immunity.
Write Protect: When tied to VDD, addresses in the entire memory map will be writeprotected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
Supply Voltage: 2.7V to 5.5V
Ground
Page 2 of 14
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Overview
Two-wire Interface
The FM24W256 is a serial F-RAM memory. The
memory array is logically organized as a 32,768 x 8
bit memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the F-RAM is similar to serial EEPROMs. The major
difference between the FM24W256 and a serial
EEPROM with the same pinout relates to its superior
write performance.
The FM24W256 employs a bi-directional two-wire
bus protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24W256 in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
Memory Architecture
When accessing the FM24W256, the user addresses
32,768 locations each with 8 data bits. These data bits
are shifted serially. The 32,768 addresses are
accessed using the two-wire protocol, which includes
a slave address (to distinguish other non-memory
devices), and a 2-byte address. Only the lower 15 bits
are used by the decoder for accessing the memory.
The upper most address bit should be set to 0 for
compatibility with higher density devices in the
future.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
Users expect several obvious system benefits from
the FM24W256 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24W256 always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are in the electrical
specifications.
VDD
Rmin = 1.1 Kohm
Rmax = tR/Cbus
Microcontroller
SDA
SCL
SDA
SCL
FM24W256
FM24W256
A0 A1 A2
A0 A1 A2
Figure 2. Typical System Configuration
Note that it is the user’s responsibility to ensure that
VDD is within datasheet tolerances to prevent
incorrect operation.
Rev. 2.0
Jan. 2012
Page 3 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
SCL
SDA
7
Stop
(Master)
Start
(Master)
6
Data bits
(Transmitter)
0
Data bit Acknowledge
(Transmitter) (Receiver)
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24W256 should
end with a stop condition. If an operation is in
progress when a stop is asserted, the operation will be
aborted. The master must have control of SDA (not a
memory read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24W256 for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24W256
will continue to place data onto the bus as long as
the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24W256 to attempt to drive the
bus on the next clock while the master is sending a
new command such as stop.
Slave Address
The first byte that the FM24W256 expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select address bits, and a bit that specifies
if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24W256. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address select bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight FM24W256s can
reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
R/W=1 indicates a read operation and R/W=0
indicates a write operation.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Rev. 2.0
Jan. 2012
Page 4 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Memory Operation
Device Select
Slave ID
1
0
1
0
A2
A1
A0
R/W
7
6
5
4
3
2
1
0
Figure 4. Slave Address
Addressing Overview
After the FM24W256 (as receiver) acknowledges the
slave address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 15 address bits, the value of the
upper bit is “don’t care”. Following the MSB is the
LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24W256 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24W256 can begin. For a read operation the
FM24W256 will place 8 data bits on the bus then
wait for an acknowledge from the master. If the
acknowledge occurs, the FM24W256 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24W256 will end the read operation. For a
write operation, the FM24W256 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs MSB (most significant bit) first.
The FM24W256 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24W256 and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a slave address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the slave address to
a 0. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 7FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is no effective write delay with F-RAM. Since
the read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ready condition.
Internally, an actual memory write occurs after the
8th data bit is transferred. It will be complete before
the acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using start or stop
condition prior to the 8th data bit. The FM24W256
uses no page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24W256 will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
Rev. 2.0
Jan. 2012
Page 5 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Start
By Master
S
Stop
Address & Data
Slave Address
0 A
X
Address MSB
By FM24W256
A
Address LSB
A
Data Byte
A
P
Acknowledge
Figure 5. Single Byte Write
Start
S
By FM24W256
Stop
Address & Data
By Master
Slave Address
0 A
X
Address MSB
A
Address LSB
A
Data Byte
A
Data Byte
A
P
Acknowledge
Figure 6. Multiple Byte Write
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24W256 uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24W256 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete slave address, the FM24W256
will begin shifting out data from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM24W256 should read
out the next sequential byte.
Rev. 2.0
Jan. 2012
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the
FM24W256 attempts to read out additional data onto
the bus. The four valid methods are:
1.
2.
3.
4.
The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
The bus master issues a stop in the 9th clock
cycle.
The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
Page 6 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
loaded into the internal address latch. After the
FM24W256 acknowledges the address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read
Start
By Master
command to be issued with the slave address LSB set
to a “1”. The operation is now a current address read.
No
Acknowledge
Address
Stop
S
Slave Address
By FM24W256
1 A
Data Byte
Acknowledge
1
P
Data
Figure 7. Current Address Read
By Master
Start
Address
No
Acknowledge
Acknowledge
Stop
S
Slave Address
By FM24W256
1 A
Data Byte
A
Acknowledge
Data Byte
1 P
Data
Figure 8. Sequential Read
Start
Address
By Master
Start
No
Acknowledge
Address
Stop
S
By FM24W256
Slave Address
0 A X
Address MSB
A
Address LSB
A
S
Slave Address
Acknowledge
1 A
Data Byte
1 P
Data
Figure 9. Selective (Random) Read
Rev. 2.0
Jan. 2012
Page 7 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V *
-55C to +125C
260 C
3.5kV
1.25kV
200V
MSL-1 (SOIC)
MSL-2 (EIAJ)
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD =2.7V to 5.5V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Main Power Supply
2.7
3.3
5.5
V
IDD
VDD Supply Current
@ SCL = 100 kHz
100
A
@ SCL = 400 kHz
200
A
@ SCL = 1 MHz
400
A
ISB
Standby Current
15
30
A
ILI
Input Leakage Current
±1
A
ILO
Output Leakage Current
±1
A
VIL
Input Low Voltage
-0.3
0.3*VDD
V
VIH
Input High Voltage
0.7*VDD
VDD + 0.3
V
VOL
Output Low Voltage
@ IOL = 3.0 mA
0.4
V
RIN
Address Input Resistance (WP, A2-A0)
For VIN = VIL (max)
40
K
For VIN = VIH (min)
4
M
Notes
1
2
3
3
4
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4. The input pull-down circuit is strong (40K) when the input voltage is below V IL and weak (4M) when the
input voltage is above VIH.
Rev. 2.0
Jan. 2012
Page 8 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
AC Parameters (TA = -40 C to + 85 C, VDD =2.7V to 5.5V unless otherwise specified)
Symbol Parameter
Min Max Min Max Min
fSCL
SCL Clock Frequency
0
100
0
400
0
tLOW
Clock Low Period
4.7
1.3
0.6
tHIGH
Clock High Period
4.0
0.6
0.4
tAA
SCL Low to SDA Data Out Valid
3
0.9
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
tSP
Bus Free Before New Transmission
Start Condition Hold Time
Start Condition Setup for Repeated
Start
Data In Hold
Data In Setup
Input Rise Time
Input Fall Time
Stop Condition Setup
Data Output Hold
(from SCL @ VIL)
Noise Suppression Time Constant
on SCL, SDA
Max
1000
0.55
Units
kHz
s
s
s
4.7
4.0
4.7
1.3
0.6
0.6
0.5
0.25
0.25
s
s
s
0
250
0
100
0
100
300
100
ns
ns
ns
ns
s
ns
50
ns
1000
300
4.0
0
300
300
0.6
0
50
0.25
0
50
Notes
1
2
2
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1 The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from
DC to 1 MHz.
2 This parameter is periodically sampled and not 100% tested.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3V)
Symbol Parameter
Max
CI/O
Input/Output Capacitance (SDA)
8
CIN
Input Capacitance
6
Units
pF
pF
Notes
1
1
Notes
1 This parameter is periodically sampled and not 100% tested.
Power Cycle Timing
VDD
VDD min.
tVR
tVF
tPU
tPD
SDA,SCL
Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.7V to 5.5V unless otherwise specified)
Symbol Parameter
Min
Max
tPU
Power Up (VDD min) to First Access (Start condition)
10
tPD
Last Access (Stop condition) to Power Down (VDD min)
0
tVR
VDD Rise Time
30
tVF
VDD Fall Time
30
Notes
1. Slope measured at any point on VDD waveform.
Rev. 2.0
Jan. 2012
Units
Notes
ms
s
s/V
s/V
1
1
Page 9 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Equivalent AC Load Circuit
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
5.5V
1700
Diagram Notes
All start and stop timing parameters apply to both read and write cycles.
Clock specifications are identical for read and write cycles. Write timing
parameters apply to slave address, word address, and write data bits.
Functional relationships are illustrated in the relevant datasheet sections.
These diagrams illustrate the timing parameters only.
Output
100 pF
Read Bus Timing
tR
`
tF
t HIGH
t SP
t LOW
t SP
SCL
t SU:SDA
1/fSCL
t BUF
t HD:DAT
t SU:DAT
SDA
Start
t DH
t AA
Stop Start
Acknowledge
Write Bus Timing
t HD:DAT
SCL
t HD:STA
t SU:STO
t SU:DAT
t AA
SDA
Start
Data Retention
Symbol
Parameter
TDR
@ +85ºC
@ +80ºC
@ +75ºC
Rev. 2.0
Jan. 2012
Stop Start
Acknowledge
Min
10
19
38
Max
-
Units
Years
Years
Years
Notes
Page 10 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
0.65
1.27
Pin 1
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.19
0.25
45
0.10 mm
0-8
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXX-P
RLLLLLLL
RICYYWW
Legend:
XXXXXX= part number, P= package type (G=SOIC, EG=EIAJ SOIC)
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24W256, “Green” SOIC package, Year 2010, Work Week 37
FM24W256-G
A00002G1
RIC1037
Rev. 2.0
Jan. 2012
Page 11 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
8-pin EIAJ SOIC (Wide Body)
Recommended PCB Footprint
9.30
5.28 ±0.10
5.00
8.00 ±0.25
D
E
D
S
N
E GN
M SI 6-G
M
5
E
2
O
D 24W
C
E
M
W
F
R E e:
T
N
iv
t
a
O
n
R
N O lter
F A
2.15
0.65
1.27
Pin 1
5.23 ±0.10
1.27
0.36
0.50
0.19
0.25
1.78
2.00
0.05
0.25
0.10 mm
0- 8
0.51
0.76
All dimensions in millimeters.
EIAJ SOIC Package Marking Scheme
XXXXXXX-P
RLLLLLLL
RIC YYWW
Legend:
XXXXXX= part number, P= package type (G=SOIC, EG=EIAJ SOIC)
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24W256, “Green” EIAJ SOIC package, Year 2010, Work Week 37
FM24W256-EG
A00002G1
RIC1037
Rev. 2.0
Jan. 2012
Page 12 of 13
FM24W256 - 256Kb Wide Voltage I2C F-RAM
Revision History
Revision
1.0
1.1
1.2
1.3
2.0
Rev. 2.0
Jan. 2012
Date
11/19/2010
1/17/2011
2/15/2011
7/12/2011
1/6/2012
Summary
Initial Release
Added ESD ratings. Changed VIH (max) to VDD+0.3V.
Changed to MSL-2 for EIAJ package. Changed tPU and tVF spec limits.
EIAJ package is Not Recommended for New Designs (NRND).
Changed to Pre-Production status. Changed tVF spec.
Page 13 of 13
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