Numonyx™ Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3 (x16)
Datasheet
Product Features
Flexible SmartVoltage Technology
— 2.7 V– 3.6 V read/program/erase
— 12 V for fast production programming
1.65 V to 2.5 V or 2.7 V to 3.6 V I/O Option
— Reduces overall system power
High Performance
— 2.7 V– 3.6 V: 70 ns max access time
Optimized Architecture for Code Plus Data
Storage
— Eight 4 Kword blocks, top or bottom
parameter boot
— Up to 127 x 32 Kword blocks
— Fast program suspend capability
— Fast erase suspend capability
Flexible Block Locking
— Lock/unlock any block
— Full protection on power-up
— Write Protect (WP#) pin for hardware block
protection
Low Power Consumption
— 9 mA typical read
— 7 uA typical standby with Automatic Power
Savings feature
Extended Temperature Operation
— -40 °C to +85 °C
128-bit Protection Register
— 64 bit unique device identifier
— 64 bit user programmable OTP cells
Extended Cycling Capability
— Minimum 100,000 block erase cycles
Software
— Supported by Numonyx Advanced Flash
File Managers -- Numonyx™ VFM,
Numonyx™ FDI, etc.
— Code and data storage in the same
memory device
— Robust Power Loss Recovery for Data Loss
Prevention
— Common Flash Interface
Standard Surface Mount Packaging
— 48-Ball μBGA*/VFBGA
— 64-Ball Easy BGA packages
— 48-TSOP package
Intel ETOX* VIII (0.13 μm) Flash Technology
— 8, 16, 32 Mbit
Intel ETOX* VII (0.18 μm) Flash Technology
— 16, 32 Mbit
Intel ETOX* VI (0.25 μm) Flash Technology
— 8, 16 and 32 Mbit
290645-24
March 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet
2
March 2008
290645-24
C3 Discrete
Contents
1.0
Introduction .............................................................................................................. 7
1.1
Nomenclature ..................................................................................................... 7
1.2
Conventions ....................................................................................................... 8
2.0
Functional Overview .................................................................................................. 9
2.1
Product Overview ................................................................................................ 9
2.2
Block Diagram .................................................................................................. 10
2.3
Memory Map..................................................................................................... 10
3.0
Package Information ............................................................................................... 13
3.1
mBGA* and VF BGA Package .............................................................................. 13
3.2
TSOP Package................................................................................................... 14
3.3
Easy BGA Package............................................................................................. 15
4.0
Ballout and Signal Descriptions ............................................................................... 16
4.1
48-Lead TSOP Package ...................................................................................... 16
4.2
64-Ball Easy BGA Package .................................................................................. 19
4.3
Signal Descriptions ............................................................................................ 19
5.0
Maximum Ratings and Operating Conditions............................................................ 21
5.1
Absolute Maximum Ratings................................................................................. 21
5.2
Operating Conditions ......................................................................................... 21
6.0
Electrical Specifications ........................................................................................... 23
6.1
Current Characteristics....................................................................................... 23
6.2
DC Voltage Characteristics.................................................................................. 24
7.0
AC Characteristics ................................................................................................... 26
7.1
AC Read Characteristics ..................................................................................... 26
7.2
AC Write Characteristics ..................................................................................... 30
7.3
Erase and Program Timings ................................................................................ 34
7.4
AC I/O Test Conditions....................................................................................... 34
7.5
Device Capacitance ........................................................................................... 35
8.0
Power and Reset Specifications ............................................................................... 36
8.1
Active Power (Program/Erase/Read) .................................................................... 36
8.2
Automatic Power Savings (APS) .......................................................................... 36
8.3
Standby Power.................................................................................................. 36
8.4
Deep Power-Down Mode..................................................................................... 36
8.5
Power and Reset Considerations .......................................................................... 37
8.5.1 Power-Up/Down Characteristics................................................................ 37
8.5.2 RP# Connected to System Reset .............................................................. 37
8.5.3 VCC, VPP and RP# Transitions.................................................................. 37
8.5.4 Reset Specifications................................................................................ 37
8.6
Power Supply Decoupling ................................................................................... 38
9.0
Device Operations ................................................................................................... 39
9.1
Bus Operations ................................................................................................. 39
9.1.1 Read .................................................................................................... 39
9.1.2 Write .................................................................................................... 39
9.1.3 Output Disable ....................................................................................... 39
9.1.4 Standby ................................................................................................ 39
9.1.5 Reset.................................................................................................... 40
10.0 Modes of Operation ................................................................................................. 41
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Datasheet
3
C3 Discrete
10.1
10.2
10.3
Read Mode........................................................................................................41
10.1.1 Read Array ............................................................................................41
10.1.2 Read Identifier .......................................................................................41
10.1.3 CFI Query ..............................................................................................42
10.1.4 Read Status Register...............................................................................42
10.1.4.1 Clear Status Register .................................................................43
Program Mode...................................................................................................43
10.2.1 12-Volt Production Programming ..............................................................43
10.2.2 Suspending and Resuming Program ..........................................................44
Erase Mode .......................................................................................................44
10.3.1 Suspending and Resuming Erase ..............................................................44
11.0 Security Modes ........................................................................................................48
11.1 Flexible Block Locking.........................................................................................48
11.1.1 Locking Operation...................................................................................48
11.1.1.1 Locked State ............................................................................49
11.1.1.2 Unlocked State .........................................................................49
11.1.1.3 Lock-Down State.......................................................................49
11.2 Reading Block-Lock Status ..................................................................................49
11.3 Locking Operations during Erase Suspend .............................................................49
11.4 Status Register Error Checking ............................................................................50
11.5 128-Bit Protection Register .................................................................................50
11.5.1 Reading the Protection Register ................................................................50
11.5.2 Programming the Protection Register.........................................................51
11.5.3 Locking the Protection Register.................................................................51
11.6 VPP Program and Erase Voltages ..........................................................................51
11.6.1 Program Protection .................................................................................51
Datasheet
4
March 2008
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C3 Discrete
Revision History
Date of
Revision
Version
05/12/98
-001
Original version
-002
48-Lead TSOP package diagram change
μBGA package diagrams change
32-Mbit ordering information change (Section 6)
CFI Query Structure Output Table Change (Table C2)
CFI Primary-Vendor Specific Extended Query Table Change for Optional Features and
Command Support change (Table C8)
Protection Register Address Change
IPPD test conditions clarification (Section 4.3)
μBGA package top side mark information clarification (Section 6)
10/03/98
-003
Byte-Wide Protection Register Address change
VIH Specification change (Section 4.3)
VIL Maximum Specification change (Section 4.3)
ICCS test conditions clarification (Section 4.3)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory
Family.
12/04/98
-004
Added tBHWH/tBHEH and tQVBL (Section 4.6)
Programming the Protection Register clarification (Section 3.4.2)
12/31/98
-005
Removed all references to x8 configurations
02/24/99
-006
Removed reference to 40-Lead TSOP from front page
06/10/99
-007
Added Easy BGA package (Section 1.2)
Removed 1.8 V I/O references
Locking Operations Flowchart changed (Appendix B)
Added tWHGL (Section 4.6)
CFI Primary Vendor-Specific Extended Query changed (Appendix C)
03/20/00
-008
Max ICCD changed to 25 µA
Table 10, added note indicating VCCMax = 3.3 V for 32-Mbit device
04/24/00
-009
Added specifications for 0.18 micron product offerings throughout document Added 64Mbit density
-010
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
Changed VccMax=3.3V reference to indicate that the affected product is the 0.25μm
32Mbit device.
Minor text edits throughout document.
7/20/01
-011
Added 1.8v I/O operation documentation where applicable
Added TSOP PCN ‘Pin-1’ indicator information
Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Information
Removed 0.4 µm references in DC characteristics table
Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA
Corrected ‘bottom’ parameter block sizes to on 8Mb device to 8 x 4KWords
Minor text edits throughout document
10/02/01
-012
Added specifications for 0.13 micron product offerings throughout document
-013
Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
4/05/02
-014
Updated 64Mb product offerings.
Updated 16Mb product offerings.
Revised and corrected DC Characteristics Table.
Added mechanicals for Easy BGA.
Minor text edits throughout document.
3/06/03
-016
Complete technical update.
07/21/98
10/12/00
2/05/02
March 2008
290645-24
Description
Datasheet
5
C3 Discrete
Date of
Revision
Version
10/01/03
-017
Corrected information in the Device Geometry Details table, address 0x34.
5/20/04
-018
Updated the layout of the datasheet.
9/1/04
-019
Fixed typo for Standby power on cover page.
9/14/04
-020
Added lead-free line items to Table 38, “Product Information Ordering Matrix” on page 70.
9/27/04
-021
Added specification for 8Mb 0.13 micron device.
Added 0.13 micron to Table 38, “Product Information Ordering Matrix” on page 70.
1/26/05
-022
Converted datasheet to new template. Deleted Description in Table 4. Deleted Note in
Figure 5.
5/16/05
-023
Removed all 64M ordering information, removed VF BGA 8M ordering information.
Removed 64M reference in title page only. Added software verbiage in title page. Corrected
Lead Width (b) measurement in Fig 2., uBGA and VF BGA Package Drawing and
Dimensions, page 12.
March 2008
24
Datasheet
6
Description
Applied Numnyx branding.
March 2008
290645-24
C3 Discrete
1.0
Introduction
This datasheet contains the specifications for the Numonyx™ Advanced+ Boot Block
Flash Memory (C3) device family, hereafter called the C3 flash memory device. These
flash memories add features such as instant block locking and protection registers that
can be used to enhance the security of systems.
The Numonyx™ Advanced+ Book Block Flash Memory (C3) device, manufactured on
Intel’s latest 0.13 μm and 0.18 μm technologies, represents a feature-rich solution for
low-power applications. The C3 device incorporates low-voltage capability (3 V read,
program, and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Numonyx™
Flash Data Integrator (Numonyx™ FDI) software and you have a cost-effective,
flexible, monolithic code plus data storage solution. Numonyx™ Advanced+ Boot Block
Flash Memory (C3) products are available in 48-lead TSOP, 48-ball CSP, and 64-ball
Easy BGA packages. Additional information on this product family can be obtained from
the Numonyx™ Flash website: http://www.Numonyx.com
1.1
Nomenclature
0x
Hexadecimal prefix
0b
Binary prefix
Byte
8 bits
Word
16 bits
KW or Kword 1024 words
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290645-24
Mword
1,048,576 words
Kb
1024 bits
KB
1024 bytes
Mb
1,048,576 bits
MB
1,048,576 bytes
APS
Automatic Power Savings
CSP
Chip Scale Package
CUI
Command User Interface
OTP
One Time Programmable
PR
Protection Register
PRD
Protection Register Data
PLR
Protection Lock Register
RFU
Reserved for Future Use
SR
Status Register
SRD
Status Register Data
WSM
Write State Machine
Datasheet
7
C3 Discrete
1.2
Conventions
The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package; for chip scale package (CSP) the term ball is used.
Group Membership Brackets: Square brackets will be used to designate group
membership or to define a group of signals with similar function (i.e. A[21:1], SR[4:1])
Set: When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block: A group of bits (or words) that erase simultaneously with one block erase
instruction.
Main Block: A block that contains 32 Kwords.
Parameter Block: A block that contains 4 Kwords.
Datasheet
8
March 2008
290645-24
C3 Discrete
2.0
Functional Overview
This section provides an overview of the Numonyx™ Advanced+ Boot Block Flash
Memory (C3) device features and architecture.
2.1
Product Overview
The C3 flash memory device provides high-performance asynchronous reads in
package-compatible densities with a 16 bit data bus. Individually-erasable memory
blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks
are located in the boot block at either the top or bottom of the device’s memory map.
The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3
V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC
and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O
voltage flexibility, the dedicated VPP input provides complete data protection when VPP
≤ VPPLK.
The C3 Discrete device features a 128-bit protection register enabling security
techniques and data protection schemes through a combination of factory-programmed
and user-programmable OTP data registers. Zero-latency locking/unlocking on any
memory block provides instant and complete protection for critical system code and
data. Additional block lock-down capability provides hardware protection where
software commands alone cannot change the block’s protection status.
A command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence issued to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS),
standby mode, and deep power-down mode. The device automatically enters APS
mode following read cycle completion. Standby mode begins when the system
deselects the flash memory by deasserting Chip Enable, CE#. The deep power-down
mode begins when Reset Deep Power-Down, RP# is asserted, which deselects the
memory and places the outputs in a high-impedance state, producing ultra-low power
savings. Combined, these three power-savings features significantly enhanced power
consumption flexibility.
March 2008
290645-24
Datasheet
9
C3 Discrete
2.2
Figure 1:
Block Diagram
C3 Flash Memory Device Block Diagram
DQ 0-DQ 15
VCCQ
Input Buffer
Identifier
Register
Status
Register
Power
Reduction
Control
Data
Comparator
Y-Decoder
Y-Gating/Sensing
Da ta
Re gi ster
Outp ut
M ulti ple xer
Output Buffer
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
WP#
X-Decoder
Address
Counter
2.3
32- KWord
M ain Blo ck
Address
Latch
4 -KWor d
Para mete r B loc k
32- KWord
M ain Blo ck
Input Buffer
4 -KWor d
Para mete r B loc k
A[MAX:MIN]
Write State
Machine
Program/Erase
Voltage Switch
VPP
VCC
GND
Memory Map
The C3 Discrete device is asymmetrically blocked, which enables system code and data
integration within a single flash device. The bulk of the array is divided into 32 Kword
main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage
of boot code or for frequently changing small parameters. See Table 1, “Top Boot
Memory Map” on page 11 and Table 2, “Bottom Boot Memory Map” on page 12 for
details.
Datasheet
10
March 2008
290645-24
C3 Discrete
Table 1:
Top Boot Memory Map
Size
(KW
)
Blk
8-Mbit
Memory
Addressin
g (Hex)
Size
(KW
)
Blk
16-Mbit
Memory
Addressing
(Hex)
Size
(KW
)
Blk
32-Mbit
Memory
Addressin
g (Hex)
Size
(KW
)
Blk
64-Mbit
Memory
Addressing
(Hex)
4
22
7F0007FFFF
4
38
FF000-FFFFF
4
70
1FF0001FFFFF
4
134
3FF000-3FFFFF
4
21
7E0007EFFF
4
37
FE000-FEFFF
4
69
1FE0001FEFFF
4
133
3FE000-3FEFFF
4
20
7D0007DFFF
4
36
FD000-FDFFF
4
68
1FD0001FDFFF
4
132
3FD000-3FDFFF
4
19
7C0007CFFF
4
35
FC000-FCFFF
4
67
1FC0001FCFFF
4
131
3FC000-3FCFFF
4
18
7B0007BFFF
4
34
FB000-FBFFF
4
66
1FB0001FBFFF
4
130
3FB000-3FBFFF
4
17
7A0007AFFF
4
33
FA000-FAFFF
4
65
1FA0001FAFFF
4
129
3FA000-3FAFFF
4
16
7900079FFF
4
32
F9000-F9FFF
4
64
1F90001F9FFF
4
128
3F9000-3F9FFF
4
15
7800078FFF
4
31
F8000-F8FFF
4
63
1F80001F8FFF
4
127
3F8000-3F8FFF
32
14
7000077FFF
32
30
F0000-F7FFF
32
62
1F00001F7FFF
32
126
3F0000-3F7FFF
32
13
680006FFFF
32
29
E8000-EFFFF
32
61
1E80001EFFFF
32
125
3E8000-3EFFFF
32
12
6000067FFF
32
28
E0000-E7FFF
32
60
1E00001E7FFF
32
124
3E0000-3E7FFF
32
11
580005FFFF
32
27
D8000-DFFFF
32
59
1D80001DFFFF
32
123
3D8000-3DFFFF
...
...
...
...
...
...
...
...
...
...
...
...
32
2
1000017FFF
32
2
10000-17FFF
32
2
1000017FFF
32
2
10000-17FFF
32
1
8000-0FFFF
32
1
08000-0FFFF
32
1
080000FFFF
32
1
08000-0FFFF
32
0
0000-07FFF
32
0
00000-07FFF
32
0
0000007FFF
32
0
00000-07FFF
March 2008
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Datasheet
11
C3 Discrete
Table 2:
Bottom Boot Memory Map
Size
(KW
)
Blk
8-Mbit
Memory
Addressin
g (Hex)
Size
(KW
)
Blk
16-Mbit
Memory
Addressing
(Hex)
Size
(KW
)
Blk
32-Mbit
Memory
Addressing
(Hex)
Size
(KW
)
Blk
64-Mbit
Memory
Addressing
(Hex)
32
22
780007FFFF
32
38
F8000-FFFFF
32
70
1F80001FFFFF
32
134
3F8000-3FFFFF
32
21
7000077FFF
32
37
F0000-F7FFF
32
69
1F00001F7FFF
32
133
3F0000-3F7FFF
32
20
680006FFFF
32
36
E8000-EFFFF
32
68
1E80001EFFFF
32
132
3E8000-3EFFFF
32
19
6000067FFF
32
35
E0000-E7FFF
32
67
1E00001E7FFF
32
131
3E0000-3E7FFF
...
...
...
...
...
...
...
...
...
.
...
...
32
10
180001FFFF
32
10
18000-1FFFF
32
10
18000-1FFFF
32
10
18000-1FFFF
32
9
1000017FFF
32
9
10000-17FFF
32
9
10000-17FFF
32
9
10000-17FFF
32
8
080000FFFF
32
8
08000-0FFFF
32
8
08000-0FFFF
32
8
08000-0FFFF
4
7
0700007FFF
4
7
07000-07FFF
4
7
07000-07FFF
4
7
07000-07FFF
4
6
0600006FFF
4
6
06000-06FFF
4
6
06000-06FFF
4
6
06000-06FFF
4
5
0500005FFF
4
5
05000-05FFF
4
5
05000-05FFF
4
5
05000-05FFF
4
4
0400004FFF
4
4
04000-04FFF
4
4
04000-04FFF
4
4
04000-04FFF
4
3
0300003FFF
4
3
03000-03FFF
4
3
03000-03FFF
4
3
03000-03FFF
4
2
0200002FFF
4
2
02000-02FFF
4
2
02000-02FFF
4
2
02000-02FFF
4
1
0100001FFF
4
1
01000-01FFF
4
1
01000-01FFF
4
1
01000-01FFF
4
0
0000000FFF
4
0
00000-00FFF
4
0
00000-00FFF
4
0
00000-00FFF
Datasheet
12
March 2008
290645-24
C3 Discrete
3.0
Package Information
3.1
μBGA* and VF BGA Package
Figure 2:
μBGA* and VF BGA Package Drawing and Dimensions
C3 Discrete 8/16/32/64M,
.25,.18, .13u ubga/VFBGA
R0
Ball A1
Corner
D
1
E
2
3
4
S1
5
6
7
8
8
A
A
B
B
C
C
D
D
E
E
F
F
7
6
4
5
3
Ball A1
Corner
S2
2 1
e
b
Bottom View -Bump side up
Top View - Bump Side down
A
1
A2
A
Seating
Y
Plan
Side View
Note: Drawing not to scale
Dimensions
Symbol
Package Height
A
Ball Height
A1
Package Body Thickness
A2
Ball (Lead) Width
b
Package Body Length 8M (.25)
D
Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13)
D
Package Body Length 64M (.18)
D
Package Body Width 8M (.25)
E
Package Body Width 16M (.25/.18/.13) 32M (.18/.13)
E
Package Body Width 32M (.25)
E
Package Body Width 64M (.18)
E
Pitch
e
Ball (Lead) Count 8M, 16M
N
Ball (Lead) Count 32M
N
Ball (Lead) Count 64M
N
Seating Plane Coplanarity
Y
Corner to Ball A1 Distance Along D 8M (.25)
S1
Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13)
S1
Corner to Ball A1 Distance Along D 64M (.18)
S1
Corner to Ball A1 Distance Along E 8M (.25)
S2
Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13)
S2
Corner to Ball A1 Distance Along E 32M (.25)
S2
Corner to Ball A1 Distance Along E 64M (.18)
S2
March 2008
290645-24
Min
Millimeters
Nom
Max
1.000
0.150
0.325
7.810
7.186
7.600
6.400
6.864
10.750
8.900
1.230
0.918
1.125
1.275
1.507
3.450
2.525
Min
Inches
Nom
Max
0.0394
0.0059
0.665
0.375
7.910
7.286
7.700
6.500
6.964
10.850
9.000
0.750
46
47
48
1.330
1.018
1.225
1.375
1.607
3.550
2.625
0.0128
0.0262
0.0148
0.425
8.010
7.386
7.800
6.600
7.064
10.860
9.100
0.2829
0.2992
0.2520
0.2702
0.4232
0.3504
0.2868
0.3031
0.2559
0.2742
0.4272
0.3543
0.0295
46
47
48
0.100
1.430
1.118
1.325
1.475
1.707
3.650
2.725
0.0484
0.0361
0.0443
0.0502
0.0593
0.1358
0.0994
0.0524
0.0401
0.0482
0.0541
0.0633
0.1398
0.1033
0.0167
0.2908
0.3071
0.2598
0.2781
0.4276
0.3583
0.0039
0.0563
0.0440
0.0522
0.0581
0.0672
0.1437
0.1073
Datasheet
13
C3 Discrete
3.2
TSOP Package
Figure 3:
TSOP Package Drawing and Dimensions
Z
A2
See Notes 1, 2, 3 and 4
Pin 1
e
See Detail B
E
Y
D1
A1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
b
0
L
Notes:
1.
One dimple on package denotes Pin 1.
2.
If two dimples, then the larger dimple denotes Pin 1.
3.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Table 3:
TSOP Package Dimensions
Millimeters
Parameter
Inches
Symbol
Min
Package Height
A
Nom
Max
Min
Nom
1.200
Standoff
A1
0.050
Package Body Thickness
A2
0.950
Max
0.047
0.002
1.000
1.050
0.037
0.039
0.041
Lead Width
b
0.150
0.200
0.300
0.006
0.008
0.012
Lead Thickness
c
0.100
0.150
0.200
0.004
0.006
0.008
Package Body Length
D1
18.200
18.400
18.600
0.717
0.724
0.732
Package Body Width
E
11.800
12.000
12.200
0.465
0.472
0.480
Lead Pitch
e
Terminal Dimension
D
19.800
20.000
20.200
0.780
0.787
0.795
Lead Tip Length
L
0.500
0.600
0.700
0.020
0.024
0.028
Lead Count
N
Lead Tip Angle
Θ
Seating Plane Coplanarity
Y
Lead to Package Offset
Z
Datasheet
14
0.500
0.0197
48
0°
3°
48
5°
0°
3°
0.100
0.150
0.250
0.350
5°
0.004
0.006
0.010
0.014
March 2008
290645-24
C3 Discrete
3.3
Figure 4:
Easy BGA Package
Easy BGA Package Drawing and Dimension
Ball A1
Corner
D
1
E
2
3
4
Ball A1
Corner
S1
5
6
7
8
8
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
7
6
5
4
3
2
1
S2
b
e
Top View - Ball side down
Bottom View - Ball Side Up
A1
A2
A
Seating
Y
Plane
Side View
Note: Drawing not to scale
Dimensions Table
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Symbol
A
A1
A2
b
D
E
[e]
N
Y
S1
S2
Millimeters
Min
Nom
Max
1.200
Notes
0.250
0.330
9.900
12.900
1.400
2.900
Inches
Min
Nom
Max
0.0472
0.0098
0.780
0.430
10.000
13.000
1.000
64
1.500
3.000
0.530
10.100
13.100
1
1
0.0130
0.3898
0.5079
0.100
1.600
3.100
1
1
0.0551
0.1142
0.0307
0.0169
0.3937
0.5118
0.0394
64
0.0591
0.1181
0.0209
0.3976
0.5157
0.0039
0.0630
0.1220
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
March 2008
290645-24
Datasheet
15
C3 Discrete
4.0
Ballout and Signal Descriptions
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball μBGA, and Easy
BGA packages. See Figure 5 on page 16, Figure 7 on page 18, and Figure 8 on
page 19, respectively.
4.1
48-Lead TSOP Package
Figure 5:
48-Lead TSOP Package
64 M
32 M
16 M
Datasheet
16
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
March 2008
290645-24
C3 Discrete
Figure 6:
Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-Mb and 32-Mb TSOP
Current M ark:
New M ark:
Note:
Table 4:
The topside marking on 8 Mb, 16 Mb, and 32 Mb Numonyx™ Advanced and Advanced +
Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator.
Products without the white triangle will continue to use a dimple as a Pin 1 indicator.
There are no other changes in package size, materials, functionality, customer
handling, or manufacturability. Product will continue to meet Numonyx stringent quality
requirements. Products affected are Numonyx Ordering Codes shown in Table 4.
48-Lead TSOP
Extended 64 Mbit
Extended
Extended 32 Mbit
Extended 16 Mbit
TE28F320C3TD70
TE28F320C3BD70
TE28F160C3TD70
TE28F160C3BD70
TE28F800C3TA90
TE28F800C3BA90
TE28F320C3TC70
TE28F320C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC90
TE28F320C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100
TE28F160C3TA110
TE28F160C3BA110
TE28F320C3TA110
TE28F320C3BA110
March 2008
290645-24
Datasheet
17
C3 Discrete
Figure 7:
48-Ball µBGA* and 48-Ball VF BGA Chip Scale Package (Top View, Ball
Down)1,2,3
1
2
3
4
5
6
7
8
16M
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
WE#
RP#
A18
A17
A5
A2
64M
32M
C
A15
A12
A9
A21
A20
A6
A3
A1
D
A16
D14
D5
D11
D2
D8
CE#
A0
E
VCCQ
D15
D6
D12
D3
D9
D0
GND
F
GND
D7
D13
D4
VCC
D10
D1
OE#
Notes:
1.
Shaded connections indicate the upgrade address connections. Numonyx recommends to not use routing in this area.
2.
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
3.
Unused address balls are not populated.
Datasheet
18
March 2008
290645-24
C3 Discrete
4.2
64-Ball Easy BGA Package
Figure 8:
64-Ball Easy BGA Package1,2
1
2
3
4
5
6
7
8
A
8
7
6
5
4
3
2
1
VPP
A18
A
A1
A6
A18
VPP
VCC GND A10
A15
B
A15
A10 GND VCC
A6
A1
A14
A11 A20(1) DU RP# A19(1) A17
A2
A13
A12 A21(1) DU WE# WP# A7
A3
A9
A8
A4
B
A2
A17 A19(1) RP# DU A20(1) A11
A14
C
C
A3
A7
WP# WE# DU A21(1) A12
A13
D
D
A4
A5
DU
DU
DU DU
A8
A9
DQ8 DQ1 DQ9 DQ3 DQ12 DQ6
DU
DU
E
DU
DU
DU DU
A5
E
F
DU
DU DQ6 DQ12 DQ3 DQ9 DQ1 DQ8
DU
DU DQ14 DQ5 DQ11 DQ10 DQ0 CE#
F
CE# DQ0 DQ10 DQ11 DQ5 DQ14 DU
DU
G
G
A0
VSSQ DQ2 DQ4 DQ13 DQ15 VSSQ A16
H
A16 VSSQ D15
D13
DQ4 DQ2 VSSQ
A0
DU VCCQ
VSSQ VCC VCCQ OE# A22(2)
H
A22(2) OE# VCCQ VCC VSSQ DQ7 VCCQ
DU
Top View- Ball Side
D7
Bottom View - Ball Side
Notes:
1.
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2.
Unused address balls are not populated.
4.3
Table 5:
Symbol
Signal Descriptions
Signal Descriptions
Type
Description
A[MAX:0]
Input
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DQ[15:0]
Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
CE#
Input
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
OE#
Input
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
Input
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
RP#
March 2008
290645-24
Datasheet
19
C3 Discrete
Table 5:
Signal Descriptions
Symbol
Type
Description
WE#
Input
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of the WE# pulse.
Input
WRITE PROTECT: Active-low input.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be
unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are
now locked and can be unlocked and locked through software. After WP# goes low, any blocks
previously marked lock-down revert to the lock-down state.
See Section 11.0, “Security Modes” on page 48 for details on block locking.
VPP
Input/
Power
PROGRAM/ERASE Power Supply: Operates as an input at logic levels to control complete device
protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. Do not
leave this pin floating.
Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands.
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can drop
as low as 1.65 V to allow for resistor or diode drop from the system supply.
Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5%
to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the boot
blocks. VPP can be connected to 12 V for a total of 80 hours maximum. See Section 11.6 for details
on VPP voltage configurations.
VCC
Power
DEVICE CORE Power Supply: Supplies power for device operations.
VCCQ
Power
OUTPUT Power Supply: Output-driven source voltage. This ball can be tied directly to VCC if
operating within VCC range.
GND
Power
Ground: For all internal circuitry. All ground inputs must be connected.
DU
—
Do Not Use: Do not use this ball. This ball must not be connected to any power supplies, signals or
other balls,; it must be left floating.
NC
—
No Connect
WP#
Datasheet
20
March 2008
290645-24
C3 Discrete
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These ratings are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended, and extended exposure beyond the “Operating
Conditions” may affect device reliability.
.
NOTICE: Specifications are subject to change without notice. Verify with your local Numonyx Sales office that you have the
latest datasheet before finalizing a design.
Parameter
Maximum Rating
Notes
Extended Operating Temperature
During Read
–40 °C to +85 °C
During Block Erase and Program
–40 °C to +85 °C
Temperature under Bias
–40 °C to +85 °C
Storage Temperature
–65 °C to +125 °C
Voltage On Any Pin (except VCC and VPP) with Respect to GND
–0.5 V to +3.7 V
VPP Voltage (for Block Erase and Program) with Respect to GND
–0.5 V to +13.5 V
VCC and VCCQ Supply Voltage with Respect to GND
–0.2 V to +3.6 V
Output Short Circuit Current
100 mA
1
1,2,3
4
Notes:
1.
Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V
for periods
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