THIS SPEC IS OBSOLETE
Spec No: 001-52037
Spec Title: STK14D88 32KX8 AUTOSTORE NVSRAM
Sunset Owner: Girija Chougala (GVCH)
Replaced by: None
STK14D88
32Kx8 AutoStore nvSRAM
Features
Description
■
25, 35, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V +20%, -10% Power Supply
■
Commercial, Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
Logic Block Diagram
VCCX
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INPUT BUFFERS
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
Quantum Trap
512 x 512
VCAP
POWER
CONTROL
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
COLUMN I/O
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52037 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 02, 2011
STK14D88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics .............................................................. 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
SRAM READ Cycles #1 and #2 ..................................... 6
SRAM WRITE Cycle #1 and #2 ..................................... 7
AutoStore/POWER UP RECALL ......................................... 8
Software-Controlled STORE/RECALL Cycle..................... 9
Hardware STORE Cycle ..................................................... 10
Soft Sequence Commands ............................................... 10
Mode Selection ................................................................... 11
Document Number: 001-52037 Rev. *B
nvSRAM Operation............................................................ 12
nvSRAM ....................................................................... 12
SRAM READ ................................................................ 12
SRAM WRITE .............................................................. 12
AutoStore Operation...................................................... 12
Hardware STORE (HSB) Operation............................. 12
Software STORE.......................................................... 12
Software RECALL ........................................................ 13
Data Protection............................................................. 13
Best Practices .............................................................. 13
Low Average Active Power .......................................... 13
Noise Considerations ................................................... 14
Preventing AutoStore ................................................... 14
Part Numbering Nomenclature......................................... 16
Package Diagrams............................................................. 17
Document History Page ..................................................... 19
Sales, Solutions, and Legal Information ......................... 19
Worldwide Sales and Design Support.......................... 19
Products ....................................................................... 19
Page 2 of 18
STK14D88
Pin Configurations
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
32-SOIC
48-Pin SSOP
VCAP
1
48
NC
A14
2
47
3
46
A12
A7
4
5
45
44
A6
A5
6
43
7
42
HSB
W
A13
A8
A9
NC
A4
8
41
NC
9
40
A11
NC
10
39
NC
NC
NC
11
38
NC
37
VSS
13
36
NC
NC
14
35
15
34
DQ0
16
33
A3
A2
17
32
G
18
31
A10
A1
19
30
E
A0
DQ1
DQ2
20
29
21
28
22
23
27
26
DQ7
DQ5
DQ4
DQ3
24
25
VCC
TOP
VCAP
1
32
VCC
A14
2
31
HSB
A12
A7
3
30
4
A6
A5
5
29
28
6
27
W
A13
A8
A9
A4
A3
7
26
A11
8
25
NC
A2
9
24
G
NC
10
23
A10
11
22
NC
A1
A0
12
21
E
DQ7
VSS
NC
DQ0
DQ1
13
20
DQ6
14
19
DQ5
NC
DQ6
DQ2
VSS
15
18
16
17
DQ4
DQ3
TOP
Relative PCB Area Usage[1]
SSOP
NC
NC
12
VCC
NC
Pin Descriptions
Pin Name
I/O
Description
A14-A0
Input
DQ7-DQ0
I/O
E
Input
Chip Enable: The active low E input selects the device
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
VCC
HSB
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Power Supply Power: 3.0V, +20%, -10%
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin
high if not connected. (Connection Optional).
VCAP
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply Ground
NC
No Connect
Unlabeled pins have no internal connections.
Note
1. See “Package Diagrams” on page 16 for detailed package size specifications.
Document Number: 001-52037 Rev. *B
Page 3 of 18
STK14D88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS ...........–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55C to 125C
Storage Temperature .................................... –65C to 140C
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
jc 5.4 C/W; ja 44.3 [0 fpm], 37.9 [200 fpm], 35.1 C/W [500 fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
jc 6.2 C/W; ja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm].
DC Characteristics
(VCC = 2.7V-3.6V)
Symbol
Parameter[2]
Commercial
Min
Max
Industrial
Min
Max
Unit
Notes
ICC1
Average VCC Current
65
55
50
70
60
55
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
Dependent on output loading and
cycle rate. Values obtained without
output loads.
ICC2
Average VCC Current during
STORE
3
3
mA
All Inputs Don’t Care, VCC = max
Average current for duration of
STORE cycle (tSTORE)
ICC3
Average VCC Current at tAVAV =
200ns
3V, 25°C, Typical
10
10
mA
W (V CC – 0.2V)
All Others Cycling, CMOS Levels
Dependent on output loading and
cycle rate. Values obtained without
output loads.
ICC4
Average VCAP Current during
AutoStore Cycle
3
3
mA
All Inputs Don’t Care
Average current for duration of
STORE cycle (tSTORE)
ISB
VCC Standby Current
(Standby, Stable CMOS Input
Levels)
3
3
mA
E (V CC – 0.2V)
All Others VIN 0.2V or (VCC – 0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
1
1
A
VCC = max
VIN = VSS to VCC
IOLK
Off State Output Leakage Current
1
1
A
VCC = max
VIN = VSS to VCC, E or G VIH
VIH
Input Logic “1” Voltage
2.0
VCC + .5
2.0
VCC + .5
V
All Inputs
VSS – .5
0.8
VSS – .5
0.8
VIL
Input Logic “0” Voltage
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
2.4
2.4
0.4
0.4
V
All Inputs
V
IOUT = – 2 mA
V
IOUT = 4 mA
Note:
2. The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested
Document Number: 001-52037 Rev. *B
Page 4 of 18
STK14D88
DC Characteristics (continued)
(VCC = 2.7V-3.6V)
Commercial
Parameter[2]
Symbol
TA
Operating Temperature
Industrial
Min
Max
Min
Max
0
70
- 40
85
Unit
Notes
C
VCC
Operating Voltage
2.7
3.6
2.7
3.6
V
3.3V +20%, -10%
VCAP
Storage Capacitance
17
120
17
120
F
Between VCAP pin and VSS, 5V Rated
DATAR
Data Retention
20
20
NVC
Nonvolatile STORE Operations
200
200
K
Years At 55C
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................
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