PSMN4R2-40VSHX

PSMN4R2-40VSH Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 16 August 2021 Product data sheet 1. General description D1 Dual, standard level N-channel MOSFET in an LFPAK56D package (halfbridge configuration), using NextpowerS3 technology. An internal connection is made between the source (S1) of the high-side FET to the drain (D2) of the low-side FET, making the device ideal to use as a half-bridge switch in high-performance PWM and space constrained motor drive applications G1 S1, D2 G2 S2 aaa-028081 2. Features and benefits • • • • • • • LFPAK56D package with half-bridge configuration enables: • Reduced PCB layout complexity • Module shrinkage through reduced component count • Improved system level Rth(j-amb) due to optimized package design • Lower parasitic inductance to support higher efficiency • Footprint compatibility with LFPAK56D Dual package NextpowerS3 technology Low power losses, high power density Superior avalanche performance Repetitive avalanche rated LFPAK copper clip packaging provides high robustness and reliability Gull wing leads support high manufacturability and Automated Optical Inspection (AOI) 3. Applications • • • • Handheld power tools, portable appliance and space constrained applications Brushless or brushed DC motor drive DC-to-DC systems LED lighting 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit - - 40 V - - 98 A - - 85 W -55 - 175 °C Limiting values FET1 and FET2 VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 Ptot total power dissipation Tmb = 25 °C; Fig. 1 Tj junction temperature [1] PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Typ Max Unit VGS = 10 V; ID = 20 A; Tj = 25 °C; Fig. 8 - 3.5 4.2 mΩ 1.4 4.7 9.4 nC 17 26 37 nC Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge QG(tot) total gate charge [1] ID = 20 A; VDS = 32 V; VGS = 10 V; Fig. 10; Fig. 11 98A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S2 source2 2 G2 gate2 3 S1 source1 4 G1 gate1 5 D1 drain1 6 D1 drain1 7 S1, D2 source1, drain2 8 S1, D2 source1, drain2 Simplified outline 8 7 6 Graphic symbol 5 D1 G1 S1, D2 G2 1 2 3 4 S2 LFPAK56D; Dual LFPAK (SOT1205) aaa-028081 6. Ordering information Table 3. Ordering information Type number Package PSMN4R2-40VSH Name Description Version LFPAK56D; Dual LFPAK plastic, single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code PSMN4R2-40VSH 4H2S40V 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Limiting values FET1 and FET2 VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VDSM peak drain-source voltage tp = 20 ns; f = 500 kHz; EDS(AL) = 200 nJ; pulsed - 45 V PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Max Unit VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 40 V VGS gate-source voltage Tj ≤ 175 °C -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 85 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 98 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 69.5 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 393 A [1] IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 85 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 393 A - 42.3 mJ - 82.6 A Avalanche ruggedness FET1 and FET2 EDS(AL)S non-repetitive drainID = 82.6 A; Vsup ≤ 40 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 20 µs IAS non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω [1] [2] [2] 98A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Protected by 100% test 03aa16 120 Pder (%) aaa-032380 100 ID (A) 80 80 60 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Fig. 2. Product data sheet 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 10 V (1) 98A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Normalized total power dissipation as a function of mounting base temperature PSMN4R2-40VSH 0 Continuous drain current as a function of mounting base temperature, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) ID (A) aaa-032382 103 Limit RDSon = VDS / ID 102 tp = 10 µs 100 µs 10 DC 1 ms 10 ms 100 ms 1 10-1 10-1 1 10 102 VDS (V) Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and FET2 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Rth(j-mb) Conditions thermal resistance from Fig. 4 junction to mounting base Min Typ Max Unit - 1.64 1.76 K/W aaa-032383 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 P 10-1 0.05 δ= tp T 0.02 single shot 10-2 10-6 Fig. 4. 10-5 t tp 10-4 10-3 10-2 T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and FET2 PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 2.4 3 3.6 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -6.2 - mV/K IDSS drain leakage current VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.01 1 µA VDS = 16 V; VGS = 0 V; Tj = 125 °C - 0.3 10 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA Static characteristics FET1 and FET2 V(BR)DSS IGSS gate leakage current VGS = -20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA RDSon drain-source on-state resistance VGS = 10 V; ID = 20 A; Tj = 25 °C; Fig. 8 - 3.5 4.2 mΩ VGS = 10 V; ID = 20 A; Tj = 175 °C; Fig. 9 - - 8.8 mΩ gate resistance f = 1 MHz; Tj = 25 °C 0.72 1.8 4.5 Ω ID = 20 A; VDS = 32 V; VGS = 10 V; Fig. 10; Fig. 11 17 26 37 nC ID = 0 A; VDS = 0 V; VGS = 10 V - 13 - nC ID = 20 A; VDS = 32 V; VGS = 10 V; Fig. 10; Fig. 11 4.7 7.8 12 nC 3 5.1 7.7 nC RG Dynamic characteristics FET1 and FET2 QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gatesource charge QGS(th-pl) post-threshold gatesource charge 1.6 2.7 4 nC QGD gate-drain charge 1.4 4.7 9.4 nC VGS(pl) gate-source plateau voltage ID = 20 A; VDS = 32 V; Fig. 10; Fig. 11 - 4.4 - V Ciss input capacitance 1202 1850 2590 pF Coss output capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 12 367 565 791 pF Crss reverse transfer capacitance 27 91 200 pF td(on) turn-on delay time - 7 - ns tr rise time - 9 - ns td(off) turn-off delay time - 19 - ns tf fall time - 11.8 - ns Qoss output charge VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C - 22 - nC IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 13 - 0.81 1 V VDS = 30 V; RL = 1.5 Ω; VGS = 10 V; RG(ext) = 5 Ω Source-drain diode FET1 and FET2 VSD source-drain voltage PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 5 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) Symbol Parameter Conditions Min Typ Max Unit trr reverse recovery time - 18.6 - ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Fig. 14 [1] - 9.2 - nC ta reverse recovery rise time - 10.3 - ns tb reverse recovery fall time - 8.2 - ns [1] includes capacitive recovery ID (A) aaa-032384 80 VGS = 5.5 V 5V 64 8 48 6 10 V 32 0 Fig. 5. 4 4.5 V 16 2 4V 0 1 2 3 VDS (V) aaa-032385 10 RDSon (mΩ) 0 4 0 4 8 12 16 VGS (V) 20 Tj = 25 °C Tj = 25 °C; ID = 20 A Output characteristics; drain current as a Fig. 6. function of drain-source voltage; typical values, FET1 and FET2 Drain-source on-state resistance as a function of gate-source voltage; typical values, FET1 and FET2 aaa-033171 160 ID (A) aaa-032387 20 RDSon (mΩ) 4.5 V 5V 16 120 12 80 8 40 175°C 5.5 V 4 25°C 6V 0 0 1 2 3 4 5 6 VGS (V) 0 7 VDS = 8 V Fig. 7. Product data sheet 16 32 48 64 ID (A) 80 Tj = 25 °C Transfer characteristics; drain current as a function of gate-source voltage; typical values, FET1 and FET2 PSMN4R2-40VSH 0 VGS = 10 V 8V Fig. 8. Drain-source on-state resistance as a function of drain current; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) a aaa-032388 2.4 VGS (V) aaa-032389 10 8 1.8 6 1.2 32 V 4 VDS = 14 V 0.6 0 -60 2 -30 0 30 60 90 120 150 Tj (°C) 0 180 0 4 8 12 16 20 24 28 QG (nC) 32 Tj = 25 °C; ID = 20 A Fig. 9. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 and FET2 Fig. 10. Gate-source voltage as a function of gate charge; typical values, FET1 and FET2 aaa-032390 104 C (pF) VDS ID Ciss 103 Coss VGS(pl) 102 VGS(th) Crss VGS QGS2 QGS1 QGS 10 10-1 QGD QG(tot) PSMN4R2-40VSH Product data sheet 10 VDS (V) 102 VGS = 0 V; f = 1 MHz 003aaa508 Fig. 11. Gate charge waveform definitions 1 Fig. 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) IS (A) 003aal160 aaa-033170 102 ID (A) trr ta tb 0 10 0.25 IRM 175°C 1 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) IRM t (s) 1.2 VGS = 0 V Fig. 14. Reverse recovery timing definition Fig. 13. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1 and FET2 PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads E SOT1205 A A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 mm 5 mm scale Dimensions Unit y C A max 1.05 nom min 1.02 D(1) D1(1) D2 (ref) E(1) E1(1) 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 A1 b b1 0.1 0.50 0.0 0.35 c c1 E2 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 w y 0.25 0.1 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA θ 8° 0° sot1205_po European projection Issue date 14-08-21 14-10-28 SOT1205 Fig. 15. Package outline LFPAK56D; Dual LFPAK (SOT1205) PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 12. Soldering Footprint information for reflow soldering of LFPAK56D package SOT1205 5.85 0.57 0.025 0.57 0.7 1.97 0.65 1.27 1.9 3.325 3.175 3.2 2.0 1.275 0.8 1.875 2.1 2.7 1.0 3.85 3.975 0.025 1.1 1.15 0.65 1.27 1.1 1.44 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm Issue date 0.7 14-07-28 20-04-20 sot1205_fr Fig. 16. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205) PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 PSMN4R2-40VSH Nexperia Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 16 August 2021 PSMN4R2-40VSH Product data sheet All information provided in this document is subject to legal disclaimers. 16 August 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12