S-8211E Series
www.ablic.com
www.ablicinc.com
BATTERY PROTECTION IC
FOR 1-CELL PACK
Rev.2.4_03
© ABLIC Inc., 2009-2015
The S-8211E Series has high-accuracy voltage detections circuit and delay circuits.
The S-8211E Series is suitable for monitoring overcharge and overdischarge of 1-cell lithium ion / lithium polymer
rechargeable battery pack.
Features
(1) High-accuracy voltage detection circuit
Overcharge detection voltage
(2)
(3)
(4)
(5)
(6)
3.6 V to 4.5 V (5 mV step)
Accuracy 25 mV (25C)
Accuracy 30 mV (5C to 55C)
Accuracy 50 mV
Accuracy 50 mV
Accuracy 100 mV
Overcharge release voltage
3.5 V to 4.4 V*1
Overdischarge detection voltage
2.0 V to 3.0 V (10 mV step)
*2
Overdischarge release voltage
2.0 V to 3.4 V
Detection delay times are generated by an internal circuit
(external capacitors are unnecessary)
Accuracy 20%
Wide operating temperature range
40C to 85C
Low current consumption
During operation
3.0 A typ., 5.5 A max. (25C)
During overdischarge
2.0 A typ., 3.5 A max. (25C)
Output logic of CO pin is selectable.
Active “H”, Active “L”
Lead-free, Sn 100%, halogen-free*3
*1. Overcharge release voltage = Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.)
*2. Overdischarge release voltage = Overdischarge detection voltage Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.)
*3. Refer to “ Product Name Structure” for details.
Applications
Lithium-ion rechargeable battery pack
Lithium-polymer rechargeable battery pack
Packages
SOT-23-5
SNT-6A
1
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Block Diagram
VDD
Output control circuit
DO
Divider control
circuit
＋
Oscillator control
circuit
－
Overcharge
detection
comparator
CO
＋
－
Overdischarge
detection
comparator
VM
VSS
Remark All diodes shown in figure are parasitic diodes.
Figure 1
2
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Product Name Structure
1. Product Name
S-8211E
xx
-
xxxx
U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
2. Packages
Package Name
SOT-23-5
SNT-6A
Package
MP005-A-P-SD
PG006-A-P-SD
Drawing Code
Tape
Reel
MP005-A-C-SD
MP005-A-R-SD
PG006-A-C-SD
PG006-A-R-SD
Land
PG006-A-L-SD
3
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
3. Product Name List
3. 1 SOT-23-5
Table 1
Overcharge
Detection
Voltage
[VCU]
Overcharge
Release
Voltage
[VCL]
Overdischarge
Detection
Voltage
[VDL]
Overdischarge
Release
Voltage
[VDU]
Delay Time
Combination*1
CO Pin
Output Form
S-8211EAF-M5T1U
3.600 V
3.650 V
3.600 V
3.550 V
2.00 V
2.00 V
2.00 V
2.30 V
(1)
(2)
CMOS output active “L”
CMOS output active “L”
S-8211EAG-M5T1U
3.800 V
3.600 V
2.00 V
2.30 V
(2)
CMOS output active “L”
S-8211EAJ-M5T1U
4.180 V
4.180 V
2.50 V
3.00 V
(1)
CMOS output active “H”
S-8211EAK-M5T1U
3.600 V
3.600 V
2.00 V
2.30 V
(1)
CMOS output active “H”
Product Name
S-8211EAC-M5T1U
*1. Refer to the Table 3 about the details of the delay time combinations (1), (2).
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
3. 2 SNT-6A
Table 2
Overcharge
Detection
Voltage
[VCU]
Overcharge
Release
Voltage
[VCL]
Overdischarge
Detection
Voltage
[VDL]
Overdischarge
Release
Voltage
[VDU]
S-8211EAB-I6T1U
4.220 V
4.270 V
4.220 V
4.270 V
2.00 V
2.00 V
2.00 V
2.00 V
S-8211EAD-I6T1U
4.220 V
4.220 V
2.50 V
2.50 V
S-8211EAE-I6T1U
4.220 V
4.220 V
2.30 V
2.30 V
S-8211EAH-I6T1U
4.000 V
3.800 V
3.00 V
S-8211EAI-I6T1U
3.800 V
3.700 V
2.30 V
S-8211EAP-I6T1U
4.280 V
4.080 V
2.50 V
Product Name
S-8211EAA-I6T1U
Delay Time
Combination*1
CO Pin
Output Form
(2)
CMOS output active “L”
(2)
CMOS output active “L”
(2)
CMOS output active “L”
CMOS output active “L”
3.20 V
(2)
(1)
2.40 V
(1)
CMOS output active “L”
2.50 V
(1)
CMOS output active “L”
CMOS output active “L”
*1. Refer to the Table 3 about the details of the delay time combinations (1), (2).
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
Table 3
Delay Time
Combination
Overcharge Detection Delay Time
[tCU]
Overdischarge Detection Delay Time
[tDL]
(1)
(2)
1.2 s
573 ms
150 ms
300 ms
Remark
The delay times can be changed within the range listed Table 4. For details, please contact our sales office.
Table 4
Delay Time
Selection Range
Remark
Overcharge detection delay time
tCU
143 ms
573 ms
1.2 s
Select a value from the left.
Overdischarge detection delay time
tDL
38 ms
150 ms
300 ms
Select a value from the left.
Remark
4
Symbol
The value surrounded by bold lines is the delay time of the standard products.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Pin Configurations
1.
SOT-23-5
Table 5
SOT-23-5
Top view
5
Pin No.
4
1
2
Symbol
1
2
3
VM
VDD
VSS
4
DO
5
CO
Description
Negative power supply input pin for CO pin
Input pin for positive power supply
Input pin for negative power supply
Output pin for overdischarge detection
(CMOS output)
Output pin for overcharge detection
(CMOS output)
3
Figure 2
2.
SNT-6A
SNT-6A
Table 6
Top view
Pin No.
1
6
2
5
3
4
Figure 3
1
Symbol
NC*1
Description
No connection
Output pin for overcharge detection
2
CO
(CMOS output)
Output pin for overdischarge detection
3
DO
(CMOS output)
4
VSS
Input pin for negative power supply
5
VDD
Input pin for positive power supply
6
VM
Negative power supply input pin for CO pin
*1. The NC pin is electrically open.
The NC pin can be connected to VDD pin or VSS pin.
5
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Absolute Maximum Ratings
Table 7
(Ta = 25C unless otherwise specified)
Item
Symbol
Input voltage between VDD pin and
VSS pin
VM pin input voltage
Applied pin
Absolute Maximum Ratings
Unit
VDS
VDD
VSS 0.3 to VSS 12
V
VVM
VM
VDD 28 to VDD 0.3
V
DO pin output voltage
VDO
DO
VSS 0.3 to VDD 0.3
V
CO pin output voltage
SOT-23-5
Power dissipation
SNT-6A
Operating ambient temperature
VCO
CO
VVM 0.3 to VDD 0.3
600*1
400*1
40 to 85
V
mW
mW
C
55 to 125
C
PD
Topr
Storage temperature
Tstg
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name: JEDEC STANDARD51-7
Caution
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (P D) [mW]
700
600
SOT-23-5
500
SNT-6A
400
300
200
100
0
0
100
150
50
Ambient Temperature (Ta) [C]
Figure 4 Power Dissipation of Package (When Mounted on Board)
6
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Electrical Characteristics
1. Except Detection Delay Time (25C)
Table 8
Item
Symbol
Condition
(Ta = 25C unless otherwise specified)
Test
Test
Min.
Typ. Max. Unit CondiCircuit
tion
DETECTION VOLTAGE
Overcharge detection voltage
Overcharge release voltage
Overdischarge detection voltage
Overdischarge release voltage
VCU
VCL
VDL
VDU
3.60 V to 4.50 V, Adjustable
VCU
0.025
VCU
VCU
0.025
V
1
1
3.60 V to 4.50 V, Adjustable,
*1
Ta = 5C to 55C
VCU
0.03
VCU
VCU
0.03
V
1
1
VCL VCU
VCL
0.05
VCL
VCL
0.05
V
1
1
VCL = VCU
VCL
0.05
VCL
VCL
0.025
V
1
1
2.00 V to 3.00 V, Adjustable
VDL
0.05
VDL
VDL
0.05
V
2
2
VDU VDL
VDU
0.10
VDU
VDU
0.10
V
2
2
VDU = VDL
VDU
0.05
VDU
VDU
0.05
V
2
2
1.5
8
V
3.50 V to 4.40 V,
Adjustable
2.00 V to 3.40 V,
Adjustable
INPUT VOLTAGE
Operating voltage between VDD pin and VSS pin
VDSOP1
INPUT CURRENT
Current consumption during operation
IOPE
VDD = 3.5 V, VVM = 0 V
1.0
2
Current consumption during overdischarge
0.3
5.5
3.5
3
VDD = 1.5 V, VVM = 0 V
3.0
2.0
A
IOPED
A
3
2
2.5
5
10
k
4
3
CO pin output logic active “H”
2.5
9
15
k
4
3
CO pin output logic active “L”
2.5
5
10
k
4
3
2.5
5
10
k
5
3
2.5
5
10
k
5
3
OUTPUT RESISTANCE
CO pin resistance “H”
RCOH
CO pin resistance “L”
RCOL
DO pin resistance “H”
RDOH
DO pin resistance “L”
RDOL
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
7
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
2. Except Detection Delay Time (40°C to 85°C *1)
Table 9
Item
Symbol
Condition
(Ta = 40°C to 85°C *1 unless otherwise specified)
Test
Test
CondiMin.
Typ. Max. Unit
Circuit
tion
DETECTION VOLTAGE
Overcharge detection voltage
Overcharge release voltage
Overdischarge detection voltage
Overdischarge release voltage
VCU
3.60 V to 4.50 V, Adjustable
VCU
0.060
VCU
VCU
V
0.040
1
1
VCL VCU
VCL
V
0.065
1
1
VCL
VCL
0.08
VCL
3.50 V to 4.40 V,
Adjustable
VCL = VCU
VCL
0.08
VCL
VCL
0.04
V
1
1
2.00 V to 3.00 V, Adjustable
VDL
0.11
VDL
VDL
0.13
V
2
2
VDU VDL
VDU
0.15
VDU
VDU
0.19
V
2
2
VDU = VDL
VDU
0.11
VDU
VDU
0.13
V
2
2
1.5
8
V
0.7
3.0
6.0
A
3
2
3
2
VDL
VDU
2.00 V to 3.40 V,
Adjustable
INPUT VOLTAGE
Operating voltage between VDD pin and VSS pin VDSOP1
INPUT CURRENT
Current consumption during operation
IOPE
VDD = 3.5 V, VVM = 0 V
Current consumption during overdischarge
IOPED
VDD = 1.5 V, VVM = 0 V
0.2
2.0
3.8
A
1.2
5
15
k
4
3
CO pin output logic active “H”
1.2
9
27
k
4
3
CO pin output logic active “L”
1.2
5
15
k
4
3
5
3
5
3
OUTPUT RESISTANCE
CO pin resistance “H”
RCOH
CO pin resistance “L”
RCOL
DO pin resistance “H”
RDOH
DO pin resistance “L”
RDOL
1.2
5
15
k
1.2
5
15
k
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
8
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
3. Detection Delay Time
3. 1 S-8211EAC, S-8211EAH, S-8211EAI, S-8211EAJ, S-8211EAK, S-8211EAP
Table 10
Item
Symbol
Condition
Min.
Typ.
Max.
Test
Test
Unit CondiCircuit
tion
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
0.96
1.2
1.4
s
6
4
Overdischarge detection delay time
tDL
120
150
180
ms
6
4
Overcharge detection delay time
tCU
0.7
1.2
2.0
s
6
4
Overdischarge detection delay time
tDL
83
150
255
ms
6
4
DELAY TIME (Ta = 40°C to 85°C) *1
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
3. 2 S-8211EAA, S-8211EAB, S-8211EAD, S-8211EAE, S-8211EAF, S-8211EAG
Table 11
Item
Condition
Min.
Typ.
Max.
Test
Test
Unit CondiCircuit
tion
tCU
tDL
458
573
687
ms
6
4
240
300
360
ms
6
4
tCU
tDL
334
573
955
ms
6
4
166
300
510
ms
6
4
Symbol
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
Overdischarge detection delay time
DELAY TIME (Ta = 40°C to 85°C)
Overcharge detection delay time
Overdischarge detection delay time
*1
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
9
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (VCO) are judged by VVM
1.0 V, and the output voltage levels “H” and “L” at DO pin (VDO) are judged by VSS 1.0 V. Judge the
CO pin level with respect to VVM and the DO pin level with respect to VSS.
1. Overcharge Detection Voltage, Overcharge Release Voltage
(Test Condition 1, Test Circuit 1)
1. 1 CO pin output logic = Active “H”
Overcharge detection voltage (VCU) is defined as the voltage between the VDD pin and VSS pin at which VCO
goes from “L” to “H” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V.
Overcharge release voltage (VCL) is defined as the voltage between the VDD pin and VSS pin at which VCO goes
from “H” to “L” when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined
as the difference between overcharge detection voltage (VCU) and overcharge release voltage (VCL).
1. 2 CO pin output logic = Active “L”
Overcharge detection voltage (VCU) is defined as the voltage between the VDD pin and VSS pin at which VCO
goes from “H” to “L” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V.
Overcharge release voltage (VCL) is defined as the voltage between the VDD pin and VSS pin at which VCO goes
from “L” to “H” when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined
as the difference between overcharge detection voltage (VCU) and overcharge release voltage (VCL).
2. Overdischarge Detection Voltage, Overdischarge Release Voltage
(Test Condition 2, Test Circuit 2)
Overdischarge detection voltage (VDL) is defined as the voltage between the VDD pin and VSS pin at which VDO goes
from “H” to “L” when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V, V2 = 0 V.
Overdischarge release voltage (VDU) is defined as the voltage between the VDD pin and VSS pin at which VDO goes
from “L” to “H” when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (VHD) is defined as
the difference between overdischarge release voltage (VDU) and overdischarge detection voltage (VDL).
3. Current Consumption during Operation
(Test Condition 3, Test Circuit 2)
The current consumption during operation (IOPE) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = 3.5 V and V2 = 0 V (normal status).
4. Current Consumption during Overdischarge
(Test Condition 3, Test Circuit 2)
The current consumption during overdischarge (IOPED) is the current that flows through the VDD pin (IDD) under the
set conditions of V1 = 1.5 V, V2 = 0V (overdischarge status).
10
Rev.2.4_03
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
5. CO Pin Resistance “H”
(Test Condition 4, Test Circuit 3)
5. 1 CO pin output logic = Active “H”
The CO pin resistance “H” (RCOH) is the resistance at the CO pin under the set conditions of V1 = 4.5 V, V2 =
0 V, V3 = 4.0 V.
5. 2 CO pin output logic = Active “L”
The CO pin resistance “H” (RCOH) is the resistance at the CO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V3 = 3.0 V.
6. CO Pin Resistance “L”
(Test Condition 4, Test Circuit 3)
6. 1 CO pin output logic = Active “H”
The CO pin resistance “L” (RCOL) is the resistance at the CO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V3 = 0.5 V.
6. 2 CO pin output logic = Active “L”
The CO pin resistance “L” (RCOL) is the resistance at the CO pin under the set conditions of V1 = 4.5 V, V2 =
0 V, V3 = 0.5 V.
7. DO Pin Resistance “H”
(Test Condition 5, Test Circuit 3)
The DO pin “H” resistance (RDOH) is the resistance at the DO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V4 = 3.0 V.
8. DO Pin Resistance “L”
(Test Condition 5, Test Circuit 3)
The DO pin “L” resistance (RDOL) is the resistance at the DO pin under the set conditions of V1 = 1.8 V, V2 =
0 V, V4 = 0.5 V.
9. Overcharge Detection Delay Time
(Test Condition 6, Test Circuit 4)
9. 1 CO pin output logic = Active “H”
The overcharge detection delay time (tCU) is the time needed for VCO to change from “L” to “H” just after the
voltage V1 momentarily increases (within 10 s) from overcharge detection voltage (VCU) 0.2 V to overcharge
detection voltage (VCU) 0.2 V under the set conditions of V2 = 0 V.
9. 2 CO pin output logic = Active “L”
The overcharge detection delay time (tCU) is the time needed for VCO to change from “H” to “L” just after the
voltage V1 momentarily increases (within 10 s) from overcharge detection voltage (VCU) 0.2 V to overcharge
detection voltage (VCU) 0.2 V under the set conditions of V2 = 0 V.
10. Overdischarge Detection Delay Time
(Test Condition 6, Test Circuit 4)
The overdischarge detection delay time (tDL) is the time needed for VDO to change from “H” to “L” just after the voltage
V1 momentarily decreases (within 10 s) from overdischarge detection voltage (VDL) 0.2 V to overdischarge
detection voltage (VDL) 0.2 V under the set condition of V2 = 0 V.
11
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
R1 =
220
IDD
A
VDD
V1
Rev.2.4_03
V1
S-8211E Series
VSS
VM
DO
CO
V VDO
V VDO
V VCO
CO
V VCO
V2
COM
COM
Figure 5 Test Circuit 1
Figure 6 Test Circuit 2
VDD
VDD
V1
V1
S-8211E Series
VSS
S-8211E Series
VSS
VM
DO
VM
DO
CO
A IDO
A ICO
V4
V3
Oscilloscope
V2
CO
Oscilloscope
COM
COM
Figure 7 Test Circuit 3
12
S-8211E Series
VSS
VM
DO
VDD
Figure 8 Test Circuit 4
V2
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Operation
Remark Refer to the “ Battery Protection IC Connection Example”.
1. Normal Status
The S-8211E Series monitors the voltage of the battery connected between the VDD and VSS pins.
In case of overdischarge detection voltage (VDL) battery voltage overcharge detection voltage (VCU), the output
levels of CO and DO pins are as follows. This is the normal status.
Table 12
CO Pin Output Logic
CO Pin
DO Pin
Active “H”
VVM
VDD
Active “L”
VDD
VDD
2. Overcharge Status
When the battery voltage in the normal status exceeds the overcharge detection voltage (VCU) during charge, and this
status is held for the overcharge detection delay time (tCU) or more, the output levels of CO and DO pins are as
follows. This is the overcharge status.
This overcharge status is released when the battery voltage decreases to the overcharge release voltage (VCL) or
less.
Table 13
CO Pin Output Logic
CO Pin
DO Pin
Active “H”
VDD
VDD
Active “L”
VVM
VDD
3. Overdischarge Status
When the battery voltage in the normal status decreases than the overcharge detection voltage (VDL) during
discharge, and this status is held for the overdischarge detection delay time (tDL) or more, the output levels of CO and
DO pins are as follows. This is the overdischarge status.
This overdischarge status is released when the battery voltage increases to the overdischarge release voltage (VDU)
or more.
Table 14
CO Pin Output Logic
CO Pin
DO Pin
Active “H”
VVM
VSS
Active “L”
VDD
VSS
4. Delay Circuit
The detection delay times are determined by dividing a clock of approximately 3.5 kHz by the counter.
13
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Timing Chart
1. Overcharge Detection, Overdischarge Detection
VCU
VCL
Battery voltage
VDU
VDL
VDD
DO pin voltage
VSS
VDD
CO pin voltage
(active ”H”)
VM
VDD
CO pin voltage
(active ”L”)
VM
V
Overcharge detection delay time (tCU)
*1
Status
(1)
(2)
(1)
*1. (1) : Normal status
(2) : Overcharge status
(3) : Overdischarge status
Figure 9
14
Overdischarge detection delay time (tDL)
(3)
(1)
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Battery Protection IC Connection Example
R1
VDD
Battery
C1
S-8211E Series
VSS
DO
CO
VM
R2
CO
DO
Figure 10
Table 15 Constants for External Components
Symbol
Part
Purpose
Min.
Typ.
Max.
R1
Resistor
ESD protection,
For power fluctuation
100
220
330
C1
Capacitor
For power fluctuation
0.022 F
0.1 F
1.0 F
*3
Remark
Resistance should be as small as possible to
avoid lowering the overcharge detection
accuracy due to current consumption. *1
Connect a capacitor of 0.022 F or higher
between VDD pin and VSS pin. *2
-
R2
Resistor
ESD protection
300
1 k
4 k
*1. Insert a resistor of 100 or higher as R1 for ESD protection.
*2. If a capacitor of less than 0.022 F is connected to C1, DO pin may oscillate. Be sure to connect a capacitor of 0.022 F
or higher to C1.
*3. Be sure to using R2, connect the VM pin with the VSS pin.
Caution
1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do not
guarantee proper operation. Perform thorough evaluation using the actual application to set the
constant.
15
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Application Circuit Examples
1. Protection circuits series multi-cells
R1
VDD
Battery
C1
S-8211E Series
VSS
DO
CO
VM
R2
CO
DO
R1
VDD
Battery
C1
S-8211E Series
VSS
DO
CO
VM
R2
CO
DO
R1
VDD
Battery
C1
S-8211E Series
VSS
DO
CO
VM
R2
CO
DO
R1
VDD
Battery
C1
S-8211E Series
VSS
DO
CO
R2
CO
DO
Figure 11
16
VM
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
2. Charge cell-balance detection circuit
R1
EB
VDD
C1
Battery
S-8211E Series
VSS
DO
CO
VM
R2
R1
VDD
C1
Battery
S-8211E Series
VSS
DO
CO
VM
R2
R1
VDD
C1
Battery
S-8211E Series
VSS
DO
CO
VM
R2
Protection IC
R1
VDD
Battery
C1
S-8211E Series
VSS
EB
DO
CO
VM
R2
Figure 12
17
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Be sure to using R2, connect the VM pin with the VSS pin.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
18
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Characteristics (Typical Data)
1. Current Consumption
1. 1 IOPE vs. Ta
1. 2 IOPED vs. Ta
4
5
4
IOPED [A]
IOPE [A]
6
3
2
1
0
40 25
0
25
Ta [C]
50
75 85
4
VDD [V]
6
8
3
2
1
0
4025
0
25
Ta [C]
50
75 85
1. 3 IOPE vs. VDD
IOPE [A]
6
5
4
3
2
1
0
0
2
2. Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent
Detection Voltage, and Delay Time
4.350
4.345
4.340
4.335
4.330
4.325
4.320
4.315
4.310
4.305
4.300
40 25
2. 2 VCL vs. Ta
VCL [V]
VCU [V]
2. 1 VCU vs. Ta
0
25
Ta [C]
50
75 85
2.95
2.94
2.93
2.92
2.91
2.90
2.89
2.88
2.87
2.86
2.85
40 25
0
25
Ta [C]
50
75 85
50
75 85
2. 4 VDL vs. Ta
VDL [V]
VDU [V]
2. 3 VDU vs. Ta
4.125
4.115
4.105
4.095
4.085
4.075
4.065
4.055
4.045
4.035
4.025
40 25
0
25
50
Ta [C]
75 85
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
40 25
0
25
Ta [C]
19
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
2. 6 tDL vs. Ta
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
40 25
tDL [ms]
tCU [s]
2. 5 tCU vs. Ta
Rev.2.4_03
0
25
Ta [C]
50
7585
200
190
180
170
160
150
140
130
120
110
100
40 25
0
25
Ta [C]
50
2
VCO [V]
3
7585
3. CO pin / DO pin
3. 1 ICOH vs. VCO
3. 2 ICOL vs. VCO
0
0.5
0.4
ICOL [mA]
ICOH [mA]
0.1
0.2
0.3
0.4
0.5
0.3
0.2
0.1
0
1
2
3
0
4
0
1
VCO [V]
3. 4 IDOL vs. VDO
0
0.05
0.10
0.20
IDOL [mA]
IDOH [mA]
3. 3 IDOH vs. VDO
0.15
0.20
0.25
0.30
0
1
2
VDO [V]
20
4
3
4
0.15
0.10
0.05
0
0
0.5
1.0
VDO [V]
1.5
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series
Rev.2.4_03
Marking Specifications
1. SOT-23-5
Top view
5
4
(1) to (3):
Product Code (refer to Product Name vs. Product Code)
(4)
Lot number
:
(1) (2) (3) (4)
1
2
3
Product Name vs. Product Code
Product Code
(1)
(2)
(3)
Product Name
S-8211EAC-M5T1U
S-8211EAF-M5T1U
S-8211EAG-M5T1U
S-8211EAJ-M5T1U
S-8211EAK-M5T1U
R
R
R
R
R
3
3
3
3
3
C
F
G
J
K
2. SNT-6A
Top view
6
5
(1) to (3):
(4) to (6):
4
Product Code (refer to Product Name vs. Product Code)
Lot number
(1) (2) (3)
(4) (5) (6)
1
2
3
Product Name vs. Product Code
Product Name
S-8211EAA-I6T1U
S-8211EAB-I6T1U
S-8211EAD-I6T1U
S-8211EAE-I6T1U
S-8211EAH-I6T1U
S-8211EAI-I6T1U
S-8211EAP-I6T1U
Product Code
(1)
(2)
(3)
R
3
A
R
3
B
R
3
D
R
3
E
3
R
H
R
3
I
3
R
P
21
2.9±0.2
1.9±0.2
4
5
1
2
+0.1
0.16 -0.06
3
0.95±0.1
0.4±0.1
No. MP005-A-P-SD-1.3
TITLE
SOT235-A-PKG Dimensions
No.
MP005-A-P-SD-1.3
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
ø1.5 -0
+0.2
ø1.0 -0
2.0±0.05
0.25±0.1
4.0±0.1
1.4±0.2
3.2±0.2
3 2 1
4
5
Feed direction
No. MP005-A-C-SD-2.1
TITLE
SOT235-A-Carrier Tape
No.
MP005-A-C-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP005-A-R-SD-1.1
SOT235-A-Reel
TITLE
No.
MP005-A-R-SD-1.1
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
3,000
1.57±0.03
6
1
5
4
2
3
+0.05
0.08 -0.02
0.5
0.48±0.02
0.2±0.05
No. PG006-A-P-SD-2.1
TITLE
SNT-6A-A-PKG Dimensions
No.
PG006-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
1.85±0.05
ø0.5 -0
4.0±0.1
0.65±0.05
3 2 1
4
5 6
Feed direction
No. PG006-A-C-SD-2.0
TITLE
SNT-6A-A-Carrier Tape
No.
PG006-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PG006-A-R-SD-1.0
SNT-6A-A-Reel
TITLE
No.
PG006-A-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
5,000
0.52
1.36
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.30 mm ~ 1.40 mm)
No. PG006-A-L-SD-4.1
TITLE
SNT-6A-A
-Land Recommendation
No.
PG006-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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