MC100EP445FAG

MC10EP445, MC100EP445 3.3V/5V ECL 8-Bit Serial/Parallel Converter Description The MC10/100EP445 is an integrated 8–bit differential serial to parallel data converter with asynchronous data synchronization. The device has two modes of operation. CKSEL HIGH mode is designed to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode is designed to operate at twice the internal clock data rate of up to 5.0 Gb/s. The conversion sequence was chosen to convert the first serial bit to Q0, the second bit to Q1, etc. Two selectable differential serial inputs, which are selected by SINSEL, provide this device with loop−back testing capability. The MC10/100EP445 has a SYNC pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from Dn to Dn+1. Each additional shift requires an additional pulse to be applied to the SYNC pin. Control pins are provided to reset and disable internal clock circuitry. Additionally, VBB pin is provided for single−ended input condition. The 100 Series contains temperature compensation. • • • • 1530 ps Propagation Delay 5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode Differential Clock and Serial Inputs VBB Output for Single-Ended Input Applications Asynchronous Data Synchronization (SYNC) Asynchronous Master Reset (RESET) PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State CLK ENABLE Immune to Runt Pulse Generation These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 16 MARKING DIAGRAM* MCxxx EP445 AWLYYWWG LQFP−32 FA SUFFIX CASE 873A 1 1 32 QFN32 MN SUFFIX CASE 488AM Features • • • • • • • http://onsemi.com MCxx EP445 AWLYYWWG G xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. 1 Publication Order Number: MC10EP445/D MC10EP445, MC100EP445 VCC SINA SINA VBB0 VEE SINB SINB SINSEL 32 RESET 31 30 29 28 27 26 25 1 24 VCC SYNC 2 23 PCLK CKEN 3 22 PCLK CLK 4 21 Q0 20 VCC MC10EP445 MC100EP445 CLK 5 VBB1 6 19 Q1 CKSEL 7 18 Q2 VCC 8 17 VCC 9 Q7 10 Q6 11 12 13 Q5 VCC VCC 14 15 16 Q4 Q3 VEE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION Exposed Pad (EP) VCC SINA SINA VBB0 VEE SINB SINB SINSEL 32 RESET 31 30 29 28 27 26 25 1 24 VCC 2 23 PCLK CKEN 3 CLK 4 SYNC MC10EP445 MC100EP445 21 Q0 SYNC* ECL Conversion Synchronizing Input CKSEL* ECL Clock Input Selector Pin CKEN* ECL Clock Enable Pin RESET* ECL Reset Pin VBB0, VBB1 Output Reference Voltage VCC Positive Supply VEE Negative Supply EP The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE. 8 17 V CC Q7 Q6 14 Q5 VCC VCC 20 VCC 15 ECL Serial Input Selector Pin ECL Differential Parallel Clock Output 18 Q2 13 SINSEL* PCLK, PCLK 7 12 ECL Differential Serial Data Input B 22 PCLK 19 Q1 11 SINB*, SINB* ECL Parallel Data Outputs 6 10 ECL Differential Serial Data Input A ECL Differential Clock Inputs VBB1 9 SINA*, SINA* CLK*, CLK* 5 VCC Function Q0−Q7 CLK CKSEL Pin 16 Q4 Q3 VEE Figure 2. 32−Lead QFN Pinout (Top View) * Pins will default logic LOW or differential logic LOW when left open. http://onsemi.com 2 MC10EP445, MC100EP445 Table 2. TRUTH TABLE FUNCTION High PIN SINSEL CKSEL Low Select SINB Input Select SINA Input Q: PCLK = 8:1 CLK: Q = 1:1 Q: PCLK = 8:1 CLK: Q = 1:2 CLK CLK Q Q CKEN Synchronously Disable Internal Clock Circuitry Synchronously Enable Internal Clock Circuitry RESET Asynchronous Master Reset Synchronous Enable SYNC Asynchronously Applied to Swallow a Data Bit Normal Conversion Process SINA VEE SINA SINB 1:2 DEMUX SINB 1:2 DEMUX 1:2 DEMUX SINSEL 1:2 DEMUX CKEN T C Q4 Q2 Q6 Q 1:2 DEMUX R T C Q0 Q R 1:2 DEMUX 1:2 DEMUX SYNC Q1 Q5 Q3 Q7 Control Logic DIV2 CLK DIV2 PCLK PCLK CLK CKSEL RESET Figure 3. Logic Diagram http://onsemi.com 3 MC10EP445, MC100EP445 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pull−up Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP−32 QFN−32 Flammability Rating Oxygen Index: 28 to 34 > 2 kV > 200 V > 2 kV Pb Pkg Pb−Free Pkg Level 2 N/A Level 2 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 993 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W JC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder 3.3 V, 5  to 10  in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V. 7. All loading with 50  to VCC − 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP445, MC100EP445 Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 9) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 10) 95 119 143 98 122 146 100 125 150 mA VOH Output HIGH Voltage (Note 11) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 11) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference −1510 −1310 −1445 −1245 −1385 −1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current −1410 VEE+2.0 0.0 −1345 VEE+2.0 150 0.5 0.0 −1285 VEE+2.0 150 0.5 A 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Input and output parameters vary 1:1 with VCC. 10. Required 500 lfpm air flow when using −5 V power supply. For (VCC − VEE) >3.3 V, 5  to 10  in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V. 11. All loading with 50  to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 95 119 143 98 122 146 100 125 150 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 14) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1305 1675 1305 1675 1305 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1875 2.0 150 0.5 1875 150 0.5 0.5 1875 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 14. All loading with 50  to VCC − 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 MC10EP445, MC100EP445 Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 16) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 17) 95 119 143 98 122 146 100 125 150 mA VOH Output HIGH Voltage (Note 18) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 18) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3005 3375 3005 3375 3005 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current 3575 2.0 3575 150 3575 150 0.5 0.5 A 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 17. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) >3.3 V, 5  to 10  in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V. 18. All loading with 50  to VCC − 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 20) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 21) 95 119 143 98 122 146 100 125 150 mA VOH Output HIGH Voltage (Note 22) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 22) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 23) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current −1425 VEE + 2.0 0.0 VEE + 2.0 150 0.5 −1425 0.0 VEE + 2.0 150 0.5 −1425 0.5 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Input and output parameters vary 1:1 with VCC. 21. Required 500 lfpm air flow when using −5.0 V power supply. For (VCC − VEE) > 3.3 V, 5  to 10  in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC − VEE operation at v 3.3 V. 22. All loading with 50  to VCC − 2.0 V. 23. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 7 MC10EP445, MC100EP445 Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 24) −40°C Min Typ CKSEL = LOW CKSEL = HIGH 2.0 2.8 2.5 3.3 CLK to Q CLK TO PCLK 1280 1000 1475 1240 Setup Time SINA, B+ TO CLK+ (Figure 5) CKEN+ TO CLK− (Figure 6) −400 100 th Hold Time CLK+ TO SINA, B− (Figure 5) CLK− TO CKEN (Figure 6) tRR/tRR2 Reset Recovery (Figure 4) tPW Minimum Pulse Width tJITTER RMS Random Clock Jitter @ 2.0 GHz CLK_SEL LOW @ 2.5 GHz CLK_SELF HIGH @ 3.0 GHz CLK_SEL HIGH Characteristic Symbol fmax Maximum Input CLK Frequency (See Figure 13. Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential ts RESET 25°C Max Min Typ 2.0 2.8 2.5 3.3 1335 1050 1557 1310 −459 50 −420 100 533 45 474 −35 350 180 1710 1490 400 85°C Max Min Typ 1.7 2.8 2.2 3.3 1450 1140 1663 1420 −479 50 −440 100 −492 50 ps 550 45 490 −35 560 45 508 −35 ps 350 180 350 180 ps 1795 1580 400 Max Unit GHz 1950 1710 400 ps ps ps 1.5 1.0 1.5 1.5 1.0 2.0 1.5 1.5 2.5 VPP Input Voltage Swing (Differential Configuration) (Note 25) 150 800 1200 150 800 1200 150 800 1200 mV tr tf Output Rise/Fall Times (20% − 80%) 100 100 180 180 400 250 100 100 200 200 400 300 125 125 230 230 425 325 ps Q/Q PCLK/PCLK NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50  to VCC − 2.0 V. 25. VPP(min) is the minimum input swing for which AC parameters are guaranteed. http://onsemi.com 8 MC10EP445, MC100EP445 Reset tRR CLK CLK Figure 4. Reset Recovery CLK Data Setup Time + − ts Data Hold Time + − th Figure 5. Data Setup and Hold Time CLK CKEN Setup Time + − ts CKEN Hold Time − + th Figure 6. CKEN Setup and Hold Time http://onsemi.com 9 MC10EP445, MC100EP445 APPLICATION INFORMATION The two selectable serial data paths can be used for loop−back testing as well as the bit error testing. Upon power−up, the internal flip−flops will attain a random state. To synchronize multiple flip–flops in the device, the Reset (pin 1) must be asserted. The reset pin will disable the internal clock signal irrespective of the CKEN state (CKEN disables the internal clock circuitry). The device will grab the first stream of data after the falling edge of RESETÀ, followed by the falling edge of CLKÁ, on second rising edge of CLKÂ in either CKSEL modes. (See Figure 6) The MC10/100EP445 is an integrated 1:8 serial to parallel converter with two modes of operation selected by CKSEL (Pin 7). CKSEL HIGH mode only latches data on the rising edge of the input CLK and CKSEL LOW mode latches data on both the rising and falling edge of the input CLK. CKSEL LOW is the open default state. Either of the two differential input serial data path provided for this device, SINA and SINB, can be chosen with the SINSEL pin (pin 25). SINA is the default input path when SINSEL pin is left floating. Because of internal pull−downs on the input pins, all input pins will default to logic low when left open. RESET (Asynchronous Reset) RESET (Synchronous ENABLE) Á CLK À RESET PCLK Figure 7. Reset Timing Diagram http://onsemi.com 10 Â MC10EP445, MC100EP445 For CKSEL LOW operation, the data is latched on both the rising edge and the falling edge of the clock and the time from when the serial data is latchedÀ to when the data is seen on the parallel outputÁ is 6 clock cycles (see Figure 8). Number of Clock Cycles from Data Latch to Q 1 2 3 4 5 6 À CLK SINA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 RESET CKEN CKSEL PCLK Á Q0 D0 D8 D16 Q1 D1 D9 D17 Q2 D2 D10 D18 Q3 D3 D11 D19 Q4 D4 D12 D20 Q5 D5 D13 D21 Q6 D6 D14 D22 Q7 D7 D15 D23 Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW http://onsemi.com 11 MC10EP445, MC100EP445 Similarly, for CKSEL HIGH operation, the data is latched only on the rising edge of the clock and the time from when the serial data is latchedÀ to when the data is seen on the parallel outputÁ is 12 clock cycles (see Figure 9). Number of Clock Cycles from Data Latch to Q 2 3 4 5 6 7 8 9 10 1 11 12 À CLK SINA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 RESET CKEN CKSEL PCLK Á Q0 D0 Q1 D1 Q2 D2 Q3 D3 Q4 D4 Q5 D5 Q6 D6 Q7 D7 Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH http://onsemi.com 12 MC10EP445, MC100EP445 clock cycles shifts the start bit for conversion from Qn to Qn−1. The bit is swallowed following the two clock cycle pulse width of SYNCÀ on the next triggering edge of clockÁ (either on the rising or the falling edge of the clock). Each additional shift requires an additional pulse to be applied to the SYNC pin. (See Figure 10) To allow the user to synchronize the output byte data correctly, the start bit for conversion can be moved using the SYNC input pin (pin 2). Asynchronously asserting the SYNC pin will force the internal clock to swallow a clock pulse, effectively shifting a bit from the Qn to the Qn−1 output as shown in Figure 10 and Figure 11. For CKSEL LOW, a single pulse applied asynchronously for two consecutive 2 Clock Cycles for SYNC 1 2 Á Next Triggering Edge of Clock Bit D8 is Swallowed CLK SINA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 CKSEL PCLK SYNC À Q0 D0 D9 D17 Q1 D1 D10 D18 Q2 D2 D11 D19 Q3 D3 D12 D20 Q4 D4 D13 D21 Q5 D5 D14 D22 Q6 D6 D15 D23 Q7 D7 D16 D24 Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW http://onsemi.com 13 MC10EP445, MC100EP445 For CKSEL HIGH, a single pulse applied asynchronously for three consecutive clock cycles shifts the start bit for conversion from Qn to Qn−1. The bit is swallowed following the three clock cycle pulse width of SYNCÀ on the next 3 Clock Cycles for Sync 1 2 3 SYNC Next Triggering Edge of Clock Bit D8 is Swallowed Á CLK SINA triggering edge of clockÁ (on the rising edge of the clock only). Each additional shift requires an additional pulse to be applied to the SYNC pin. (See Figure 11) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 À PCLK Q0 D0 D9 D17 Q1 D1 D10 D18 Q2 D2 D11 D19 Q3 D3 D12 D20 Q4 D4 D13 D21 Q5 D5 D14 D22 Q6 D6 D15 D23 Q7 D7 D16 D24 Figure 11. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH http://onsemi.com 14 MC10EP445, MC100EP445 The synchronous CKEN (pin 3) applied with at least one clock cycle pulse length will disable the internal clock signal. The synchronous CKEN will suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the falling Internal Clock Disabled edge of CLK will suspend all activities. The first data bit will clock on the rising edge, since the falling edge of CKEN followed by the falling edge of the incoming clock triggers the enabling of the internal process. (See Figure 12) Internal Clock Enabled CLK CKEN PCLK CKSEL Figure 12. Timing Diagram with CKEN with CKSEL HIGH conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor, which will limit the current sourcing or sinking to 0.5mA. When not used, VBB should be left open. Also, both outputs of the differential pair must be terminated (50  to VTT = VCC – 2 V) even if only one output is used. The differential PCLK output (pins 22 and 23) is a word framer and can help the user to synchronize the parallel data outputs. During CKSEL LOW operation, the PCLK will provide a divide by 4−clock frequency, which frames the serial data in period of PCLK output. Likewise during CKSEL HIGH operation, the PCLK will provide a divide by 8−clock frequency. The VBB pin, an internally generated voltage supply, is available to this device only. For single–ended input http://onsemi.com 15 MC10EP445, MC100EP445 1000 VOUTpp (mV) 900 9 800 8 700 7 CKSEL LOW 600 6 500 5 400 4 300 3 200 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ (JITTER) 100 0 0 500 1000 1500 2000 2500 3000 ÉÉ ÉÉ 2 1 3500 INPUT CLK FREQUENCY (MHz) Figure 13. Fmax/Jitter Q Zo = 50  D Receiver Device Driver Device Q Zo = 50  D 50  50  VTT VTT = VCC − 2.0 V Figure 14. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 16 JITTEROUT ps (RMS) 10 CKSEL HIGH MC10EP445, MC100EP445 ORDERING INFORMATION Device MC10EP445FAG MC10EP445FAR2G MC10EP445MNG MC10EP445MNR4G MC100EP445FAG MC100EP445FAR2G MC100EP445MNG MC100EP445MNR4G Package Shipping† LQFP−32 (Pb−Free) 250 Units / Tray 2000 / Tape & Reel 74 Units / Rail QFN−32 (Pb−Free) 1000 / Tape & Reel 250 Units / Tray LQFP−32 (Pb−Free) 2000 / Tape & Reel 74 Units / Rail QFN−32 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 17 MC10EP445, MC100EP445 PACKAGE DIMENSIONS A 4X A1 32 −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C 25 0.20 (0.008) AB T-U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 ÉÉ ÉÉ ÉÉ −Z− 9 S1 4X 0.20 (0.008) AC T-U Z F S 8X M_ J R D DETAIL AD G SECTION AE−AE −AB− C E −AC− H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 18 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q_ 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE M N 9 0.20 (0.008) DETAIL Y AC T-U Z AE B1 MC10EP445, MC100EP445 PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A É É PIN ONE LOCATION A B D L L L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C A DETAIL B 0.10 C ÉÉÉ ÇÇÇ ÇÇÇ EXPOSED Cu TOP VIEW (A3) A1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION 0.08 C SEATING PLANE C SIDE VIEW NOTE 4 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 9 K D2 5.30 17 8 32X MILLIMETERS MIN MAX 1.00 0.80 0.05 −−− 0.20 REF 0.30 0.18 5.00 BSC 3.25 2.95 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 3.35 L 32X 0.63 E2 1 32 3.35 5.30 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW NOTE 3 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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